design.txt

all gates have one output port and 1 to 3 input ports
inverter: output is high if the number of input highs is even (xnor)
transistor: output is high if all connected inputs are high (and)

bridge: not a gate, but provide horizontal and vertical bypassing, can also add optional spillage so horizontal highs are outputted to vertical or vice versa
tunnel: signal connection between neighboring layers
the graphics for these two can simply contain an extra carved out section that is colored with the wire, pointing towards the output direction

one we way to make supporting modules easier is by disallowing the placement of gates near a module's edge.
or we can simply draw a box around the module and say gates do not work across boundaries.

TODO:
V add inverter and transistor
V support connecting to gates around wires
V begin work on wire update engine (basic)
V support copy and pasting (basic)
V support saving and loading files (basic)
- add a layer of indirection between wire index and wire state
- begin basic experimenting with graph optimization techniques
- feature to allow comments or design scratch notes in app
- add greedy meshing (single axis or both axis?)
- add vertex buffer batching between chunks
- add modules system

IMPROVEMENTS:
V switch wire placement to only commit on release (reduce snapping to wrong axis)
- create and use PositionMap and PositionSet to accelerate searching
- use https://github.com/mateidavid/zstr for stream compression
- RecyclingList can use a bit-tree structure for fast occupancy information

IDEAS:
- a new kind of bridge (or integrate with existing bridge) to allow Factorio style jumps

module ModuleName
(
    wire InputWireName0;
    wire InputWireName1;
    wire[64] InputWiresName0;
)
{
    wire ModuleWireName0;
    wire ModuleWireName1;

    and ModuleWireName0 InputWireName0 InputWireName1;
    xnor ModuleWireName1 InputWireName0 InputWireName1;
}

calculator planning:
states:
0 = waiting for digit
1 = digit button down
2 = display result

TODO: don't need the input to the shift registers from the result because
1) we can simply display the result and
2) the accumulator is already there
so we can remove that complicated thing where we have to store to display