Detecting source-header dependencies for Verilog

[Risto97]

Currently, there is no way to retrigger targets if the verilog header files change.
This is a similar problem to how C++ header files are tracked with depend.make in Makefiles.

Currently, easiest solution to implement is to list the header files manually, something like:

ip_sources(${IP} SYSTEMVERILOG
    HEADERS 
     file1.sv
....