Better alignment and clearer structures of std_cell

[SteffenReith]

Minor details concerning the clarity of the design of the standard cells. Even if such things have no technical impact, they should be corrected as they confuse people who are learning the ropes and make the learning process unnecessarily difficult.

Which cell: sg13g2_inv_1

What has been noticed:

• misaligned contact (layer Cont_drawing) at 1080, 2540, 1240, 2700 should be aligned at y-position to contract at 560, 22585, 720, 2745

• misaligned contact (layer Cont_drawing) at 1080, 2155, 1240, 2315 should be aligned at y-position to contact 560,2235,720,2395

• unneeded corner (layer GatPoly_drawing) roughly at 9550 1520.46 should be removed to make a continous line. The width of the gate should be the same in PMOS and NMOS regions.

• misaligned contact (layer Cont_drawing) at 550, 1095, 710, 1235 should be aligned at x-position to contact 560, 2235, 720, 2395

• misaligned contact (layer Cont_drawing) at 550, 670, 710, 830 should be aligned at x-position to contact 560, 2235, 720, 2395

• width of metal1 at roughly 468, 1302 (towards VSS) should be the same as
  the width of metal1 at roughly 519, 2215 (towards VDD)

• distance from gate_poly to metal1 (towards VDD, layer GatePoly_drawing) at roughly 833 3376 differs from distance to metal1 (signal Y)

• distance from gate_poly to metal1 (towards VDD, layer GatePoly_drawing) at roughly 824 12933 differs from distance to metal1 (signal Y)

Suggestions for improvement:

• simply make all positions of contacts (in x and y) consistent

• remove unneeded corners

• center a gates in the channels of PMOS and NMOS

[sergeiandreyev]

Hi @SteffenReith, we agree that all these optimizations are good to have! currently we're in progress of a full library revision and will certainly consider these points as well.
more on that in the email :)