From efea8e3d81a06f59d1ecd67a092f6fa6cf9f2455 Mon Sep 17 00:00:00 2001
From: Bhusan Gupta <bgupta@thronax.com>
Date: Wed, 18 Sep 2024 11:32:44 -0700
Subject: [PATCH] added forwarder for circuits, added missing ones and
 reordered alphabetically

---
 src/bundles.stanza            |  4 ++--
 src/circuits.stanza           | 10 ++++++++++
 src/pin-assignment.stanza     |  2 +-
 src/protocols.stanza          | 11 +++--------
 src/protocols/ethernet.stanza |  4 +++-
 src/si.stanza                 |  2 +-
 6 files changed, 20 insertions(+), 13 deletions(-)
 create mode 100644 src/circuits.stanza

diff --git a/src/bundles.stanza b/src/bundles.stanza
index 7c0b56c9..fdbeb458 100644
--- a/src/bundles.stanza
+++ b/src/bundles.stanza
@@ -4,10 +4,10 @@ defpackage jsl/bundles:
   import jitx
   import jitx/commands
 
-  forward jsl/bundles/general
-  forward jsl/bundles/debug
   forward jsl/bundles/comms
+  forward jsl/bundles/debug
   forward jsl/bundles/gates
+  forward jsl/bundles/general
 
 ; Utilities
 
diff --git a/src/circuits.stanza b/src/circuits.stanza
new file mode 100644
index 00000000..0830b7d5
--- /dev/null
+++ b/src/circuits.stanza
@@ -0,0 +1,10 @@
+#use-added-syntax(jitx)
+defpackage jsl/circuits:
+
+  forward jsl/circuits/Bypass
+  forward jsl/circuits/ConfigStrap
+  forward jsl/circuits/CrystalResonator
+  forward jsl/circuits/Network
+  forward jsl/circuits/Pullups
+  forward jsl/circuits/utils
+  
\ No newline at end of file
diff --git a/src/pin-assignment.stanza b/src/pin-assignment.stanza
index 8d3e6d30..0ef32e1c 100644
--- a/src/pin-assignment.stanza
+++ b/src/pin-assignment.stanza
@@ -5,7 +5,7 @@ defpackage jsl/pin-assignment:
   import jitx/commands
 
   forward jsl/pin-assignment/checks
-  forward jsl/pin-assignment/generators
   forward jsl/pin-assignment/circuit-pool
+  forward jsl/pin-assignment/generators
 
 
diff --git a/src/protocols.stanza b/src/protocols.stanza
index 128798d0..fbed5289 100644
--- a/src/protocols.stanza
+++ b/src/protocols.stanza
@@ -3,15 +3,10 @@ defpackage jsl/protocols:
   import core
   import jitx
 
-  forward jsl/protocols/pcie
   forward jsl/protocols/displayport
-  forward jsl/protocols/usb
-  forward jsl/protocols/ethernet/MDI/e10GBASE-KR
-  forward jsl/protocols/ethernet/MDI/MDI-1000Base-T
-  forward jsl/protocols/ethernet/MII/GMII
-  forward jsl/protocols/ethernet/MII/MII
-  forward jsl/protocols/ethernet/MII/RGMII
-  forward jsl/protocols/ethernet/MII/RMII
+  forward jsl/protocols/ethernet
+  forward jsl/protocols/pcie
   forward jsl/protocols/sata
+  forward jsl/protocols/usb
   
   
diff --git a/src/protocols/ethernet.stanza b/src/protocols/ethernet.stanza
index 3d4e404b..91c534ee 100644
--- a/src/protocols/ethernet.stanza
+++ b/src/protocols/ethernet.stanza
@@ -2,12 +2,14 @@
 defpackage jsl/protocols/ethernet:
   ; MDI
   forward jsl/protocols/ethernet/MDI/e10GBASE-KR
+  forward jsl/protocols/ethernet/MDI/MDI-100Base-TX
   forward jsl/protocols/ethernet/MDI/MDI-1000Base-T
 
   ; MII
+  forward jsl/protocols/ethernet/MII/GMII
   forward jsl/protocols/ethernet/MII/MII
+  forward jsl/protocols/ethernet/MII/MIIM
   forward jsl/protocols/ethernet/MII/RMII
   forward jsl/protocols/ethernet/MII/RGMII
-  forward jsl/protocols/ethernet/MII/MIIM
 
   forward jsl/protocols/ethernet/utils
\ No newline at end of file
diff --git a/src/si.stanza b/src/si.stanza
index a13199c8..50a642f6 100644
--- a/src/si.stanza
+++ b/src/si.stanza
@@ -3,6 +3,7 @@ defpackage jsl/si:
   import core
   import jitx
 
+  forward jsl/si/bus
   forward jsl/si/constraints
   forward jsl/si/couplers
   forward jsl/si/helpers
@@ -11,4 +12,3 @@ defpackage jsl/si:
   forward jsl/si/physics
   forward jsl/si/signal-ends
   forward jsl/si/TransmissionLine
-  forward jsl/si/bus