main.stanza

#use-added-syntax(jitx)
defpackage nrf-motion:
  import core
  import math
  import jitx
  import jitx/commands

  import ocdb/utils/checks
  import ocdb/utils/generic-components
  ; import ocdb/utils/defaults
  import ocdb/utils/generator-utils
  import ocdb/utils/design-vars
  import ocdb/artwork/jitx-logo

  import jsl/bundles
  import jsl/si

  import amplifiers
  import helpers
  import nRF

public val board-shape:Shape = Rectangle(31.0, 20.0)

OPTIMIZE-FOR = ["area"]
OPERATING-TEMPERATURE = min-max(0.0 50.0)
MIN-PKG = "0402"

; top level design
pcb-module nrf-motion :
  ; Coin cell holder placed on bottom
  inst bat : components/MYOUNG/MY-1632-03/module
  place(bat.holder) at loc(-2.401, 2.413, 0.0) on Bottom

  ; setup voltage range for design
  val vbat-range = min-max(2.8, 3.0)
  setup-supply-rail(bat.vout, vbat-range)

  ; MCU instantiation
  inst mcu : nRF-mcu

  ; Accelerometer
  inst xl : components/STMicroelectronics/LIS3DHTR/module

  ; MCU and Accelerometer (XL) are in the same power domain because
  ;   the XL will generate a WAKE signal to wake the MCU out of
  ;   sleep.
  net always-on (bat.vout, xl.power, mcu.supply)
  net (xl.vio, self.VDD) ; Need to use self.VDD as this net is generated by the setup-supply-rail() function

  ; Connect the XL to the NRF's i2c bus
  net (mcu.i2c-bus, xl.i2c)
  ;  We use the interrupt from the XL to wake the MCU from deep sleep
  net (mcu.wake, xl.int[1])

  ; RF Interface for the MCU
  inst RF : RF-frontend
  place(RF.ant.ant) at loc(9.556, 5.000, 270.0) on Top
  topo-net(mcu.ant, RF.sig)
  rf-routing-structure(rf-constraint, mcu.ant, find-signal-end(RF.sig))

  net (self.GND RF.gnd) ; Need to use self.GND as this net is generated by the setup-supply-rail() function

  ; Power switch for the Analog Power Domain
  ;   We want to be able to turn this section off while we
  ;   are sleeping to reduce power usage.
  val PMOS-def = components/ON-Semiconductor/NTA4151PT1G/component
  inst load-sw : load-switch/high-side-mosfet-switch(PMOS-def)

  net (always-on, load-sw.vin)
  net (mcu.vdda-en, load-sw.control)

  ; Establish a Supply rail for the output of the load switch
  ;   and give it is own symbol for clarity.
  net VDDA (load-sw.vout.V+)
  symbol(VDDA) = ocdb/utils/symbols/supply-sym
  property(VDDA.voltage) = vbat-range

  ; Analog Interface
  inst mic : components/ALLPOWER-ShenZhen-Quan-Li-Semiconductor-/AP3722AT/module

  ; This opamp shows proper corner frequency at 20kHz as expected.
  val OpAmpType = components/STMicroelectronics/TS971ILT/module

  val bandpass = BandpassConfig(34.0, 100.0, 20.0e3)
  val preampType = amplifiers/microphone-preamp(OpAmpType, bandpass)
  inst amp : preampType

  schematic-group([mic, amp]) = audio

  ; Add the analog power to the switchable power domain for low power operation.
  net (load-sw.vout, amp.vin, mic.vin)

  ;  The mic is connected to the pre-amp
  net (mic.out, amp.in)
  ;  The pre-amp is connected to the ADC
  net (amp.out, mcu.mic-in)

  net GND (self.GND)
  net VDD (self.VDD)

  via-stitch(board-shape, GND)

  ; Run the schematic review
  check-design(self)

; compile the design
set-current-design("nrf-design")
set-paper(ANSI-B)
setup-board(board-shape)

var main-module = ocdb/utils/generator-utils/run-final-passes(nrf-motion) ; Analyze design with a pass
set-main-module(main-module) ; Treat the provided module as a design, and compile it.

view-schematic()
view-board()