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extintrin.h
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extintrin.h
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/**
* @file extintrin.h
* @author Jens Munk Hansen <jens.munk.hansen@gmail.com>
* @date Tue May 5 20:13:58 2015
*
* @brief Extensions to Intel's intrinsics
*
*
*/
/*
* This file is part of SOFUS.
*
* SOFUS is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* SOFUS is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with SOFUS. If not, see <http://www.gnu.org/licenses/>.
*/
#pragma once
// Using AVX2, shifts can be made using _mm_sllv_epi32 (sse_halfs)
#include <sps/cenv.h>
#include <sps/debug.h>
#include <float.h>
#include <stdint.h>
#include <sps/config.h>
#ifndef SPS_DEBUG_INFINITY
# define SPS_DEBUG_INFINITY 1
#endif
#ifdef HAVE_CONFIG_H
#else
// Check is __AVX__ __AVX2__ __SSE4_1__ __SSE3__ __SSE2__ __SSE__
# pragma message("Warning SSE2,SSE3,SSE4(1,2) and AVX is enabled")
# define HAVE_EMMINTRIN_H 1
# define HAVE_PMMINTRIN_H 1
# define HAVE_SMMINTRIN_H 1
# define HAVE_NMMINTRIN_H 1
# define HAVE_IMMINTRIN_H 1
#endif
#ifdef HAVE_EMMINTRIN_H
# include <emmintrin.h> // SSE2
#endif
#ifdef HAVE_PMMINTRIN_H
# include <tmmintrin.h> // SSE3
#endif
#ifdef HAVE_SMMINTRIN_H
# include <smmintrin.h> // SSE4.1
#endif
#ifdef HAVE_NMMINTRIN_H
# include <nmmintrin.h> // SSE4.2
#endif
#ifdef HAVE_IMMINTRIN_H
# include <immintrin.h> // AVX
#endif
#ifdef HAVE_STDINT_H
# include <stdint.h>
#endif
#ifdef WIN32
// Bulldozer AMD
// # include <x86intrin.h>
#endif
#ifdef __cplusplus
# include <iostream>
extern "C" {
#endif
/**
* \defgroup Other constants
* @{
*/
const __m128 _m_half_ps = _mm_set1_ps(0.5f);
const __m128 _m_m_half_ps = _mm_set1_ps(-0.5f);
const __m128 _m_one_ps = _mm_set1_ps(1.0f);
const __m128 _m_sixth_ps = _mm_set1_ps(0.166666666f);
const __m128i _m_one_si = _mm_set1_epi32(1);
// Consider moving these elsewhere (gives warning if non-static)
static const __m128 _m_m_one_ps = _mm_set1_ps(-1.0f);
static const __m128 _m_eps_ps = _mm_set1_ps(FLT_EPSILON);
const __m128d _m_half_pd = _mm_set1_pd(0.5);
const __m128d _m_one_pd = _mm_set1_pd(1.0);
static const __m128d _m_eps_pd = _mm_set1_pd(DBL_EPSILON);
static const __m256d _m256_m_one_pd = _mm256_set1_pd(-1.0);
static const __m256d _m256_one_pd = _mm256_set1_pd(1.0);
static const __m256d _m256_half_pd = _mm256_set1_pd(0.5);
/**@}*/
/**
* \defgroup Constants used by functions
* @{
*/
const ALIGN16_BEGIN int _clear_signmask[4] ALIGN16_END =
{0x7FFFFFFFL,0x7FFFFFFFL,0x7FFFFFFFL,0x7FFFFFFFL}; ///< clear sign mask for ps
const ALIGN16_BEGIN long long int _clear_signmaskd[2] ALIGN16_END =
{0x7FFFFFFFFFFFFFFF,0x7FFFFFFFFFFFFFFF}; ///< clear sign mask for pd
const ALIGN32_BEGIN long long int _clear_signmask_256[4] ALIGN32_END =
{0x7FFFFFFFFFFFFFFF,0x7FFFFFFFFFFFFFFF,0x7FFFFFFFFFFFFFFF,0x7FFFFFFFFFFFFFFF}; ///< clear sign mask for ps
#ifdef _WIN32
const __m128 signmask = _mm_castsi128_ps(_mm_set1_epi32(0x80000000L)); ///< signmask for ps (packed singles)
#elif defined(__GNUC__)
const __m128 signmask = _mm_castsi128_ps(_mm_set1_epi32(-2147483648)); ///< signmask for ps (packed singles)
#endif
const __m128 mantmask = _mm_castsi128_ps(_mm_set1_epi32(0x7FFFFFFFL)); ///< mantissa + exp mask for ps
const ALIGN16_BEGIN int _neg_signmask[4] ALIGN16_END =
{(int)0x80000000L,(int)0x80000000L,(int)0x80000000L,(int)0x80000000L}; ///< negative sign mask for ps
const ALIGN16_BEGIN long long int _neg_signmaskd[2] ALIGN16_END =
{(long long int)0x8000000000000000,(long long int)0x8000000000000000}; ///< negative sign mask for pd
const __m128i negmask = _mm_set1_epi32(-1); ///< negate mask 0xFFFFFFFF for epi32
const __m256i negmask_256 = _mm256_set_epi64x(-1,-1,-1,-1); ///< negate mask 0xFFFFFFFFFFFFFFFF for epi32
/**@}*/
#ifdef _MSC_VER
typedef union __declspec(intrin_type) _CRT_ALIGN(16) v4f {
__m128 v;
float f32[4];
uint64_t uint64[2];
int8_t int8[16];
int16_t int16[8];
int32_t int32[4];
int64_t int64[2];
uint8_t uint8[16];
uint16_t uint16[8];
uint32_t uint32[4];
v4f() {
v = _mm_setzero_ps();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v4f(const __m128& _v) {
v = _v;
}
v4f(const float& f3, const float& f2, const float& f1, const float& f0) {
f32[0] = f0;
f32[1] = f1;
f32[2] = f2;
f32[3] = f3;
}
///@}
} v4f;
typedef union __declspec(intrin_type) _CRT_ALIGN(16) v4i {
__m128i v;
float f32[4];
uint64_t uint64[2];
int8_t int8[16];
int16_t int16[8];
int32_t int32[4];
int64_t int64[2];
uint8_t uint8[16];
uint16_t uint16[8];
uint32_t uint32[4];
v4i() {
v = _mm_setzero_si128();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v4i(const __m128i& _v) {
v = _v;
}
v4i(const int& i3, const int& i2, const int& i1, const int& i0) {
int32[0] = i0;
int32[1] = i1;
int32[2] = i2;
int32[3] = i3;
}
///@}
} v4i;
typedef union __declspec(intrin_type)_CRT_ALIGN(32) v8f {
__m256 v;
float f32[8];
uint64_t uint64[4];
int8_t int8[32];
int16_t int16[16];
int32_t int32[8];
int64_t int64[4];
uint8_t uint8[32];
uint16_t uint16[16];
uint32_t uint32[8];
v8f() {
v = _mm256_setzero_ps();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v8f(const __m256 &_v) {
v = _v;
}
v8f(const float& f7, const float& f6, const float& f5, const float& f4,
const float& f3, const float& f2, const float& f1, const float& f0) {
f32[0] = f0;
f32[1] = f1;
f32[2] = f2;
f32[3] = f3;
f32[4] = f4;
f32[5] = f5;
f32[6] = f6;
f32[7] = f7;
}
///@}
} v8f;
typedef union __declspec(intrin_type)_CRT_ALIGN(32) v8i {
__m256i v;
float f32[8];
uint64_t uint64[4];
int8_t int8[32];
int16_t int16[16];
int32_t int32[8];
int64_t int64[4];
uint8_t uint8[32];
uint16_t uint16[16];
uint32_t uint32[8];
v8i() {
v = _mm256_setzero_si256();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v8i(const __m256i & _v) {
v = _v;
}
v8i(const int& i7, const int& i6, const int& i5, const int& i4,
const int& i3, const int& i2, const int& i1, const int& i0) {
int32[0] = i0;
int32[1] = i1;
int32[2] = i2;
int32[3] = i3;
int32[4] = i4;
int32[5] = i5;
int32[6] = i6;
int32[7] = i7;
}
///@}
} v8i;
typedef union __declspec(intrin_type) _CRT_ALIGN(32) v4d {
__m256d v;
double f64[4];
v4d() {
v = _mm256_setzero_pd();
}
v4d(const __m256d& _v) {
v = _v;
}
} v4d;
#else
typedef union v4f {
__m128 v;
float f32[4];
uint64_t uint64[2];
int8_t int8[16];
int16_t int16[8];
int32_t int32[4];
int64_t int64[2];
uint8_t uint8[16];
uint16_t uint16[8];
uint32_t uint32[4];
v4f() {
v = _mm_setzero_ps();
}
v4f(const __m128& _v) {
v = _v;
}
} v4f __attribute__ ((aligned (16)));
typedef union v4i {
__m128i v;
float f32[4];
uint64_t uint64[2];
int8_t int8[16];
int16_t int16[8];
int32_t int32[4];
int64_t int64[2];
uint8_t uint8[16];
uint16_t uint16[8];
uint32_t uint32[4];
v4i() {
v = _mm_setzero_si128();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v4i(const __m128i& _v) {
v = _v;
}
v4i(const int& i3, const int& i2, const int& i1, const int& i0) {
int32[0] = i0;
int32[1] = i1;
int32[2] = i2;
int32[3] = i3;
}
///@}
} v4i __attribute__ ((aligned (16)));
typedef union v4d {
__m256d v;
double f64[4];
v4d() {
v = _mm256_setzero_pd();
}
v4d(const __m256d& _v) {
v = _v;
}
} v4d __attribute__ ((aligned (32)));
typedef union v8f {
__m256 v;
float f32[8];
uint64_t uint64[4];
int8_t int8[32];
int16_t int16[16];
int32_t int32[8];
int64_t int64[4];
uint8_t uint8[32];
uint16_t uint16[16];
uint32_t uint32[8];
v8f() {
v = _mm256_setzero_ps();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v8f(const __m256 & _v) {
v = _v;
}
v8f(const float& f7, const float& f6, const float& f5, const float& f4,
const float& f3, const float& f2, const float& f1, const float& f0) {
f32[0] = f0;
f32[1] = f1;
f32[2] = f2;
f32[3] = f3;
f32[4] = f4;
f32[5] = f5;
f32[6] = f6;
f32[7] = f7;
}
///@}
} v8f __attribute__((aligned(32)));
typedef union v8i {
__m256i v;
float f32[8];
uint64_t uint64[4];
int8_t int8[32];
int16_t int16[16];
int32_t int32[8];
int64_t int64[4];
uint8_t uint8[32];
uint16_t uint16[16];
uint32_t uint32[8];
v8i() {
v = _mm256_setzero_si256();
}
/** @name Initializers useful for constant initializations
*
*/
///@{
v8i(const __m256i & _v) {
v = _v;
}
v8i(const int& i7, const int& i6, const int& i5, const int& i4,
const int& i3, const int& i2, const int& i1, const int& i0) {
int32[0] = i0;
int32[1] = i1;
int32[2] = i2;
int32[3] = i3;
int32[4] = i4;
int32[5] = i5;
int32[6] = i6;
int32[7] = i7;
}
///@}
} v8i __attribute__((aligned(32)));
#endif
/**
* Enable exceptions: default is to clear all exceptions and mask all exceptions, except INVALID and OVERFLOW.
*
* We stop on _MM_MASK_DIV_ZERO, _MM_MASK_UNDERFLOW, _MM_MASK_DENORM, _MM_MASK_INEXACT
*/
STATIC_INLINE_BEGIN void _mm_enable_exceptions(int mask = _MM_MASK_MASK & ~ (_MM_MASK_OVERFLOW|_MM_MASK_INVALID)) {
_mm_setcsr(mask);
// Disable denormals
// mask = mask | 0x8040;
#if 0
// the ICC compiler has a -ftz flag ==> flush to zero
//on GCC, the -ffast-math or -funsafe-math-optimizations flag includes flush to zero operation
// Ignore under-/overflow, div-zero, invalid
// _MM_SET_EXCEPTION_MASK(_MM_GET_EXCEPTION_MASK() & ~(_MM_MASK_INVALID | _MM_MASK_OVERFLOW | _MM_MASK_UNDERFLOW | _MM_MASK_DIV_ZERO));
#ifdef __SSE2__
// Avoid costly denormals FZ (flush to zero) & DAZ (denormals are zero) = 0x8040
#define AVOIDDENORMALS _mm_setcsr(_mm_getcsr() | 0x8040)
#else
#define AVOIDDENORMALS _mm_setcsr(_mm_getcsr() | 0x8000)
#endif
#endif
}
#ifdef __INTEL_COMPILER // icc doesn't support __nodebug__
#define vect_128_intrs_signt_attrs __attribute__((__always_inline__))
#elif defined(__GNUC__)
#define vect_128_intrs_signt_attrs __attribute__((__always_inline__))
#elif defined(_MSC_VER)
#define vect_128_intrs_signt_attrs
#else
#define vect_128_intrs_signt_attrs __attribute__((__always_inline__, __nodebug__))
#endif
#ifdef _MSC_VER
# define vect_128_intrs_signt(ret_t) static inline ret_t vect_128_intrs_signt_attrs
#else
# define vect_128_intrs_signt(ret_t) static __inline__ ret_t vect_128_intrs_signt_attrs
#endif
#define _mm_setbits_si128(a) _mm_cmpeq_epi32(a, a) // 1 cycle ...
vect_128_intrs_signt(__m128i) _mm_invert_si128(__m128i a) {
return _mm_xor_si128(a, _mm_setbits_si128(a)); // returns ~a, 2 cycles ...
}
vect_128_intrs_signt(__m128i) _mm_cmpge_epi32(__m128i a, __m128i b) { // 3 cycles ...
return _mm_invert_si128(_mm_cmplt_epi32(a, b)); // a >= b == ~(a < b)
}
vect_128_intrs_signt(__m128i) _mm_cmple_epi32(__m128i a, __m128i b) { // 3 cycles ...
return _mm_invert_si128(_mm_cmpgt_epi32(a, b)); // a <= b == ~(a > b)
}
STATIC_INLINE_BEGIN int _mm_movemask_epi32(__m128i a) {
return _mm_movemask_ps(_mm_castsi128_ps(a));
}
STATIC_INLINE_BEGIN __m256d _mm256_movehl_pd(__m256d a, __m256d b) {
return _mm256_castps_pd(_mm256_permute2f128_ps(_mm256_castpd_ps(a), _mm256_castpd_ps(b), 0x11 /*0x21*/));
}
STATIC_INLINE_BEGIN __m128 _mm_clamp_ps(__m128 value, __m128 low, __m128 high) {
return _mm_min_ps(high, _mm_max_ps(low, value));
}
#ifdef __GNUC__
#include <cstdint>
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wpedantic"
STATIC_INLINE_BEGIN int clz_u128 (unsigned __int128 u) {
#if 1
uint64_t hi = u>>64;
uint64_t lo = u;
int retval[3]= {
__builtin_clzll(hi),
__builtin_clzll(lo)+64,
128
};
int idx = !hi + ((!lo)&(!hi));
return retval[idx];
#else
uint64_t hi = u>>64;
uint64_t lo = u;
lo = (hi == 0) ? lo : -1ULL;
return _lzcnt_u64(hi) + _lzcnt_u64(lo);
#endif
}
#pragma GCC diagnostic pop
#endif
/**
* Multiply and accumulate
*
* @param x
* @param y
* @param z
*
* @return (x * y) + z
*/
STATIC_INLINE_BEGIN __m128 _mm_madd_ps(__m128 a, __m128 b, __m128 c) STATIC_INLINE_END;
STATIC_INLINE_BEGIN __m256d _mm256_rcp_pd(__m256d a) {
return _mm256_div_pd(_m256_one_pd, a);
}
STATIC_INLINE_BEGIN __m128 _mm_rcp_nz_ps(__m128 input) {
__m128 mask = _mm_cmpeq_ps(_mm_set1_ps(0.0f), input);
__m128 recip = _mm_rcp_ps(input);
return _mm_andnot_ps(mask, recip);
}
#ifndef _MSC_VER
/**
* 64-bit full multiplication and shift
*
* @param a
* @param b
* @param s
*
* @return
*/
STATIC_INLINE_BEGIN int64_t mulshift (int64_t a, int64_t b, int s) {
int64_t res;
__asm__ volatile ( // rax = a, rdx = b, ecx = s
"imulq %%rdx;\n\t" // rdx:rax = rax * rdx
"shrdq %%cl, %%rdx, %%rax;\n\t" // rax = int64_t (rdx:rax >> s)
"movq %%rax, %0;" // res = rax
: "=rm" (res)
: "a"(a), "d"(b), "c"(s));
return res;
}
#endif
/**
* Complex multiply, 2.5 instructions per multiplication instead of 6
*
* @param a
* @param b
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_mulcmplx_ps(const __m128 &a, const __m128 &b) STATIC_INLINE_END;
/**
* Test x==y for each packed single in a and b
*
* @param a
* @param b
*
* @return 1 if any of the packed floats are equal, else 0
*/
STATIC_INLINE_BEGIN int _mm_any_eq( __m128 a, __m128 b ) STATIC_INLINE_END;
/**
* More accurate reciprocal square root using Newton-Rhapson
*
* @param a
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_rsqrt_nr_ps(const __m128& a) STATIC_INLINE_END;
STATIC_INLINE_BEGIN __m128 _mm_rcp_nr_ps(const __m128& x) STATIC_INLINE_END;
STATIC_INLINE_BEGIN __m128 _mm_sqrt_zero_ps(const __m128& x) STATIC_INLINE_END;
STATIC_INLINE_BEGIN __m128 _mm_rcp_nr_ps(const __m128& x) {
__m128 res = _mm_rcp_ps(x);
__m128 muls = _mm_mul_ps(x, _mm_mul_ps(res, res));
return res = _mm_sub_ps(_mm_add_ps(res, res), muls);
}
// AVX-512 (HACK)
#if defined(_MSC_VER) && (_MSC_VER < 1914)
STATIC_INLINE_BEGIN __m256d _mm256_rcp14_pd(__m256d x) {
__m128 x1 = _mm256_cvtpd_ps(x);
x1 = _mm_rcp_ps(x1);
return _mm256_cvtps_pd(x1);
}
#endif
// SVML (Intel) provides _mm256_exp_pd in ia32intrin.h
#if !defined(INTEL_COMPILER) && !(defined(__clang__)) && !(defined(_MSC_VER) && (_MSC_VER >= 1914)) && !(defined(__GNUC__) && __GNUC__ > 7)
STATIC_INLINE_BEGIN double
_mm256_cvtsd_f64(__m256d d) {
// TODO: Keep input argument in register
v4d _d;
_d.v = d;
return _d.f64[0];
}
#endif
/**
* Absolute values of packed singles.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_fabs_ps(__m128 x) STATIC_INLINE_END;
/**
* Absolute values of packed doubles.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128d _mm_fabs_pd(__m128d x) STATIC_INLINE_END;
/**
* Absolute values of packed doubles.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m256d _mm256_fabs_pd(__m256d x) STATIC_INLINE_END;
#ifndef _INCLUDED_IMM
/**
* Floating point modulo of packed singles
*
* @param a
* @param aDiv
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_fmod_ps(const __m128& a, const __m128& aDiv) STATIC_INLINE_END;
STATIC_INLINE_BEGIN __m128 _mm_fmod_ps(const __m128& a, const __m128& aDiv) {
__m128 c = _mm_div_ps(a,aDiv);
__m128i i = _mm_cvttps_epi32(c);
__m128 cTrunc = _mm_cvtepi32_ps(i);
__m128 base = _mm_mul_ps(cTrunc, aDiv);
__m128 r = _mm_sub_ps(a, base);
return r;
}
#endif
#ifndef HAVE_SMMINTRIN_H
//SSE2: multiply 8 16-bit integers and return full 32-bit result in high and low result
STATIC_INLINE_BEGIN void _mm_mul_epi16_full(__m128i &hiResult, __m128i &loResult, const __m128i a, const __m128i b) {
__m128i hi = _mm_mulhi_epi16( a, b ); // (a7*b7[16:31],a6*b6[16:31],a5*b5[16:31],a4*b4[16:31],a3*b3[16:31],a2*b2[16:31],a1*b1[16:31],a0*b0[16:31])
__m128i low = _mm_mullo_epi16( a, b ); // (a7*b7[0:15] ,a6*b6[0:15] ,a5*b5[0:15] ,a4*b4[0:15],a3*b3[0:15] ,a2*b2[0:15] ,a1*b1[0:15] ,a0*b0[0:15])
loResult = _mm_unpacklo_epi16( hi, low ); // (a3*b3[0:15],a3*b3[16:31],a2*b2[0:15],a2*b2[16:31],a1*b1[0:15],a1*b1[16:31],a0*b0[0:15],a0*b0[16:31])
hiResult = _mm_unpackhi_epi16( hi, low ); // (a7*b7[0:15],a7*b7[16:31],a6*b6[0:15],a6*b6[16:31],a5*b5[0:15],a5*b5[16:31],a4*b4[0:15],a4*b4[16:31])
}
#endif
STATIC_INLINE_BEGIN void _mm_mul_epi32_full(__m128i &loResult, __m128i &hiResult, __m128i a, __m128i b) {
__m128i _a = _mm_castps_si128(_mm_permute_ps(_mm_castsi128_ps(a),0xB1));
__m128i _b = _mm_castps_si128(_mm_permute_ps(_mm_castsi128_ps(b),0xB1));
__m128i c1 = _mm_mul_epi32(a,b); // 0 and 2
__m128i c2 = _mm_mul_epi32(_a,_b); // 1 and 3
loResult = _mm_unpacklo_epi64(c1,c2);
hiResult = _mm_unpackhi_epi64(c1,c2);
}
STATIC_INLINE_BEGIN __m128 _mm_mulcmplx_ps(const __m128 &a, const __m128 &b) {
// 2.5 instructions instead of 6
const __m128 xmm4 = _mm_set_ps(1.0f,-1.0f,1.0f,-1.0f);
__m128 xmm2 = _mm_shuffle_ps(b,b, 0xA0 ); // c3a c3a c4a c4a
__m128 xmm1 = _mm_shuffle_ps(b,b, 0xF5);
__m128 xmm3 = _mm_shuffle_ps(a,a, 0xB1);
__m128 xmm0 = _mm_mul_ps(a,xmm2);
xmm3 = _mm_mul_ps(xmm1,xmm3);
xmm3 = _mm_mul_ps(xmm4,xmm3); // Replaced with FMA
xmm0 = _mm_add_ps(xmm0,xmm3);
return xmm0;
}
/**
* Horizontal AND values, 32-bit at a time. Result is placed in the
* least significant 32-bit integer.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128i _mm_hand_epi32(__m128i x) {
__m128i r = _mm_and_si128(x,_mm_srli_si128(x,8));
r = _mm_and_si128(r,_mm_srli_si128(r,4));
return r;
}
/**
* Horizontal OR values, 32-bit at a time. Result is placed in the
* least significant 32-bit integer.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128i _mm_hor_epi32(__m128i x) {
__m128i r = _mm_or_si128(x,_mm_srli_si128(x,8));
r = _mm_or_si128(r,_mm_srli_si128(r,4));
return r;
}
#if defined(NDEBUG) && !defined(_MSC_VER) && !defined(__clang__)
/**
* Right(logic)-shift packed singles
*
* @param x
* @param imm
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_srli_ps(__m128 x, const int imm) {
return _mm_castsi128_ps(_mm_srli_si128(_mm_castps_si128(x),imm));
}
#else
// 8-bit const immediates cannot be considered immediate when debugging
# define _mm_srli_ps(x,imm) \
_mm_castsi128_ps(_mm_srli_si128(_mm_castps_si128(x),imm))
#endif
#if defined(NDEBUG) && !defined(_MSC_VER) && !defined(__CYGWIN__) && !defined(__clang__)
/**
* Left-shift of packed singles
*
* @param x
* @param imm Number of bits (a constant immediate)
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_slli_ps(__m128 x, const int imm) {
return _mm_castsi128_ps(_mm_slli_si128(_mm_castps_si128(x),imm));
}
#else
// 8-bit const immediates cannot be considered immediate when debugging
# define _mm_slli_ps(x,imm) \
_mm_castsi128_ps(_mm_slli_si128(_mm_castps_si128(x),imm))
#endif
#if HAVE_SMMINTRIN_H
STATIC_INLINE_BEGIN int _mm_dp1_epi32(__m128i x, __m128i y) {
__m128i s = _mm_mullo_epi32(x,y);
s = _mm_add_epi32(s, _mm_srli_si128(s, 8));
s = _mm_add_epi32(s, _mm_srli_si128(s, 4));
int sum = _mm_cvtsi128_si32(s);
return sum;
}
STATIC_INLINE_BEGIN __m128i _mm_dp_epi32(__m128i x, __m128i y) {
__m128i s = _mm_mullo_epi32(x,y);
s = _mm_add_epi32(s, _mm_srli_si128(s, 8));
s = _mm_add_epi32(s, _mm_srli_si128(s, 4));
return s;
}
#endif
STATIC_INLINE_BEGIN __m128d _mm256_hsum_pd(__m256d x1, __m256d x2) {
// calculate 4 two-element horizontal sums:
// lower 64 bits contain x1[0] + x1[1]
// next 64 bits contain x2[0] + x2[1]
// next 64 bits contain x1[2] + x1[3]
// next 64 bits contain x2[2] + x2[3]
__m256d sum = _mm256_hadd_pd(x1, x2);
// extract upper 128 bits of result
__m128d sum_high = _mm256_extractf128_pd(sum, 1);
// add upper 128 bits of sum to its lower 128 bits
__m128d result = _mm_add_pd(sum_high, _mm256_castpd256_pd128(sum));
// lower 64 bits of result contain the sum of x1[0], x1[1], x1[2], x1[3]
// upper 64 bits of result contain the sum of x2[0], x2[1], x2[2], x2[3]
return result;
}
STATIC_INLINE_BEGIN __m256d _mm256_dp_pd(const __m256d& x, const __m256d& y, const int mask) STATIC_INLINE_END;
STATIC_INLINE_BEGIN __m256d _mm256_dp_pd(const __m256d& x, const __m256d& y, const int mask) {
// Without AVX-512 and __m256_cmp_epu32 a few casts are needed
const __m256i smask = _mm256_set_epi64x(0x80,0x40,0x20,0x10);
const __m256i omask = _mm256_set_epi64x(0x08,0x04,0x02,0x01);
const __m256i bum = _mm256_set1_epi64x(mask);
#ifdef HAVE_ZMMINTRIN_H
const __m256d selectMask = _mm256_cmp_pd(
_mm256_castsi256_pd(_mm256_and_si256(smask, bum)),
_mm256_castsi256_pd(smask),
_CMP_EQ_UQ);
const __m256d outputMask = _mm256_cmp_pd(
_mm256_castsi256_pd(_mm256_and_si256(omask, bum)),
_mm256_castsi256_pd(omask),
_CMP_EQ_UQ);
#else
// Without AVX-2 more casts are needed
const __m256d selectMask = _mm256_cmp_pd(
_mm256_castps_pd(_mm256_and_ps(_mm256_castsi256_ps(smask), _mm256_castsi256_ps(bum))),
_mm256_castsi256_pd(smask),
_CMP_EQ_UQ);
const __m256d outputMask = _mm256_cmp_pd(
_mm256_castps_pd(_mm256_and_ps(_mm256_castsi256_ps(omask), _mm256_castsi256_ps(bum))),
_mm256_castsi256_pd(omask),
_CMP_EQ_UQ);
#endif
__m256d xy = _mm256_mul_pd( x, y );
xy = _mm256_and_pd(xy,selectMask);
__m256d temp = _mm256_hadd_pd( xy, xy );
// Without AVX-512 and _mm256_permute2f128_pd, we need a few casts
__m256d temp_high_low = _mm256_castps_pd(_mm256_permute2f128_ps(_mm256_castpd_ps(temp), _mm256_castpd_ps(temp), 0x21));
__m256d r3 = _mm256_add_pd(temp, temp_high_low);
return _mm256_and_pd(r3,outputMask);
}
#if HAVE_SMMINTRIN_H
/*
SSE4.1 provides _mm_dp_ps.
Note 4 (4-vector) dot products using _mm_mul_ps and _mm_add_ps
takes 5 clock cycles (4 clock cycles using FMA). Using
_mm_dp_ps, it takes 4 clock cycles, 1 clock cycle for each dot
product.
*/
#else
/**
* Dot-product of packed singles
*
* @param __X
* @param __Y
* @param __M
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_dp_ps(__m128 __X, __m128 __Y, const int __M) {
# if HAVE_PMMINTRIN_H
const __m128 smask = _mm_set_epi32(0x80,0x40,0x20,0x10);
const __m128 omask = _mm_set_epi32(0x08,0x04,0x02,0x01);
// TODO: Need comparison to form mask
const __m128 selectMask = _mm_castsi128_ps(_mm_and_si128(smask,_mm_set1_epi32(__M)));
const __m128 outputMask = _mm_castsi128_ps(_mm_and_si128(omask,_mm_set1_epi32(__M)));
const r1 = _mm_mul_ps(__X, __Y);
const r1 = _mm_and_ps(r1,selectMask);
const r2 = _mm_hadd_ps(r1, r1);
const r3 = _mm_hadd_ps(r2, r2);
return _mm_and_ps(r3,outputMask);
# elif HAVE_EMMINTRIN_H
const __m128 smask = _mm_set_epi32(0x80,0x40,0x20,0x10);
const __m128 omask = _mm_set_epi32(0x08,0x04,0x02,0x01);
// TODO: Need comparison to form mask
const __m128 selectMask = _mm_castsi128_ps(_mm_and_si128(smask,_mm_set1_epi32(__M)));
const __m128 outputMask = _mm_castsi128_ps(_mm_and_si128(omask,_mm_set1_epi32(__M)));
const __m128 mult = _mm_mul_ps(a, b);
const __m128 shuf1 = _mm_shuffle_ps(mult, mult, _MM_SHUFFLE(0, 3, 2, 1));
const __m128 shuf2 = _mm_shuffle_ps(mult, mult, _MM_SHUFFLE(1, 0, 3, 2));
const __m128 shuf3 = _mm_shuffle_ps(mult, mult, _MM_SHUFFLE(2, 1, 0, 3));
return _mm_add_ps(_mm_add_ps(_mm_add_ps(mult, shuf1), shuf2), shuf3);
# else
# error Enable SSE2, SSE3 or SSE4
# endif
}
#endif
/*
__m256d xy = _mm256_mul_pd( x, y );
__m256d temp = _mm256_hadd_pd( xy, xy );
__m128d hi128 = _mm256_extractf128_pd( temp, 1 );
__m128d dotproduct = _mm_add_pd( (__m128d)temp, hi128 );
Edit:
After an idea of Norbert P. I extended this version to do 4 dot products at one time.
__m256d xy0 = _mm256_mul_pd( x[0], y[0] );
__m256d xy1 = _mm256_mul_pd( x[1], y[1] );
__m256d xy2 = _mm256_mul_pd( x[2], y[2] );
__m256d xy3 = _mm256_mul_pd( x[3], y[3] );
// low to high: xy00+xy01 xy10+xy11 xy02+xy03 xy12+xy13
__m256d temp01 = _mm256_hadd_pd( xy0, xy1 );
// low to high: xy20+xy21 xy30+xy31 xy22+xy23 xy32+xy33
__m256d temp23 = _mm256_hadd_pd( xy2, xy3 );
// low to high: xy02+xy03 xy12+xy13 xy20+xy21 xy30+xy31
__m256d swapped = _mm256_permute2f128_pd( temp01, temp23, 0x21 );
// low to high: xy00+xy01 xy10+xy11 xy22+xy23 xy32+xy33
__m256d blended = _mm256_blend_pd(temp01, temp23, 0b1100);
__m256d dotproduct = _mm256_add_pd( swapped, blended );
*/
/**
* Absolute value of packed singles
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_fabs_ps(__m128 x) {
// Same as _mm_set1_ps(-0.f);
return _mm_and_ps(x,_mm_load_ps((float *) _clear_signmask));
}
STATIC_INLINE_BEGIN __m128d _mm_fabs_pd(__m128d x) {
return _mm_and_pd(x,_mm_load_pd((double *) _clear_signmaskd));
}
STATIC_INLINE_BEGIN __m256d _mm256_fabs_pd(__m256d x) {
return _mm256_and_pd(x,_mm256_load_pd((double *) _clear_signmask_256));
}
/**
* Negate packed singles.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128 _mm_neg_ps(__m128 x) {
return _mm_xor_ps(x,_mm_load_ps((float *) _neg_signmask));
}
/**
* Negate packed doubles.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128d _mm_neg_pd(__m128d x) {
return _mm_xor_pd(x,_mm_load_pd((double *) _neg_signmaskd));
}
/**
* Negate packed integers.
*
* @param x
*
* @return
*/
STATIC_INLINE_BEGIN __m128i _mm_neg_epi32(__m128i x) {
return _mm_sub_epi32(_mm_setzero_si128(), x);
// or (x ^ 0xFFFFFFFF) + 1
}
/**
* Select packed floating point result based on mask.
*