The Removable Instruction Cache and Data Cache

[chenjie35335]

Before start

• I have read the RISC-V ISA Manual. 我已经阅读过 RISC-V 指令集手册。
• I have read the XiangShan Documents. 我已经阅读过香山文档。
• I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue，并没有找到相关的。
• I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions，并没有找到相关的。
• I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the feature you'd like

We find that there are two properties in the config of Xiangshan called 'HasICache' and 'HasDCache'. However, we find that two caches still exist in Xiangshan if we assign them false. Therefore, we propose to implement a removable instruction cache and data cache.

Additional context

No response

[Ma-YX]

Thanks for your question.

Currently, XiangShan does not support removable ICache and DCache. The HasICache and HasDCache you mentioned in XSCoreParameters are not actively used. As a result, setting these parameters false will not disable or remove ICache and DCache.

Additionally, XSCoreParameters defines default parameters of XiangShan. During compilation, some parameters are redefined in file Configs(located in folder top). To experiment with removing the DCache, you can try disabling WithNKBL1D in this file.

In the near future, we have no plans to implement this feature. If you're interested, you could explore implementing removable ICache and DCache functionality and submit a pull request to the XiangShan repository.