From a00c709ccf4ad1fc6531595065fd255e12a6a9c3 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 20 Aug 2023 05:19:39 -0700 Subject: [PATCH 1/2] fix RTL bugs before GL --- verilog/rtl/counter_timer_high.v | 17 ++++++++++++----- verilog/rtl/counter_timer_low.v | 17 ++++++++++++----- verilog/rtl/picosoc.v | 2 +- verilog/rtl/simple_spi_master.v | 9 ++++++++- 4 files changed, 33 insertions(+), 12 deletions(-) diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v index e13172e..2029492 100755 --- a/verilog/rtl/counter_timer_high.v +++ b/verilog/rtl/counter_timer_high.v @@ -168,10 +168,10 @@ always @(posedge clkin or negedge resetn) begin if (resetn == 1'b0) begin value_reset <= 32'd0; end else begin - if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24]; - if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16]; - if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8]; - if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0]; + if (reg_dat_we[3]) value_reset[31:24] <= reg_val_di[31:24]; + if (reg_dat_we[2]) value_reset[23:16] <= reg_val_di[23:16]; + if (reg_dat_we[1]) value_reset[15:8] <= reg_val_di[15:8]; + if (reg_dat_we[0]) value_reset[7:0] <= reg_val_di[7:0]; end end @@ -187,6 +187,13 @@ assign value_check_plus = (is_offset) ? value_cur_plus : value_cur; assign enable_out = enable; assign loc_enable = (chain == 1'b1) ? (enable && enable_in) : enable; +// stop_out delayed signal +reg stop_out_delayed; +always @(posedge clkin or negedge resetn) + if (resetn == 1'b0) + stop_out_delayed <= 0; + else: + stop_out_delayed <= stop_out; // When acting as the high 32 bit word of a 64-bit chained counter: // // It counts when the low 32-bit counter strobes (strobe == 1). @@ -210,7 +217,7 @@ always @(posedge clkin or negedge resetn) begin end else if (loc_enable == 1'b1) begin /* IRQ signals one cycle after stop, if IRQ is enabled */ /* IRQ lasts for one cycle only. */ - irq_out <= (irq_ena) ? (stop_out & ~irq_out) : 1'b0; + irq_out <= (irq_ena) ? (stop_out & ~stop_out_delayed & ~irq_out) : 1'b0; if (updown == 1'b1) begin if (lastenable == 1'b0) begin diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v index 06ed5d1..3596869 100755 --- a/verilog/rtl/counter_timer_low.v +++ b/verilog/rtl/counter_timer_low.v @@ -171,10 +171,10 @@ always @(posedge clkin or negedge resetn) begin if (resetn == 1'b0) begin value_reset <= 32'd0; end else begin - if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24]; - if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16]; - if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8]; - if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0]; + if (reg_dat_we[3]) value_reset[31:24] <= reg_val_di[31:24]; + if (reg_dat_we[2]) value_reset[23:16] <= reg_val_di[23:16]; + if (reg_dat_we[1]) value_reset[15:8] <= reg_val_di[15:8]; + if (reg_dat_we[0]) value_reset[7:0] <= reg_val_di[7:0]; end end @@ -195,6 +195,13 @@ assign enable_out = enable; assign is_offset = ((updown == 1'b1) && (value_reset == 0)); +// stop_out delayed signal +reg stop_out_delayed; +always @(posedge clkin or negedge resetn) + if (resetn == 1'b0) + stop_out_delayed <= 0; + else: + stop_out_delayed <= stop_out; // When acting as low 32-bit word of a 64-bit chained counter: // It sets the output strobe on the stop condition, one cycle early. // It stops on the stop condition if "stop_in" is high. @@ -218,7 +225,7 @@ always @(posedge clkin or negedge resetn) begin end else if (loc_enable == 1'b1) begin /* IRQ signals one cycle after stop_out, if IRQ is enabled */ /* IRQ lasts for one clock cycle only. */ - irq_out <= (irq_ena) ? (stop_out & ~irq_out) : 1'b0; + irq_out <= (irq_ena) ? (stop_out & ~stop_out_delayed & ~irq_out) : 1'b0; if (updown == 1'b1) begin if (lastenable == 1'b0) begin diff --git a/verilog/rtl/picosoc.v b/verilog/rtl/picosoc.v index 26e0d98..b2c4b5c 100644 --- a/verilog/rtl/picosoc.v +++ b/verilog/rtl/picosoc.v @@ -132,7 +132,7 @@ module picosoc ( /* PicoRV32 configuration */ parameter [31:0] STACKADDR = (4*(`MEM_WORDS)); // end of memory parameter [31:0] PROGADDR_RESET = 32'h 1000_0000; - parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000; + parameter [31:0] PROGADDR_IRQ = 32'h 1000_0010; // Wishbone base addresses parameter RAM_BASE_ADR = 32'h0000_0000; diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v index 4a708fe..ff4cb80 100755 --- a/verilog/rtl/simple_spi_master.v +++ b/verilog/rtl/simple_spi_master.v @@ -181,6 +181,7 @@ module simple_spi_master ( parameter FINISH = 2'b11; reg done; + reg done_delayed; reg isdo, hsck, icsb; reg [1:0] state; reg isck; @@ -216,7 +217,7 @@ module simple_spi_master ( assign sdoenb = icsb; assign sdo = isdo; - assign irq_out = irqena & done; + assign irq_out = irqena & done & ~done_delayed; assign hk_connect = (enable == 1'b1) ? hkconn : 1'b0; assign spi_enabled = enable; @@ -226,6 +227,12 @@ module simple_spi_master ( assign reg_dat_wait = ~done; assign reg_dat_do = done ? rreg : ~0; + always @(posedge clk or negedge resetn) + if (resetn == 1'b0) + done_delayed <= 0; + else + done_delayed <= done; + // Write configuration register always @(posedge clk or negedge resetn) begin if (resetn == 1'b0) begin From 5e426be7eda98a63bb3627f14b62e271105cc308 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 27 Aug 2023 00:40:54 -0700 Subject: [PATCH 2/2] revert changes to the timer reset_value setter --- verilog/rtl/counter_timer_high.v | 8 ++++---- verilog/rtl/counter_timer_low.v | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v index 2029492..1a8ee3e 100755 --- a/verilog/rtl/counter_timer_high.v +++ b/verilog/rtl/counter_timer_high.v @@ -168,10 +168,10 @@ always @(posedge clkin or negedge resetn) begin if (resetn == 1'b0) begin value_reset <= 32'd0; end else begin - if (reg_dat_we[3]) value_reset[31:24] <= reg_val_di[31:24]; - if (reg_dat_we[2]) value_reset[23:16] <= reg_val_di[23:16]; - if (reg_dat_we[1]) value_reset[15:8] <= reg_val_di[15:8]; - if (reg_dat_we[0]) value_reset[7:0] <= reg_val_di[7:0]; + if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24]; + if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16]; + if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8]; + if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0]; end end diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v index 3596869..c250baf 100755 --- a/verilog/rtl/counter_timer_low.v +++ b/verilog/rtl/counter_timer_low.v @@ -171,10 +171,10 @@ always @(posedge clkin or negedge resetn) begin if (resetn == 1'b0) begin value_reset <= 32'd0; end else begin - if (reg_dat_we[3]) value_reset[31:24] <= reg_val_di[31:24]; - if (reg_dat_we[2]) value_reset[23:16] <= reg_val_di[23:16]; - if (reg_dat_we[1]) value_reset[15:8] <= reg_val_di[15:8]; - if (reg_dat_we[0]) value_reset[7:0] <= reg_val_di[7:0]; + if (reg_val_we[3]) value_reset[31:24] <= reg_val_di[31:24]; + if (reg_val_we[2]) value_reset[23:16] <= reg_val_di[23:16]; + if (reg_val_we[1]) value_reset[15:8] <= reg_val_di[15:8]; + if (reg_val_we[0]) value_reset[7:0] <= reg_val_di[7:0]; end end