From 650c0669fa3994ccbbe4f199c10732e535e17df8 Mon Sep 17 00:00:00 2001 From: Tim Edwards Date: Mon, 28 Aug 2023 10:36:17 -0400 Subject: [PATCH] Fixed two syntax errors per PR #20 from Mostafa Rady (except that the pull request contains too many other changes, so I'm just doing this one by hand). --- verilog/rtl/counter_timer_high.v | 2 +- verilog/rtl/counter_timer_low.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/rtl/counter_timer_high.v b/verilog/rtl/counter_timer_high.v index 1a8ee3e..0ca0b22 100755 --- a/verilog/rtl/counter_timer_high.v +++ b/verilog/rtl/counter_timer_high.v @@ -192,7 +192,7 @@ reg stop_out_delayed; always @(posedge clkin or negedge resetn) if (resetn == 1'b0) stop_out_delayed <= 0; - else: + else stop_out_delayed <= stop_out; // When acting as the high 32 bit word of a 64-bit chained counter: // diff --git a/verilog/rtl/counter_timer_low.v b/verilog/rtl/counter_timer_low.v index c250baf..cf7f206 100755 --- a/verilog/rtl/counter_timer_low.v +++ b/verilog/rtl/counter_timer_low.v @@ -200,7 +200,7 @@ reg stop_out_delayed; always @(posedge clkin or negedge resetn) if (resetn == 1'b0) stop_out_delayed <= 0; - else: + else stop_out_delayed <= stop_out; // When acting as low 32-bit word of a 64-bit chained counter: // It sets the output strobe on the stop condition, one cycle early.