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Copy pathBrent Kung Adder
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Brent Kung Adder
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Verilog code:
module BrentKungAdder (
input [3:0] A, B,
output reg [3:0] sum,c);
wire [3:0] P, G;
reg [2:0] C;
assign P = A ^ B;
assign G = A & B;
always @* begin
C[0] = G[0];
C[1] = G[1] | (P[1] & G[0]);
C[2] = G[2] | (P[2] & (G[1] | (P[1] & G[0])));
c=C[2];
sum[0] = P[0];
sum[1] = P[1] ^ C[0];
sum[2] = P[2] ^ C[1];
sum[3] = P[3] ^ C[2];
end
endmodule
Testbench code:
module bk4();
reg [3:0]A,B;
wire [3:0]sum,c;
BrentKungAdder UUT(
.A(A),
.B(B),
.sum(sum),
.c(c));
initial begin
// Test case 1: A = 6, B = 5 (0110 + 0101 = 1011)
A = 4'b0110;
B = 4'b0101;
#10; // Wait for some time for the output to stabilize
$display("A = %b, B = %b, Sum = %b", A, B, sum);
// Test case 2: A = 9, B = 3 (1001 + 0011 = 1100)
A = 4'b1001;
B = 4'b0011;
#10;
$display("A = %b, B = %b, Sum = %b", A, B, sum);
A = 4'b1101;
B = 4'b1011;
#10;
$finish;
end
endmodule