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Copy pathCarry look ahead Adder
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Carry look ahead Adder
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verilog code:
module full_adder (
input a,
input b,
input cin,
output sum,
output cout);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
module cla_adder_4bit (
input [3:0] a,
input [3:0] b,
output [3:0] sum,
output cout);
wire [3:0] generae, propagate;
wire [4:0] carry;
// Generate and propagate signals for each bit
assign generae[0] = a[0] & b[0];
assign propagate[0] = a[0] | b[0];
assign generae[1] = a[1] & b[1] | generae[0];
assign propagate[1] = a[1] | b[1];
assign generae[2] = a[2] & b[2] | generae[1];
assign propagate[2] = a[2] | b[2];
assign generae[3] = a[3] & b[3] | generae[2];
assign propagate[3] = a[3] | b[3];
// Full adder instances
full_adder fa0(.a(a[0]), .b(b[0]), .cin(1'b0), .sum(sum[0]), .cout(carry[1]));
full_adder fa1(.a(a[1]), .b(b[1]), .cin(carry[1]), .sum(sum[1]), .cout(carry[2]));
full_adder fa2(.a(a[2]), .b(b[2]), .cin(carry[2]), .sum(sum[2]), .cout(carry[3]));
full_adder fa3(.a(a[3]), .b(b[3]), .cin(carry[3]), .sum(sum[3]), .cout(cout));
endmodule
Testbench code:
module test_bench();
reg [3:0] a;
reg [3:0] b;
wire [3:0] sum;
wire cout;
// Instantiate the cla_adder_4bit module
cla_adder_4bit dut(
.a(a),
.b(b),
.sum(sum),
.cout(cout)
);
initial begin
// Test case 1: a=3, b=5
a = 4'b0011;
b = 4'b0101;
#10;
// Test case 2: a=7, b=9
a = 4'b0111;
b = 4'b1001;
#10;
$stop;
end
endmodule