diff --git a/NXP.FRDM-MCXN947_BSP.pdsc b/NXP.FRDM-MCXN947_BSP.pdsc
index 4ea4811..5e6851e 100644
--- a/NXP.FRDM-MCXN947_BSP.pdsc
+++ b/NXP.FRDM-MCXN947_BSP.pdsc
@@ -1705,7 +1705,6 @@
-
The Blinky example that shows the integration with the MCUXpresso Config Tools.
@@ -1748,6 +1747,9 @@
Single-core project without TrustZone using MCUXpresso Config Tools
+
+ Single-core project with RAM and ROM targets, no TrustZone, MCUXpresso Config Tools
+
Single-core project with TrustZone
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/ConfigTools.cgen.yml b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/ConfigTools.cgen.yml
new file mode 100644
index 0000000..990dc2f
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/ConfigTools.cgen.yml
@@ -0,0 +1,12 @@
+generator-import:
+ generated-by: 'MCUXpresso config tools Generated: 16/10/2024 15:42:42'
+ for-device: MCXN947
+ groups:
+ - group: ConfigTools board
+ files:
+ - file: board/clock_config.c
+ - file: board/clock_config.h
+ - file: board/peripherals.c
+ - file: board/peripherals.h
+ - file: board/pin_mux.c
+ - file: board/pin_mux.h
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/MCXN947.mex b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/MCXN947.mex
new file mode 100644
index 0000000..65684fc
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/MCXN947.mex
@@ -0,0 +1,176 @@
+
+
+
+ MCXN947
+ MCXN947VDF
+ ksdk2_0
+
+
+
+
+ Configuration for MCXN947
+
+
+ true
+ false
+ false
+ true
+ false
+
+
+
+
+
+
+
+
+ 16.3.0
+
+
+
+
+
+ true
+ cm33_core0
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16.3.0
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+
+
+
+
+
+
+ N/A
+
+
+
+
+
+
+
+
+
+ 16.3.0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ N/A
+
+
+
+
\ No newline at end of file
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/clock_config.c b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/clock_config.c
new file mode 100644
index 0000000..f231875
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/clock_config.c
@@ -0,0 +1,128 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Set up wait states of the flash.
+ *
+ * 3. Set up all dividers.
+ *
+ * 4. Set up all selectors to provide selected clocks.
+ *
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v14.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 16.3.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_clock.h"
+#include "clock_config.h"
+#include "fsl_spc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: CLK_144M_clock.outFreq, value: 144 MHz}
+- {id: CLK_48M_clock.outFreq, value: 48 MHz}
+- {id: FREQME_reference_clock.outFreq, value: 144 MHz}
+- {id: FREQME_target_clock.outFreq, value: 144 MHz}
+- {id: FRO_12M_clock.outFreq, value: 12 MHz}
+- {id: FRO_HF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: Slow_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+- {id: gdet_clock.outFreq, value: 48 MHz}
+- {id: trng_clock.outFreq, value: 48 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ CLOCK_EnableClock(kCLOCK_Scg); /*!< Enable SCG clock */
+
+ /* FRO OSC setup - begin, attach FRO12M to MainClock for safety switching */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12M first to ensure we can change the clock setting */
+
+ /* Set the LDO_CORE VDD regulator to 1.0 V voltage level */
+ spc_active_mode_core_ldo_option_t ldoOpt = {
+ .CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage,
+ .CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
+ };
+ SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOpt);
+ /* Set the DCDC VDD regulator to 1.0 V voltage level */
+ spc_active_mode_dcdc_option_t dcdcOpt = {
+ .DCDCVoltage = kSPC_DCDC_MidVoltage,
+ .DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
+ };
+ SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &dcdcOpt);
+ /* Configure Flash wait-states to support 1V voltage level and 48000000Hz frequency */;
+ FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x1U));
+ /* Specifies the 1V operating voltage for the SRAM's read/write timing margin */
+ spc_sram_voltage_config_t sramCfg = {
+ .operateVoltage = kSPC_sramOperateAt1P0V,
+ .requestVoltageUpdate = true,
+ };
+ SPC_SetSRAMOperateVoltage(SPC0, &sramCfg);
+
+ CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
+
+ /* Configure FREQME clock */
+ SYSCON->CLOCK_CTRL |=
+ SYSCON_CLOCK_CTRL_FRO_HF_ENA_MASK | SYSCON_CLOCK_CTRL_FRO12MHZ_ENA_MASK |
+ SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK; /* Enable FRO 1M, 12M and HF to frequency measure module */
+ CLOCK_EnableClock(kCLOCK_InputMux);
+ INPUTMUX->FREQMEAS_REF = INPUTMUX_FREQMEAS_REF_INP(2);
+ INPUTMUX->FREQMEAS_TAR = INPUTMUX_FREQMEAS_REF_INP(2);
+
+ /*!< Set up clock selectors */
+ CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK);
+ CLOCK_AttachClk(kFRO_HF_to_FLEXSPI); /*!< Switch FLEXSPI to FRO_HF */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
+
+ /* Set SystemCoreClock variable */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/clock_config.h b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/clock_config.h
new file mode 100644
index 0000000..721f02f
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/clock_config.h
@@ -0,0 +1,155 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
+#define BOARD_BOOTCLOCKRUN_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
+
+/* Clock outputs (values are in Hz): */
+#define BOARD_BOOTCLOCKRUN_ADC0_CLOCK 0UL /* Clock consumers of ADC0_clock output : ADC0 */
+#define BOARD_BOOTCLOCKRUN_ADC1_CLOCK 0UL /* Clock consumers of ADC1_clock output : ADC1 */
+#define BOARD_BOOTCLOCKRUN_CLK16K0_TOVBAT_CLOCK 0UL /* Clock consumers of CLK16K0_toVBAT_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK16K1_TOVSYS_CLOCK 0UL /* Clock consumers of CLK16K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
+#define BOARD_BOOTCLOCKRUN_CLK16K2_TOWAKE_CLOCK 0UL /* Clock consumers of CLK16K2_toWAKE_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK16K3_TOMAIN_CLOCK 0UL /* Clock consumers of CLK16K3_toMAIN_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLKOUT_CLOCK 0UL /* Clock consumers of CLKOUT_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_144M_CLOCK 144000000UL /* Clock consumers of CLK_144M_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_1M_CLOCK 0UL /* Clock consumers of CLK_1M_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_48M_CLOCK 48000000UL /* Clock consumers of CLK_48M_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_CLK_IN_CLOCK 0UL /* Clock consumers of CLK_IN_clock output : LPTMR0, LPTMR1 */
+#define BOARD_BOOTCLOCKRUN_CMP0FDIV_CLOCK 0UL /* Clock consumers of CMP0FDIV_clock output : CMP0 */
+#define BOARD_BOOTCLOCKRUN_CMP0RRDIV_CLOCK 0UL /* Clock consumers of CMP0RRDIV_clock output : CMP0 */
+#define BOARD_BOOTCLOCKRUN_CMP1FDIV_CLOCK 0UL /* Clock consumers of CMP1FDIV_clock output : CMP1 */
+#define BOARD_BOOTCLOCKRUN_CMP1RRDIV_CLOCK 0UL /* Clock consumers of CMP1RRDIV_clock output : CMP1 */
+#define BOARD_BOOTCLOCKRUN_CMP2FDIV_CLOCK 0UL /* Clock consumers of CMP2FDIV_clock output : CMP2 */
+#define BOARD_BOOTCLOCKRUN_CMP2RRDIV_CLOCK 0UL /* Clock consumers of CMP2RRDIV_clock output : CMP2 */
+#define BOARD_BOOTCLOCKRUN_CTIMER0_CLOCK 0UL /* Clock consumers of CTIMER0_clock output : CTIMER0 */
+#define BOARD_BOOTCLOCKRUN_CTIMER1_CLOCK 0UL /* Clock consumers of CTIMER1_clock output : CTIMER1 */
+#define BOARD_BOOTCLOCKRUN_CTIMER2_CLOCK 0UL /* Clock consumers of CTIMER2_clock output : CTIMER2 */
+#define BOARD_BOOTCLOCKRUN_CTIMER3_CLOCK 0UL /* Clock consumers of CTIMER3_clock output : CTIMER3 */
+#define BOARD_BOOTCLOCKRUN_CTIMER4_CLOCK 0UL /* Clock consumers of CTIMER4_clock output : CTIMER4 */
+#define BOARD_BOOTCLOCKRUN_DAC0_CLOCK 0UL /* Clock consumers of DAC0_clock output : DAC0 */
+#define BOARD_BOOTCLOCKRUN_DAC1_CLOCK 0UL /* Clock consumers of DAC1_clock output : DAC1 */
+#define BOARD_BOOTCLOCKRUN_DAC2_CLOCK 0UL /* Clock consumers of DAC2_clock output : DAC2 */
+#define BOARD_BOOTCLOCKRUN_EMVSIM0_CLOCK 0UL /* Clock consumers of EMVSIM0_clock output : EMVSIM0 */
+#define BOARD_BOOTCLOCKRUN_EMVSIM1_CLOCK 0UL /* Clock consumers of EMVSIM1_clock output : EMVSIM1 */
+#define BOARD_BOOTCLOCKRUN_ENETPTPREFCLK_CLOCK 0UL /* Clock consumers of ENETPTPREFCLK_clock output : ENET0 */
+#define BOARD_BOOTCLOCKRUN_ENETRMII_CLOCK 0UL /* Clock consumers of ENETRMII_clock output : ENET0 */
+#define BOARD_BOOTCLOCKRUN_EWM_CLOCK 0UL /* Clock consumers of EWM_clock output : EWM0 */
+#define BOARD_BOOTCLOCKRUN_FLEXCAN0_CLOCK 0UL /* Clock consumers of FLEXCAN0_clock output : CAN0 */
+#define BOARD_BOOTCLOCKRUN_FLEXCAN1_CLOCK 0UL /* Clock consumers of FLEXCAN1_clock output : CAN1 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM0_CLOCK 0UL /* Clock consumers of FLEXCOMM0_clock output : LPI2C0, LPSPI0, LPUART0, LP_FLEXCOMM0 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM1_CLOCK 0UL /* Clock consumers of FLEXCOMM1_clock output : LPI2C1, LPSPI1, LPUART1, LP_FLEXCOMM1 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM2_CLOCK 0UL /* Clock consumers of FLEXCOMM2_clock output : LPI2C2, LPSPI2, LPUART2, LP_FLEXCOMM2 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM3_CLOCK 0UL /* Clock consumers of FLEXCOMM3_clock output : LPI2C3, LPSPI3, LPUART3, LP_FLEXCOMM3 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM4_CLOCK 0UL /* Clock consumers of FLEXCOMM4_clock output : LPI2C4, LPSPI4, LPUART4, LP_FLEXCOMM4 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM5_CLOCK 0UL /* Clock consumers of FLEXCOMM5_clock output : LPI2C5, LPSPI5, LPUART5, LP_FLEXCOMM5 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM6_CLOCK 0UL /* Clock consumers of FLEXCOMM6_clock output : LPI2C6, LPSPI6, LPUART6, LP_FLEXCOMM6 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM7_CLOCK 0UL /* Clock consumers of FLEXCOMM7_clock output : LPI2C7, LPSPI7, LPUART7, LP_FLEXCOMM7 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM8_CLOCK 0UL /* Clock consumers of FLEXCOMM8_clock output : LPI2C8, LPSPI8, LPUART8, LP_FLEXCOMM8 */
+#define BOARD_BOOTCLOCKRUN_FLEXCOMM9_CLOCK 0UL /* Clock consumers of FLEXCOMM9_clock output : LPI2C9, LPSPI9, LPUART9, LP_FLEXCOMM9 */
+#define BOARD_BOOTCLOCKRUN_FLEXIO_CLOCK 0UL /* Clock consumers of FLEXIO_clock output : FLEXIO0 */
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLOCK 0UL /* Clock consumers of FLEXSPI_clock output : FLEXSPI0 */
+#define BOARD_BOOTCLOCKRUN_FREQME_REFERENCE_CLOCK 144000000UL /* Clock consumers of FREQME_reference_clock output : FREQME0 */
+#define BOARD_BOOTCLOCKRUN_FREQME_TARGET_CLOCK 144000000UL /* Clock consumers of FREQME_target_clock output : FREQME0 */
+#define BOARD_BOOTCLOCKRUN_FRO_12M_CLOCK 12000000UL /* Clock consumers of FRO_12M_clock output : LPTMR0, LPTMR1 */
+#define BOARD_BOOTCLOCKRUN_FRO_HF_DIV_CLOCK 0UL /* Clock consumers of FRO_HF_DIV_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_FRO_HF_CLOCK 48000000UL /* Clock consumers of FRO_HF_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_I3C0_FCLK_CLOCK 0UL /* Clock consumers of I3C0_FCLK_clock output : I3C0 */
+#define BOARD_BOOTCLOCKRUN_I3C0_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C0_SLOW_TC_clock output : I3C0 */
+#define BOARD_BOOTCLOCKRUN_I3C0_SLOW_CLOCK 0UL /* Clock consumers of I3C0_SLOW_clock output : I3C0 */
+#define BOARD_BOOTCLOCKRUN_I3C1_FCLK_CLOCK 0UL /* Clock consumers of I3C1_FCLK_clock output : I3C1 */
+#define BOARD_BOOTCLOCKRUN_I3C1_SLOW_TC_CLOCK 0UL /* Clock consumers of I3C1_SLOW_TC_clock output : I3C1 */
+#define BOARD_BOOTCLOCKRUN_I3C1_SLOW_CLOCK 0UL /* Clock consumers of I3C1_SLOW_clock output : I3C1 */
+#define BOARD_BOOTCLOCKRUN_LP_OSC_CLOCK 0UL /* Clock consumers of LP_OSC_clock output : RTC0, TDET0, WUU0 */
+#define BOARD_BOOTCLOCKRUN_MAIN_CLOCK 48000000UL /* Clock consumers of MAIN_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_MICFILFCLK_CLOCK 0UL /* Clock consumers of MICFILFCLK_clock output : PDM */
+#define BOARD_BOOTCLOCKRUN_OSTIMER_CLOCK 0UL /* Clock consumers of OSTIMER_clock output : OSTIMER0 */
+#define BOARD_BOOTCLOCKRUN_PLL0_CLK_CLOCK 0UL /* Clock consumers of PLL0_CLK_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL1_CLK_CLOCK 0UL /* Clock consumers of PLL1_CLK_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL_DIV_CLOCK 0UL /* Clock consumers of PLL_DIV_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLUCLKIN_CLOCK 0UL /* Clock consumers of PLUCLKIN_clock output : PLU0 */
+#define BOARD_BOOTCLOCKRUN_PLU_GLITCH_12MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_12MHz_clock output : PLU0 */
+#define BOARD_BOOTCLOCKRUN_PLU_GLITCH_1MHZ_CLOCK 0UL /* Clock consumers of PLU_GLITCH_1MHz_clock output : PLU0 */
+#define BOARD_BOOTCLOCKRUN_SAI0_CLOCK 0UL /* Clock consumers of SAI0_clock output : SAI0 */
+#define BOARD_BOOTCLOCKRUN_SAI1_CLOCK 0UL /* Clock consumers of SAI1_clock output : SAI1 */
+#define BOARD_BOOTCLOCKRUN_FIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.FIRC_TRIM_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_SIRC_TRIM_CLOCK 0UL /* Clock consumers of SCG.SIRC_TRIM_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_SCT_CLOCK 0UL /* Clock consumers of SCT_clock output : SCT0 */
+#define BOARD_BOOTCLOCKRUN_SINCFILT_CLOCK 0UL /* Clock consumers of SINCFILT_clock output : SINC0 */
+#define BOARD_BOOTCLOCKRUN_SYSTICK0_CLOCK 0UL /* Clock consumers of SYSTICK0_clock output : SysTick0 */
+#define BOARD_BOOTCLOCKRUN_SYSTICK1_CLOCK 0UL /* Clock consumers of SYSTICK1_clock output : SysTick1 */
+#define BOARD_BOOTCLOCKRUN_SLOW_CLOCK 12000000UL /* Clock consumers of Slow_clock output : CMC0, CMP0, CMP1, GPIO5, LPTMR0, LPTMR1, PORT5, RTC0, SPC0, TDET0, TSI0 */
+#define BOARD_BOOTCLOCKRUN_SYSTEM_CLOCK 48000000UL /* Clock consumers of System_clock output : ADC0, ADC1, CACHE64_CTRL0, CACHE64_POLSEL0, CAN0, CAN1, CMP2, CMX_PERFMON0, CMX_PERFMON1, CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4, DAC0, DAC1, DAC2, DMA0, DMA1, EMVSIM0, EMVSIM1, ENET0, EVTG0, EWM0, FLEXIO0, FLEXSPI0, FREQME0, GDET0, GDET1, GPIO0, GPIO0_ALIAS1, GPIO1, GPIO1_ALIAS1, GPIO2, GPIO2_ALIAS1, GPIO3, GPIO3_ALIAS1, GPIO4, GPIO4_ALIAS1, GPIO5_ALIAS1, I3C0, I3C1, INTM0, LPI2C0, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6, LPI2C7, LPI2C8, LPI2C9, LPSPI0, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6, LPSPI7, LPSPI8, LPSPI9, LPUART0, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LP_FLEXCOMM0, LP_FLEXCOMM1, LP_FLEXCOMM2, LP_FLEXCOMM3, LP_FLEXCOMM4, LP_FLEXCOMM5, LP_FLEXCOMM6, LP_FLEXCOMM7, LP_FLEXCOMM8, LP_FLEXCOMM9, MAILBOX, MRT0, OSTIMER0, PDM, PLU0, PORT0, PORT1, PORT2, PORT3, PORT4, POWERQUAD, PUF, PUF_ALIAS1, PUF_ALIAS2, PUF_ALIAS3, PWM0, PWM1, QDC0, QDC1, SAI0, SAI1, SCT0, SINC0, SWD, SysTick0, SysTick1, USBFS0, USBHS1_PHY_DCD, USDHC0, UTICK0, WUU0, WWDT0, WWDT1 */
+#define BOARD_BOOTCLOCKRUN_TRACE_CLOCK 0UL /* Clock consumers of TRACE_clock output : SWD */
+#define BOARD_BOOTCLOCKRUN_TSI_CLOCK 0UL /* Clock consumers of TSI_clock output : TSI0 */
+#define BOARD_BOOTCLOCKRUN_USB_HSPLL_CLOCK 0UL /* Clock consumers of USB_HSPLL_clock output : USBHS1_PHY_DCD */
+#define BOARD_BOOTCLOCKRUN_USB_PLL_CLOCK 0UL /* Clock consumers of USB_PLL_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_USB_CLOCK 0UL /* Clock consumers of USB_clock output : USBFS0 */
+#define BOARD_BOOTCLOCKRUN_UTICK_CLOCK 0UL /* Clock consumers of UTICK_clock output : UTICK0 */
+#define BOARD_BOOTCLOCKRUN_WDT0_CLOCK 0UL /* Clock consumers of WDT0_clock output : WWDT0 */
+#define BOARD_BOOTCLOCKRUN_WDT1_CLOCK 0UL /* Clock consumers of WDT1_clock output : WWDT1 */
+#define BOARD_BOOTCLOCKRUN_XTAL32K0_TOVBAT_CLOCK 0UL /* Clock consumers of XTAL32K0_toVBAT_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_XTAL32K1_TOVSYS_CLOCK 0UL /* Clock consumers of XTAL32K1_toVSYS_clock output : CMP0, CMP1, CMP2, LPTMR0, LPTMR1 */
+#define BOARD_BOOTCLOCKRUN_XTAL32K2_TOWAKE_CLOCK 0UL /* Clock consumers of XTAL32K2_toWAKE_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_XTAL32K3_TOMAIN_CLOCK 0UL /* Clock consumers of XTAL32K3_toMAIN_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_GDET_CLOCK 48000000UL /* Clock consumers of gdet_clock output : GDET0, GDET1 */
+#define BOARD_BOOTCLOCKRUN_PLL1_CLK0_CLOCK 0UL /* Clock consumers of pll1_clk0_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_PLL1_CLK1_CLOCK 0UL /* Clock consumers of pll1_clk1_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_TRNG_CLOCK 48000000UL /* Clock consumers of trng_clock output : N/A */
+#define BOARD_BOOTCLOCKRUN_USDHC_CLOCK 0UL /* Clock consumers of uSDHC_clock output : USDHC0 */
+
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/peripherals.c b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/peripherals.c
new file mode 100644
index 0000000..8937a06
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/peripherals.c
@@ -0,0 +1,94 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v15.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 16.3.0
+functionalGroups:
+- name: BOARD_InitPeripherals
+ UUID: dadba190-16f6-4a39-b99a-26a4d5e08346
+ called_from_default_init: true
+ selectedCore: cm33_core0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'system'
+- type_id: 'system'
+- global_system_definitions:
+ - user_definitions: ''
+ - user_includes: ''
+ - global_init: ''
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'uart_cmsis_common'
+- type_id: 'uart_cmsis_common'
+- global_USART_CMSIS_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+component:
+- type: 'gpio_adapter_common'
+- type_id: 'gpio_adapter_common'
+- global_gpio_adapter_common:
+ - quick_selection: 'default'
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "peripherals.h"
+
+/***********************************************************************************************************************
+ * BOARD_InitPeripherals functional group
+ **********************************************************************************************************************/
+/***********************************************************************************************************************
+ * NVIC initialization code
+ **********************************************************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+instance:
+- name: 'NVIC'
+- type: 'nvic'
+- mode: 'general'
+- custom_name_enabled: 'false'
+- type_id: 'nvic'
+- functional_group: 'BOARD_InitPeripherals'
+- peripheral: 'NVIC'
+- config_sets:
+ - nvic:
+ - interrupt_table: []
+ - interrupts: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/* Empty initialization function (commented out)
+static void NVIC_init(void) {
+} */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+void BOARD_InitPeripherals(void)
+{
+ /* Initialize components */
+}
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void)
+{
+ BOARD_InitPeripherals();
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/peripherals.h b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/peripherals.h
new file mode 100644
index 0000000..2a75809
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/peripherals.h
@@ -0,0 +1,33 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+/***********************************************************************************************************************
+ * Included files
+ **********************************************************************************************************************/
+#include "fsl_common.h"
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/***********************************************************************************************************************
+ * Initialization functions
+ **********************************************************************************************************************/
+
+void BOARD_InitPeripherals(void);
+
+/***********************************************************************************************************************
+ * BOARD_InitBootPeripherals function
+ **********************************************************************************************************************/
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _PERIPHERALS_H_ */
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/pin_mux.c b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/pin_mux.c
new file mode 100644
index 0000000..7747554
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/pin_mux.c
@@ -0,0 +1,54 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v16.0
+processor: MCXN947
+package_id: MCXN947VDF
+mcu_data: ksdk2_0
+processor_version: 16.3.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
+- pin_list: []
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description :
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/pin_mux.h b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/pin_mux.h
new file mode 100644
index 0000000..b8b69ce
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/MCUXpressoConfig/board/pin_mux.h
@@ -0,0 +1,45 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ * @brief
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld
new file mode 100644
index 0000000..4c7b5dd
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld
@@ -0,0 +1,249 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+TEXT_START = DEFINED(__qspi_xip__) ? 0x80001000 : 0x00000000; /* flexspi boot image start with 0x80000000 */
+TEXT_SIZE = DEFINED(__qspi_xip__) ? 0x0FFFF000 : 0x000C0000; /* flexspi boot image offset at 0x80001000 */
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = TEXT_START, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = TEXT_START + 0x00000400, LENGTH = TEXT_SIZE - 0x00000400
+ m_core1_image (RX) : ORIGIN = 0x000C0000, LENGTH = 0x00040000
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0004E000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x2004E000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
+ m_flash1 (RX) : ORIGIN = 0x00100000, LENGTH = 0x00100000
+ m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000
+ m_flash_config (RX) : ORIGIN = 0x80000400, LENGTH = 0x00000200
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ .flash_config :
+ {
+ . = ALIGN(4);
+ __FLASH_BASE = .;
+ KEEP(* (.flexspi_fcb)) /* FCB section */
+ . = ALIGN(4);
+ } > m_flash_config
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld.base@1.0.0
new file mode 100644
index 0000000..4c7b5dd
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld.base@1.0.0
@@ -0,0 +1,249 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+TEXT_START = DEFINED(__qspi_xip__) ? 0x80001000 : 0x00000000; /* flexspi boot image start with 0x80000000 */
+TEXT_SIZE = DEFINED(__qspi_xip__) ? 0x0FFFF000 : 0x000C0000; /* flexspi boot image offset at 0x80001000 */
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = TEXT_START, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = TEXT_START + 0x00000400, LENGTH = TEXT_SIZE - 0x00000400
+ m_core1_image (RX) : ORIGIN = 0x000C0000, LENGTH = 0x00040000
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0004E000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x2004E000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
+ m_flash1 (RX) : ORIGIN = 0x00100000, LENGTH = 0x00100000
+ m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000
+ m_flash_config (RX) : ORIGIN = 0x80000400, LENGTH = 0x00000200
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ .flash_config :
+ {
+ . = ALIGN(4);
+ __FLASH_BASE = .;
+ KEEP(* (.flexspi_fcb)) /* FCB section */
+ . = ALIGN(4);
+ } > m_flash_config
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf
new file mode 100644
index 0000000..c6d2fb3
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf
@@ -0,0 +1,129 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#if (defined(__qspi_xip__))
+ #define m_interrupts_start 0x80001000
+ #define m_interrupts_size 0x00000400
+
+ #define m_text_start 0x80001400
+ #define m_text_size 0x0FFFEC00
+#else
+ #define m_interrupts_start 0x00000000
+ #define m_interrupts_size 0x00000400
+
+ #define m_text_start 0x00000400
+ #define m_text_size 0x000BFC00
+#endif
+
+
+#define m_flash1_start 0x00100000
+#define m_flash1_size 0x00100000
+
+#define m_sramx_start 0x04000000
+#define m_sramx_size 0x00018000
+
+
+#define m_core1_image_start 0x000C0000
+#define m_core1_image_size 0x00040000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004C000
+ #define m_rpmsg_sh_mem_start 0x2004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004E000
+#endif
+#define m_usb_sram_start 0x400BA000
+#define m_usb_sram_size 0x00001000
+
+#define m_boot_flash_conf_start 0x80000400
+
+LR_m_flash_conf m_boot_flash_conf_start 0x400 {
+ FLASH_CONFIG m_boot_flash_conf_start 0x400{ ; load address = execution address
+ * (.flexspi_fcb)
+ }
+}
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
+
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf.base@1.0.0
new file mode 100644
index 0000000..c6d2fb3
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf.base@1.0.0
@@ -0,0 +1,129 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#if (defined(__qspi_xip__))
+ #define m_interrupts_start 0x80001000
+ #define m_interrupts_size 0x00000400
+
+ #define m_text_start 0x80001400
+ #define m_text_size 0x0FFFEC00
+#else
+ #define m_interrupts_start 0x00000000
+ #define m_interrupts_size 0x00000400
+
+ #define m_text_start 0x00000400
+ #define m_text_size 0x000BFC00
+#endif
+
+
+#define m_flash1_start 0x00100000
+#define m_flash1_size 0x00100000
+
+#define m_sramx_start 0x04000000
+#define m_sramx_size 0x00018000
+
+
+#define m_core1_image_start 0x000C0000
+#define m_core1_image_size 0x00040000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004C000
+ #define m_rpmsg_sh_mem_start 0x2004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004E000
+#endif
+#define m_usb_sram_start 0x400BA000
+#define m_usb_sram_size 0x00001000
+
+#define m_boot_flash_conf_start 0x80000400
+
+LR_m_flash_conf m_boot_flash_conf_start 0x400 {
+ FLASH_CONFIG m_boot_flash_conf_start 0x400{ ; load address = execution address
+ * (.flexspi_fcb)
+ }
+}
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
+
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.ld b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.ld
new file mode 100644
index 0000000..0f6a08f
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.ld
@@ -0,0 +1,239 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x00020000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x00020400, LENGTH = 0x0009FC00
+ m_core1_image (RX) : ORIGIN = 0x000C0000, LENGTH = 0x00040000
+ m_data (RW) : ORIGIN = 0x20008000, LENGTH = 0x00046000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x2004C000, LENGTH = RPMSG_SHMEM_SIZE
+ m_flash1 (RX) : ORIGIN = 0x00100000, LENGTH = 0x00100000
+ m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000
+
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.ld.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.ld.base@1.0.0
new file mode 100644
index 0000000..0f6a08f
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.ld.base@1.0.0
@@ -0,0 +1,239 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x00020000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x00020400, LENGTH = 0x0009FC00
+ m_core1_image (RX) : ORIGIN = 0x000C0000, LENGTH = 0x00040000
+ m_data (RW) : ORIGIN = 0x20008000, LENGTH = 0x00046000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x2004C000, LENGTH = RPMSG_SHMEM_SIZE
+ m_flash1 (RX) : ORIGIN = 0x00100000, LENGTH = 0x00100000
+ m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00018000
+
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.scf b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.scf
new file mode 100644
index 0000000..f01518d
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.scf
@@ -0,0 +1,114 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#define m_interrupts_start 0x00020000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x00020400
+#define m_text_size 0x0009FC00
+
+
+#define m_flash1_start 0x00100000
+#define m_flash1_size 0x00100000
+
+#define m_sramx_start 0x04000000
+#define m_sramx_size 0x00018000
+
+
+#define m_core1_image_start 0x000C0000
+#define m_core1_image_size 0x00040000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x20008000
+ #define m_data_size 0x00044000
+ #define m_rpmsg_sh_mem_start 0x2004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x20008000
+ #define m_data_size 0x00046000
+#endif
+#define m_usb_sram_start 0x400BA000
+#define m_usb_sram_size 0x00001000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.scf.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.scf.base@1.0.0
new file mode 100644
index 0000000..f01518d
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_ns.scf.base@1.0.0
@@ -0,0 +1,114 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#define m_interrupts_start 0x00020000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x00020400
+#define m_text_size 0x0009FC00
+
+
+#define m_flash1_start 0x00100000
+#define m_flash1_size 0x00100000
+
+#define m_sramx_start 0x04000000
+#define m_sramx_size 0x00018000
+
+
+#define m_core1_image_start 0x000C0000
+#define m_core1_image_size 0x00040000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x20008000
+ #define m_data_size 0x00044000
+ #define m_rpmsg_sh_mem_start 0x2004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x20008000
+ #define m_data_size 0x00046000
+#endif
+#define m_usb_sram_start 0x400BA000
+#define m_usb_sram_size 0x00001000
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.ld b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.ld
new file mode 100644
index 0000000..2d047b6
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.ld
@@ -0,0 +1,250 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+/* Specify the memory areas */
+/* First 128K flash and first 32K SRAM are used as secure memory. */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x10000000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x10000400, LENGTH = 0x0001FA00
+ m_veneer_table (RX) : ORIGIN = 0x1001FE00, LENGTH = 0x00000200
+ m_core1_image (RX) : ORIGIN = 0x100C0000, LENGTH = 0x00040000
+ m_data (RW) : ORIGIN = 0x30000000, LENGTH = 0x00008000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x3004C000, LENGTH = RPMSG_SHMEM_SIZE
+ m_flash1 (RX) : ORIGIN = 0x10100000, LENGTH = 0x00100000
+ m_sramx (RW) : ORIGIN = 0x14000000, LENGTH = 0x00018000
+
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ /* section for veneer table */
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > m_veneer_table
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.ld.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.ld.base@1.0.0
new file mode 100644
index 0000000..2d047b6
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.ld.base@1.0.0
@@ -0,0 +1,250 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+/* Specify the memory areas */
+/* First 128K flash and first 32K SRAM are used as secure memory. */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x10000000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x10000400, LENGTH = 0x0001FA00
+ m_veneer_table (RX) : ORIGIN = 0x1001FE00, LENGTH = 0x00000200
+ m_core1_image (RX) : ORIGIN = 0x100C0000, LENGTH = 0x00040000
+ m_data (RW) : ORIGIN = 0x30000000, LENGTH = 0x00008000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x3004C000, LENGTH = RPMSG_SHMEM_SIZE
+ m_flash1 (RX) : ORIGIN = 0x10100000, LENGTH = 0x00100000
+ m_sramx (RW) : ORIGIN = 0x14000000, LENGTH = 0x00018000
+
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ /* section for veneer table */
+ .gnu.sgstubs :
+ {
+ . = ALIGN(32);
+ _start_sg = .;
+ *(.gnu.sgstubs*)
+ . = ALIGN(32);
+ _end_sg = .;
+ } > m_veneer_table
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.scf b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.scf
new file mode 100644
index 0000000..fe4a79a
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.scf
@@ -0,0 +1,121 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+/* First 128K flash and first 32K SRAM are used as secure memory. */
+#define m_interrupts_start 0x10000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x10000400
+#define m_text_size 0x0001FA00
+
+
+#define m_flash1_start 0x10100000
+#define m_flash1_size 0x00100000
+
+#define m_sramx_start 0x14000000
+#define m_sramx_size 0x00018000
+
+
+#define m_core1_image_start 0x100C0000
+#define m_core1_image_size 0x00040000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x30000000
+ #define m_data_size 0x00008000
+ #define m_rpmsg_sh_mem_start 0x3004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x30000000
+ #define m_data_size 0x00008000
+#endif
+#define m_usb_sram_start 0x500BA000
+#define m_usb_sram_size 0x00001000
+
+/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
+#define m_veneer_table_start 0x1001FE00
+#define m_veneer_table_size 0x00000200
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+ ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
+ *(Veneer$$CMSE)
+ }
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.scf.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.scf.base@1.0.0
new file mode 100644
index 0000000..fe4a79a
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash_s.scf.base@1.0.0
@@ -0,0 +1,121 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+/* First 128K flash and first 32K SRAM are used as secure memory. */
+#define m_interrupts_start 0x10000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x10000400
+#define m_text_size 0x0001FA00
+
+
+#define m_flash1_start 0x10100000
+#define m_flash1_size 0x00100000
+
+#define m_sramx_start 0x14000000
+#define m_sramx_size 0x00018000
+
+
+#define m_core1_image_start 0x100C0000
+#define m_core1_image_size 0x00040000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x30000000
+ #define m_data_size 0x00008000
+ #define m_rpmsg_sh_mem_start 0x3004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x30000000
+ #define m_data_size 0x00008000
+#endif
+#define m_usb_sram_start 0x500BA000
+#define m_usb_sram_size 0x00001000
+
+/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
+#define m_veneer_table_start 0x1001FE00
+#define m_veneer_table_size 0x00000200
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+ ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
+ *(Veneer$$CMSE)
+ }
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld
new file mode 100644
index 0000000..7ea1191
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld
@@ -0,0 +1,235 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x04000400, LENGTH = 0x00017C00
+ m_core1_image (RX) : ORIGIN = 0x2004E000, LENGTH = 0x0000D000
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0004E000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x2004E000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld.base@1.0.0
new file mode 100644
index 0000000..7ea1191
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld.base@1.0.0
@@ -0,0 +1,235 @@
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: GNU C Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+RPMSG_SHMEM_SIZE = DEFINED(__use_shmem__) ? 0x2000 : 0;
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x04000000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x04000400, LENGTH = 0x00017C00
+ m_core1_image (RX) : ORIGIN = 0x2004E000, LENGTH = 0x0000D000
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x0004E000 - RPMSG_SHMEM_SIZE
+ rpmsg_sh_mem (RW) : ORIGIN = 0x2004E000 - RPMSG_SHMEM_SIZE, LENGTH = RPMSG_SHMEM_SIZE
+ m_usb_sram (RW) : ORIGIN = 0x400BA000, LENGTH = 0x00001000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* section for storing the secondary core image */
+ .core1_code :
+ {
+ . = ALIGN(4) ;
+ KEEP (*(.core1_code))
+ *(.core1_code*)
+ . = ALIGN(4) ;
+ } > m_core1_image
+
+ /* NOINIT section for rpmsg_sh_mem */
+ .noinit_rpmsg_sh_mem (NOLOAD) : ALIGN(4)
+ {
+ __RPMSG_SH_MEM_START__ = .;
+ *(.noinit.$rpmsg_sh_mem*)
+ . = ALIGN(4) ;
+ __RPMSG_SH_MEM_END__ = .;
+ } > rpmsg_sh_mem
+
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(NonCacheable.init) /* NonCacheable init section */
+ *(NonCacheable) /* NonCacheable section */
+ *(CodeQuickAccess) /* quick access code section */
+ *(DataQuickAccess) /* quick access data section */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf
new file mode 100644
index 0000000..2d79bc3
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf
@@ -0,0 +1,108 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#define m_interrupts_start 0x04000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x04000400
+#define m_text_size 0x00017C00
+
+
+#define m_core1_image_start 0x2004E000
+#define m_core1_image_size 0x0000D000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004C000
+ #define m_rpmsg_sh_mem_start 0x2004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004E000
+#endif
+#define m_usb_sram_start 0x400BA000
+#define m_usb_sram_size 0x00001000
+
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
+
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf.base@1.0.0 b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf.base@1.0.0
new file mode 100644
index 0000000..2d79bc3
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf.base@1.0.0
@@ -0,0 +1,108 @@
+#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
+/*
+** ###################################################################
+** Processors: MCXN947VDF_cm33_core0
+** MCXN947VNL_cm33_core0
+**
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: MCXNx4x Reference Manual
+** Version: rev. 1.0, 2021-08-03
+** Build: b231116
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2023 NXP
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+
+/* USB BDT size */
+#define usb_bdt_size 0x200
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+#define m_interrupts_start 0x04000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x04000400
+#define m_text_size 0x00017C00
+
+
+#define m_core1_image_start 0x2004E000
+#define m_core1_image_size 0x0000D000
+
+#if (defined(__use_shmem__))
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004C000
+ #define m_rpmsg_sh_mem_start 0x2004C000
+ #define m_rpmsg_sh_mem_size 0x00002000
+#else
+ #define m_data_start 0x20000000
+ #define m_data_size 0x0004E000
+#endif
+#define m_usb_sram_start 0x400BA000
+#define m_usb_sram_size 0x00001000
+
+
+
+LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
+
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (.isr_vector,+FIRST)
+ }
+
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__use_shmem__))
+ RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
+ * (rpmsg_sh_mem_section)
+ }
+#endif
+
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ * (RamFunction)
+ * (NonCacheable.init)
+ * (*NonCacheable)
+ * (CodeQuickAccess)
+ * (DataQuickAccess)
+ }
+ ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+
+ RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (*m_usb_bdt)
+ }
+
+ RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (*m_usb_global)
+ }
+ }
+
+LR_CORE1_IMAGE m_core1_image_start {
+ CORE1_REGION m_core1_image_start m_core1_image_size {
+ * (.core1_code)
+ }
+}
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/Simple2.cproject.yml b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/Simple2.cproject.yml
new file mode 100644
index 0000000..d66fbb9
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/Simple2.cproject.yml
@@ -0,0 +1,52 @@
+# A project translates into one executable or library.
+project:
+ device: :cm33_core0
+
+ generators:
+ options:
+ - generator: MCUXpressoConfig
+ path: ./MCUXpressoConfig
+ name: ConfigTools
+
+ setups:
+ - setup: Options for project
+ processor:
+ fpu: sp
+ trustzone: "off"
+
+ # List components to use for your application.
+ # A software component is a re-usable unit that may be configurable.
+ components:
+ - component: Device:Config Tools:Init
+ - component: Device:Startup
+ - component: Device:CMSIS:MCXN947_header
+ - component: Device:CMSIS:MCXN947_system
+
+ - component: Device:SDK Drivers:clock
+ - component: Device:SDK Drivers:common
+ - component: Device:SDK Drivers:mcx_spc
+ - component: Device:SDK Drivers:reset
+
+ - component: CMSIS:CORE
+
+ groups:
+ - group: Main
+ files:
+ - file: ./main.c
+
+ linker:
+ - script: RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.scf
+ for-compiler: AC6
+ for-context: +ROM
+
+ - script: RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_flash.ld
+ for-compiler: GCC
+ for-context: +ROM
+
+ - script: RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.scf
+ for-compiler: AC6
+ for-context: +RAM
+
+ - script: RTE/Device/MCXN947VDF_cm33_core0/MCXN947_cm33_core0_ram.ld
+ for-compiler: GCC
+ for-context: +RAM
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/Simple2.csolution.yml b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/Simple2.csolution.yml
new file mode 100644
index 0000000..6e359a3
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/Simple2.csolution.yml
@@ -0,0 +1,38 @@
+# A solution is a collection of related projects that share same base configuration.
+solution:
+ created-for: CMSIS-Toolbox@2.6.0
+ cdefault:
+
+ # List of tested compilers that can be selected
+ select-compiler:
+ - compiler: AC6
+ - compiler: GCC
+ - compiler: IAR
+
+ # List the packs that define the device and/or board.
+ packs:
+ - pack: NXP::FRDM-MCXN947_BSP
+ - pack: NXP::MCXN947_DFP
+ - pack: ARM::CMSIS
+
+ # List different hardware targets that are used to deploy the solution.
+ target-types:
+ - type: ROM
+ device: NXP::MCXN947VDF
+
+ - type: RAM
+ device: NXP::MCXN947VDF
+
+ # List of different build configurations.
+ build-types:
+ - type: Debug
+ debug: on
+ optimize: none
+
+ - type: Release
+ debug: off
+ optimize: balanced
+
+ # List related projects.
+ projects:
+ - project: Simple2.cproject.yml
diff --git a/boards/frdmmcxn947/cmsis/templates/Device/Simple2/main.c b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/main.c
new file mode 100644
index 0000000..71b61f0
--- /dev/null
+++ b/boards/frdmmcxn947/cmsis/templates/Device/Simple2/main.c
@@ -0,0 +1,27 @@
+/*---------------------------------------------------------------------------
+ * Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *---------------------------------------------------------------------------*/
+
+#include "RTE_Components.h"
+#include CMSIS_device_header
+
+int main (void) {
+
+ while(1) {
+ ;
+ }
+}