|
Frozen
|
The XTheadFMemIdx extension is stable.
|
The XTheadFMemIdx ISA extension provides indexed memory operations
for floating-point registers.
Extension version: 1.0.
The table below gives an overview of the instructions:
| RV32 | RV64 | F | D | Mnemonic | Instruction |
|---|---|---|---|---|---|
Y |
Y |
N |
Y |
th.flrd rd, rs1, rs2, imm2 |
|
Y |
Y |
Y |
Y |
th.flrw rd, rs1, rs2, imm2 |
|
N |
Y |
N |
Y |
th.flurd rd, rs1, rs2, imm2 |
|
N |
Y |
Y |
Y |
th.flurw rd, rs1, rs2, imm2 |
|
Y |
Y |
N |
Y |
th.fsrd rd, rs1, rs2, imm2 |
|
Y |
Y |
Y |
Y |
th.fsrw rd, rs1, rs2, imm2 |
|
N |
Y |
N |
Y |
th.fsurd rd, rs1, rs2, imm2 |
|
N |
Y |
Y |
Y |
th.fsurw rd, rs1, rs2, imm2 |
The first four columns show the requirements of the instructions.
E.g. th.flurd is only available on harts that implement the rv64i base
and the D double-precision floating-point extensions.
The XTheadFMemIdx extension’s availability can be probed via the
th.sxstatus.THEADISAEE bit (bit 22).
The XTheadFMemIdx extension is available if and only if this bit is 1.
Refer to [xtheadsxstatus] for more information about the th.sxstatus CSR.