diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..4aae708 --- /dev/null +++ b/.gitignore @@ -0,0 +1,5 @@ +*.pdf +.asciidoctor +images/diag-* +revision.adoc-snippet* + diff --git a/Makefile b/Makefile new file mode 100644 index 0000000..87eba0f --- /dev/null +++ b/Makefile @@ -0,0 +1,31 @@ +SPEC=xthead +HEADER_SOURCE := $(SPEC).adoc +GITVER=$(shell git describe --tag --always --dirty) +GITDATE=$(shell git show -s --format=%ci | cut -d ' ' -f 1) + +# e.g. "2022-07-29-d027732", or "2022-08-01-dbd4007-dirty" +VERSION="$(GITDATE)-$(GITVER)" + +$(SPEC)-$(VERSION).pdf: *.adoc revision.adoc-snippet + @echo "Building asciidoc" + asciidoctor-pdf \ + --attribute=mathematical-format=svg \ + --attribute=pdf-fontsdir=resources/fonts \ + --attribute=pdf-style=resources/themes/thead-pdf.yml \ + --failure-level=ERROR \ + --require=asciidoctor-diagram \ + --require=asciidoctor-mathematical \ + --out-file=$@ \ + $(HEADER_SOURCE) + +.PHONY: revision.adoc-snippet +revision.adoc-snippet: + echo ":revdate: ${GITDATE}" >> $@-tmp + echo ":revnumber: ${GITVER}" >> $@-tmp + diff $@ $@-tmp || mv $@-tmp $@ + +all: $(SPEC)-$(VERSION).pdf + +clean: + rm -f $(SPEC)-*.pdf + rm -f revision.adoc-snippet* diff --git a/README.md b/README.md index 9ac5be7..5aef68b 100644 --- a/README.md +++ b/README.md @@ -1,2 +1,13 @@ -# thead-extension-spec -T-head vendor extension Instruction Set spec +# T-Head ISA extensions (Xthead*) + +This repository contains the T-Head RISC-V ISA extensions (Xthead*) specifications. + +## Build instructions + +The specification is written in AsciiDoc. +The following instructions can be used to generate a PDF containing +all specifications: + +``` +make +``` diff --git a/docinfo.adoc b/docinfo.adoc new file mode 100644 index 0000000..1b64886 --- /dev/null +++ b/docinfo.adoc @@ -0,0 +1,35 @@ +== Document information + +=== Copyright and license information +This specification is licensed under the Apache License, Version 2.0 +(Apache-2.0). The full license text is available at +https://www.apache.org/licenses/LICENSE-2.0. + +Copyright 2022 T-Head Semiconductor Co., Ltd. + +Copyright 2022 VRULL GmbH + +=== Contributors + +The list below includes all contributors to this document in alphabetical order: + +[%hardbreaks] +* Christoph Müllner +* Cooper Qu +* Lifang Xia +* Philipp Tomsich +* Yunhai Shang < yunhai@linux.alibaba.com> +* Zhiwei Liu + +=== Changelog + +* 2022-07-12: Initial draft with four CMO instructions +* 2022-07-16: Adding complete XTheadCmo extension +* 2022-07-20: Adding XTheadMemPair extension, adding HW requirements for XTheadCmo +* 2022-07-26: Adding XTheadCmo U mode permission, Adding XTHeadSync, XTheadFMemIdx +* 2022-07-27: Adding XTheadMemPair, XTheadMemIdx, XTheadMac, XThadCondMov, XTheadB[a,b,s] +* 2022-07-29: Adding XTheadEE (mxstatus.theadisaee) and mxstatus.ucme (as part of XTheadCmo) +* 2022-08-01: Remove XTheadEE and rework availability/permission documentation, adding lifecycle-states, + adding doc versioning and changelog +* 2022-08-10: *.adoc: Fix several formatting issues +* 2022-08-25: Adjusting contributors list diff --git a/images/t-head.png b/images/t-head.png new file mode 100644 index 0000000..b9a2a94 Binary files /dev/null and b/images/t-head.png differ diff --git a/intro.adoc b/intro.adoc new file mode 100644 index 0000000..7cdb7b6 --- /dev/null +++ b/intro.adoc @@ -0,0 +1,82 @@ +== Introduction + +The T-Head extension collection was created to augment +the RISC-V ISA by adding additional functionality +to enable faster and more energy-efficient solutions. + +The RISC-V ISA and its standardized extensions provide a rich set of +instructions suitable for a wide range of applications, starting from +specialized microcontrollers to HPC systems. +The suitability for such a range of systems comes from the fact that +the RISC-V ISA is modularized with a base instruction set and a range +of extensions that target specific target applications and functionality. + +The RISC-V ISA and its authors strongly advertise the ability +to create vendor extensions. Dedicated encoding spaces ensure, +that there are not conflicts with standard extensions. + +This document specifies the T-Head extension collection, +a collection of vendor extensions that are implemented +in many T-Head processors. + +=== Overview + +The T-Head extension collection follows the principles of the RISC-V ISA. +The collection consists of the following ISA extensions: + +* `XTheadCmo` provides instructions for cache management. +* `XTheadSync` provides instructions for multi-processor synchronization. +* `XTheadBa` provides instructions for address calculations. +* `XTheadBb` provides instructions for basic bit-manipulation. +* `XTheadBs` provides single-bit instructions. +* `XTheadCondMov` provides instructions for conditional moves. +* `XTheadMemIdx` provides GPR memory operations. +* `XTheadMemPair` provides two-GP-register memory operations. +* `XTheadFMemIdx` provides floating-point memory operations. +* `XTheadMac` provides multiply-accumulate instructions. + +=== Dependencies to standard extensions + +The T-Head extension collection is designed to be compatible +with RISC-V's base integer instruction sets RV32I and RV64I. + +Some instructions are only available if the system's +`XLEN` is 64 (i.e. integer registers and supported user +address space is 64 bits). +To highlight the availability, each extension documents +this for each instruction. + +Instruction that operate on floating-point registers can +be used in combination with `F` (32-bit floating-point register) +or `D` (64-bit floating-point registers). +Some instruction are only available if the system implements +the `D` extension. To highlight the availability, each +floating-point extension document this for each instruction. + +=== Enablement of extensions and instructions + +All extensions and instructions are expected to be enabled at all times. +The instructions can be used at any time when executing in the documented +privilege levels, that permit the execution of the instruction. + +However, there might be SoC-specific mechanisms to ensure this behaviour. +E.g. the T-Head C906 requires the CSR field `mxstatus.theadisaee` to +be set to `1` to enable the ISA extensions. +Another example is the CSR field `mxstatus.ucme` of the T-Head C906, +that is required to be set to `1` in order to execute cache management +instructions in `U` mode (if the instruction is documented that this +is permitted). + +=== Lifecycle + +The lifecycle of the extensions included in this document is +defined on a per-extension base. + +Possible states are: + +* `Draft`: No guarantees (everything may change). +* `Stable`: No feature additions/removals/changes. Only clarifications. + +A `draft` specification is expected to become `stable` in the future +(with exepcted changes until then). A `stable` extension remains in that +state for ever. diff --git a/resources/fonts/Montserrat-ExtraLight.ttf b/resources/fonts/Montserrat-ExtraLight.ttf new file mode 100755 index 0000000..ca0bbb6 Binary files /dev/null and b/resources/fonts/Montserrat-ExtraLight.ttf differ diff --git a/resources/fonts/Montserrat-ExtraLightItalic.ttf b/resources/fonts/Montserrat-ExtraLightItalic.ttf new file mode 100755 index 0000000..f3c1559 Binary files /dev/null and b/resources/fonts/Montserrat-ExtraLightItalic.ttf differ diff --git a/resources/fonts/Montserrat-Italic.ttf b/resources/fonts/Montserrat-Italic.ttf new file mode 100755 index 0000000..eb4232a Binary files /dev/null and b/resources/fonts/Montserrat-Italic.ttf differ diff --git a/resources/fonts/Montserrat-Light.ttf b/resources/fonts/Montserrat-Light.ttf new file mode 100755 index 0000000..990857d Binary files /dev/null and b/resources/fonts/Montserrat-Light.ttf differ diff --git a/resources/fonts/Montserrat-Medium.ttf b/resources/fonts/Montserrat-Medium.ttf new file mode 100755 index 0000000..6e079f6 Binary files /dev/null and b/resources/fonts/Montserrat-Medium.ttf differ diff --git a/resources/fonts/Montserrat-MediumItalic.ttf b/resources/fonts/Montserrat-MediumItalic.ttf new file mode 100755 index 0000000..0dc3ac9 Binary files /dev/null and b/resources/fonts/Montserrat-MediumItalic.ttf differ diff --git a/resources/fonts/Montserrat-Regular.ttf b/resources/fonts/Montserrat-Regular.ttf new file mode 100755 index 0000000..8d443d5 Binary files /dev/null and b/resources/fonts/Montserrat-Regular.ttf differ diff --git a/resources/fonts/OFL-M.txt b/resources/fonts/OFL-M.txt new file mode 100755 index 0000000..7881887 --- /dev/null +++ b/resources/fonts/OFL-M.txt @@ -0,0 +1,93 @@ +Copyright 2011 The Montserrat Project Authors (https://github.com/JulietaUla/Montserrat) + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. The +fonts, including any derivative works, can be bundled, embedded, +redistributed and/or sold with any software provided that any reserved +names are not used by derivative works. The fonts and derivatives, +however, cannot be released under any other type of license. The +requirement for fonts to remain under this license does not apply +to any document created using the fonts or their derivatives. + +DEFINITIONS +"Font Software" refers to the set of files released by the Copyright +Holder(s) under this license and clearly marked as such. This may +include source files, build scripts and documentation. + +"Reserved Font Name" refers to any names specified as such after the +copyright statement(s). + +"Original Version" refers to the collection of Font Software components as +distributed by the Copyright Holder(s). + +"Modified Version" refers to any derivative made by adding to, deleting, +or substituting -- in part or in whole -- any of the components of the +Original Version, by changing formats or by porting the Font Software to a +new environment. + +"Author" refers to any designer, engineer, programmer, technical +writer or other person who contributed to the Font Software. + +PERMISSION & CONDITIONS +Permission is hereby granted, free of charge, to any person obtaining +a copy of the Font Software, to use, study, copy, merge, embed, modify, +redistribute, and sell modified and unmodified copies of the Font +Software, subject to the following conditions: + +1) Neither the Font Software nor any of its individual components, +in Original or Modified Versions, may be sold by itself. + +2) Original or Modified Versions of the Font Software may be bundled, +redistributed and/or sold with any software, provided that each copy +contains the above copyright notice and this license. These can be +included either as stand-alone text files, human-readable headers or +in the appropriate machine-readable metadata fields within text or +binary files as long as those fields can be easily viewed by the user. + +3) No Modified Version of the Font Software may use the Reserved Font +Name(s) unless explicit written permission is granted by the corresponding +Copyright Holder. This restriction only applies to the primary font name as +presented to the users. + +4) The name(s) of the Copyright Holder(s) or the Author(s) of the Font +Software shall not be used to promote, endorse or advertise any +Modified Version, except to acknowledge the contribution(s) of the +Copyright Holder(s) and the Author(s) or with their explicit written +permission. + +5) The Font Software, modified or unmodified, in part or in whole, +must be distributed entirely under this license, and must not be +distributed under any other license. The requirement for fonts to +remain under this license does not apply to any document created +using the Font Software. + +TERMINATION +This license becomes null and void if any of the above conditions are +not met. + +DISCLAIMER +THE FONT SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT +OF COPYRIGHT, PATENT, TRADEMARK, OR OTHER RIGHT. IN NO EVENT SHALL THE +COPYRIGHT HOLDER BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +INCLUDING ANY GENERAL, SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL +DAMAGES, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +FROM, OUT OF THE USE OR INABILITY TO USE THE FONT SOFTWARE OR FROM +OTHER DEALINGS IN THE FONT SOFTWARE. diff --git a/resources/fonts/OFL-P.txt b/resources/fonts/OFL-P.txt new file mode 100755 index 0000000..79320bd --- /dev/null +++ b/resources/fonts/OFL-P.txt @@ -0,0 +1,93 @@ +Copyright 2019 The Petrona Project Authors (https://github.com/RingoSeeber/Petrona) + +This Font Software is licensed under the SIL Open Font License, Version 1.1. +This license is copied below, and is also available with a FAQ at: +http://scripts.sil.org/OFL + + +----------------------------------------------------------- +SIL OPEN FONT LICENSE Version 1.1 - 26 February 2007 +----------------------------------------------------------- + +PREAMBLE +The goals of the Open Font License (OFL) are to stimulate worldwide +development of collaborative font projects, to support the font creation +efforts of academic and linguistic communities, and to provide a free and +open framework in which fonts may be shared and improved in partnership +with others. + +The OFL allows the licensed fonts to be used, studied, modified and +redistributed freely as long as they are not sold by themselves. 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If the provision + cannot be reformed, it shall be severed from this Public License + without affecting the enforceability of the remaining terms and + conditions. + + c. No term or condition of this Public License will be waived and no + failure to comply consented to unless expressly agreed to by the + Licensor. + + d. Nothing in this Public License constitutes or may be interpreted + as a limitation upon, or waiver of, any privileges and immunities + that apply to the Licensor or You, including from the legal + processes of any jurisdiction or authority. + + +======================================================================= + +Creative Commons is not a party to its public +licenses. Notwithstanding, Creative Commons may elect to apply one of +its public licenses to material it publishes and in those instances +will be considered the “Licensor.” The text of the Creative Commons +public licenses is dedicated to the public domain under the CC0 Public +Domain Dedication. Except for the limited purpose of indicating that +material is shared under a Creative Commons public license or as +otherwise permitted by the Creative Commons policies published at +creativecommons.org/policies, Creative Commons does not authorize the +use of the trademark "Creative Commons" or any other trademark or logo +of Creative Commons without its prior written consent including, +without limitation, in connection with any unauthorized modifications +to any of its public licenses or any other arrangements, +understandings, or agreements concerning use of licensed material. For +the avoidance of doubt, this paragraph does not form part of the +public licenses. + +Creative Commons may be contacted at creativecommons.org. diff --git a/resources/fonts/Petrona-Light.ttf b/resources/fonts/Petrona-Light.ttf new file mode 100755 index 0000000..687a25f Binary files /dev/null and b/resources/fonts/Petrona-Light.ttf differ diff --git a/resources/fonts/Petrona-LightItalic.ttf b/resources/fonts/Petrona-LightItalic.ttf new file mode 100755 index 0000000..0fd2e15 Binary files /dev/null and b/resources/fonts/Petrona-LightItalic.ttf differ diff --git a/resources/fonts/Petrona-Medium.ttf b/resources/fonts/Petrona-Medium.ttf new file mode 100755 index 0000000..eecc1b6 Binary files /dev/null and b/resources/fonts/Petrona-Medium.ttf differ diff --git a/resources/fonts/Petrona-MediumItalic.ttf b/resources/fonts/Petrona-MediumItalic.ttf new file mode 100755 index 0000000..d316f85 Binary files /dev/null and b/resources/fonts/Petrona-MediumItalic.ttf differ diff --git a/resources/fonts/Petrona-Thin.ttf b/resources/fonts/Petrona-Thin.ttf new file mode 100755 index 0000000..6c61a3c Binary files /dev/null and b/resources/fonts/Petrona-Thin.ttf differ diff --git a/resources/fonts/Petrona-ThinItalic.ttf b/resources/fonts/Petrona-ThinItalic.ttf new file mode 100755 index 0000000..85a0624 Binary files /dev/null and b/resources/fonts/Petrona-ThinItalic.ttf differ diff --git a/resources/fonts/cmunbmr.ttf b/resources/fonts/cmunbmr.ttf new file mode 100755 index 0000000..a9eb24f Binary files /dev/null and b/resources/fonts/cmunbmr.ttf differ diff --git a/resources/fonts/cmunbtl.ttf b/resources/fonts/cmunbtl.ttf new file mode 100755 index 0000000..b0f26fa Binary files /dev/null and b/resources/fonts/cmunbtl.ttf differ diff --git a/resources/fonts/cmunbto.ttf b/resources/fonts/cmunbto.ttf new file mode 100755 index 0000000..10fcbbc Binary files /dev/null and b/resources/fonts/cmunbto.ttf differ diff --git a/resources/fonts/droid-sans-fallback.ttf b/resources/fonts/droid-sans-fallback.ttf new file mode 100755 index 0000000..ad1efca Binary files /dev/null and b/resources/fonts/droid-sans-fallback.ttf differ diff --git a/resources/fonts/mplus-1mn-bold.ttf b/resources/fonts/mplus-1mn-bold.ttf new file mode 100755 index 0000000..b631cf9 Binary files /dev/null and b/resources/fonts/mplus-1mn-bold.ttf differ diff --git a/resources/fonts/mplus-1mn-light.ttf b/resources/fonts/mplus-1mn-light.ttf new file mode 100755 index 0000000..2abb31f Binary files /dev/null and b/resources/fonts/mplus-1mn-light.ttf differ diff --git a/resources/fonts/mplus-1mn-medium.ttf b/resources/fonts/mplus-1mn-medium.ttf new file mode 100755 index 0000000..2ccef34 Binary files /dev/null and b/resources/fonts/mplus-1mn-medium.ttf differ diff --git a/resources/fonts/mplus-1mn-regular.ttf b/resources/fonts/mplus-1mn-regular.ttf new file mode 100755 index 0000000..9442e59 Binary files /dev/null and b/resources/fonts/mplus-1mn-regular.ttf differ diff --git a/resources/fonts/mplus-1mn-thin.ttf b/resources/fonts/mplus-1mn-thin.ttf new file mode 100755 index 0000000..2af69a6 Binary files /dev/null and b/resources/fonts/mplus-1mn-thin.ttf differ diff --git a/resources/fonts/mplus-1p-regular-fallback.ttf b/resources/fonts/mplus-1p-regular-fallback.ttf new file mode 100755 index 0000000..cccc405 Binary files /dev/null and b/resources/fonts/mplus-1p-regular-fallback.ttf differ diff --git a/resources/themes/thead-pdf.yml b/resources/themes/thead-pdf.yml new file mode 100644 index 0000000..2e178d6 --- /dev/null +++ b/resources/themes/thead-pdf.yml @@ -0,0 +1,296 @@ +font: + catalog: + merge: false + #Petrona + body: + normal: Petrona-Light.ttf + bold: Petrona-Medium.ttf + italic: Petrona-LightItalic.ttf + bold_italic: Petrona-MediumItalic.ttf + header_thin: Petrona-Thin.ttf + #Montserrat + headings: + normal: Montserrat-Regular.ttf + italic: Montserrat-Italic.ttf + bold: Montserrat-Medium.ttf + light: Montserrat-Light.ttf + code: + normal: cmunbtl.ttf + bold: cmunbtl.ttf + italic: cmunbto.ttf + bold_italic: cmunbto.ttf + # M+ 1mn supports ASCII and the circled numbers used for conums + M+ 1mn: + normal: mplus-1mn-regular.ttf + bold: mplus-1mn-bold.ttf + italic: mplus-1mn-light.ttf + bold_italic: mplus-1mn-medium.ttf + M+ 1p Fallback: + normal: mplus-1p-regular-fallback.ttf + bold: mplus-1p-regular-fallback.ttf + italic: mplus-1p-regular-fallback.ttf + bold_italic: mplus-1p-regular-fallback.ttf + Droid Fallback: + normal: droid-sans-fallback.ttf + # M+ 1p supports Latin, Latin-1 Supplement, Latin Extended, Greek, Cyrillic, Vietnamese, Japanese & an assortment of symbols + # It also provides arrows for ->, <-, => and <= replacements in case these glyphs are missing from font + fallbacks: + - M+ 1p Fallback + - Droid Fallback +page: + background_color: ffffff + layout: portrait + margin: [0.5in, 0.67in, 0.67in, 0.67in] + # margin_inner and margin_outer keys are used for recto/verso print margins when media=prepress + margin_inner: 0.75in + margin_outer: 0.59in + size: A4 +base: + font-family: body + font_size: 11.5 + line_height_length: 12 + font_style: normal + font_size_large: round($base_font_size * 1.25) + font_size_small: round($base_font_size * 0.85) + font_size_min: $base_font_size * 0.75 + border_radius: 3 + border_width: 0.25 +vertical_rhythm: $base_line_height_length +horizontal_rhythm: $base_line_height_length + # QUESTION should vertical_spacing be block_spacing instead? +vertical_spacing: $vertical_rhythm +link: + font_color: 428bca + # literal is currently used for inline monospaced in prose and table cells +literal: + font_color: b12146 + font_family: code +menu_caret_content: " \u203a " +heading: + align: left + font_color: 3e058e + font_family: headings + font_style: light + h1_font_size: floor($base_font_size * 2.8) + # h2 is used for chapter titles (book doctype only) + h2_font_size: floor($base_font_size * 2.15) + h3_font_size: round($base_font_size * 1.7) + h4_font_size: $base_font_size_large + h5_font_size: $base_font_size + h6_font_size: $base_font_size_small +title_page: + align: right + logo: + top: 10% + title: + font_family: headings + font_style: light + font_size: floor($base_font_size * 2.8) + top: 55% + font_color: 3e058e + subtitle: + font_family: headings + font_style: light + font_size: floor($base_font_size * 1.2) + authors: + font_family: headings + font_color: 3e058e + font_style: light + font_size: floor($base_font_size * .8) + revision: + margin_top: $base_font_size * 1.25 +block: + margin_top: 0 + margin_bottom: $vertical_rhythm +caption: + align: left + font_size: $base_font_size * 0.95 + font_style: italic + # FIXME perhaps set line_height instead of / in addition to margins? + margin_inside: $vertical_rhythm / 3 + #margin_inside: $vertical_rhythm / 4 + margin_outside: 0 +lead: + font_size: $base_font_size_large + line_height: 1.4 +abstract: + font_color: 5c6266 + font_size: $lead_font_size + line_height: $lead_line_height + font_style: italic + first_line_font_style: bold + title: + align: left + font_color: $heading_font_color + font_family: $heading_font_family + font_size: $heading_h4_font_size + font_style: $heading_font_style +sidebar: + font-style: italic + background-color: f5f5fc + border-color: 8d81b8 + border-radius: 3 + border-width: 0.2 +sidebar-title: + font_family: $heading_font_family + font-style: light + font-color: $heading-font-color + font-size: 11 + align: left +admonition: + font-style: italic + column_rule_color: $base_border_color + column_rule_width: $base_border_width + padding: [0, $horizontal_rhythm, 0, $horizontal_rhythm] + icon: + note: + name: pencil-square-o + stroke_color: 6489b3 + tip: + name: comments-o + stroke_color: 646b74 + size: 24 + important: + name: info + stroke_color: 5f8c8b + warning: + stroke_color: 9c4d4b + caution: + stroke_color: c99a2c + label: + text_transform: uppercase + font_style: bold +#blockquote: +# font_color: $base_font_color +# font_size: $base_font_size_large +# border_color: $base_border_color +# border_width: 2 + # FIXME disable negative padding bottom once margin collapsing is implemented +# padding: [0, $horizontal_rhythm, $block_margin_bottom * -0.75, $horizontal_rhythm + $blockquote_border_width / 2] +# cite_font_size: $base_font_size_small +# cite_font_color: 51278d +# code is used for source blocks (perhaps change to source or listing?) +code: + font_color: $base_font_color + font_family: $literal_font_family + #font_size: ceil($base_font_size) + font-size: 11 + padding: $code_font_size + line_height: 1.15 + # line_gap is an experimental property to control how a background color is applied to an inline block element + line_gap: 3.8 + background_color: f4f4fb + border_color: cccccc + border_radius: $base_border_radius + border_width: 0.2 +conum: + font_family: M+ 1mn + font_color: $literal_font_color + font_size: $base_font_size + line_height: 4 / 3 +example: + border_color: $base_border_color + border_radius: $base_border_radius + border_width: 0.2 + background_color: ffffff + # FIXME reenable padding bottom once margin collapsing is implemented + padding: [$vertical_rhythm, $horizontal_rhythm, 0, $horizontal_rhythm] +image: + align: left +prose: + margin_top: $block_margin_top + margin_bottom: $block_margin_bottom +thematic_break: + border_color: $base_border_color + border_style: solid + border_width: $base_border_width + margin_top: $vertical_rhythm * 0.5 + margin_bottom: $vertical_rhythm * 1.5 +description_list: + term_font_style: bold + term_spacing: $vertical_rhythm / 4 + description_indent: $horizontal_rhythm * 1.25 +outline_list: + indent: $horizontal_rhythm * 1.5 + #marker_font_color: 404040 + # NOTE outline_list_item_spacing applies to list items that do not have complex content + item_spacing: $vertical_rhythm / 2 +table: + background_color: $page_background_color + #head_background_color: + #head_font_color: $base_font_color + head_font_style: bold + #body_background_color: + body_stripe_background_color: d7d7d7 + foot_background_color: f0f0f0 + border_color: dddddd + border_width: $base_border_width + cell_padding: 3 +toc: + indent: $horizontal_rhythm + line_height: 1.4 + dot_leader: + #content: ". " + font_color: a9a9a9 + #levels: 2 3 +# NOTE in addition to footer, header is also supported +header: + font_size: $base_font_size_small + # NOTE if background_color is set, background and border will span width of page + border_color: dddddd + border_width: 0.35 + height: $base_line_height_length * 2.6 + line_height: 1 + padding: [$base_line_height_length / 1.3, 1, 0, 1] + vertical_align: margin_inside + #image_vertical_align: or + # additional attributes for content: + # * {page-count} + # * {page-number} + # * {document-title} + # * {document-subtitle} + # * {chapter-title} + # * {section-title} + # * {section-or-chapter-title} + recto: + right: + content: '{section-or-chapter-title} | Page {page-number}' + verso: + left: + content: '{section-or-chapter-title} | Page {page-number}' + # left: 'Page {page-number} | {section-or-chapter-title}' +footer: + font_size: $base_font_size_small + # NOTE if background_color is set, background and border will span width of page + border_color: dddddd + border_width: 0.25 + height: $base_line_height_length * 2.5 + line_height: 1 + padding: [$base_line_height_length / 2, 1, 0, 1] + vertical_align: top + #image_vertical_align: or + # additional attributes for content: + # content: '{company}' + # * {page-count} + # * {page-number} + #center: + #content: '{document-title}' + # * {document-subtitle} + # * {chapter-title} + # * {section-title} + # * {section-or-chapter-title} + recto: + #columns: "<50% =0% >50%" + right: + #content: '{page-number}' + content: '{document-title} | © VRULL' + #content: '{document-title} | © VRULL' + #center: '{page-number}' + #content: '{revdate}' + verso: + #columns: $footer_recto_columns + left: + content: $footer_recto_right_content + #center: '{page-number}' + #content: '{page-number}' + diff --git a/xthead.adoc b/xthead.adoc new file mode 100644 index 0000000..b131a05 --- /dev/null +++ b/xthead.adoc @@ -0,0 +1,46 @@ +[[header]] +:description: T-Head ISA extensions (Xthead*) +:company: T-Head Semiconductor Co., Ltd +include::revision.adoc-snippet[] +:url-thead: https://www.t-head.cn +:doctype: book +:preface-title: Preamble +:colophon: +:appendix-caption: Appendix +:imagesdir: images +// Settings: +:experimental: +:reproducible: +:imagesoutdir: images +:icons: font +:lang: en +:listing-caption: Listing +:sectnums: +:toc: left +:toclevels: 4 +:source-highlighter: pygments +ifdef::backend-pdf[] +:source-highlighter: coderay +endif::[] +:data-uri: +:hide-uri-scheme: +:stem: latexmath +:footnote: +:xrefstyle: short + += T-Head ISA extension specification (Xthead*) + +include::docinfo.adoc[] + +include::intro.adoc[] + +include::xtheadcmo.adoc[] +include::xtheadsync.adoc[] +include::xtheadba.adoc[] +include::xtheadbb.adoc[] +include::xtheadbs.adoc[] +include::xtheadcondmov.adoc[] +include::xtheadmemidx.adoc[] +include::xtheadmempair.adoc[] +include::xtheadfmemidx.adoc[] +include::xtheadmac.adoc[] diff --git a/xtheadba.adoc b/xtheadba.adoc new file mode 100644 index 0000000..97fb053 --- /dev/null +++ b/xtheadba.adoc @@ -0,0 +1,20 @@ +[#xtheadba] +== Address calculation instructions (XTheadBa) + +[NOTE,caption=Frozen] +The `XTheadBa` extension is `stable`. + +The `XTheadBa` ISA extension provides bitmanipulation instructions +for address calculation. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.addsl _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadba-insns-addsl>> +|=== + +[#xtheadba-insns,reftext="Instructions"] +=== Instructions +include::xtheadba/addsl.adoc[] diff --git a/xtheadba/addsl.adoc b/xtheadba/addsl.adoc new file mode 100644 index 0000000..1eace94 --- /dev/null +++ b/xtheadba/addsl.adoc @@ -0,0 +1,45 @@ +[#xtheadba-insns-addsl,reftext=Add shifted operand] +==== th.addsl + +Synopsis:: +Add a shifted operand to a second operand. + +Mnemonic:: +th.addsl _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x00 }, +]} +.... + +Description:: +This operation adds the shifted operand (_rs2_ << _imm2_) with _rs1_. + +Operation:: +[source,sail] +-- +reg[rd] := reg[rs1] + (reg[rs2] << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBa (<<#xtheadba>>) +|=== diff --git a/xtheadbb.adoc b/xtheadbb.adoc new file mode 100644 index 0000000..62cc682 --- /dev/null +++ b/xtheadbb.adoc @@ -0,0 +1,43 @@ +[#xtheadbb] +== Basic bit-manipulation (XTheadBb) + +[NOTE,caption=Frozen] +The `XTheadBb` extension is `stable`. + +The `XTheadBb` ISA extension provides conditional basic bit-manipulation instructions. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.srri _rd_, _rs1_, _imm6_ | <<#xtheadbb-insns-srri>> +| N | Y | th.srriw _rd_, _rs1_, _imm5_ | <<#xtheadbb-insns-srriw>> +| Y | Y | th.ext _rd_, _rs1_, _imm1_, _imm2_ | <<#xtheadbb-insns-ext>> +| Y | Y | th.extu _rd_, _rs1_, _imm1_, _imm2_ | <<#xtheadbb-insns-extu>> +| Y | Y | th.ff0 _rd_, _rs1_ | <<#xtheadbb-insns-ff0>> +| Y | Y | th.ff1 _rd_, _rs1_ | <<#xtheadbb-insns-ff1>> +| Y | Y | th.rev _rd_, _rs1_ | <<#xtheadbb-insns-rev>> +| N | Y | th.revw _rd_, _rs1_ | <<#xtheadbb-insns-revw>> +| Y | Y | th.tstnbz _rd_, _rs1_ | <<#xtheadbb-insns-tstnbz>> +|=== + +[#xtheadbb-insns,reftext="Instructions"] +=== Instructions +include::xtheadbb/srri.adoc[] +<<< +include::xtheadbb/srriw.adoc[] +<<< +include::xtheadbb/ext.adoc[] +<<< +include::xtheadbb/extu.adoc[] +<<< +include::xtheadbb/ff0.adoc[] +<<< +include::xtheadbb/ff1.adoc[] +<<< +include::xtheadbb/rev.adoc[] +<<< +include::xtheadbb/revw.adoc[] +<<< +include::xtheadbb/tstnbz.adoc[] diff --git a/xtheadbb/ext.adoc b/xtheadbb/ext.adoc new file mode 100644 index 0000000..5b16a8c --- /dev/null +++ b/xtheadbb/ext.adoc @@ -0,0 +1,44 @@ +[#xtheadbb-insns-ext,reftext=Extract and sign-extend bits] +==== th.ext + +Synopsis:: +Extract and sign-extend bits. + +Mnemonic:: +th.ext _rd_, _rs1_, _imm1_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x2, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'imm2' }, + { bits: 6, name: 'imm1' }, +]} +.... + +Description:: +This operation extract the bits _imm1_.._imm2_ from register _rs1_, sign-extends the value, and stores the result in _rd_. + +Operation:: +[source,sail] +-- +reg[rd] := sign_extend(reg[rs1][imm1:imm2]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/extu.adoc b/xtheadbb/extu.adoc new file mode 100644 index 0000000..d0e865a --- /dev/null +++ b/xtheadbb/extu.adoc @@ -0,0 +1,44 @@ +[#xtheadbb-insns-extu,reftext=Extract and zero-extend bits] +==== th.extu + +Synopsis:: +Extract and zero-extend bits. + +Mnemonic:: +th.extu _rd_, _rs1_, _imm1_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x3, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'imm2' }, + { bits: 6, name: 'imm1' }, +]} +.... + +Description:: +This operation extract the bits _imm1_.._imm2_ from register _rs1_, zero-extends the value, and stores the result in _rd_. + +Operation:: +[source,sail] +-- +reg[rd] := zero_extend(reg[rs1][imm1:imm2]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/ff0.adoc b/xtheadbb/ff0.adoc new file mode 100644 index 0000000..80648fc --- /dev/null +++ b/xtheadbb/ff0.adoc @@ -0,0 +1,50 @@ +[#xtheadbb-insns-ff0,reftext=Find first '0'-bit] +==== th.ff0 + +Synopsis:: +Find first '0'-bit + +Mnemonic:: +th.ff0 _rd_, _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1 }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0 }, + { bits: 2, name: 0x2 }, + { bits: 5, name: 0x10 }, +]} +.... + +Description:: +Finds the first bit with the value of '0' from the highest bit of _rs1_ and writes the index back into register _rd_. +If the highest bit of _rs1_ is '0', the result '0' is returned. +If all the bits in _rs1_ are '1', the result '64' is returned. + +Operation:: +[source,sail] +-- +for i=xlen..0: + if reg[rs1][i] == 0: + break; +reg[rd] = i +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/ff1.adoc b/xtheadbb/ff1.adoc new file mode 100644 index 0000000..78cf34b --- /dev/null +++ b/xtheadbb/ff1.adoc @@ -0,0 +1,50 @@ +[#xtheadbb-insns-ff1,reftext=Find first '1'-bit] +==== th.ff1 + +Synopsis:: +Find first '1'-bit + +Mnemonic:: +th.ff1 _rd_, _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1 }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0 }, + { bits: 2, name: 0x3 }, + { bits: 5, name: 0x10 }, +]} +.... + +Description:: +Finds the first bit with the value of '1' from the highest bit of _rs1_ and writes the index back into register _rd_. +If the highest bit of _rs1_ is '1', the result '0' is returned. +If all the bits in _rs1_ are '1', the result '64' is returned. + +Operation:: +[source,sail] +-- +for i=xlen..0: + if reg[rs1][i] == 1: + break; +reg[rd] = i +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/rev.adoc b/xtheadbb/rev.adoc new file mode 100644 index 0000000..3ba703c --- /dev/null +++ b/xtheadbb/rev.adoc @@ -0,0 +1,48 @@ +[#xtheadbb-insns-rev,reftext=Reverse byte order] +==== th.rev + +Synopsis:: +Reverse the byte order. + +Mnemonic:: +th.rev _rd_, _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0 }, + { bits: 2, name: 0x1 }, + { bits: 5, name: 0x10 }, +]} +.... + +Description:: +This operation reverses the byte order of the value in _rs1_ and stores the result in _rd_. + +Operation:: +[source,sail] +-- +for i=0..(xlen/8-1): + j := xlen/8 - 1 - i + tmp[i] := reg[rs1][j] +reg[rd] := tmp +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/revw.adoc b/xtheadbb/revw.adoc new file mode 100644 index 0000000..cd802cf --- /dev/null +++ b/xtheadbb/revw.adoc @@ -0,0 +1,48 @@ +[#xtheadbb-insns-revw,reftext=Reverse byte order of word operand] +==== th.revw + +Synopsis:: +Reverse the byte order of a word operand. + +Mnemonic:: +th.revw _rd_, _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0 }, + { bits: 2, name: 0x0 }, + { bits: 5, name: 0x12 }, +]} +.... + +Description:: +This operation reverses the byte order of the 32-bit value in _rs1_ and stores the result in _rd_. + +Operation:: +[source,sail] +-- +for i=0..3: + j := 3 - i + tmp[i] := reg[rs1][j] +reg[rd] := tmp +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/srri.adoc b/xtheadbb/srri.adoc new file mode 100644 index 0000000..11d1686 --- /dev/null +++ b/xtheadbb/srri.adoc @@ -0,0 +1,47 @@ +[#xtheadbb-insns-srri,reftext=Cyclic right shift] +==== th.srri + +Synopsis:: +Perform a cyclic right shift. + +Mnemonic:: +th.srri _rd_, _rs1_, _imm6_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'imm6' }, + { bits: 6, name: 0x04 }, +]} +.... + +Description:: +This operation rotates the contents of _rs1_ by _imm6_ bits and stores the result in _rd_. + +Operation:: +[source,sail] +-- +if (xlen == 32) + imm6 &= 0x1f + +reg[rd] := (reg[rs1] >> imm6) | (reg[rs1] << (xlen - imm6)) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/srriw.adoc b/xtheadbb/srriw.adoc new file mode 100644 index 0000000..0f2aae9 --- /dev/null +++ b/xtheadbb/srriw.adoc @@ -0,0 +1,45 @@ +[#xtheadbb-insns-srriw,reftext=Cyclic right shift on word operand] +==== th.srriw + +Synopsis:: +Perform a cyclic right shift on word operand. + +Mnemonic:: +th.srriw _rd_, _rs1_, _imm5_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 7, name: 0x0a }, +]} +.... + +Description:: +This operation rotates the contents of the 32-bit value in _rs1_ by _imm5_ bits and stores the result in _rd_. + +Operation:: +[source,sail] +-- +data := zext.w(reg[rs1]) +reg[rd] := (data >> imm5) | (data << (32 - imm5)) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbb/tstnbz.adoc b/xtheadbb/tstnbz.adoc new file mode 100644 index 0000000..b873fba --- /dev/null +++ b/xtheadbb/tstnbz.adoc @@ -0,0 +1,51 @@ +[#xtheadbb-insns-tstnbz,reftext=Test for NUL bytes] +==== th.tstnbz + +Synopsis:: +Test for NUL bytes. + +Mnemonic:: +th.tstnbz _rd_, _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1 }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x0 }, + { bits: 2, name: 0x0 }, + { bits: 5, name: 0x10 }, +]} +.... + +Description:: +Tests each byte in register _rs1_ for equality with 0. +If a byte is 0, then the corresponding byte in register _rd_ will be set to 0xff. +Otherwise, the corresponding byte in register _rd_ will be set to 0. + +Operation:: +[source,sail] +-- +for i=0..(xlen/8-1): + if reg[rs1][i] == 0: + reg[rd][i] := 0xff + else + reg[rd][i] := 0 +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBb (<<#xtheadbb>>) +|=== diff --git a/xtheadbs.adoc b/xtheadbs.adoc new file mode 100644 index 0000000..d3a3718 --- /dev/null +++ b/xtheadbs.adoc @@ -0,0 +1,19 @@ +[#xtheadbs] +== Single-bit instructions (XTheadBs) + +[NOTE,caption=Frozen] +The `XTheadBs` extension is `stable`. + +The `XTheadBs` ISA extension provides instructions to access a single bit in a register. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.tst _rd_, _rs1_, _imm6_ | <<#xtheadbs-insns-tst>> +|=== + +[#xtheadbs-insns,reftext="Instructions"] +=== Instructions +include::xtheadbs/tst.adoc[] diff --git a/xtheadbs/tst.adoc b/xtheadbs/tst.adoc new file mode 100644 index 0000000..1654870 --- /dev/null +++ b/xtheadbs/tst.adoc @@ -0,0 +1,48 @@ +[#xtheadbs-insns-tst,reftext=Test bit] +==== th.tst + +Synopsis:: +Tests if a single bit is set. + +Mnemonic:: +th.tst _rd_, _rs1_, _imm6_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 6, name: 'rs2' }, + { bits: 6, name: 0x22 }, +]} +.... + +Description:: +This instruction tests if a single bit is set. +If so, _rd_ will be set to 1. Otherwise, _rd_ will be set to 0. + +Operation:: +[source,sail] +-- +if (reg[rs1] & (1 << imm6)) + rd := 1 +else + rd := 0 +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadBs (<<#xtheadbs>>) +|=== diff --git a/xtheadcmo.adoc b/xtheadcmo.adoc new file mode 100644 index 0000000..79b867f --- /dev/null +++ b/xtheadcmo.adoc @@ -0,0 +1,86 @@ +[#xtheadcmo] +== Cache Management Operations (XTheadCmo) + +[NOTE,caption=Frozen] +The `XTheadCmo` extension is `stable`. + +The `XTheadCmo` ISA extension provides cache management operations. + +The table below gives an overview of the instructions: + +[cols="^3,^3,10,18,12",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction | HW requirements +| Y | Y | th.dcache.call | <<#insns-xtheadcmo-dcache_call>> | D-cache +| Y | Y | th.dcache.ciall | <<#insns-xtheadcmo-dcache_ciall>> | D-cache +| Y | Y | th.dcache.iall | <<#insns-xtheadcmo-dcache_call>> | D-cache +| Y | Y | th.dcache.cpa _rs1_ | <<#insns-xtheadcmo-dcache_cpa>> | D-cache +| Y | Y | th.dcache.cipa _rs1_ | <<#insns-xtheadcmo-dcache_cipa>> | D-cache +| Y | Y | th.dcache.ipa _rs1_ | <<#insns-xtheadcmo-dcache_ipa>> | D-cache +| Y | Y | th.dcache.cva _rs1_ | <<#insns-xtheadcmo-dcache_cva>> | D-cache, MMU +| Y | Y | th.dcache.civa _rs1_ | <<#insns-xtheadcmo-dcache_civa>> | D-cache, MMU +| Y | Y | th.dcache.iva _rs1_ | <<#insns-xtheadcmo-dcache_iva>> | D-cache, MMU +| Y | Y | th.dcache.csw _rs1_ | <<#insns-xtheadcmo-dcache_csw>> | D-cache +| Y | Y | th.dcache.cisw _rs1_ | <<#insns-xtheadcmo-dcache_cisw>> | D-cache +| Y | Y | th.dcache.isw _rs1_ | <<#insns-xtheadcmo-dcache_isw>> | D-cache +| Y | Y | th.dcache.cpal1 _rs1_ | <<#insns-xtheadcmo-dcache_cpal1>> | D-cache, 2nd level cache +| Y | Y | th.dcache.cval1 _rs1_ | <<#insns-xtheadcmo-dcache_cval1>> | D-cache, 2nd level cache, MMU +| Y | Y | th.icache.iall | <<#insns-xtheadcmo-icache_iall>> | I-cache +| Y | Y | th.icache.ialls | <<#insns-xtheadcmo-icache_ialls>> | I-cache, multicore +| Y | Y | th.icache.ipa _rs1_ | <<#insns-xtheadcmo-icache_ipa>> | I-cache +| Y | Y | th.icache.iva _rs1_ | <<#insns-xtheadcmo-icache_iva>> | I-cache, MMU +| Y | Y | th.l2cache.call | <<#insns-xtheadcmo-l2cache_call>> | D/I-cache, 2nd level cache +| Y | Y | th.l2cache.ciall | <<#insns-xtheadcmo-l2cache_ciall>> | D/I-cache, 2nd level cache +| Y | Y | th.l2cache.iall | <<#insns-xtheadcmo-l2cache_iall>> | D/I-cache, 2nd level cache +|=== + +The last column of the table above names the HW requirements of the instructions. +E.g. to clean the data cache using `dcache.call`, a D-cache is required. +Instructions that are executed without the required HW requirements available +(e.g. `l2cache.call` on a system without a L2 cache) do not chance any architecturally +visible state, except for advancing the program counter and incrementing any applicable +performance counters (i.e. it behaves like executing a `NOP` instruction). + +[#insns,reftext="Instructions"] +=== Instructions +include::xtheadcmo/dcache_call.adoc[] +<<< +include::xtheadcmo/dcache_ciall.adoc[] +<<< +include::xtheadcmo/dcache_iall.adoc[] +<<< +include::xtheadcmo/dcache_cpa.adoc[] +<<< +include::xtheadcmo/dcache_cipa.adoc[] +<<< +include::xtheadcmo/dcache_ipa.adoc[] +<<< +include::xtheadcmo/dcache_cva.adoc[] +<<< +include::xtheadcmo/dcache_civa.adoc[] +<<< +include::xtheadcmo/dcache_iva.adoc[] +<<< +include::xtheadcmo/dcache_csw.adoc[] +<<< +include::xtheadcmo/dcache_cisw.adoc[] +<<< +include::xtheadcmo/dcache_isw.adoc[] +<<< +include::xtheadcmo/dcache_cpal1.adoc[] +<<< +include::xtheadcmo/dcache_cval1.adoc[] +<<< +include::xtheadcmo/icache_iall.adoc[] +<<< +include::xtheadcmo/icache_ialls.adoc[] +<<< +include::xtheadcmo/icache_ipa.adoc[] +<<< +include::xtheadcmo/icache_iva.adoc[] +<<< +include::xtheadcmo/l2cache_call.adoc[] +<<< +include::xtheadcmo/l2cache_ciall.adoc[] +<<< +include::xtheadcmo/l2cache_iall.adoc[] diff --git a/xtheadcmo/dcache_call.adoc b/xtheadcmo/dcache_call.adoc new file mode 100644 index 0000000..c0c2eb5 --- /dev/null +++ b/xtheadcmo/dcache_call.adoc @@ -0,0 +1,55 @@ +[#insns-xtheadcmo-dcache_call,reftext=Clean all D-cache] +==== th.dcache.call + +Synopsis:: +Clean all D-cache + +Mnemonic:: +th.dcache.call + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x1, attr: ['dcache.call'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction cleans all cache lines of the data cache on the local hart. + +Dirty cache lines will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_ciall.adoc b/xtheadcmo/dcache_ciall.adoc new file mode 100644 index 0000000..dcbf750 --- /dev/null +++ b/xtheadcmo/dcache_ciall.adoc @@ -0,0 +1,55 @@ +[#insns-xtheadcmo-dcache_ciall,reftext=Clean & invalidate all D-cache] +==== th.dcache.ciall + +Synopsis:: +Clean & invalidate all D-cache + +Mnemonic:: +th.dcache.ciall + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x3, attr: ['dcache.ciall']}, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction cleans and invalidates all cache lines of the data cache on the local hart. +Dirty cache lines will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_cipa.adoc b/xtheadcmo/dcache_cipa.adoc new file mode 100644 index 0000000..6aeddcd --- /dev/null +++ b/xtheadcmo/dcache_cipa.adoc @@ -0,0 +1,55 @@ +[#insns-xtheadcmo-dcache_cipa,reftext=Clean & invalidate D-cache at PA] +==== th.dcache.cipa + +Synopsis:: +Clean and invalidate D-cache at PA + +Mnemonic:: +th.dcache.cipa _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0xB, attr: ['dcache.cipa'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction cleans and invalidates the cache lines that match the specified physical address in the D-cache. +If a cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_cisw.adoc b/xtheadcmo/dcache_cisw.adoc new file mode 100644 index 0000000..1c63641 --- /dev/null +++ b/xtheadcmo/dcache_cisw.adoc @@ -0,0 +1,86 @@ +[#insns-xtheadcmo-dcache_cisw,reftext=Clean & invalidate D-cache by set/way] +==== th.dcache.cisw + +Synopsis:: +Clean & invalidate D-cache by set/way + +Mnemonic:: +th.dcache.cisw _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x3, attr: ['dcache.cisw'] }, + { bits: 7, name: 0x01 }, +]} +.... + +The register content of `rs1` defines the set/way and has the following bit assignment: + +* rs1[64:31]...reserved (write `0`) +* rs1[31:32-w]...number of the way to operate on +* rs1[w-1:l+s]...reserved (write `0`) +* rs1[l+s-1:l]...number of the set to operate on +* rs1[l-1:4]...reserved (write `0`) +* rs1[3:1]...cache level to operate on (`0` for L1 cache, `1` for L2 cache, etc.) +* rs1[0]...reserved (write `0`) + +The bit positions to specify the set and the way to operate on depend on the actual cache implementation. +There are three cache properties that need to be considered: + +* `nways` (number of ways) +* `nsets` (number of sets) +* `linesize` (size of a cache line in bytes) + +Derived from these numbers the following constants are defined: + +* `w := log2(nways)` +* `s := log2(nsets)` +* `l := log2(linesize)` + +E.g. a 64 KiB, 2-way set-associative cache (`w = 1`) with a cacheline size of 64 bytes (`l = 6`) +has 512 sets (`s = 9`) and needs to use the following bits to set the set and the way to operate on: + +* [31]...number of the way (`0` or `1`) +* [14:6] number of the set (`0`..`512`) + +//- + +Description:: +This instruction cleans and invalidates the cache line that matches the specified set/way in the D-cache. +If the cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_civa.adoc b/xtheadcmo/dcache_civa.adoc new file mode 100644 index 0000000..7d15d38 --- /dev/null +++ b/xtheadcmo/dcache_civa.adoc @@ -0,0 +1,49 @@ +[#insns-xtheadcmo-dcache_civa,reftext=Clean & invalidate D-cache at VA] +==== th.dcache.civa + +Synopsis:: +Clean and invalidate D-cache at VA + +Mnemonic:: +th.dcache.civa _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x7, attr: ['dcache.cipa'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction cleans and invalidates the cache lines that match the specified virtual address in the D-cache. +If a cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- + + +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache, MMU +|=== + diff --git a/xtheadcmo/dcache_cpa.adoc b/xtheadcmo/dcache_cpa.adoc new file mode 100644 index 0000000..45e941f --- /dev/null +++ b/xtheadcmo/dcache_cpa.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-dcache_cpa,reftext=Clean D-cache at PA] +==== th.dcache.cpa + +Synopsis:: +Clean D-cache at PA + +Mnemonic:: +th.dcache.cpa _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x9, attr: ['dcache.cpa'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction cleans the cache lines that match the specified physical address in the D-cache. +If a cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_cpal1.adoc b/xtheadcmo/dcache_cpal1.adoc new file mode 100644 index 0000000..cd56ae9 --- /dev/null +++ b/xtheadcmo/dcache_cpal1.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-dcache_cpal1,reftext=Clean L1 D-cache at PA] +==== th.dcache.cpal1 + +Synopsis:: +Clean L1 D-cache at PA + +Mnemonic:: +th.dcache.cpal1 _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x8, attr: ['dcache.cpal1'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction cleans the cache lines that match the specified physical address in the L1 D-cache. +If a cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache, 2nd level cache +|=== + diff --git a/xtheadcmo/dcache_csw.adoc b/xtheadcmo/dcache_csw.adoc new file mode 100644 index 0000000..aedfa23 --- /dev/null +++ b/xtheadcmo/dcache_csw.adoc @@ -0,0 +1,85 @@ +[#insns-xtheadcmo-dcache_csw,reftext=Clean D-cache by set/way] +==== th.dcache.csw + +Synopsis:: +Clean D-cache by set/way + +Mnemonic:: +th.dcache.csw _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x1, attr: ['dcache.csw'] }, + { bits: 7, name: 0x01 }, +]} +.... + +The register content of `rs1` defines the set/way and has the following bit assignment: + +* rs1[64:31]...reserved (write `0`) +* rs1[31:32-w]...number of the way to operate on +* rs1[w-1:l+s]...reserved (write `0`) +* rs1[l+s-1:l]...number of the set to operate on +* rs1[l-1:4]...reserved (write `0`) +* rs1[3:1]...cache level to operate on (`0` for L1 cache, `1` for L2 cache, etc.) +* rs1[0]...reserved (write `0`) + +The bit positions to specify the set and the way to operate on depend on the actual cache implementation. +There are three cache properties that need to be considered: + +* `nways` (number of ways) +* `nsets` (number of sets) +* `linesize` (size of a cache line in bytes) + +Derived from these numbers the following constants are defined: + +* `w := log2(nways)` +* `s := log2(nsets)` +* `l := log2(linesize)` + +E.g. a 64 KiB, 2-way set-associative cache (`w = 1`) with a cacheline size of 64 bytes (`l = 6`) +has 512 sets (`s = 9`) and needs to use the following bits to set the set and the way to operate on: + +* [31]...number of the way (`0` or `1`) +* [14:6] number of the set (`0`..`512`) + +//- + +Description:: +This instruction cleans the cache line that matches the specified set/way in the D-cache. +If the cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_cva.adoc b/xtheadcmo/dcache_cva.adoc new file mode 100644 index 0000000..82c60e1 --- /dev/null +++ b/xtheadcmo/dcache_cva.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-dcache_cva,reftext=Clean D-cache at VA] +==== th.dcache.cva + +Synopsis:: +Clean D-cache at VA + +Mnemonic:: +th.dcache.cva _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x5, attr: ['dcache.cva'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction cleans the cache lines that match the specified virtual address in the D-cache. +If a cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache, MMU +|=== + diff --git a/xtheadcmo/dcache_cval1.adoc b/xtheadcmo/dcache_cval1.adoc new file mode 100644 index 0000000..e69266d --- /dev/null +++ b/xtheadcmo/dcache_cval1.adoc @@ -0,0 +1,48 @@ +[#insns-xtheadcmo-dcache_cval1,reftext=Clean L1 D-cache at VA] +==== th.dcache.cval1 + +Synopsis:: +Clean L1 D-cache at VA + +Mnemonic:: +th.dcache.cval1 _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x4, attr: ['dcache.cval1'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction cleans the cache lines that match the specified virtual address in the L1 D-cache. +If a cache line is dirty it will be written back to the next-level storage. + +Operation:: +[source,sail] +-- + +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache, 2nd level cache, MMU +|=== + diff --git a/xtheadcmo/dcache_iall.adoc b/xtheadcmo/dcache_iall.adoc new file mode 100644 index 0000000..0d0bc4c --- /dev/null +++ b/xtheadcmo/dcache_iall.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-dcache_iall,reftext=Invalidate all D-cache] +==== th.dcache.iall + +Synopsis:: +Invalidate all D-cache + +Mnemonic:: +th.dcache.iall + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x2, attr: ['dcache.iall'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction invalidates all cache lines of the data cache on the local hart. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_ipa.adoc b/xtheadcmo/dcache_ipa.adoc new file mode 100644 index 0000000..8445974 --- /dev/null +++ b/xtheadcmo/dcache_ipa.adoc @@ -0,0 +1,53 @@ +[#insns-xtheadcmo-dcache_ipa,reftext=Invalidate D-cache at PA] +==== th.dcache.ipa + +Synopsis:: +Invalidate D-cache at PA + +Mnemonic:: +th.dcache.ipa _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0xA, attr: ['dcache.ipa'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction invalidates the cache lines that match the specified physical address in the D-cache. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_isw.adoc b/xtheadcmo/dcache_isw.adoc new file mode 100644 index 0000000..e736778 --- /dev/null +++ b/xtheadcmo/dcache_isw.adoc @@ -0,0 +1,85 @@ +[#insns-xtheadcmo-dcache_isw,reftext=Invalidate D-cache by set/way] +==== th.dcache.isw + +Synopsis:: +Invalidate D-cache by set/way + +Mnemonic:: +th.dcache.isw _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x2, attr: ['dcache.isw'] }, + { bits: 7, name: 0x01 }, +]} +.... + +The register content of `rs1` defines the set/way and has the following bit assignment: + +* rs1[64:31]...reserved (write `0`) +* rs1[31:32-w]...number of the way to operate on +* rs1[w-1:l+s]...reserved (write `0`) +* rs1[l+s-1:l]...number of the set to operate on +* rs1[l-1:4]...reserved (write `0`) +* rs1[3:1]...cache level to operate on (`0` for L1 cache, `1` for L2 cache, etc.) +* rs1[0]...reserved (write `0`) + +The bit positions to specify the set and the way to operate on depend on the actual cache implementation. +There are three cache properties that need to be considered: + +* `nways` (number of ways) +* `nsets` (number of sets) +* `linesize` (size of a cache line in bytes) + +Derived from these numbers the following constants are defined: + +* `w := log2(nways)` +* `s := log2(nsets)` +* `l := log2(linesize)` + +E.g. a 64 KiB, 2-way set-associative cache (`w = 1`) with a cacheline size of 64 bytes (`l = 6`) +has 512 sets (`s = 9`) and needs to use the following bits to set the set and the way to operate on: + +* [31]...number of the way (`0` or `1`) +* [14:6] number of the set (`0`..`512`) + +//- + +Description:: +This instruction invalidates the cache line that matches the specified set/way in the D-cache. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache +|=== + diff --git a/xtheadcmo/dcache_iva.adoc b/xtheadcmo/dcache_iva.adoc new file mode 100644 index 0000000..2abe857 --- /dev/null +++ b/xtheadcmo/dcache_iva.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-dcache_iva,reftext=Invalidate D-cache at VA] +==== th.dcache.iva + +Synopsis:: +Invalidate D-cache at VA + +Mnemonic:: +th.dcache.iva _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x6, attr: ['dcache.iva'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction invalidates the cache lines that match the specified virtual address in the D-cache. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D-cache, MMU +|=== + diff --git a/xtheadcmo/icache_iall.adoc b/xtheadcmo/icache_iall.adoc new file mode 100644 index 0000000..3200408 --- /dev/null +++ b/xtheadcmo/icache_iall.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-icache_iall,reftext=Invalidate all I-cache] +==== th.icache.iall + +Synopsis:: +Invalidate all I-cache + +Mnemonic:: +th.icache.iall + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x10, attr: ['iache.iall'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction invalidates all cache lines of the instruction cache on the local hart. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|I-cache +|=== + diff --git a/xtheadcmo/icache_ialls.adoc b/xtheadcmo/icache_ialls.adoc new file mode 100644 index 0000000..971eaa4 --- /dev/null +++ b/xtheadcmo/icache_ialls.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-icache_ialls,reftext=Invalidate all I-cache on all harts] +==== th.icache.ialls + +Synopsis:: +Invalidate all I-cache on all harts + +Mnemonic:: +th.icache.ialls + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x11, attr: ['iache.ialls'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction invalidates all cache lines of the instruction cache on all harts (using broadcasting). +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|I-cache +|=== + diff --git a/xtheadcmo/icache_ipa.adoc b/xtheadcmo/icache_ipa.adoc new file mode 100644 index 0000000..dba93f8 --- /dev/null +++ b/xtheadcmo/icache_ipa.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-icache_ipa,reftext=Invalidate I-cache at PA] +==== th.icache.ipa + +Synopsis:: +Invalidate I-cache at PA + +Mnemonic:: +th.icache.ipa _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x18, attr: ['icache.ipa'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction invalidates the cache lines that match the specified physical address in the I-cache. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|I-cache +|=== + diff --git a/xtheadcmo/icache_iva.adoc b/xtheadcmo/icache_iva.adoc new file mode 100644 index 0000000..f79a3bf --- /dev/null +++ b/xtheadcmo/icache_iva.adoc @@ -0,0 +1,48 @@ +[#insns-xtheadcmo-icache_iva,reftext=Invalidate I-cache at VA] +==== th.icache.iva + +Synopsis:: +Invalidate I-cache at VA + +Mnemonic:: +th.icache.iva _rs1_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 0x10, attr: ['icache.iva'] }, + { bits: 7, name: 0x01 }, +]} +.... + +Description:: +This instruction invalidates the cache lines that match the specified virtual address in the I-cache. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- + +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|I-cache, MMU +|=== + diff --git a/xtheadcmo/l2cache_call.adoc b/xtheadcmo/l2cache_call.adoc new file mode 100644 index 0000000..bd11935 --- /dev/null +++ b/xtheadcmo/l2cache_call.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-l2cache_call,reftext=Clean all L2 cache] +==== th.l2cache.call + +Synopsis:: +Clean all L2 cache + +Mnemonic:: +th.l2cache.call + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x15, attr: ['l2cache.call'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction cleans all cache lines of the L2 cache. +Dirty cache lines will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D/I-cache, 2nd level cache +|=== + diff --git a/xtheadcmo/l2cache_ciall.adoc b/xtheadcmo/l2cache_ciall.adoc new file mode 100644 index 0000000..06b0ca3 --- /dev/null +++ b/xtheadcmo/l2cache_ciall.adoc @@ -0,0 +1,55 @@ +[#insns-xtheadcmo-l2cache_ciall,reftext=Clean & invalidate all L2 cache] +==== th.l2cache.ciall + +Synopsis:: +Clean & invalidate all L2 cache + +Mnemonic:: +th.l2cache.ciall + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x17, attr: ['l2cache.ciall']}, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction cleans and invalidates all cache lines of the L2 cache. +Dirty cache lines will be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D/I-cache, 2nd level cache +|=== + diff --git a/xtheadcmo/l2cache_iall.adoc b/xtheadcmo/l2cache_iall.adoc new file mode 100644 index 0000000..2fc0ff4 --- /dev/null +++ b/xtheadcmo/l2cache_iall.adoc @@ -0,0 +1,54 @@ +[#insns-xtheadcmo-l2cache_iall,reftext=Invalidate all L2 cache] +==== th.ll2cache.iall + +Synopsis:: +Invalidate all L2 cache + +Mnemonic:: +th.l2cache.iall + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x16, attr: ['l2cache.iall'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction invalidates all cache lines of the L2 cache. +Dirty cache lines will not be written back to the next-level storage. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + + +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header,cols="4,2"] +|=== +|Extension +|HW requirements + +|XTheadCmo (<<#xtheadcmo>>) +|D/I-cache, 2nd level cache +|=== + diff --git a/xtheadcondmov.adoc b/xtheadcondmov.adoc new file mode 100644 index 0000000..f50d150 --- /dev/null +++ b/xtheadcondmov.adoc @@ -0,0 +1,22 @@ +[#xtheadcondmov] +== Conditional move (XTheadCondMov) + +[NOTE,caption=Frozen] +The `XTheadCondMov` extension is `stable`. + +The `XTheadCondMov` ISA extension provides conditional move instructions. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.mveqz _rd_, _rs1_, _rs2_ | <<#xtheadcondmov-insns-mveqz>> +| Y | Y | th.mvnez _rd_, _rs1_, _rs2_ | <<#xtheadcondmov-insns-mvnez>> +|=== + +[#xtheadcondmov-insns,reftext="Instructions"] +=== Instructions +include::xtheadcondmov/mveqz.adoc[] +<<< +include::xtheadcondmov/mvnez.adoc[] diff --git a/xtheadcondmov/mveqz.adoc b/xtheadcondmov/mveqz.adoc new file mode 100644 index 0000000..e1a0123 --- /dev/null +++ b/xtheadcondmov/mveqz.adoc @@ -0,0 +1,46 @@ +[#xtheadcondmov-insns-mveqz,reftext=Move if equal zero] +==== th.mveqz + +Synopsis:: +Move if equal zero. + +Mnemonic:: +th.mveqz _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x00 }, + { bits: 5, name: 0x08 }, +]} +.... + +Description:: +This instruction moves the content of register _rs1_ into _rd_ if the content of _rs2_ is 0x0. Otherwise, the value of _rd_ does not change. + +Operation:: +[source,sail] +-- +if (reg[rs2] == 0x0) + reg[rd] := reg[rs1] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadCondMov (<<#xtheadcondmov>>) +|=== diff --git a/xtheadcondmov/mvnez.adoc b/xtheadcondmov/mvnez.adoc new file mode 100644 index 0000000..7aefa09 --- /dev/null +++ b/xtheadcondmov/mvnez.adoc @@ -0,0 +1,46 @@ +[#xtheadcondmov-insns-mvnez,reftext=Move if not equal zero] +==== th.mvnez + +Synopsis:: +Move if not equal zero. + +Mnemonic:: +th.mvnez _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x01 }, + { bits: 5, name: 0x08 }, +]} +.... + +Description:: +This instruction moves the content of register _rs1_ into _rd_ if the content of _rs2_ is not 0x0. Otherwise, the value of _rd_ does not change. + +Operation:: +[source,sail] +-- +if (reg[rs2] != 0x0) + reg[rd] := reg[rs1] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadCondMov (<<#xtheadcondmov>>) +|=== diff --git a/xtheadfmemidx.adoc b/xtheadfmemidx.adoc new file mode 100644 index 0000000..ee65342 --- /dev/null +++ b/xtheadfmemidx.adoc @@ -0,0 +1,46 @@ +[#xtheadfmemidx] +== Indexed memory operations for floating-point registers (XTheadFMemIdx) + +[NOTE,caption=Frozen] +The `XTheadFMemIdx` extension is `stable`. + +The `XTheadFMemIdx` ISA extension provides indexed memory operations +for floating-point registers. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| F | D | Mnemonic | Instruction +| Y | Y | th.flrd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-flrd>> +| Y | Y | th.flrw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-flrw>> +| N | Y | th.flurd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-flurd>> +| N | Y | th.flurw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-flurw>> +| Y | Y | th.fsrd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-fsrd>> +| Y | Y | th.fsrw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-flrw>> +| N | Y | th.fsurd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-fsurd>> +| N | Y | th.fsurw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadfmemidx-insns-flurw>> +|=== + +All instructions are available for `RV32` and `RV64`. +Additionally at least the `F` extension needs to be available. +In order to have all instructions available, the `D` extensions +needs to be implemented. + +[#xtheadfmemidx-insns,reftext="Instructions"] +=== Instructions +include::xtheadfmemidx/flrd.adoc[] +<<< +include::xtheadfmemidx/flrw.adoc[] +<<< +include::xtheadfmemidx/flurd.adoc[] +<<< +include::xtheadfmemidx/flurw.adoc[] +<<< +include::xtheadfmemidx/fsrd.adoc[] +<<< +include::xtheadfmemidx/fsrw.adoc[] +<<< +include::xtheadfmemidx/fsurd.adoc[] +<<< +include::xtheadfmemidx/fsurw.adoc[] diff --git a/xtheadfmemidx/flrd.adoc b/xtheadfmemidx/flrd.adoc new file mode 100644 index 0000000..f9d4f4e --- /dev/null +++ b/xtheadfmemidx/flrd.adoc @@ -0,0 +1,47 @@ +[#xtheadfmemidx-insns-flrd,reftext=Load indexed double] +==== th.flrd + +Synopsis:: +Load indexed double-precision floating point value. + +Mnemonic:: +th.flrd _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['FMem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0c }, +]} +.... + +Description:: +This instruction loads a double-precision floating point value into FP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := fmem[addr+7:addr] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `FLD` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/flrw.adoc b/xtheadfmemidx/flrw.adoc new file mode 100644 index 0000000..f6d5ce6 --- /dev/null +++ b/xtheadfmemidx/flrw.adoc @@ -0,0 +1,49 @@ +[#xtheadfmemidx-insns-flrw,reftext=Load indexed float] +==== th.flrw + +Synopsis:: +Load indexed single-precision floating point value. + +Mnemonic:: +th.flrw _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['FMem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x08 }, +]} +.... + +Description:: +This instruction loads a single-precision floating point value into FP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +If the `D` extension is available the value will be one-extended. + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := one_extend(fmem[addr+3:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `FLW` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/flurd.adoc b/xtheadfmemidx/flurd.adoc new file mode 100644 index 0000000..cd85b63 --- /dev/null +++ b/xtheadfmemidx/flurd.adoc @@ -0,0 +1,49 @@ +[#xtheadfmemidx-insns-flurd,reftext=Load unsigned indexed double] +==== th.flurd + +Synopsis:: +Load unsigned indexed double-precision floating point value. + +Mnemonic:: +th.flurd _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['FMem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0e }, +]} +.... + +Description:: +This instruction loads a double-precision floating point value into FP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.flrd` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := fmem[addr+7:addr] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `FLD` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/flurw.adoc b/xtheadfmemidx/flurw.adoc new file mode 100644 index 0000000..e29c307 --- /dev/null +++ b/xtheadfmemidx/flurw.adoc @@ -0,0 +1,51 @@ +[#xtheadfmemidx-insns-flurw,reftext=Load unsigned indexed float] +==== th.flurw + +Synopsis:: +Load unsigned indexed single-precision floating point value. + +Mnemonic:: +th.flurw _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x6, attr: ['FMem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0a }, +]} +.... + +Description:: +This instruction loads a single-precision floating point value into FP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +If the `D` extension is available the value will be one-extended. + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.flrw` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := one_extend(fmem[addr+3:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `FLW` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/fsrd.adoc b/xtheadfmemidx/fsrd.adoc new file mode 100644 index 0000000..e650b99 --- /dev/null +++ b/xtheadfmemidx/fsrd.adoc @@ -0,0 +1,47 @@ +[#xtheadfmemidx-insns-fsrd,reftext=Store indexed double] +==== th.fsrd + +Synopsis:: +Store indexed double-precision floating point value. + +Mnemonic:: +th.fsrd _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['FMem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0c }, +]} +.... + +Description:: +This instruction stores a double-precision floating point value from the FP register _rd_ to the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +fmem[addr+7:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `FSD` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/fsrw.adoc b/xtheadfmemidx/fsrw.adoc new file mode 100644 index 0000000..083c93f --- /dev/null +++ b/xtheadfmemidx/fsrw.adoc @@ -0,0 +1,47 @@ +[#xtheadfmemidx-insns-fsrw,reftext=Store indexed float] +==== th.fsrw + +Synopsis:: +Store indexed single-precision floating point value. + +Mnemonic:: +th.fsrw _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['FMem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x08 }, +]} +.... + +Description:: +This instruction stores a single-precision floating point value from the FP register _rd_ to the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +fmem[addr+3:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `FSW` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/fsurd.adoc b/xtheadfmemidx/fsurd.adoc new file mode 100644 index 0000000..6ca3bff --- /dev/null +++ b/xtheadfmemidx/fsurd.adoc @@ -0,0 +1,49 @@ +[#xtheadfmemidx-insns-fsurd,reftext=Store unsigned indexed double] +==== th.fsurd + +Synopsis:: +Store unsigned indexed double-precision floating point value. + +Mnemonic:: +th.fsurd _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['FMem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0e }, +]} +.... + +Description:: +This instruction stores a double-precision floating point value from FP register _rd_ to the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.fsrd` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +fmem[addr+7:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `FSD` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadfmemidx/fsurw.adoc b/xtheadfmemidx/fsurw.adoc new file mode 100644 index 0000000..d5a3c3b --- /dev/null +++ b/xtheadfmemidx/fsurw.adoc @@ -0,0 +1,49 @@ +[#xtheadfmemidx-insns-fsurw,reftext=Store unsigned indexed float] +==== th.fsurw + +Synopsis:: +Store unsigned indexed single-precision floating point value. + +Mnemonic:: +th.fsurw _rd_, _rs1_, _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x7, attr: ['FMem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0a }, +]} +.... + +Description:: +This instruction stores a single-precision floating point value from FP register _rd_ to the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.fsrw` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +fmem[addr+3:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `FLW` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadFMemIdx (<<#xtheadfmemidx>>) +|=== + diff --git a/xtheadmac.adoc b/xtheadmac.adoc new file mode 100644 index 0000000..cf970f4 --- /dev/null +++ b/xtheadmac.adoc @@ -0,0 +1,34 @@ +[#xtheadmac] +== Multiply-accumulate instructions (XTheadMac) + +[NOTE,caption=Frozen] +The `XTheadMac` extension is `stable`. + +The `XTheadMac` ISA extension provides multiply-accumulate instructions. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.mula _rd_, _rs1_, _rs2_ | <<#xtheadmac-insns-mula>> +| Y | Y | th.mulah _rd_, _rs1_, _rs2_ | <<#xtheadmac-insns-mulah>> +| N | Y | th.mulaw _rd_, _rs1_, _rs2_ | <<#xtheadmac-insns-mulaw>> +| Y | Y | th.muls _rd_, _rs1_, _rs2_ | <<#xtheadmac-insns-muls>> +| Y | Y | th.mulsh _rd_, _rs1_, _rs2_ | <<#xtheadmac-insns-mulsh>> +| Y | Y | th.mulsw _rd_, _rs1_, _rs2_ | <<#xtheadmac-insns-mulsw>> +|=== + +[#xtheadmac-insns,reftext="Instructions"] +=== Instructions +include::xtheadmac/mula.adoc[] +<<< +include::xtheadmac/mulah.adoc[] +<<< +include::xtheadmac/mulaw.adoc[] +<<< +include::xtheadmac/muls.adoc[] +<<< +include::xtheadmac/mulsh.adoc[] +<<< +include::xtheadmac/mulsw.adoc[] diff --git a/xtheadmac/mula.adoc b/xtheadmac/mula.adoc new file mode 100644 index 0000000..653becf --- /dev/null +++ b/xtheadmac/mula.adoc @@ -0,0 +1,46 @@ +[#xtheadmac-insns-mula,reftext=Multiply-add double-words] +==== th.mula + +Synopsis:: +Compute multiply-add result of double-word operands. + +Mnemonic:: +th.mula _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x0 }, + { bits: 5, name: 0x04 }, +]} +.... + +Description:: +This instruction computes the multiply-add result of the provided double-word operands. + +Operation:: +[source,sail] +-- +M := reg[rs1] * reg[rs2] +reg[rd] := zext.d(reg[rd] + M) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMac (<<#xtheadmac>>) +|=== diff --git a/xtheadmac/mulah.adoc b/xtheadmac/mulah.adoc new file mode 100644 index 0000000..8712087 --- /dev/null +++ b/xtheadmac/mulah.adoc @@ -0,0 +1,46 @@ +[#xtheadmac-insns-mulah,reftext=Multiply-add half-words] +==== th.mulah + +Synopsis:: +Compute multiply-add result of half-word operands. + +Mnemonic:: +th.mulah _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x0 }, + { bits: 5, name: 0x05 }, +]} +.... + +Description:: +This instruction computes the multiply-add result of the provided half-word operands. + +Operation:: +[source,sail] +-- +M := zext.h(reg[rs1]) * zext.h(reg[rs2]) +reg[rd] := sext.w(zext.w(reg[rd] + M)) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMac (<<#xtheadmac>>) +|=== diff --git a/xtheadmac/mulaw.adoc b/xtheadmac/mulaw.adoc new file mode 100644 index 0000000..80aed01 --- /dev/null +++ b/xtheadmac/mulaw.adoc @@ -0,0 +1,46 @@ +[#xtheadmac-insns-mulaw,reftext=Multiply-add words] +==== th.mulaw + +Synopsis:: +Compute multiply-add result of word operands. + +Mnemonic:: +th.mulaw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x2 }, + { bits: 5, name: 0x04 }, +]} +.... + +Description:: +This instruction computes the multiply-add result of the provided word operands. + +Operation:: +[source,sail] +-- +M := zext.w(reg[rs1]) * zext.w(reg[rs2]) +reg[rd] := sext.w(zext.w(reg[rd] + M)) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMac (<<#xtheadmac>>) +|=== diff --git a/xtheadmac/muls.adoc b/xtheadmac/muls.adoc new file mode 100644 index 0000000..28df4b5 --- /dev/null +++ b/xtheadmac/muls.adoc @@ -0,0 +1,46 @@ +[#xtheadmac-insns-muls,reftext=Multiply-subtract double-words] +==== th.muls + +Synopsis:: +Compute multiply-subtract result of double-word operands. + +Mnemonic:: +th.muls _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x1 }, + { bits: 5, name: 0x04 }, +]} +.... + +Description:: +This instruction computes the multiply-subtract result of the provided double-word operands. + +Operation:: +[source,sail] +-- +M := reg[rs1] * reg[rs2] +reg[rd] := zext.d(reg[rd] - M) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMac (<<#xtheadmac>>) +|=== diff --git a/xtheadmac/mulsh.adoc b/xtheadmac/mulsh.adoc new file mode 100644 index 0000000..13d5ccc --- /dev/null +++ b/xtheadmac/mulsh.adoc @@ -0,0 +1,46 @@ +[#xtheadmac-insns-mulsh,reftext=Multiply-subtract half-words] +==== th.mulsh + +Synopsis:: +Compute multiply-subtract result of half-word operands. + +Mnemonic:: +th.mulsh _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x01 }, + { bits: 5, name: 0x05 }, +]} +.... + +Description:: +This instruction computes the multiply-subtract result of the provided half-word operands. + +Operation:: +[source,sail] +-- +M := zext.h(reg[rs1]) * zext.h(reg[rs2]) +reg[rd] := sext.w(zext.w(reg[rd] - M)) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMac (<<#xtheadmac>>) +|=== diff --git a/xtheadmac/mulsw.adoc b/xtheadmac/mulsw.adoc new file mode 100644 index 0000000..32f1fab --- /dev/null +++ b/xtheadmac/mulsw.adoc @@ -0,0 +1,46 @@ +[#xtheadmac-insns-mulsw,reftext=Multiply-subtract words] +==== th.mulsw + +Synopsis:: +Compute multiply-subtract result of word operands. + +Mnemonic:: +th.mulsw _rd_, _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x1, attr: ['Arithmetic'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 0x03 }, + { bits: 5, name: 0x04 }, +]} +.... + +Description:: +This instruction computes the multiply-subtract result of the provided word operands. + +Operation:: +[source,sail] +-- +M := zext.w(reg[rs1]) * zext.w(reg[rs2]) +reg[rd] := sext.w(zext.w(reg[rd] - M)) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMac (<<#xtheadmac>>) +|=== diff --git a/xtheadmemidx.adoc b/xtheadmemidx.adoc new file mode 100644 index 0000000..120213c --- /dev/null +++ b/xtheadmemidx.adoc @@ -0,0 +1,149 @@ +[#xtheadmemidx] +== Indexed memory operations (XTheadMemIdx) + +[NOTE,caption=Frozen] +The `XTheadMemIdx` extension is `stable`. + +The `XTheadMemIdx` ISA extension provides indexed memory operations. +for GP registers. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.lbia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lbia>> +| Y | Y | th.lbib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lbib>> +| Y | Y | th.lbuia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lbuia>> +| Y | Y | th.lbuib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lbuib>> +| Y | Y | th.lhia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lhia>> +| Y | Y | th.lhib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lhib>> +| Y | Y | th.lhuia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lhuia>> +| Y | Y | th.lhuib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lhuib>> +| Y | Y | th.lwia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lwia>> +| Y | Y | th.lwib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lwib>> +| N | Y | th.lwuia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lwuia>> +| N | Y | th.lwuib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-lwuib>> +| N | Y | th.ldia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-ldia>> +| N | Y | th.ldib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-ldib>> +| Y | Y | th.sbia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-sbia>> +| Y | Y | th.sbib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-sbib>> +| Y | Y | th.shia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-shia>> +| Y | Y | th.shib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-shib>> +| Y | Y | th.swia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-swia>> +| Y | Y | th.swib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-swib>> +| N | Y | th.sdia _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-sdia>> +| N | Y | th.sdib _rd_, (_rs1_), _imm5_, _imm2_ | <<#xtheadmemidx-insns-sdib>> +| Y | Y | th.lrb _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrb>> +| Y | Y | th.lrbu _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrbu>> +| Y | Y | th.lrh _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrh>> +| Y | Y | th.lrhu _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrhu>> +| Y | Y | th.lrw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrw>> +| N | Y | th.lrwu _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrwu>> +| N | Y | th.lrd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lrd>> +| Y | Y | th.srb _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-srb>> +| Y | Y | th.srh _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-srh>> +| Y | Y | th.srw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-srw>> +| N | Y | th.srd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-srd>> +| Y | Y | th.lurb _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurb>> +| Y | Y | th.lurbu _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurbu>> +| Y | Y | th.lurh _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurh>> +| Y | Y | th.lurhu _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurhu>> +| Y | Y | th.lurw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurw>> +| N | Y | th.lurwu _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurwu>> +| N | Y | th.lurd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-lurd>> +| Y | Y | th.surb _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-surb>> +| Y | Y | th.surh _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-surh>> +| Y | Y | th.surw _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-surw>> +| N | Y | th.surd _rd_, _rs1_, _rs2_, _imm2_ | <<#xtheadmemidx-insns-surd>> +|=== + +[#xtheadmemidx-insns,reftext="Instructions"] +=== Instructions +include::xtheadmemidx/lbia.adoc[] +<<< +include::xtheadmemidx/lbib.adoc[] +<<< +include::xtheadmemidx/lbuia.adoc[] +<<< +include::xtheadmemidx/lbuib.adoc[] +<<< +include::xtheadmemidx/lhia.adoc[] +<<< +include::xtheadmemidx/lhib.adoc[] +<<< +include::xtheadmemidx/lhuia.adoc[] +<<< +include::xtheadmemidx/lhuib.adoc[] +<<< +include::xtheadmemidx/lwia.adoc[] +<<< +include::xtheadmemidx/lwib.adoc[] +<<< +include::xtheadmemidx/lwuia.adoc[] +<<< +include::xtheadmemidx/lwuib.adoc[] +<<< +include::xtheadmemidx/ldia.adoc[] +<<< +include::xtheadmemidx/ldib.adoc[] +<<< +include::xtheadmemidx/sbia.adoc[] +<<< +include::xtheadmemidx/sbib.adoc[] +<<< +include::xtheadmemidx/shia.adoc[] +<<< +include::xtheadmemidx/shib.adoc[] +<<< +include::xtheadmemidx/swia.adoc[] +<<< +include::xtheadmemidx/swib.adoc[] +<<< +include::xtheadmemidx/sdia.adoc[] +<<< +include::xtheadmemidx/sdib.adoc[] +<<< +include::xtheadmemidx/lrb.adoc[] +<<< +include::xtheadmemidx/lrbu.adoc[] +<<< +include::xtheadmemidx/lrh.adoc[] +<<< +include::xtheadmemidx/lrhu.adoc[] +<<< +include::xtheadmemidx/lrw.adoc[] +<<< +include::xtheadmemidx/lrwu.adoc[] +<<< +include::xtheadmemidx/lrd.adoc[] +<<< +include::xtheadmemidx/srb.adoc[] +<<< +include::xtheadmemidx/srh.adoc[] +<<< +include::xtheadmemidx/srw.adoc[] +<<< +include::xtheadmemidx/srd.adoc[] +<<< +include::xtheadmemidx/lurb.adoc[] +<<< +include::xtheadmemidx/lurbu.adoc[] +<<< +include::xtheadmemidx/lurh.adoc[] +<<< +include::xtheadmemidx/lurhu.adoc[] +<<< +include::xtheadmemidx/lurw.adoc[] +<<< +include::xtheadmemidx/lurwu.adoc[] +<<< +include::xtheadmemidx/lurd.adoc[] +<<< +include::xtheadmemidx/surb.adoc[] +<<< +include::xtheadmemidx/surh.adoc[] +<<< +include::xtheadmemidx/surw.adoc[] +<<< +include::xtheadmemidx/surd.adoc[] diff --git a/xtheadmemidx/lbia.adoc b/xtheadmemidx/lbia.adoc new file mode 100644 index 0000000..cda4c76 --- /dev/null +++ b/xtheadmemidx/lbia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lbia,reftext=Load indexed byte, increment-after] +==== th.lbia + +Synopsis:: +Load indexed byte, increment address after loading. + +Mnemonic:: +th.lbia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x03 }, +]} +.... + +Description:: +This instruction loads a sign extended 8-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rd := sign_extend(mem[rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lbib.adoc b/xtheadmemidx/lbib.adoc new file mode 100644 index 0000000..c7f70f5 --- /dev/null +++ b/xtheadmemidx/lbib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lbib,reftext=Load indexed byte, increment-before] +==== th.lbib + +Synopsis:: +Load indexed byte, increment address before loading. + +Mnemonic:: +th.lbib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x01 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a sign extended 8-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := sign_extend(mem[rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lbuia.adoc b/xtheadmemidx/lbuia.adoc new file mode 100644 index 0000000..56c83db --- /dev/null +++ b/xtheadmemidx/lbuia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lbuia,reftext=Load indexed unsigned byte, increment-after] +==== th.lbuia + +Synopsis:: +Load indexed unsigned byte, increment address after loading. + +Mnemonic:: +th.lbuia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x13 }, +]} +.... + +Description:: +This instruction loads a zero extended 8-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs := zero_extend(mem[rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LBU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lbuib.adoc b/xtheadmemidx/lbuib.adoc new file mode 100644 index 0000000..2568a04 --- /dev/null +++ b/xtheadmemidx/lbuib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lbuib,reftext=Load indexed unsigned byte, increment-before] +==== th.lbuib + +Synopsis:: +Load indexed unsigned byte, increment address before loading. + +Mnemonic:: +th.lbuib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x11 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a zero extended 8-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := zero_extend(mem[rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LBU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/ldia.adoc b/xtheadmemidx/ldia.adoc new file mode 100644 index 0000000..c9e0a73 --- /dev/null +++ b/xtheadmemidx/ldia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-ldia,reftext=Load indexed double-word, increment-after] +==== th.ldia + +Synopsis:: +Load indexed double-word, increment address after loading. + +Mnemonic:: +th.ldia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0f }, +]} +.... + +Description:: +This instruction loads a sign extended 64-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rd := sign_extend(mem[rs1+7:rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/ldib.adoc b/xtheadmemidx/ldib.adoc new file mode 100644 index 0000000..3b33bd4 --- /dev/null +++ b/xtheadmemidx/ldib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-ldib,reftext=Load indexed double-word, increment-before] +==== th.ldib + +Synopsis:: +Load indexed double-word, increment address before loading. + +Mnemonic:: +th.lwib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0d }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a sign extended 64-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := sign_extend(mem[rs1+7:rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lhia.adoc b/xtheadmemidx/lhia.adoc new file mode 100644 index 0000000..8411842 --- /dev/null +++ b/xtheadmemidx/lhia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lhia,reftext=Load indexed half-word, increment-after] +==== th.lhia + +Synopsis:: +Load indexed half-word, increment address after loading. + +Mnemonic:: +th.lhia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x07 }, +]} +.... + +Description:: +This instruction loads a sign extended 16-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rd := sign_extend(mem[rs1+1:rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lhib.adoc b/xtheadmemidx/lhib.adoc new file mode 100644 index 0000000..f11393b --- /dev/null +++ b/xtheadmemidx/lhib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lhib,reftext=Load indexed half-word, increment-before] +==== th.lhib + +Synopsis:: +Load indexed half-word, increment address before loading. + +Mnemonic:: +th.lhib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x05 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a sign extended 16-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := sign_extend(mem[rs1+1:rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lhuia.adoc b/xtheadmemidx/lhuia.adoc new file mode 100644 index 0000000..e5bfe26 --- /dev/null +++ b/xtheadmemidx/lhuia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lhuia,reftext=Load indexed unsigned half-word, increment-after] +==== th.lhuia + +Synopsis:: +Load indexed unsigned half-word, increment address after loading. + +Mnemonic:: +th.lhuia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x17 }, +]} +.... + +Description:: +This instruction loads a zero extended 16-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rd := zero_extend(mem[rs1+1:rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LHU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lhuib.adoc b/xtheadmemidx/lhuib.adoc new file mode 100644 index 0000000..df7fec0 --- /dev/null +++ b/xtheadmemidx/lhuib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lhuib,reftext=Load indexed unsigned half-word, increment-before] +==== th.lhuib + +Synopsis:: +Load indexed unsigned half-word, increment address before loading. + +Mnemonic:: +th.lhuib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x15 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a zero extended 16-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := zero_extend(mem[rs1+1:rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LHU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lrb.adoc b/xtheadmemidx/lrb.adoc new file mode 100644 index 0000000..50ca338 --- /dev/null +++ b/xtheadmemidx/lrb.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-lrb,reftext=Load indexed byte] +==== th.lrb + +Synopsis:: +Load indexed byte. + +Mnemonic:: +th.lrb _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x00 }, +]} +.... + +Description:: +This instruction loads a sign extended 8-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := sign_extend(mem[addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/lrbu.adoc b/xtheadmemidx/lrbu.adoc new file mode 100644 index 0000000..a31eb76 --- /dev/null +++ b/xtheadmemidx/lrbu.adoc @@ -0,0 +1,47 @@ +[#xtheadmemidx-insns-lrbu,reftext=Load indexed unsigned byte] +==== th.lrbu + +Synopsis:: +Load indexed unsigned byte. + +Mnemonic:: +th.lrbu _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x10 }, +]} +.... + +Description:: +This instruction loads a zero extended 8-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := zero_extend(mem[addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LBU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lrd.adoc b/xtheadmemidx/lrd.adoc new file mode 100644 index 0000000..e4fe51a --- /dev/null +++ b/xtheadmemidx/lrd.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-lrd,reftext=Load indexed double-word] +==== th.lrd + +Synopsis:: +Load indexed word. + +Mnemonic:: +th.lrd _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0c }, +]} +.... + +Description:: +This instruction loads a sign extended 64-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := sign_extend(mem[addr+7:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/lrh.adoc b/xtheadmemidx/lrh.adoc new file mode 100644 index 0000000..a7bc981 --- /dev/null +++ b/xtheadmemidx/lrh.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-lrh,reftext=Load indexed half-word] +==== th.lrh + +Synopsis:: +Load indexed half-word. + +Mnemonic:: +th.lrh _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x04 }, +]} +.... + +Description:: +This instruction loads a sign extended 16-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := sign_extend(mem[addr+1:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/lrhu.adoc b/xtheadmemidx/lrhu.adoc new file mode 100644 index 0000000..9f52eb6 --- /dev/null +++ b/xtheadmemidx/lrhu.adoc @@ -0,0 +1,47 @@ +[#xtheadmemidx-insns-lrhu,reftext=Load indexed unsigned half-word] +==== th.lrhu + +Synopsis:: +Load indexed unsigned half-word. + +Mnemonic:: +th.lrhu _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x14 }, +]} +.... + +Description:: +This instruction loads a zero extended 16-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := zero_extend(mem[addr+1:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LHU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lrw.adoc b/xtheadmemidx/lrw.adoc new file mode 100644 index 0000000..1995b3b --- /dev/null +++ b/xtheadmemidx/lrw.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-lrw,reftext=Load indexed word] +==== th.lrw + +Synopsis:: +Load indexed word. + +Mnemonic:: +th.lrw _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x08 }, +]} +.... + +Description:: +This instruction loads a sign extended 32-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := sign_extend(mem[addr+3:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/lrwu.adoc b/xtheadmemidx/lrwu.adoc new file mode 100644 index 0000000..b5a4793 --- /dev/null +++ b/xtheadmemidx/lrwu.adoc @@ -0,0 +1,47 @@ +[#xtheadmemidx-insns-lrwu,reftext=Load indexed unsigned word] +==== th.lrwu + +Synopsis:: +Load indexed unsigned word. + +Mnemonic:: +th.lrwu _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x18 }, +]} +.... + +Description:: +This instruction loads a zero extended 32-bit value into the GP register _rd_ from the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +rd := zero_extend(mem[addr+3:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LWU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lurb.adoc b/xtheadmemidx/lurb.adoc new file mode 100644 index 0000000..0b08826 --- /dev/null +++ b/xtheadmemidx/lurb.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-lurb,reftext=Load unsigned indexed byte] +==== th.lurb + +Synopsis:: +Load unsigned indexed byte. + +Mnemonic:: +th.lurb _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x02 }, +]} +.... + +Description:: +This instruction loads a sign extended 8-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrb` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := sign_extend(mem[addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lurbu.adoc b/xtheadmemidx/lurbu.adoc new file mode 100644 index 0000000..bfbc3ff --- /dev/null +++ b/xtheadmemidx/lurbu.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-lurbu,reftext=Load unsigned indexed unsigned byte] +==== th.lurbu + +Synopsis:: +Load unsigned indexed unsigned byte. + +Mnemonic:: +th.lurbu _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x12 }, +]} +.... + +Description:: +This instruction loads a zero extended 8-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrbu` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := zero_extend(mem[addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LBU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lurd.adoc b/xtheadmemidx/lurd.adoc new file mode 100644 index 0000000..1ffc5a5 --- /dev/null +++ b/xtheadmemidx/lurd.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-lurd,reftext=Load unsigned indexed double-word] +==== th.lurd + +Synopsis:: +Load unsigned indexed double-word. + +Mnemonic:: +th.lurd _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0e }, +]} +.... + +Description:: +This instruction loads a sign extended 64-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrd` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := sign_extend(mem[addr+7:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/lurh.adoc b/xtheadmemidx/lurh.adoc new file mode 100644 index 0000000..45d1a65 --- /dev/null +++ b/xtheadmemidx/lurh.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-lurh,reftext=Load unsigned indexed half-word] +==== th.lurh + +Synopsis:: +Load unsigned indexed half-word. + +Mnemonic:: +th.lurh _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x06 }, +]} +.... + +Description:: +This instruction loads a sign extended 16-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrh` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := sign_extend(mem[addr+1:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lurhu.adoc b/xtheadmemidx/lurhu.adoc new file mode 100644 index 0000000..1959f6c --- /dev/null +++ b/xtheadmemidx/lurhu.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-lurhu,reftext=Load unsigned indexed unsigned half-word] +==== th.lurhu + +Synopsis:: +Load unsigned indexed unsigned half-word. + +Mnemonic:: +th.lurhu _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x16 }, +]} +.... + +Description:: +This instruction loads a zero extended 16-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrhu` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := zero_extend(mem[addr+1:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LHU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lurw.adoc b/xtheadmemidx/lurw.adoc new file mode 100644 index 0000000..eb3ac2a --- /dev/null +++ b/xtheadmemidx/lurw.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-lurw,reftext=Load unsigned indexed word] +==== th.lurw + +Synopsis:: +Load unsigned indexed word. + +Mnemonic:: +th.lurw _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0a }, +]} +.... + +Description:: +This instruction loads a sign extended 32-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrw` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := sign_extend(mem[addr+3:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lurwu.adoc b/xtheadmemidx/lurwu.adoc new file mode 100644 index 0000000..765410c --- /dev/null +++ b/xtheadmemidx/lurwu.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-lurwu,reftext=Load unsigned indexed unsigned word] +==== th.lurwu + +Synopsis:: +Load unsigned indexed unsigned word. + +Mnemonic:: +th.lurwu _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1a }, +]} +.... + +Description:: +This instruction loads a zero extended 16-bit value into GP register _rd_ from the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.lrwu` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +rd := zero_extend(mem[addr+3:addr]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LWU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lwia.adoc b/xtheadmemidx/lwia.adoc new file mode 100644 index 0000000..75b243e --- /dev/null +++ b/xtheadmemidx/lwia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lwia,reftext=Load indexed word, increment-after] +==== th.lwia + +Synopsis:: +Load indexed word, increment address after loading. + +Mnemonic:: +th.lwia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0b }, +]} +.... + +Description:: +This instruction loads a sign extended 32-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rd := sign_extend(mem[rs1+3:rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lwib.adoc b/xtheadmemidx/lwib.adoc new file mode 100644 index 0000000..1d1e5c6 --- /dev/null +++ b/xtheadmemidx/lwib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lwib,reftext=Load indexed word, increment-before] +==== th.lwib + +Synopsis:: +Load indexed word, increment address before loading. + +Mnemonic:: +th.lwib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x09 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a sign extended 32-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := sign_extend(mem[rs1+3:rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lwuia.adoc b/xtheadmemidx/lwuia.adoc new file mode 100644 index 0000000..948a5db --- /dev/null +++ b/xtheadmemidx/lwuia.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lwuia,reftext=Load indexed unsigned word, increment-after] +==== th.lwuia + +Synopsis:: +Load indexed unsigned word, increment address after loading. + +Mnemonic:: +th.lwuia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1b }, +]} +.... + +Description:: +This instruction loads a zero extended 32-bit value into the GP register _rd_ from the address _rs1_. +After the load, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rd := zero_extend(mem[rs1+3:rs1]) +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LWU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/lwuib.adoc b/xtheadmemidx/lwuib.adoc new file mode 100644 index 0000000..c3cda9e --- /dev/null +++ b/xtheadmemidx/lwuib.adoc @@ -0,0 +1,50 @@ +[#xtheadmemidx-insns-lwuib,reftext=Load indexed unsigned word, increment-before] +==== th.lwuib + +Synopsis:: +Load indexed unsigned word, increment address before loading. + +Mnemonic:: +th.lwuib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x19 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction loads a zero extended 32-bit value into the GP register _rd_ from the (incremented) address _rs1_. + +The values of _rd_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +rd := zero_extend(mem[rs1+3:rs1]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `LWU` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/sbia.adoc b/xtheadmemidx/sbia.adoc new file mode 100644 index 0000000..db99348 --- /dev/null +++ b/xtheadmemidx/sbia.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-sbia,reftext=Store indexed byte, increment-after] +==== th.sbia + +Synopsis:: +Store indexed byte, increment address after loading. + +Mnemonic:: +th.sbia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x03 }, +]} +.... + +Description:: +This instruction stores an 8-bit value from the GP register _rd_ to the address _rs1_. +After the store, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +Operation:: +[source,sail] +-- +mem[rs1] := rd +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/sbib.adoc b/xtheadmemidx/sbib.adoc new file mode 100644 index 0000000..7626af5 --- /dev/null +++ b/xtheadmemidx/sbib.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-sbib,reftext=Store indexed byte, increment-before] +==== th.sbib + +Synopsis:: +Store indexed byte, increment address before loading. + +Mnemonic:: +th.sbib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x01 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction stores an 8-bit value from the GP register _rd_ to the (incremented) address _rs1_. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +mem[rs1] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/sdia.adoc b/xtheadmemidx/sdia.adoc new file mode 100644 index 0000000..0495906 --- /dev/null +++ b/xtheadmemidx/sdia.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-sdia,reftext=Store indexed double-word, increment-after] +==== th.sdia + +Synopsis:: +Store indexed double-word, increment address after loading. + +Mnemonic:: +th.sdia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0f }, +]} +.... + +Description:: +This instruction stores an 64-bit value from the GP register _rd_ to the address _rs1_. +After the store, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +Operation:: +[source,sail] +-- +mem[rs1+7:rs1] := rd +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/sdib.adoc b/xtheadmemidx/sdib.adoc new file mode 100644 index 0000000..c1fba09 --- /dev/null +++ b/xtheadmemidx/sdib.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-sdib,reftext=Store indexed double-word, increment-before] +==== th.sdib + +Synopsis:: +Store indexed double-word, increment address before loading. + +Mnemonic:: +th.sdib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0d }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction stores an 64-bit value from the GP register _rd_ to the (incremented) address _rs1_. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +mem[rs1+7:rs1] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/shia.adoc b/xtheadmemidx/shia.adoc new file mode 100644 index 0000000..312d58b --- /dev/null +++ b/xtheadmemidx/shia.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-shia,reftext=Store indexed half-word, increment-after] +==== th.shia + +Synopsis:: +Store indexed half-word, increment address after loading. + +Mnemonic:: +th.shia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x07 }, +]} +.... + +Description:: +This instruction stores an 16-bit value from the GP register _rd_ to the address _rs1_. +After the store, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +Operation:: +[source,sail] +-- +mem[rs1+1:rs1] := rd +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/shib.adoc b/xtheadmemidx/shib.adoc new file mode 100644 index 0000000..19980e0 --- /dev/null +++ b/xtheadmemidx/shib.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-shib,reftext=Store indexed half-word, increment-before] +==== th.shib + +Synopsis:: +Store indexed half-word, increment address before loading. + +Mnemonic:: +th.shib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x05 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction stores an 16-bit value from the GP register _rd_ to the (incremented) address _rs1_. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +mem[rs1+1:rs1] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/srb.adoc b/xtheadmemidx/srb.adoc new file mode 100644 index 0000000..25a442b --- /dev/null +++ b/xtheadmemidx/srb.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-srb,reftext=Store indexed byte] +==== th.srb + +Synopsis:: +Store indexed byte. + +Mnemonic:: +th.srb _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x00 }, +]} +.... + +Description:: +This instruction stores an 8-bit value from the GP register _rd_ to the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +mem[addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/srd.adoc b/xtheadmemidx/srd.adoc new file mode 100644 index 0000000..6f6ba04 --- /dev/null +++ b/xtheadmemidx/srd.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-srd,reftext=Store indexed double-word] +==== th.srd + +Synopsis:: +Store indexed double-word. + +Mnemonic:: +th.srd _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0c }, +]} +.... + +Description:: +This instruction stores a 64-bit value from the GP register _rd_ to the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +mem[addr+7:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/srh.adoc b/xtheadmemidx/srh.adoc new file mode 100644 index 0000000..ae00a8f --- /dev/null +++ b/xtheadmemidx/srh.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-srh,reftext=Store indexed half-word] +==== th.srh + +Synopsis:: +Store indexed half-word. + +Mnemonic:: +th.srh _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x04 }, +]} +.... + +Description:: +This instruction stores a 16-bit value from the GP register _rd_ to the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +mem[addr+1:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/srw.adoc b/xtheadmemidx/srw.adoc new file mode 100644 index 0000000..acf60e2 --- /dev/null +++ b/xtheadmemidx/srw.adoc @@ -0,0 +1,46 @@ +[#xtheadmemidx-insns-srw,reftext=Store indexed word] +==== th.srw + +Synopsis:: +Store indexed word. + +Mnemonic:: +th.srw _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x08 }, +]} +.... + +Description:: +This instruction stores a 32-bit value from the GP register _rd_ to the address _rs1_ + (_rs2_ << _imm2_). + +Operation:: +[source,sail] +-- +addr := rs1 + (rs2 << imm2) +mem[addr+3:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== diff --git a/xtheadmemidx/surb.adoc b/xtheadmemidx/surb.adoc new file mode 100644 index 0000000..c4a9b29 --- /dev/null +++ b/xtheadmemidx/surb.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-surb,reftext=Store unsigned indexed byte] +==== th.surb + +Synopsis:: +Store unsigned indexed byte. + +Mnemonic:: +th.surb _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x02 }, +]} +.... + +Description:: +This instruction stores an 8-bit value from the GP register _rd_ to the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.srb` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +mem[addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SB` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/surd.adoc b/xtheadmemidx/surd.adoc new file mode 100644 index 0000000..5281236 --- /dev/null +++ b/xtheadmemidx/surd.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-surd,reftext=Store unsigned indexed double-word] +==== th.surd + +Synopsis:: +Store unsigned indexed double-word. + +Mnemonic:: +th.surd _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0e }, +]} +.... + +Description:: +This instruction stores a 64-bit value from the GP register _rd_ to the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.srd` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +mem[addr+7:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SD` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/surh.adoc b/xtheadmemidx/surh.adoc new file mode 100644 index 0000000..c159387 --- /dev/null +++ b/xtheadmemidx/surh.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-surh,reftext=Store unsigned indexed half-word] +==== th.surh + +Synopsis:: +Store unsigned indexed half-word. + +Mnemonic:: +th.surh _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x06 }, +]} +.... + +Description:: +This instruction stores a 16-bit value from the GP register _rd_ to the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.srh` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +mem[addr+1:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SH` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/surw.adoc b/xtheadmemidx/surw.adoc new file mode 100644 index 0000000..4b39a6f --- /dev/null +++ b/xtheadmemidx/surw.adoc @@ -0,0 +1,49 @@ +[#xtheadmemidx-insns-surw,reftext=Store unsigned indexed word] +==== th.surw + +Synopsis:: +Store unsigned indexed word. + +Mnemonic:: +th.surw _rd_, (_rs1_), _rs2_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rs2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0a }, +]} +.... + +Description:: +This instruction stores a 32-bit value from the GP register _rd_ to the address _rs1_ + (zero_extend(_rs2_) << _imm2_). + +Note, that this instruction is equivalent to a `zext.w _rs2_, _rs2_` followed by a `th.srw` with the same arguments. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(rs2) << imm2) +mem[addr+3:addr] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/swia.adoc b/xtheadmemidx/swia.adoc new file mode 100644 index 0000000..c97c2ea --- /dev/null +++ b/xtheadmemidx/swia.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-swia,reftext=Store indexed word, increment-after] +==== th.swia + +Synopsis:: +Store indexed word, increment address after loading. + +Mnemonic:: +th.swia _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x0b }, +]} +.... + +Description:: +This instruction stores an 32-bit value from the GP register _rd_ to the address _rs1_. +After the store, this instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. + +Operation:: +[source,sail] +-- +mem[rs1+3:rs1] := rd +rs1 := rs1 + (sign_extend(imm5) << imm2) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmemidx/swib.adoc b/xtheadmemidx/swib.adoc new file mode 100644 index 0000000..2462bd4 --- /dev/null +++ b/xtheadmemidx/swib.adoc @@ -0,0 +1,48 @@ +[#xtheadmemidx-insns-swib,reftext=Store indexed word, increment-before] +==== th.swib + +Synopsis:: +Store indexed word, increment address before loading. + +Mnemonic:: +th.swib _rd_, (_rs1_), _imm5_, _imm2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'imm5' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x09 }, +]} +.... + +Description:: +This instruction increments the value in _rs1_ by (sign_extend(_imm5_) << _imm2_) and writes the result back to _rs1_. +After the increment of _rs1_, this instruction stores an 32-bit value from the GP register _rd_ to the (incremented) address _rs1_. + +Operation:: +[source,sail] +-- +rs1 := rs1 + (sign_extend(imm5) << imm2) +mem[rs1+3:rs1] := rd +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that a corresponding `SW` instruction would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemIdx (<<#xtheadmemidx>>) +|=== + diff --git a/xtheadmempair.adoc b/xtheadmempair.adoc new file mode 100644 index 0000000..a9c0b06 --- /dev/null +++ b/xtheadmempair.adoc @@ -0,0 +1,31 @@ +[#xtheadmempair] +== Two-GPR memory operations (XTheadMemPair) + +[NOTE,caption=Frozen] +The `XTheadMemPair` extension is `stable`. + +The `XTheadMemPair` ISA extension provides two-GPR memory operations. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| N | Y | th.ldd _rd1_, _rd2_, (_rs1_), _imm2_, 4 | <<#xtheadmempair-insns-ldd>> +| Y | Y | th.lwd _rd1_, _rd2_, (_rs1_), _imm2_, 3 | <<#xtheadmempair-insns-lwd>> +| Y | Y | th.lwud _rd1_, _rd2_, (_rs1_), _imm2_, 3 | <<#xtheadmempair-insns-lwud>> +| N | Y | th.sdd _rd1_, _rd2_, (_rs1_), _imm2_, 4 | <<#xtheadmempair-insns-sdd>> +| Y | Y | th.swd _rd1_, _rd2_, (_rs1_), _imm2_, 3 | <<#xtheadmempair-insns-swd>> +|=== + +[#xtheadmempair-insns,reftext="Instructions"] +=== Instructions +include::xtheadmempair/ldd.adoc[] +<<< +include::xtheadmempair/lwd.adoc[] +<<< +include::xtheadmempair/lwud.adoc[] +<<< +include::xtheadmempair/sdd.adoc[] +<<< +include::xtheadmempair/swd.adoc[] diff --git a/xtheadmempair/ldd.adoc b/xtheadmempair/ldd.adoc new file mode 100644 index 0000000..07f6efb --- /dev/null +++ b/xtheadmempair/ldd.adoc @@ -0,0 +1,51 @@ +[#xtheadmempair-insns-ldd,reftext=Load two 64-bit values] +==== th.ldd + +Synopsis:: +Load two 64-bit values from memory into two GPRs. + +Mnemonic:: +th.ldd _rd1_, _rd2_, (_rs1_), _imm2_, 4 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd1' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rd2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1f }, +]} +.... + +Description:: +This instruction loads two 64-bit values into the two GP registers _rd1_ and _rd2_ +from the address _rs1_ + (zero_extend(_imm2_) << 4). + +The values of _rd1_, _rd2_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(imm2) << 4) +rd1 := mem[addr+7:addr] +rd2 := mem[addr+15:addr+8] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `LD` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemPair (<<#xtheadmempair>>) +|=== + diff --git a/xtheadmempair/lwd.adoc b/xtheadmempair/lwd.adoc new file mode 100644 index 0000000..1276159 --- /dev/null +++ b/xtheadmempair/lwd.adoc @@ -0,0 +1,51 @@ +[#xtheadmempair-insns-lwd,reftext=Load two signed 32-bit values] +==== th.lwd + +Synopsis:: +Load two signed 32-bit values from memory into two GPRs. + +Mnemonic:: +th.lwd _rd1_, _rd2_, (_rs1_), _imm2_, 3 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd1' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rd2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1c }, +]} +.... + +Description:: +This instruction loads two signed 32-bit values into the two GP registers _rd1_ and _rd2_ +from the address _rs1_ + (zero_extend(_imm2_) << 3). + +The values of _rd1_, _rd2_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(imm2) << 3) +reg[rd1] := sign_extend(mem[addr+3:addr]) +reg[rd2] := sign_extend(mem[addr+7:addr+3]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `LW` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemPair (<<#xtheadmempair>>) +|=== + diff --git a/xtheadmempair/lwud.adoc b/xtheadmempair/lwud.adoc new file mode 100644 index 0000000..900dead --- /dev/null +++ b/xtheadmempair/lwud.adoc @@ -0,0 +1,51 @@ +[#xtheadmempair-insns-lwud,reftext=Load two unsigned 32-bit values] +==== th.lwud + +Synopsis:: +Load two unsigned 32-bit values from memory into two GPRs. + +Mnemonic:: +th.lwud _rd1_, _rd2_, (_rs1_), _imm2_, 3 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd1' }, + { bits: 3, name: 0x4, attr: ['Mem-Load'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rd2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1e }, +]} +.... + +Description:: +This instruction loads two unsigned 32-bit values into the two GP registers _rd1_ and _rd2_ +from the address _rs1_ + (zero_extend(_imm2_) << 3). + +The values of _rd1_, _rd2_ and _rs1_ must not be the same. + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(imm2) << 3) +reg[rd1] := zero_extend(mem[addr+3:addr]) +reg[rd2] := zero_extend(mem[addr+7:addr+3]) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `LWU` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemPair (<<#xtheadmempair>>) +|=== + diff --git a/xtheadmempair/sdd.adoc b/xtheadmempair/sdd.adoc new file mode 100644 index 0000000..7a1af64 --- /dev/null +++ b/xtheadmempair/sdd.adoc @@ -0,0 +1,49 @@ +[#xtheadmempair-insns-sdd,reftext=Store two 64-bit values] +==== th.sdd + +Synopsis:: +Store two 64-bit values to memory from two GPRs. + +Mnemonic:: +th.sdd _rd1_, _rd2_, (_rs1_), _imm2_, 4 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd1' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rd2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1f }, +]} +.... + +Description:: +This instruction stores two 64-bit values from the two GP registers _rd1_ and _rd2_ +to the address _rs1_ + (zero_extend(_imm2_) << 4). + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(imm2) << 4) +mem[addr+7:addr] := reg[rd1] +mem[addr+15:addr+8] := reg[rd2] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `SD` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemPair (<<#xtheadmempair>>) +|=== + diff --git a/xtheadmempair/swd.adoc b/xtheadmempair/swd.adoc new file mode 100644 index 0000000..479cbb6 --- /dev/null +++ b/xtheadmempair/swd.adoc @@ -0,0 +1,49 @@ +[#xtheadmempair-insns-swd,reftext=Store two 32-bit values] +==== th.swd + +Synopsis:: +Store two 32-bit values to memory from two GPRs. + +Mnemonic:: +th.swd _rd1_, _rd2_, (_rs1_), _imm2_, 3 + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 'rd1' }, + { bits: 3, name: 0x5, attr: ['Mem-Store'] }, + { bits: 5, name: 'rs1' }, + { bits: 5, name: 'rd2' }, + { bits: 2, name: 'imm2' }, + { bits: 5, name: 0x1c }, +]} +.... + +Description:: +This instruction loads two 32-bit values into the two GP registers _rd1_ and _rd2_ +from the address _rs1_ + (zero_extend(_imm2_) << 3). + +Operation:: +[source,sail] +-- +addr := rs1 + (zero_extend(imm2) << 3) +mem[addr+3:addr] := reg[rd1][31:0] +mem[addr+7:addr+3] := reg[rd2][31:0] +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction triggers the same exceptions that two corresponding `SW` instructions would trigger. + +Included in:: +[%header] +|=== +|Extension + +|XTheadMemPair (<<#xtheadmempair>>) +|=== + diff --git a/xtheadsync.adoc b/xtheadsync.adoc new file mode 100644 index 0000000..20e4201 --- /dev/null +++ b/xtheadsync.adoc @@ -0,0 +1,31 @@ +[#xtheadsync] +== Multi-core synchronization instructions (XTheadSync) + +[NOTE,caption=Frozen] +The `XTheadSync` extension is `stable`. + +The `XTheadSync` ISA extension provides multi-core synchronization instructions. + +The table below gives an overview of the instructions: + +[cols="^3,^3,12,18",stripes=even,options="header"] +|=== +| RV32 | RV64 | Mnemonic | Instruction +| Y | Y | th.sfence.vmas _rs1_, _rs2_ | <<#xtheadsync-insns-sfence-vmas>> +| Y | Y | th.sync | <<#xtheadsync-insns-sync>> +| Y | Y | th.sync.s | <<#xtheadsync-insns-sync-s>> +| Y | Y | th.sync.i | <<#xtheadsync-insns-sync-i>> +| Y | Y | th.sync.is | <<#xtheadsync-insns-sync-is>> +|=== + +[#xtheadsync-insns,reftext="Instructions"] +=== Instructions +include::xtheadsync/sfence_vmas.adoc[] +<<< +include::xtheadsync/sync.adoc[] +<<< +include::xtheadsync/sync_s.adoc[] +<<< +include::xtheadsync/sync_i.adoc[] +<<< +include::xtheadsync/sync_is.adoc[] diff --git a/xtheadsync/sfence_vmas.adoc b/xtheadsync/sfence_vmas.adoc new file mode 100644 index 0000000..f4e2d74 --- /dev/null +++ b/xtheadsync/sfence_vmas.adoc @@ -0,0 +1,75 @@ +[#xtheadsync-insns-sfence-vmas,reftext=Invalidate TLB on all harts] +==== th.sfence.vmas + +Synopsis:: +Invalidate TLB (page table cache) on all harts via broadcasting. + +Mnemonic:: +th.sfence.vmas _rs1_, _rs2_ + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 'rs1', attr: ['VA'] }, + { bits: 5, name: 'rs2', attr: ['ASID'] }, + { bits: 7, name: 0x02 }, +]} +.... + +Description:: +This instruction invalidates the TLB (page table cache) on all harts via broadcasting. +The register _rs1_ holds the virtual address (VA) and _rs2_ holds the address space identifier (ASID) +of the TLB entry that will be invalidated on all harts via broadcasting. + +An operand that is zero is interpreted as match-all. +E.g. if _rs2_ is zero, then all TLB entries that match the VA in _rs1_ are invalidated on all harts via broadcasting. +Consequently, if both operands, _rs1_ and _rs2_, are zero, then all TLB entries are invalidated on all harts via broadcasting. + +Operation:: +[source,sail] +-- +if (priv_level == U) +{ + +} + +if _rs1_ != 0 +{ + va := _rs1_ +} +else +{ + va := _MATCH_ALL_VA_ +} + +if _rs2_ != 0 +{ + asid := _rs2_ +} +else +{ + asid := _MATCH_ALL_ASID_ +} + +msg := encode_invalidate_tlb(va, asid) +broadcast_to_all_harts(msg) +-- + +Permission:: +This instruction can be executed in all privilege levels higher than `U` mode. +Attempts to execute this instruction in `U` mode raise an illegal instruction exception. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadSync (<<#xtheasync>>) +|=== diff --git a/xtheadsync/sync.adoc b/xtheadsync/sync.adoc new file mode 100644 index 0000000..81780f9 --- /dev/null +++ b/xtheadsync/sync.adoc @@ -0,0 +1,44 @@ +[#xtheadsync-insns-sync,reftext=Synchronization barrier] +==== th.sync + +Synopsis:: +Ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction. + +Mnemonic:: +th.sync + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x18, attr: ['SYNC'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction. + +Operation:: +[source,sail] +-- +out_of_order_barrier() +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadSync (<<#xtheasync>>) +|=== diff --git a/xtheadsync/sync_i.adoc b/xtheadsync/sync_i.adoc new file mode 100644 index 0000000..0bdbaef --- /dev/null +++ b/xtheadsync/sync_i.adoc @@ -0,0 +1,45 @@ +[#xtheadsync-insns-sync-i,reftext=Synchronization barrier and pipeline flush] +==== th.sync.i + +Synopsis:: +Ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction and clears the pipeline when this instruction retires. + +Mnemonic:: +th.sync.i + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x1A, attr: ['SYNC.I'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction. When this instruction retires the hart's pipeline will be cleared. + +Operation:: +[source,sail] +-- +out_of_order_barrier() +pipeline_flush() +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadSync (<<#xtheasync>>) +|=== diff --git a/xtheadsync/sync_is.adoc b/xtheadsync/sync_is.adoc new file mode 100644 index 0000000..1918296 --- /dev/null +++ b/xtheadsync/sync_is.adoc @@ -0,0 +1,46 @@ +[#xtheadsync-insns-sync-is,reftext=Synchronization barrier and pipeline flush on all harts] +==== th.sync.is + +Synopsis:: +Ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction and clears the pipeline when this instruction retires on all harts. + +Mnemonic:: +th.sync.is + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x1B, attr: ['SYNC.IS'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction. When this instruction retires the hart's pipeline will be cleared. The instruction is executing on all harts via broadcasting. + +Operation:: +[source,sail] +-- +msg := encode_out_of_order_barrier() +msg += encode_pipeline_flush() +broadcast_to_all_harts(msg) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadSync (<<#xtheasync>>) +|=== diff --git a/xtheadsync/sync_s.adoc b/xtheadsync/sync_s.adoc new file mode 100644 index 0000000..1e34cbc --- /dev/null +++ b/xtheadsync/sync_s.adoc @@ -0,0 +1,45 @@ +[#xtheadsync-insns-sync-s,reftext=Synchronization barrier on all harts] +==== th.sync.s + +Synopsis:: +Broadcasts an instruction, that ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction on all harts. + +Mnemonic:: +th.sync.s + +Encoding:: +[wavedrom, , svg] +.... +{reg:[ + { bits: 7, name: 0xb, attr: ['custom-0, 32 bit'] }, + { bits: 5, name: 0x0 }, + { bits: 3, name: 0x0, attr: ['CMO'] }, + { bits: 5, name: 0x0 }, + { bits: 5, name: 0x19, attr: ['SYNC.S'] }, + { bits: 7, name: 0x00 }, +]} +.... + +Description:: +This instruction ensures that all preceding instructions retire earlier than this instruction and all subsequent instructions retire later than this instruction. The instruction is executing on all harts via broadcasting. + +Operation:: +[source,sail] +-- +msg := encode_out_of_order_barrier() +broadcast_to_all_harts(msg) +-- + +Permission:: +This instruction can be executed in all privilege levels. + +Exceptions:: +This instruction does not trigger any exceptions. + +Included in:: +[%header] +|=== +|Extension + +|XTheadSync (<<#xtheasync>>) +|===