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jwd1797.c
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// WD1797 Implementation
// By: Joe Matta
// email: jmatta1980@hotmail.com
// November 2020
// jwd1797.c
// Notes:
/* clock is assumed to be 1 MHz for single and double density mini-floppy disks
(5.25" ) */
/* Z-DOS disks are 360k disks - 40 cylinders/2 heads (sides)/9 sectors per track/
512 bytes per sector */
// A 300 RPM motor speed is also assumed
// NO write protect functionality
// the wd1797 has a 1MHz clock in the Z100 for 5.25" floppy
#include <stdlib.h>
#include <stdio.h>
#include "jwd1797.h"
#include "e8259.h"
#include "utility_functions.h"
/* TIMINGS (microseconds) */
// index hole pulses should last for a minimum of 20 microseconds (WD1797 docs)
#define INDEX_HOLE_PULSE_US 100.0
// head load timing (this can be set from 30-100 ms, depending on drive)
// set to 45 ms (45,000 us)
#define HEAD_LOAD_TIMING_LIMIT 55.0*1000
// verify time is 30 milliseconds for a 1MHz clock
#define VERIFY_HEAD_SETTLING_LIMIT 30.0*1000
// E (15 ms delay) for TYPE II and III commands (30 ms (30*1000 us) for 1 MHz clock)
#define E_DELAY_LIMIT 30.0*1000
/* COUNTS */
// when non-busy status and HLD high, reset HLD after 15 index pulses
#define HLD_IDLE_INDEX_COUNT_LIMIT 15
/* number of bytes after ID field search encounters four 0x00 bytes. This
should be 16 bytes according to WD-1797 docs. After 16 bytes the search
for the next ID field starts over. */
#define ID_FIELD_SEARCH_LIMIT 16
/* In Double Density Disks, if 43 bytes pass before Data AM is found, INTRQ */
#define DATA_AM_SEARCH_LIMIT 43
// DOS disk format (bytes per format section and byte written for each section)
#define GAP4A_LENGTH 80
#define GAP4A_BYTE 0x4E
#define SYNC_LENGTH 12
#define SYNC_BYTE 0x00
#define INDEX_AM_PREFIX_LENGTH 3
#define INDEX_AM_PREFIX_BYTE 0xC2
#define INDEX_AM_LENGTH 1
#define INDEX_AM_BYTE 0xFC
#define GAP1_LENGTH 50
#define GAP1_BYTE 0x4E
#define ID_AM_PREFIX_LENGTH 3
#define ID_AM_PREFIX_BYTE 0xA1
#define ID_AM_LENGTH 1
#define ID_AM_BYTE 0xFE
#define CYLINDER_LENGTH 1
#define HEAD_LENGTH 1
#define SECTOR_LENGTH 1
#define SECTOR_SIZE_LENGTH 1
#define CRC_LENGTH 2
#define CRC_BYTE 0x01 // PLACEHOLDER; CRC is not actually calulated or written
#define GAP2_LENGTH 22
#define GAP2_BYTE 0x4E
#define DATA_AM_PREFIX_LENGTH 3
#define DATA_AM_PREFIX_BYTE 0xA1
#define DATA_AM_LENGTH 1
#define DATA_AM_BYTE 0xFB
#define GAP3_LENGTH 54
#define GAP3_BYTE 0x4E
#define GAP4B_LENGTH 598
#define GAP4B_BYTE 0x4E
/* INTRQ (pin connected to slave PIC IRQ0 in the Z100) is set to high at the
completion of every command and when a force interrupt condition is met. It is
reset (set to low) when the status register is read or when the commandRegister
is loaded with a new command */
extern e8259_t* e8259_slave;
char* disk_content_array;
JWD1797* newJWD1797() {
JWD1797* jwd_controller = (JWD1797*)malloc(sizeof(JWD1797));
return jwd_controller;
}
void resetJWD1797(JWD1797* jwd_controller) {
jwd_controller->dataShiftRegister = 0b00000000;
jwd_controller->dataRegister = 0b00000000;
jwd_controller->trackRegister = 0b00000000;
jwd_controller->sectorRegister = 0b00000000;
jwd_controller->commandRegister = 0b00000000;
jwd_controller->statusRegister = 0b00000000;
jwd_controller->CRCRegister = 0b00000000;
jwd_controller->controlLatch = 0b00000000;
jwd_controller->controlStatus = 0b00000000;
jwd_controller->disk_img_index_pointer = 0;
jwd_controller->rotational_byte_pointer = 2500; // start at a few bytes before 0 index
jwd_controller->rw_start_byte = 0;
// jwd_controller->ready = 0; // start drive not ready
// jwd_controller->stepDirection = 0; // start direction step out -> track 00
jwd_controller->currentCommandName = "";
jwd_controller->currentCommandType = 0;
// TYPE I command bits
jwd_controller->stepRate = 0; // bits 0 and 1 determine the step rate
jwd_controller->verifyFlag = 0;
jwd_controller->headLoadFlag = 0;
jwd_controller->trackUpdateFlag = 0;
// TYPE II and III command bits
jwd_controller->dataAddressMark = 0;
jwd_controller->updateSSO = 0;
jwd_controller->delay15ms = 0;
jwd_controller->swapSectorLength = 0;
jwd_controller->multipleRecords = 0;
// TYPE IV command (forced interrupt) conditions
jwd_controller->interruptNRtoR = 0;
jwd_controller->interruptRtoNR = 0;
jwd_controller->interruptIndexPulse = 0;
jwd_controller->interruptImmediate = 0;
// command step controls
jwd_controller->command_action_done = 0;
jwd_controller->command_done = 0;
jwd_controller->head_settling_done = 0;
jwd_controller->verify_operation_active = 0;
jwd_controller->verify_operation_done = 0;
jwd_controller->e_delay_done = 0;
jwd_controller->start_byte_set = 0;
jwd_controller->terminate_command = 0;
jwd_controller->master_timer = 0.0;
jwd_controller->index_pulse_timer = 0.0;
jwd_controller->index_encounter_timer = 0.0;
jwd_controller->step_timer = 0.0;
jwd_controller->verify_head_settling_timer = 0.0;
jwd_controller->e_delay_timer = 0.0;
jwd_controller->assemble_data_byte_timer = 0.0;
jwd_controller->rotational_byte_read_limit = 0; // NANOSECONDS
jwd_controller->rotational_byte_read_timer = 0; // NANOSECONDS
jwd_controller->rotational_byte_read_timer_OVR = 0; // NANOSECONDS
jwd_controller->HLD_idle_reset_timer = 0.0;
jwd_controller->HLT_timer = 0.0;
jwd_controller->read_track_bytes_read = 0;
jwd_controller->index_pulse_pin = 0;
jwd_controller->ready_pin = 1; // make drive ready immediately after reset
jwd_controller->tg43_pin = 0;
jwd_controller->HLD_pin = 0;
jwd_controller->HLT_pin = 0;
jwd_controller->not_track00_pin = 0;
jwd_controller->direction_pin = 0;
jwd_controller->sso_pin = 0;
// jwd_controller-> test_not_pin;
jwd_controller->delayed_HLD = 0;
jwd_controller->HLT_timer_active = 0;
jwd_controller->HLD_idle_index_count = 0;
jwd_controller->drq = 0;
jwd_controller->intrq = 0;
jwd_controller->not_master_reset = 1;
jwd_controller->current_track = 0;
jwd_controller->cylinders = 0; // (tracks per side)
jwd_controller->num_heads = 0;
jwd_controller->sectors_per_track = 0;
jwd_controller->sector_length = 0;
jwd_controller->disk_img_file_size = 0;
jwd_controller->formattedDiskArray = NULL;
jwd_controller->actual_num_track_bytes = 0;
jwd_controller->new_byte_read_signal_ = 0;
jwd_controller->track_start_signal_ = 0;
jwd_controller->zero_byte_counter = 0;
jwd_controller->a1_byte_counter = 0;
jwd_controller->verify_index_count = 0;
jwd_controller->address_mark_search_count = 0;
jwd_controller->id_field_found = 0;
jwd_controller->id_field_data_array_pt = 0;
jwd_controller->id_field_data_collected = 0;
jwd_controller->data_a1_byte_counter = 0;
jwd_controller->data_mark_search_count = 0;
jwd_controller->data_mark_found = 0;
/* collects ID Field data
(0: cylinders, 1: head, 2: sector, 3: sector len, 4: CRC1, 5: CRC2)
initialize all to 0x00 */
for(int i = 0; i < 6; i++) {jwd_controller->id_field_data[i] = 0x00;}
jwd_controller->ID_data_verified = 0;
jwd_controller->intSectorLength = 0;
jwd_controller->all_bytes_inputted = 0;
jwd_controller->IDAM_byte_count = 0;
jwd_controller->start_track_read_ = 0;
// control latch initializations
jwd_controller->wait_enabled = 0;
// disk_content_array = diskImageToCharArray("z-dos-1.img", jwd_controller);
// TEST disk image to array function
// printByteArray(disk_content_array, 368640);
/* make a formatted disk array from the disk data payload image file.
will be held in jwd_controller->formattedDiskArray */
assembleFormattedDiskArray(jwd_controller, "Z_DOS_ver1.bin");
}
// read data from wd1797 according to port
unsigned int readJWD1797(JWD1797* jwd_controller, unsigned int port_addr) {
// printf("\nRead ");
// printf("%s%X\n\n", " from wd1797/port: ", port_addr);
unsigned int r_val = 0;
switch(port_addr) {
// status reg port
case 0xb0:
r_val = jwd_controller->statusRegister;
// clear interrupt
jwd_controller->intrq = 0;
e8259_set_irq0 (e8259_slave, 0);
// clear all forced interrupt flags except INTERRUPT IMMEDIATE (0xD8)
jwd_controller->interruptNRtoR = 0;
jwd_controller->interruptRtoNR = 0;
jwd_controller->interruptIndexPulse = 0;
jwd_controller->terminate_command = 0;
break;
// track reg port
case 0xb1:
r_val = jwd_controller->trackRegister;
break;
// sector reg port
case 0xb2:
r_val = jwd_controller->sectorRegister;
break;
// data reg port
case 0xb3:
r_val = jwd_controller->dataRegister;
/* if there is a byte waiting to be read from the data register
(DRQ pin high) because of a READ operation */
if((jwd_controller->currentCommandName == "READ SECTOR" ||
jwd_controller->currentCommandName == "READ ADDRESS" ||
jwd_controller->currentCommandName == "READ TRACK")
&& jwd_controller->drq) {
// reset data request line and status bit
jwd_controller->drq = 0;
jwd_controller->statusRegister &= 0b11111101;
}
break;
// control latch reg port (write)
case 0xb4:
printf(" ** WARNING: Reading from WD1797 control latch port 0xB4 (write only)!\n");
r_val = jwd_controller->controlLatch;
break;
// controller status port (read)
case 0xb5:
// printf("reading from WD1797 control status port 0xB5\n");
r_val = jwd_controller->controlStatus;
break;
default:
printf("%X is an invalid port!\n", port_addr);
}
return r_val;
}
// write data to wd1797 based on port address
void writeJWD1797(JWD1797* jwd_controller, unsigned int port_addr, unsigned int value) {
// printf("\nWrite ");
// print_bin8_representation(value);
// printf("%s%X\n\n", " to wd1797/port: ", port_addr);
switch(port_addr) {
// command reg port
case 0xb0:
jwd_controller->commandRegister = value;
// reset INTRQ when command register is written to - clear interrupt
jwd_controller->intrq = 0;
e8259_set_irq0 (e8259_slave, 0);
// clear all forced interrupt flags except INTERRUPT IMMEDIATE (0xD8)
jwd_controller->interruptNRtoR = 0;
jwd_controller->interruptRtoNR = 0;
jwd_controller->interruptIndexPulse = 0;
jwd_controller->terminate_command = 0;
/* clear INTERRUPT IMMEDIATE flag ONLY if forced int 0xD0 command is
received */
if(value == 0xD0) {
jwd_controller->interruptImmediate = 0;
}
doJWD1797Command(jwd_controller);
break;
// track reg port
case 0xb1:
jwd_controller->trackRegister = value;
break;
// sector reg port
case 0xb2:
jwd_controller->sectorRegister = value;
break;
// data reg port
case 0xb3:
jwd_controller->dataRegister = value;
if((jwd_controller->currentCommandName == "WRITE SECTOR" ||
jwd_controller->currentCommandName == "WRITE TRACK")
&& jwd_controller->drq) {
// reset data request line and status bit
jwd_controller->drq = 0;
jwd_controller->statusRegister &= 0b11111101;
}
break;
// control latch port
case 0xb4:
printf("Writing to WD1797 control port 0xB4 (ONLY wait_enabled option)\n");
jwd_controller->controlLatch = value;
// set wait enabled option according to bit 6
jwd_controller->wait_enabled = (jwd_controller->controlLatch >> 6) & 1;
if(jwd_controller->wait_enabled) {
printf("%s\n", "** FD-1797 Wait Enabled **");
}
break;
// controller status port
case 0xb5:
printf(" ** WARNING: Writing to WD1797 status port 0xB5 (read only)!\n");
break;
default:
printf("%X is an invalid port!\n", port_addr);
}
}
/* main program will add the amount of calculated time from the previous
instruction to the internal WD1797 timers */
void doJWD1797Cycle(JWD1797* w, double us) {
w->master_timer += us; // @@@ DEBUG clock @@@
/* update status register bit 7 (NOT READY) based on inverted not_master_reset
or'd with inverted ready_pin (ALL COMMANDS) */
if(((!w->ready_pin | !w->not_master_reset)&1) == 0) {
w->statusRegister &= 0b01111111; // reset NOT READY bit
}
else {w->statusRegister |= 0b10000000;} // set NOT READY bit
// update not_track00_pin
// check track and set not_track00_pin accordingly
if(w->current_track == 0) {w->not_track00_pin = 0;}
else {w->not_track00_pin = 1;}
/* check if there is a forced intr 0xD0
(NO INTRQ - terminate command immediately) */
if(w->terminate_command) {
// is there a command currently running?
if(!w->command_done) { // YES
// terminate command
w->command_done = 1;
// reset BUSY status bit ONLY - other status bits are unchanged
w->statusRegister &= 0b11111110;
}
else { // NO command running
/* reset busy status and clear SEEK ERROR and CRC ERROR bits
(reflect TYPE I status) */
w->statusRegister &= 0b11100110; // reset NOT READY bit
// change command type to I in order to update TYPE I status bits
w->currentCommandType = 1;
}
}
/* check if there is a forced intr 0xD8 (INTRQ & terminate command immediately)
(can be combined with other conditions) */
if(w->interruptImmediate) {
// is there a command currently running?
if(!w->command_done) { // YES
// terminate command
w->command_done = 1;
// reset BUSY status bit ONLY - other status bits are unchanged
w->statusRegister &= 0b11111110;
// generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
}
else { // NO command running
/* reset busy status and clear SEEK ERROR and CRC ERROR bits
(reflect TYPE I status) */
w->statusRegister &= 0b11100110; // reset NOT READY bit
// change command type to I in order to update TYPE I status bits
w->currentCommandType = 1;
// generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
}
}
// reset new byte signal every WD1797 clock cycle
w->new_byte_read_signal_ = 0;
// clock the rotational byte timer using NANOSECONDS from mainBoard
w->rotational_byte_read_timer += ((int)(us*1000.0));
// is it time to advance to the next rotational byte?
if(w->rotational_byte_read_timer >= w->rotational_byte_read_limit) {
// calculate overage for incoming time from mainBoard.c
w->rotational_byte_read_timer_OVR =
w->rotational_byte_read_timer - w->rotational_byte_read_limit;
// advance to next rotational byte (go to 0 if back to start of track)
w->rotational_byte_pointer =
(w->rotational_byte_pointer + 1) % w->actual_num_track_bytes;
// when the first byte of the track is read, signal the start of the index pulse
if(w->rotational_byte_pointer == 0) {
w->track_start_signal_ = 1;
// printf("%s\n", "Beginning of Track");
// command execution idle - clock HLD idle index counter
if((w->statusRegister & 1) == 0) {w->HLD_idle_index_count++;}
else {w->HLD_idle_index_count = 0;}
// clock verify timeout counter
if(w->verify_operation_active) {w->verify_index_count++;}
else {w->verify_index_count = 0;}
}
/* make new byte read signal (internal) go high. This signals that a new
rotational byte has been encountered */
w->new_byte_read_signal_ = 1;
// reset timer to include overage
w->rotational_byte_read_timer = w->rotational_byte_read_timer_OVR;
}
/* is it the start of a new track (rising edge of IP? = track_start_signal_)
-- with a IP forced interrupt? */
if(w->track_start_signal_ && w->interruptIndexPulse) {
printf("%s\n", "IP interrupt condition met..");
// is there a command currently running?
if(!w->command_done) { // YES
// terminate command
w->command_done = 1;
// reset BUSY status bit ONLY - other status bits are unchanged
w->statusRegister &= 0b11111110;
// generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
}
else { // NO command running
/* reset busy status and clear SEEK ERROR and CRC ERROR bits
(reflect TYPE I status) */
w->statusRegister &= 0b11100110; // reset NOT READY bit
// change command type to I in order to update TYPE I status bits
w->currentCommandType = 1;
// generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
}
}
handleIndexPulse(w, us);
handleHLTTimer(w, us);
if(w->currentCommandType == 1) {
// Type I status bit 5 (S5) will be set if HLD and HLT pins are high
if(w->HLD_pin && w->HLT_pin) {w->statusRegister |= 0b00100000;}
// clear TYPE I status bit 5 (S5) if HLD and HLT both not high
else {w->statusRegister &= 0b11011111;}
// update type I status bit 2 (S2) for track 00 status
if(!w->not_track00_pin) {w->statusRegister |= 0b00000100;}
// clear TYPE I status bit 2 (S2) if not on track 00
else {w->statusRegister &= 0b11111011;}
}
/* update DATA REQUEST status bit (S1) for type II and III commands based on
DRQ pin */
if(w->currentCommandType == 2 || w->currentCommandType == 3) {
// Type II/III status bit 1 (S1) will be set if DRQ is high
if(w->drq) {w->statusRegister |= 0b00000010;}
// ...and cleared if DRQ is low
else {w->statusRegister &= 0b11111101;}
}
// check if command is still active and do command step if so...
if(!w->command_done) {
commandStep(w, us);
}
// HLD pin will reset if drive is not busy and 15 index pulses happen
handleHLDIdle(w);
/* update control status */
updateControlStatus(w);
}
/* WD1797 accepts 11 different commands - this function will register the
command and set all paramenters associated with it */
void doJWD1797Command(JWD1797* w) {
// if the 4 high bits are 0b1101, the command is a force interrupt
if(((w->commandRegister>>4) & 15) == 13) {setupForcedIntCommand(w); return;}
// if not TYPE IV (forced interrupt), get busy status bit from status register (bit 0)
int busy = w->statusRegister & 1;
// check busy status
if(busy) {printBusyMsg(); return;} // do not run command if busy
/* determine if command in command register is a TYPE I command by checking
if the 7 bit is a zero (noly TYPE I commands have a zero (0) in the 7 bit) */
if(((w->commandRegister>>7) & 1) == 0) {
setupTypeICommand(w);
setTypeICommand(w);
}
/* Determine if command in command register is TYPE II
by checking the highest 3 bits. The two TYPE II commands have either 0b100
(Read Sector) or 0b101 (Write Sector) as the high 3 bits
**NOTE: TYPE II commands assume that the target sector has been previously
loaded into the sector register */
else if(((w->commandRegister>>5) & 7) < 6) {
printf("TYPE II Command in WD1797 command register..\n");
setupTypeIICommand(w);
setTypeIICommand(w);
}
/* Determine if command in command register is TYPE III
by checking the highest 3 bits. TYPE III commands have a higher value
then 5 in their shifted 3 high bits */
else if(((w->commandRegister>>5) & 7) > 5) {
printf("TYPE III Command in WD1797 command register..\n");
setupTypeIIICommand(w);
setTypeIIICommand(w);
}
// check command register error
else {
printf("%s\n", "Something went wrong! BAD COMMAND BITS in COMMAND REG!");
}
}
// execute command step if a command is active (not done)
// us is the time that passed since the last CPU instruction
void commandStep(JWD1797* w, double us) {
/* do what needs to be done based on which command is still active and based
on the timers */
if(w->currentCommandType == 1) {
// check if comand action is still ongoing...
if(!w->command_action_done) {
if(w->currentCommandName == "RESTORE") {
// check TR00 pin (this pin is updated in doJWD1797Cycle)
if(!w->not_track00_pin) { // indicates r/w head is over track 00
w->trackRegister = 0;
w->command_action_done = 1; // indicate end of command action
printf("%s\n", "RESTORED HEAD TO TRACK 00 - command action DONE");
return;
}
// not at track 00 - increment step timer
else {
w->step_timer += us;
/* check step timer - has it completed one step according to the step rate?
Step rates are in milliseconds (ms), so step rate must be multipled by 1000
to change it to microseconds (us). */
if(w->step_timer >= (w->stepRate*1000)) {
w->direction_pin = 0;
w->current_track--;
// step the disk image index down track bytes
// w->disk_img_index_pointer -= (w->sector_length * w->sectors_per_track);
// reset step timer
w->step_timer = 0.0;
}
}
} // END RESTORE
else if(w->currentCommandName == "SEEK") {
/* check if track register == data register (SEEK command assumes that
the data register contains the target track) */
if(w->trackRegister == w->dataRegister) { // SEEK found the target track
w->command_action_done = 1; // indicate end of command action
printf("%s\n", "SEEK found target track - command action DONE");
return;
}
else if(w->trackRegister > w->dataRegister) { // must step out
w->step_timer += us;
if(w->step_timer >= (w->stepRate*1000)) {
w->direction_pin = 0;
w->current_track--;
// step the disk image index down track bytes
// w->disk_img_index_pointer -= (w->sector_length * w->sectors_per_track);
// update track register with current track
w->trackRegister = w->current_track;
// reset step timer
w->step_timer = 0.0;
}
}
else if(w->trackRegister < w->dataRegister) { // must step in
w->step_timer += us;
if(w->step_timer >= (w->stepRate*1000)) {
w->direction_pin = 1;
w->current_track++;
// step the disk image index up track bytes
// w->disk_img_index_pointer += (w->sector_length * w->sectors_per_track);
// update track register with current track
w->trackRegister = w->current_track;
// reset step timer
w->step_timer = 0.0;
}
}
} // END SEEK
else if(w->currentCommandName == "STEP") {
/* check if direction is step out with track already at TRACK 00
(can not go to -1 track) */
if(w->not_track00_pin == 0 && w->direction_pin == 0) {
// update track register to 0 regardless of track update flag
w->trackRegister = 0;
w->command_action_done = 1; // indicate end of command action
printf("\n%s\n\n", "STEP - command action DONE (tried to step to track -1)");
return;
}
// check if step would put head past the number of tracks on the disk
else if((w->current_track == (w->cylinders - 1)) && w->direction_pin == 1) {
w->command_action_done = 1;
printf("\n%s\n\n", "STEP - command action DONE (tried to step past track limit)");
return;
}
else {
w->step_timer += us;
/* check step timer - has it completed one step according to the step rate?
Step rates are in milliseconds (ms), so step rate must be multipled by 1000
to change it to microseconds (us). */
if(w->step_timer >= (w->stepRate*1000)) {
// step track according to direction_pin
if(w->direction_pin == 0) {
w->current_track--;
// w->disk_img_index_pointer -= (w->sector_length * w->sectors_per_track);
}
else if(w->direction_pin == 1) {
w->current_track++;
// w->disk_img_index_pointer += (w->sector_length * w->sectors_per_track);
}
// update track register if track update flag is high
if(w->trackUpdateFlag) {w->trackRegister = w->current_track;}
// reset step timer
w->step_timer = 0.0;
w->command_action_done = 1; // indicate end of command action
printf("%s\n", "STEP - command action DONE");
return;
}
}
} // END STEP
else if(w->currentCommandName == "STEP-IN") {
if((w->current_track == (w->cylinders - 1))) {
w->command_action_done = 1;
printf("\n%s\n\n", "STEP-IN - command action DONE (tried to step past track limit)");
return;
}
w->step_timer += us;
/* check step timer - has it completed one step according to the step rate?
Step rates are in milliseconds (ms), so step rate must be multipled by 1000
to change it to microseconds (us). */
if(w->step_timer >= (w->stepRate*1000)) {
// step track according to direction_pin
w->current_track++;
// w->disk_img_index_pointer += (w->sector_length * w->sectors_per_track);
// update track register if track update flag is high
if(w->trackUpdateFlag) {w->trackRegister = w->current_track;}
// reset step timer
w->step_timer = 0.0;
w->command_action_done = 1; // indicate end of command action
printf("%s\n", "STEP-IN - command action DONE");
return;
}
}
else if(w->currentCommandName == "STEP-OUT") {
if(w->not_track00_pin == 0) {
// update track register to 0 regardless of track update flag
w->trackRegister = 0;
w->command_action_done = 1; // indicate end of command action
printf("\n%s\n\n", "STEP-OUT - command action DONE (tried to step to track -1)");
return;
}
else {
w->step_timer += us;
/* check step timer - has it completed one step according to the step rate?
Step rates are in milliseconds (ms), so step rate must be multipled by 1000
to change it to microseconds (us). */
if(w->step_timer >= (w->stepRate*1000)) {
// step track according to direction_pin
w->current_track--;
// w->disk_img_index_pointer -= (w->sector_length * w->sectors_per_track);
// update track register if track update flag is high
if(w->trackUpdateFlag) {w->trackRegister = w->current_track;}
// reset step timer
w->step_timer = 0.0;
w->command_action_done = 1; // indicate end of command action
printf("%s\n", "STEP - command action DONE");
return;
}
}
} // END STEP-OUT
} // END command action section
// ----------------------------------------------------
/* after all steps are done (reached track 00 in the case of RESTORE)
take care of post command varifications and delays */
else if(w->command_action_done) {
// take care of delayed HLD
if(w->delayed_HLD && w->HLD_pin == 0) {
w->HLT_timer_active = 1;
w->HLT_timer = 0.0;
w->HLD_pin = 1;
// one shot from HLD pin resets HLT pin
w->HLT_pin = 0;
// w->HLD_idle_reset_timer = 0.0;
// reset delayed HLD flag
w->delayed_HLD = 0;
}
// if NO headload or yes headload and no verify
if(!w->verifyFlag) {
// no 30 ms verification delay and HLT is not sampled - command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
printf("%s\n", "command type I complete");
return;
}
// VERIFY still waiting on verify head settling...
else if(w->verifyFlag) {
typeIVerifySequence(w, us);
} // END VERIFY sequence
} // END verify/head settling phase
} // END TYPE I command
else if(w->currentCommandType == 2) {
// stall here until E delay clock has expired, if engaged
if(handleEDelay(w, us) == 0) {return;}
// sample HLT pin - do not continue with command if HLT pin has not engaged
if(w->HLT_pin == 0) {return;}
updateTG43Signal(w);
// ID Address mark verification
if(!w->ID_data_verified) {
w->verify_operation_active = 1;
typeIICmdIDVerify(w);
// if ID data has not been verified, do not continue type II cmd
return;
}
// verify op is done
w->verify_operation_active = 0;
// READ SECTOR
if(w->currentCommandName == "READ SECTOR") {
// ID address mark data is valid.. now look for Data Address mark (DATA AM)
if(!w->data_mark_found) {
if(w->new_byte_read_signal_) {
dataAddressMarkSearch(w);
}
return;
}
// ?? after DATA AM found, put reacord type in status bit 5 ??
// check if there is a new byte to read.. (ie. "assembled in DSR")
if(w->data_mark_found && !w->all_bytes_inputted) {
// is there a new byte in the DR
if(w->new_byte_read_signal_) {
/* did computer read the last data byte in the DR? If DRQ is still high,
it did not; set lost data bit in status */
if(w->drq == 1) {w->statusRegister |= 0b00000100;}
// last byte was read (DRQ = 0) reset lost data bit
else {w->statusRegister &= 0b11111011;}
// read current byte into data register
w->dataRegister = getFDiskByte(w);
printf("%X ", w->dataRegister);
// set drq and status drq status bit
w->drq = 1;
w->statusRegister |= 0b00000010;
// decrement data field byte counter
w->intSectorLength--;
// have all bytes in data field been read?
if(w->intSectorLength == 0) {w->all_bytes_inputted = 1;}
return;
}
return;
}
// check CRC *** the next two bytes..
//...
// check multiple records flag
if(w->multipleRecords) {
w->sectorRegister++;
// check if number of sectors have been exceeded
if(w->sectorRegister > w->sectors_per_track) {
// command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// assume verification operation is successful - generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
return;
}
// if sector number not out of bounds, find next sector
else {
w->verify_index_count = 0;
w->ID_data_verified = 0;
w->zero_byte_counter = 0;
w->address_mark_search_count = 0; /* after 16 bytes (MFM) */
w->a1_byte_counter = 0; // look for three 0xA1 bytes
w->id_field_found = 0;
w->id_field_data_array_pt = 0;
w->id_field_data_collected = 0;
w->data_a1_byte_counter = 0; // counter for 0xA1 bytes for data field
w->data_mark_search_count = 0;
w->data_mark_found = 0;
w->all_bytes_inputted = 0;
return;
}
printf("%s\n", "ERROR: SOMETHING WENT WRONG WITH READING MULTIPLE SECTORS");
return;
}
// command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// assume verification operation is successful - generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
return;
} // END READ SECTOR
// WRITE SECTOR (*** NOT IMPLEMENTED - command completes without executing ***)
else if(w->currentCommandName == "WRITE SECTOR") {
printf("%s\n", "@@ ** WD-1797 WRITE SECTOR NOT IMPLEMENTED! ** @@");
// command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// assume verification operation is successful - generate interrupt
// w->intrq = 1;
// e8259_set_irq0 (e8259_slave, 1);
return;
} // END WRITE SECTOR
} // END TYPE II command
else if(w->currentCommandType == 3) {
// do delay if E set and delay not done yet
if(w->e_delay_done == 0 && w->delay15ms) {
// clock the e delay timer
w->e_delay_timer += us;
// check if E delay timer has reached limit
if(w->e_delay_timer >= E_DELAY_LIMIT) {
w->e_delay_done = 1;
w->e_delay_timer = 0.0;
}
return; // delay still in progess - do not continue with command
}
// check HLT
if(w->HLT_pin == 0) {return;}
updateTG43Signal(w);
if(w->currentCommandName == "READ ADDRESS") {
/* if ID address mark has not been found yet, verify active so that
index timeout count is incremented in doJWD1797Cycle() */
if(!w->id_field_found) {
w->verify_operation_active = 1; // verify operation = IDAM detection
// new byte available?
if(w->new_byte_read_signal_) {
// continue search for IDAM...
IDAddressMarkSearch(w);
}
// check if index pass timed out..
verifyIndexTimeout(w, 6);
return;
}
else {w->verify_operation_active = 0;}
// still collecting IDAM bytes.. new byte available?
if(w->IDAM_byte_count < 6) {
if(w->new_byte_read_signal_) {
w->dataRegister = getFDiskByte(w);
w->id_field_data[w->IDAM_byte_count] = w->dataRegister;
w->drq = 1;
w->statusRegister |= 0b00000010;
w->IDAM_byte_count++;
return;
}
return;
}
// tansfer track IDAM data byte to sector register
w->sectorRegister = w->id_field_data[0];
if(verifyCRC(w)) {
return;
}
else {
// command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// assume verification operation is successful - generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
// reset HLD idle timer
return;
}
}
else if(w->currentCommandName == "READ TRACK") {
// is there an index pulse?
if(w->index_pulse_pin) {
w->start_track_read_ = 1;
}
// wait for index pulse
if(!w->start_track_read_) {
return;
}
// new byte available?
if(w->new_byte_read_signal_) {
/* is there an index pulse? Wait until after GAP 4a has passed (80 x 0x4E)
before starting to look for another index pulse */
if((w->read_track_bytes_read > 80) && (w->index_pulse_pin)) {
// command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// assume verification operation is successful - generate interrupt
w->intrq = 1;
e8259_set_irq0 (e8259_slave, 1);
// reset HLD idle timer
return;
}
/* did computer read the last data byte in the DR? If DRQ is still high,
it did not; set lost data bit in status */
if(w->drq == 1) {w->statusRegister |= 0b00000100;}
// last byte was read (DRQ = 0) reset lost data bit
else {w->statusRegister &= 0b11111011;}
// read current byte into data register
w->dataRegister = getFDiskByte(w);
// read track takes up a new byte
w->read_track_bytes_read++;
// set drq and status drq status bit
w->drq = 1;
w->statusRegister |= 0b00000010;
return;
}
}
else if(w->currentCommandName == "WRITE TRACK") {
printf("%s\n", "@@ ** WD-1797 WRITE TRACK NOT IMPLEMENTED! ** @@");
// command is done
w->command_done = 1;
w->statusRegister &= 0b11111110; // reset (clear) busy status bit
// w->HLD_idle_reset_timer = 0.0;
// assume verification operation is successful - generate interrupt
// w->intrq = 1;
// e8259_set_irq0 (e8259_slave, 1);
return;
}
} // END TYPE III command
} // END general command step
/*
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++ HELPER FUNCTIONS ++++++++++++++++++++++++++++++++++++++++++
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
*/
void setupTypeICommand(JWD1797* w) {
// printf("TYPE I Command in WD1797 command register..\n");
w->currentCommandType = 1;
w->command_action_done = 0;
w->command_done = 0;
w->head_settling_done = 0;
w->step_timer = 0.0;
w->verify_operation_active = 0;
w->verify_index_count = 0;
w->zero_byte_counter = 0;
w->address_mark_search_count = 0; /* after 16 bytes (MFM) */
w->a1_byte_counter = 0; // look for three 0xA1 bytes
w->id_field_found = 0;
w->id_field_data_array_pt = 0;
w->id_field_data_collected = 0;
// set appropriate status bits for type I command to start
typeIStatusReset(w);
// establish step rate options (in ms) for 1MHz clock (only used with TYPE I cmds)