From c4ce534e11f8179a3a829b640d2c1d4c0cdbe963 Mon Sep 17 00:00:00 2001 From: Muhammed Efe Cetin Date: Sat, 4 Jan 2025 20:54:50 +0300 Subject: [PATCH] Add support for both eMMC/SPI boot --- config/boards/nanopi-m6.conf | 7 +- .../defconfig/nanopi-m6-rk3588s_defconfig | 1 - .../defconfig/nanopi-m6-spi-rk3588s_defconfig | 226 ++++++++++++++++++ .../dt/rk3588s-nanopi-m6-spi.dts | 48 ++++ .../dt/rk3588s-nanopi-m6.dts | 33 --- 5 files changed, 279 insertions(+), 36 deletions(-) create mode 100644 patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-spi-rk3588s_defconfig create mode 100644 patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6-spi.dts diff --git a/config/boards/nanopi-m6.conf b/config/boards/nanopi-m6.conf index 5ca16a55206a..0589dccd0a7c 100644 --- a/config/boards/nanopi-m6.conf +++ b/config/boards/nanopi-m6.conf @@ -10,11 +10,14 @@ BOOT_LOGO="desktop" IMAGE_PARTITION_TABLE="gpt" BOOT_FDT_FILE="rockchip/rk3588s-nanopi-m6.dtb" BOOT_SCENARIO="spl-blobs" -BOOT_SUPPORT_SPI="yes" -BOOT_SPI_RKSPI_LOADER="yes" DEFAULT_OVERLAYS="nanopi-m6-display-dsi1-yx35" # Enable YX35 LCD +function post_family_config__nanopi_m6_support_spi_boot() { + UBOOT_TARGET_MAP="nanopi-m6-rk3588s_defconfig BL31=$RKBIN_DIR/$BL31_BLOB spl/u-boot-spl.bin u-boot.dtb u-boot.itb;;idbloader.img u-boot.itb +nanopi-m6-spi-rk3588s_defconfig BL31=$RKBIN_DIR/$BL31_BLOB;; rkspi_loader.img" +} + function post_family_tweaks__nanopim6_naming_udev_audios() { display_alert "$BOARD" "Renaming NanoPi M6 HDMI audio" "info" diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-rk3588s_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-rk3588s_defconfig index 60f98d8b4d3d..60c77804f5af 100644 --- a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-rk3588s_defconfig +++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-rk3588s_defconfig @@ -173,7 +173,6 @@ CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_DEBUG_UART_SHIFT=2 CONFIG_ROCKCHIP_SPI=y -CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-spi-rk3588s_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-spi-rk3588s_defconfig new file mode 100644 index 000000000000..8b95a50448ef --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/nanopi-m6-spi-rk3588s_defconfig @@ -0,0 +1,226 @@ +CONFIG_ARM=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x80000 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" +CONFIG_ROCKCHIP_RK3588=y +CONFIG_ROCKCHIP_USB_BOOT=y +CONFIG_ROCKCHIP_FIT_IMAGE=y +CONFIG_ROCKCHIP_HWID_DTB=y +CONFIG_ROCKCHIP_VENDOR_PARTITION=y +CONFIG_USING_KERNEL_DTB_V2=y +CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y +CONFIG_ROCKCHIP_NEW_IDB=y +CONFIG_LOADER_INI="RK3588MINIALL.ini" +CONFIG_TRUST_INI="RK3588TRUST.ini" +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_EVB_RK3588=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_DEFAULT_DEVICE_TREE="rk3588s-nanopi-m6-spi" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_IMAGE_POST_PROCESS=y +CONFIG_FIT_HW_CRYPTO=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y +CONFIG_SPL_FIT_HW_CRYPTO=y +# CONFIG_SPL_SYS_DCACHE_OFF is not set +CONFIG_BOOTDELAY=0 +CONFIG_SYS_CONSOLE_INFO_QUIET=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_ANDROID_BOOTLOADER=y +CONFIG_ANDROID_AVB=y +CONFIG_ANDROID_BOOT_IMAGE_HASH=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set +# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1 +CONFIG_SPL_MMC_WRITE=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_ATF=y +CONFIG_FASTBOOT_BUF_ADDR=0xc00800 +CONFIG_FASTBOOT_BUF_SIZE=0x04000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DTIMG=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_FPGA is not set +CONFIG_CMD_GPT=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_BOOT_ANDROID=y +CONFIG_CMD_MMC=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_TFTP_BOOTM=y +CONFIG_CMD_TFTP_FLASH=y +# CONFIG_CMD_MISC is not set +CONFIG_CMD_MTD_BLK=y +CONFIG_CMD_REGULATOR=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DTB_MINIMUM=y +CONFIG_OF_LIVE=y +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +# CONFIG_NET_TFTP_VARS is not set +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +# CONFIG_SARADC_ROCKCHIP is not set +CONFIG_SARADC_ROCKCHIP_V2=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_SCMI=y +CONFIG_SPL_CLK_SCMI=y +CONFIG_DM_CRYPTO=y +CONFIG_SPL_DM_CRYPTO=y +CONFIG_ROCKCHIP_CRYPTO_V2=y +CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y +CONFIG_DM_RNG=y +CONFIG_RNG_ROCKCHIP=y +CONFIG_SCMI_FIRMWARE=y +CONFIG_SPL_SCMI_FIRMWARE=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_ROCKCHIP_GPIO_V2=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_DM_KEY=y +CONFIG_ADC_KEY=y +CONFIG_MISC=y +CONFIG_SPL_MISC=y +CONFIG_MISC_DECOMPRESS=y +CONFIG_SPL_MISC_DECOMPRESS=y +CONFIG_ROCKCHIP_OTP=y +CONFIG_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y +CONFIG_SPL_ROCKCHIP_SECURE_OTP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_MTD=y +CONFIG_MTD_BLK=y +CONFIG_MTD_DEVICE=y +CONFIG_NAND=y +CONFIG_MTD_SPI_NAND=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=80000000 +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_DM_ETH_PHY=y +CONFIG_DWC_ETH_QOS=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_NVME=y +CONFIG_PCI=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_DW_ROCKCHIP=y +CONFIG_PHY_ROCKCHIP_INNO_USB2=y +CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y +CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y +CONFIG_PHY_ROCKCHIP_USBDP=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_SPI_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_REGULATOR_RK860X=y +CONFIG_REGULATOR_RK806=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_TPL_RAM=y +CONFIG_ROCKCHIP_SDRAM_COMMON=y +CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 +CONFIG_DM_RESET=y +CONFIG_SPL_DM_RESET=y +CONFIG_SPL_RESET_ROCKCHIP=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_BASE=0xFEB50000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_ROCKCHIP_SPI=y +CONFIG_ROCKCHIP_SFC=y +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC3=y +CONFIG_USB_DWC3_GADGET=y +CONFIG_USB_DWC3_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x350a +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +CONFIG_DISPLAY=y +CONFIG_DRM_ROCKCHIP=y +CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y +CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y +CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_LIB_RAND=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_RSA_N_SIZE=0x200 +CONFIG_RSA_E_SIZE=0x10 +CONFIG_RSA_C_SIZE=0x20 +CONFIG_LZ4=y +CONFIG_ERRNO_STR=y +# CONFIG_EFI_LOADER is not set +CONFIG_AVB_LIBAVB=y +CONFIG_AVB_LIBAVB_AB=y +CONFIG_AVB_LIBAVB_ATX=y +CONFIG_AVB_LIBAVB_USER=y +CONFIG_RK_AVB_LIBAVB_USER=y +CONFIG_LZMA=y +CONFIG_XBC=y +CONFIG_CMD_SETEXPR=y +CONFIG_AHCI=y +CONFIG_CMD_SCSI=y +CONFIG_DM_SCSI=y +CONFIG_DWC_AHCI=y +CONFIG_LIBATA=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6-spi.dts b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6-spi.dts new file mode 100644 index 000000000000..8969e882730e --- /dev/null +++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6-spi.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Rockchip Electronics Co., Ltd + * + */ + +/dts-v1/; +#include "rk3588s-nanopi-m6.dts" + +&sdhci { + status = "disabled"; +}; + +&sfc { + u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&fspim0_pins>; + status = "okay"; +}; + +&spi_nor { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&pinctrl { + + /delete-node/ fspi; + fspi { + u-boot,dm-spl; + fspim0_pins: fspim0-pins { + u-boot,dm-spl; + rockchip,pins = + /* fspi_clk_m0 */ + <2 RK_PA0 2 &pcfg_pull_none>, + /* fspi_cs0n_m0 */ + <2 RK_PD6 2 &pcfg_pull_none>, + /* fspi_d0_m0 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* fspi_d1_m0 */ + <2 RK_PD1 2 &pcfg_pull_none>, + /* fspi_d2_m0 */ + <2 RK_PD2 2 &pcfg_pull_none>, + /* fspi_d3_m0 */ + <2 RK_PD3 2 &pcfg_pull_none>; + }; + }; +}; diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6.dts b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6.dts index dcc64e022194..78774bc21af9 100644 --- a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6.dts +++ b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3588s-nanopi-m6.dts @@ -174,40 +174,7 @@ status = "okay"; }; -&sfc { - u-boot,dm-pre-reloc; - pinctrl-names = "default"; - pinctrl-0 = <&fspim0_pins>; - status = "okay"; -}; - -&spi_nor { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &pinctrl { - /delete-node/ fspi; - fspi { - u-boot,dm-spl; - fspim0_pins: fspim0-pins { - u-boot,dm-spl; - rockchip,pins = - /* fspi_clk_m0 */ - <2 RK_PA0 2 &pcfg_pull_none>, - /* fspi_cs0n_m0 */ - <2 RK_PD6 2 &pcfg_pull_none>, - /* fspi_d0_m0 */ - <2 RK_PD0 2 &pcfg_pull_none>, - /* fspi_d1_m0 */ - <2 RK_PD1 2 &pcfg_pull_none>, - /* fspi_d2_m0 */ - <2 RK_PD2 2 &pcfg_pull_none>, - /* fspi_d3_m0 */ - <2 RK_PD3 2 &pcfg_pull_none>; - }; - }; - pcie { u-boot,dm-pre-reloc; pcie_m2_0_pwren: pcie-m20-pwren {