diff --git a/Makefile b/Makefile index 9e8d285..58d99ea 100755 --- a/Makefile +++ b/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/README.md b/README.md index bd82362..58bafe9 100644 --- a/README.md +++ b/README.md @@ -165,10 +165,72 @@ absolutely you don't need to. ```bash sudo lspci -v -d ::0200 | grep 81 +<<<<<<< HEAD 2a:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05) Kernel driver in use: r8125 Kernel modules: r8169, r8125 ``` +||||||| a9a0ddf +```bash +sudo tee -a /etc/modprobe.d/blacklist-r8169.conf > /dev/null < - If you need to load both r8169 and r8125, maybe removing r8125 firmware could make it work. Please enter `sudo rm -f /lib/firmware/rtl_nic/rtl8125*` to remove all the r8125 firmwares on the system. But it is just a workaround, you should have to do this every time installing the new kernel version or new Linux firmware. +> - In the case of the Debian package, I will update the scripts to make it do this during the installation. + +## Debian package build + +You can build yourself this after installing some dependencies including `dkms`. + +```bash +sudo apt install devscripts debmake debhelper build-essential dkms +``` + +```bash +dpkg-buildpackage -b -rfakeroot -us -uc +``` +======= +```bash +sudo tee -a /etc/modprobe.d/blacklist-r8169.conf > /dev/null < - If you need to load both r8169 and r8125, maybe removing r8125 firmware could make it work. Please enter `sudo rm -f /lib/firmware/rtl_nic/rtl8125*` to remove all the r8125 firmwares on the system. But it is just a workaround, you should have to do this every time installing the new kernel version or new Linux firmware. +> - In the case of the Debian package, I will update the scripts to make it do this during the installation. + +## Debian package build + +You can build yourself this after installing some dependencies including `dkms`. + +```bash +sudo apt install devscripts debmake debhelper build-essential dkms +``` + +```bash +dpkg-buildpackage -b -rfakeroot -us -uc +``` +>>>>>>> origin/master ## LICENSE @@ -176,5 +238,5 @@ GPL-2 on Realtek driver and the Debian packing. ## References -- [Realtek r8125 driver release page](https://www.realtek.com/en/component/zoo/category/network-interface-controllers-10-100-1000m-gigabit-ethernet-pci-express-software) +- [Realtek r8125 driver release page](https://www.realtek.com/Download/List?cate_id=584) - [ParrotSec's realtek-rtl88xxau-dkms, where got hint from](https://github.com/ParrotSec/realtek-rtl88xxau-dkms) diff --git a/REALTEK_README.txt b/REALTEK_README.txt old mode 100755 new mode 100644 index 3348a04..51eeb30 --- a/REALTEK_README.txt +++ b/REALTEK_README.txt @@ -1,6 +1,6 @@ - This is the Linux device driver released for RealTek RTL8125 2.5Gigabit Ethernet controllers with PCI-Express interface. + This is the Linux device driver released for Realtek 2.5 Gigabit Ethernet controllers with PCI-Express interface. diff --git a/debian/changelog b/debian/changelog index 4e2bc87..bcfdf69 100644 --- a/debian/changelog +++ b/debian/changelog @@ -1,3 +1,39 @@ +realtek-r8125-dkms (9.013.02-2) stable; urgency=medium + + * Rename BASEDIR to BSRC in dkms.conf + + -- Deokgyu Yang Mon, 22 Apr 2024 18:14:49 +0900 + +realtek-r8125-dkms (9.013.02-1) stable; urgency=medium + + * Update Realtek r8125 driver to 9.013.02 + + -- Deokgyu Yang Mon, 08 Apr 2024 12:19:25 +0900 + +realtek-r8125-dkms (9.012.04-1) stable; urgency=medium + + * Update Realtek r8125 driver to 9.012.04 + + -- Deokgyu Yang Tue, 02 Jan 2024 12:27:51 +0900 + +realtek-r8125-dkms (9.012.03-2) stable; urgency=medium + + * Fixed using wrong source code directory when installing new kernel + + -- Deokgyu Yang Fri, 01 Dec 2023 15:49:48 +0900 + +realtek-r8125-dkms (9.012.03-1) stable; urgency=medium + + * Update Realtek r8125 driver to 9.012.03 + + -- Deokgyu Yang Sat, 04 Nov 2023 15:28:48 +0900 + +realtek-r8125-dkms (9.011.01-1) stable; urgency=medium + + * Update Realtek r8125 driver to 9.011.01 + + -- Deokgyu Yang Wed, 26 Apr 2023 13:55:30 +0900 + realtek-r8125-dkms (9.011.00-1) stable; urgency=medium * Update Realtek r8125 driver to 9.011.00 with remaining support for kernel diff --git a/debian/control b/debian/control index 343142d..7b567d7 100644 --- a/debian/control +++ b/debian/control @@ -2,8 +2,8 @@ Source: realtek-r8125-dkms Section: contrib/kernel Priority: optional Maintainer: Deokgyu Yang -Build-Depends: debhelper (>=11~), dkms -Standards-Version: 4.1.4 +Build-Depends: debhelper (>=11~), dkms (<< 3.0.3-3~) | dh-sequence-dkms +Standards-Version: 4.6.2.1 Homepage: https://github.com/awesometic/realtek-r8125-dkms Package: realtek-r8125-dkms diff --git a/debian/prerm b/debian/prerm index 52f6f67..2a125cf 100644 --- a/debian/prerm +++ b/debian/prerm @@ -1,7 +1,7 @@ #!/bin/sh NAME=realtek-r8125 -VERSION=9.011.00 +VERSION=9.013.02 set -e diff --git a/dkms-install.sh b/dkms-install.sh index de277a4..cf70aba 100755 --- a/dkms-install.sh +++ b/dkms-install.sh @@ -9,7 +9,7 @@ fi DRV_DIR="$(pwd)" DRV_NAME=r8125 -DRV_VERSION=9.011.00 +DRV_VERSION=9.013.02 cp -r ${DRV_DIR} /usr/src/${DRV_NAME}-${DRV_VERSION} diff --git a/dkms-remove.sh b/dkms-remove.sh index 0f5e6cf..3f6163e 100755 --- a/dkms-remove.sh +++ b/dkms-remove.sh @@ -9,7 +9,7 @@ fi DRV_DIR="$(pwd)" DRV_NAME=r8125 -DRV_VERSION=9.011.00 +DRV_VERSION=9.013.02 dkms remove ${DRV_NAME}/${DRV_VERSION} --all rm -rf /usr/src/${DRV_NAME}-${DRV_VERSION} diff --git a/dkms.conf b/dkms.conf index 36c654c..960d291 100644 --- a/dkms.conf +++ b/dkms.conf @@ -1,5 +1,5 @@ PACKAGE_NAME="realtek-r8125" -PACKAGE_VERSION="9.011.00" +PACKAGE_VERSION="9.013.02" PROCS_NUM=`nproc` [ $PROCS_NUM -gt 16 ] && PROCS_NUM=16 MAKE="'make' -j$PROCS_NUM KVER=${kernelver} BSRC=/lib/modules/${kernelver} modules" diff --git a/src/Makefile b/src/Makefile old mode 100755 new mode 100644 index 10a002a..5051f7e --- a/src/Makefile +++ b/src/Makefile @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -41,13 +41,13 @@ ENABLE_S5_KEEP_CURR_MAC = n ENABLE_EEE = y ENABLE_S0_MAGIC_PACKET = n ENABLE_TX_NO_CLOSE = y -ENABLE_MULTIPLE_TX_QUEUE = n +ENABLE_MULTIPLE_TX_QUEUE = y ENABLE_PTP_SUPPORT = n ENABLE_PTP_MASTER_MODE = n ENABLE_RSS_SUPPORT = n ENABLE_LIB_SUPPORT = n ENABLE_USE_FIRMWARE_FILE = n -DISABLE_PM_SUPPORT = n +DISABLE_WOL_SUPPORT = n DISABLE_MULTI_MSIX_VECTOR = n ENABLE_DOUBLE_VLAN = n ENABLE_PAGE_REUSE = n @@ -116,8 +116,8 @@ ifneq ($(KERNELRELEASE),) r8125-objs += r8125_firmware.o EXTRA_CFLAGS += -DENABLE_USE_FIRMWARE_FILE endif - ifeq ($(DISABLE_PM_SUPPORT), y) - EXTRA_CFLAGS += -DDISABLE_PM_SUPPORT + ifeq ($(DISABLE_WOL_SUPPORT), y) + EXTRA_CFLAGS += -DDISABLE_WOL_SUPPORT endif ifeq ($(DISABLE_MULTI_MSIX_VECTOR), y) EXTRA_CFLAGS += -DDISABLE_MULTI_MSIX_VECTOR diff --git a/src/Makefile_linux24x b/src/Makefile_linux24x old mode 100755 new mode 100644 index 50aef8d..05c1f6d --- a/src/Makefile_linux24x +++ b/src/Makefile_linux24x @@ -1,10 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-only ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/r8125.h b/src/r8125.h old mode 100755 new mode 100644 index 2aad6c5..0d7474f --- a/src/r8125.h +++ b/src/r8125.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -47,12 +47,77 @@ #include "r8125_lib.h" #endif +#ifndef fallthrough +#define fallthrough +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4,3,0) +static inline +ssize_t strscpy(char *dest, const char *src, size_t count) +{ + long res = 0; + + if (count == 0) + return -E2BIG; + + while (count) { + char c; + + c = src[res]; + dest[res] = c; + if (!c) + return res; + res++; + count--; + } + + /* Hit buffer length without finding a NUL; force NUL-termination. */ + if (res) + dest[res-1] = '\0'; + + return -E2BIG; +} +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)) +static inline unsigned char *skb_checksum_start(const struct sk_buff *skb) +{ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)) + return skb->head + skb->csum_start; +#else /* < 2.6.22 */ + return skb_transport_header(skb); +#endif +} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3,3,0) +static inline void netdev_tx_sent_queue(struct netdev_queue *dev_queue, + unsigned int bytes) +{ +} +static inline void netdev_tx_completed_queue(struct netdev_queue *dev_queue, + unsigned int pkts, + unsigned int bytes) +{ +} +static inline void netdev_tx_reset_queue(struct netdev_queue *q) {} +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,2,0) +#define netdev_xmit_more() (0) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5,8,0) +#define netif_testing_on(dev) +#define netif_testing_off(dev) +#endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) typedef int netdev_tx_t; #endif #if LINUX_VERSION_CODE < KERNEL_VERSION(5,12,0) -static inline bool dev_page_is_reusable(const struct page *page) +static inline bool dev_page_is_reusable(struct page *page) { return likely(page_to_nid(page) == numa_mem_id() && !page_is_pfmemalloc(page)); @@ -170,10 +235,13 @@ do { \ #endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,0,0) #define RTL_ALLOC_SKB_INTR(napi, length) dev_alloc_skb(length) +#define R8125_USE_NAPI_ALLOC_SKB 0 #ifdef CONFIG_R8125_NAPI #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,19,0) #undef RTL_ALLOC_SKB_INTR #define RTL_ALLOC_SKB_INTR(napi, length) napi_alloc_skb(napi, length) +#undef R8125_USE_NAPI_ALLOC_SKB +#define R8125_USE_NAPI_ALLOC_SKB 1 #endif #endif @@ -207,6 +275,10 @@ do { \ #define ENABLE_R8125_PROCFS #endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) +#define ENABLE_R8125_SYSFS +#endif + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) #define NETIF_F_HW_VLAN_RX NETIF_F_HW_VLAN_CTAG_RX #define NETIF_F_HW_VLAN_TX NETIF_F_HW_VLAN_CTAG_TX @@ -314,6 +386,10 @@ do { \ #define MDIO_EEE_1000T 0x0004 #endif +#ifndef MDIO_EEE_2_5GT +#define MDIO_EEE_2_5GT 0x0001 +#endif + #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,29) #ifdef CONFIG_NET_POLL_CONTROLLER #define RTL_NET_POLL_CONTROLLER dev->poll_controller=rtl8125_netpoll @@ -398,19 +474,19 @@ do { \ #define RSS_SUFFIX "" #endif -#define RTL8125_VERSION "9.011.00" NAPI_SUFFIX DASH_SUFFIX REALWOW_SUFFIX PTP_SUFFIX RSS_SUFFIX +#define RTL8125_VERSION "9.013.02" NAPI_SUFFIX DASH_SUFFIX REALWOW_SUFFIX PTP_SUFFIX RSS_SUFFIX #define MODULENAME "r8125" #define PFX MODULENAME ": " #define GPL_CLAIM "\ -r8125 Copyright (C) 2022 Realtek NIC software team \n \ +r8125 Copyright (C) 2024 Realtek NIC software team \n \ This program comes with ABSOLUTELY NO WARRANTY; for details, please see . \n \ This is free software, and you are welcome to redistribute it under certain conditions; see . \n" #ifdef RTL8125_DEBUG #define assert(expr) \ if(!(expr)) { \ - printk( "Assertion failed! %s,%s,%s,line=%d\n", \ + printk("Assertion failed! %s,%s,%s,line=%d\n", \ #expr,__FILE__,__FUNCTION__,__LINE__); \ } #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0) @@ -448,7 +524,9 @@ This is free software, and you are welcome to redistribute it under certain cond #endif #define Reserved2_data 7 -#define RX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */ +#define RX_DMA_BURST_unlimited 7 /* Maximum PCI burst, '7' is unlimited */ +#define RX_DMA_BURST_512 5 +#define RX_DMA_BURST_256 4 #define TX_DMA_BURST_unlimited 7 #define TX_DMA_BURST_1024 6 #define TX_DMA_BURST_512 5 @@ -472,6 +550,8 @@ This is free software, and you are welcome to redistribute it under certain cond #define RxEarly_off_V1 (0x07 << 11) #define RxEarly_off_V2 (1 << 11) #define Rx_Single_fetch_V2 (1 << 14) +#define Rx_Close_Multiple (1 << 21) +#define Rx_Fetch_Number_8 (1 << 30) #define R8125_REGS_SIZE (256) #define R8125_MAC_REGS_SIZE (256) @@ -482,8 +562,12 @@ This is free software, and you are welcome to redistribute it under certain cond #define R8125_PCI_REGS_SIZE (0x100) #define R8125_NAPI_WEIGHT 64 +#define R8125_MAX_MSIX_VEC_8125A 4 #define R8125_MAX_MSIX_VEC_8125B 32 -#define R8125_MIN_MSIX_VEC_8125B 17 +#define R8125_MAX_MSIX_VEC_8125D 32 +#define R8125_MIN_MSIX_VEC_8125B 22 +#define R8125_MIN_MSIX_VEC_8125BP 31 +#define R8125_MIN_MSIX_VEC_8125D 20 #define R8125_MAX_MSIX_VEC 32 #define R8125_MAX_RX_QUEUES_VEC_V3 (16) @@ -502,7 +586,13 @@ This is free software, and you are welcome to redistribute it under certain cond #define NUM_TX_DESC MAX_NUM_TX_DESC /* Number of Tx descriptor registers */ #define NUM_RX_DESC MAX_NUM_RX_DESC /* Number of Rx descriptor registers */ -#define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */ +#ifdef ENABLE_DOUBLE_VLAN +#define RX_BUF_SIZE 0x05F6 /* 0x05F6(1526) = 1514 + 8(double vlan) + 4(crc) bytes */ +#define RT_VALN_HLEN 8 /* 8(double vlan) bytes */ +#else +#define RX_BUF_SIZE 0x05F2 /* 0x05F2(1522) = 1514 + 4(single vlan) + 4(crc) bytes */ +#define RT_VALN_HLEN 4 /* 4(single vlan) bytes */ +#endif #define R8125_MAX_TX_QUEUES (2) #define R8125_MAX_RX_QUEUES (4) @@ -586,7 +676,6 @@ This is free software, and you are welcome to redistribute it under certain cond #ifndef ADVERTISED_2500baseX_Full #define ADVERTISED_2500baseX_Full 0x8000 #endif -#define RTK_ADVERTISED_5000baseX_Full BIT(48) #define RTK_ADVERTISE_2500FULL 0x80 #define RTK_ADVERTISE_5000FULL 0x100 @@ -595,14 +684,18 @@ This is free software, and you are welcome to redistribute it under certain cond #define RTK_LPA_ADVERTISE_5000FULL 0x40 #define RTK_LPA_ADVERTISE_10000FULL 0x800 -#define RTK_EEE_ADVERTISE_2500FULL 0x01 -#define RTK_LPA_EEE_ADVERTISE_2500FULL 0x01 +#define RTK_EEE_ADVERTISE_2500FULL BIT(0) +#define RTK_EEE_ADVERTISE_5000FULL BIT(1) +#define RTK_LPA_EEE_ADVERTISE_2500FULL BIT(0) +#define RTK_LPA_EEE_ADVERTISE_5000FULL BIT(1) /* Tx NO CLOSE */ #define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000 #define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2 0xFFFF #define MAX_TX_NO_CLOSE_DESC_PTR_V3 0x100000000 #define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3 0xFFFFFFFF +#define MAX_TX_NO_CLOSE_DESC_PTR_V4 0x80000000 +#define MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4 0x7FFFFFFF #define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF #ifndef ETH_MIN_MTU @@ -622,16 +715,12 @@ This is free software, and you are welcome to redistribute it under certain cond #define READ_ONCE(var) (*((volatile typeof(var) *)(&(var)))) #endif -#ifndef SPEED_5000 -#define SPEED_5000 5000 -#endif - /*****************************************************************************/ //#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) -#if (( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27) ) || \ - (( LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0) ) && \ - ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3) ))) +#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,4,27)) || \ + ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)) && \ + (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,3)))) /* copied from linux kernel 2.6.20 include/linux/netdev.h */ #define NETDEV_ALIGN 32 #define NETDEV_ALIGN_CONST (NETDEV_ALIGN - 1) @@ -676,11 +765,11 @@ typedef int *napi_budget; typedef struct napi_struct *napi_ptr; typedef int napi_budget; -#if LINUX_VERSION_CODE < KERNEL_VERSION(6, 1, 0) -#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add(ndev, &priv->napi, function, weight) -#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0) #define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add_weight(ndev, &priv->napi, function, weight) -#endif +#else +#define RTL_NAPI_CONFIG(ndev, priv, function, weight) netif_napi_add(ndev, &priv->napi, function, weight) +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(6,1,0) #define RTL_NAPI_QUOTA(budget, ndev) min(budget, budget) #define RTL_GET_PRIV(stuct_ptr, priv_struct) container_of(stuct_ptr, priv_struct, stuct_ptr) #define RTL_GET_NETDEV(priv_ptr) struct net_device *dev = priv_ptr->dev; @@ -767,7 +856,7 @@ extern void __chk_io_ptr(void __iomem *); /*****************************************************************************/ /* 2.5.28 => 2.4.23 */ -#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28) ) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,28)) static inline void _kc_synchronize_irq(void) { @@ -788,12 +877,12 @@ static inline void _kc_synchronize_irq(void) /*****************************************************************************/ /* 2.6.4 => 2.6.0 */ -#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4) ) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,4)) #define MODULE_VERSION(_version) MODULE_INFO(version, _version) #endif /* 2.6.4 => 2.6.0 */ /*****************************************************************************/ /* 2.6.0 => 2.5.28 */ -#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0) ) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)) #define MODULE_INFO(version, _version) #ifndef CONFIG_E1000_DISABLE_PACKET_SPLIT #define CONFIG_E1000_DISABLE_PACKET_SPLIT 1 @@ -824,13 +913,13 @@ static inline int _kc_pci_dma_mapping_error(dma_addr_t dma_addr) /*****************************************************************************/ /* 2.4.22 => 2.4.17 */ -#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22) ) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,22)) #define pci_name(x) ((x)->slot_name) #endif /* 2.4.22 => 2.4.17 */ /*****************************************************************************/ /* 2.6.5 => 2.6.0 */ -#if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) ) +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5)) #define pci_dma_sync_single_for_cpu pci_dma_sync_single #define pci_dma_sync_single_for_device pci_dma_sync_single_for_cpu #endif /* 2.6.5 => 2.6.0 */ @@ -1276,6 +1365,13 @@ enum RTL8125_registers { IMR_V2_SET_REG_8125 = 0x0D0C, TDU_STA_8125 = 0x0D08, RDU_STA_8125 = 0x0D0A, + IMR_V4_L2_CLEAR_REG_8125 = 0x0D10, + IMR_V4_L2_SET_REG_8125 = 0x0D18, + ISR_V4_L2_8125 = 0x0D14, + SW_TAIL_PTR0_8125BP = 0x0D30, + SW_TAIL_PTR1_8125BP = 0x0D38, + HW_CLO_PTR0_8125BP = 0x0D34, + HW_CLO_PTR1_8125BP = 0x0D3C, DOUBLE_VLAN_CONFIG = 0x1000, TX_NEW_CTRL = 0x203E, TNPDS_Q1_LOW_8125 = 0x2100, @@ -1298,12 +1394,31 @@ enum RTL8125_registers { PTP_TIME_CORRECT_CMD_8125 = 0x6806, PTP_SOFT_CONFIG_Time_NS_8125 = 0x6808, PTP_SOFT_CONFIG_Time_S_8125 = 0x680C, + PTP_SOFT_CONFIG_Time_Sign = 0x6812, PTP_LOCAL_Time_SUB_NS_8125 = 0x6814, PTP_LOCAL_Time_NS_8125 = 0x6818, PTP_LOCAL_Time_S_8125 = 0x681C, PTP_Time_SHIFTER_S_8125 = 0x6856, PPS_RISE_TIME_NS_8125 = 0x68A0, PPS_RISE_TIME_S_8125 = 0x68A4, + PTP_EGRESS_TIME_BASE_NS_8125 = 0XCF20, + PTP_EGRESS_TIME_BASE_S_8125 = 0XCF24, + + //TCAM + TCAM_NOTVALID_ADDR = 0xA000, + TCAM_VALID_ADDR = 0xA800, + TCAM_MAC_ADDR = 448, + TCAM_VLAN_TAG = 496, + //TCAM V2 + TCAM_NOTVALID_ADDR_V2 = 0xA000, + TCAM_VALID_ADDR_V2 = 0xB000, + TCAM_MAC_ADDR_V2 = 0x00, + TCAM_VLAN_TAG_V2 = 0x03, + //ipc2 + IB2SOC_SET = 0x0010, + IB2SOC_DATA = 0x0014, + IB2SOC_CMD = 0x0018, + IB2SOC_IMR = 0x001C, }; enum RTL8125_register_content { @@ -1333,6 +1448,10 @@ enum RTL8125_register_content { RxRUNT_V3 = (1 << 19), RxCRC_V3 = (1 << 17), + RxRES_V4 = (1 << 22), + RxRUNT_V4 = (1 << 21), + RxCRC_V4 = (1 << 20), + /* ChipCmdBits */ StopReq = 0x80, CmdReset = 0x10, @@ -1367,6 +1486,7 @@ enum RTL8125_register_content { Reserved2_shift = 13, RxCfgDMAShift = 8, EnableRxDescV3 = (1 << 24), + EnableRxDescV4_1 = (1 << 24), EnableOuterVlan = (1 << 23), EnableInnerVlan = (1 << 22), RxCfg_128_int_en = (1 << 15), @@ -1374,6 +1494,7 @@ enum RTL8125_register_content { RxCfg_half_refetch = (1 << 13), RxCfg_pause_slot_en = (1 << 11), RxCfg_9356SEL = (1 << 6), + EnableRxDescV4_0 = (1 << 1), //not in rcr /* TxConfigBits */ TxInterFrameGapShift = 24, @@ -1534,16 +1655,28 @@ enum RTL8125_register_content { PTP_EXEC_CMD = (1 << 7), PTP_ADJUST_TIME_NS_NEGATIVE = (1 << 30), PTP_ADJUST_TIME_S_NEGATIVE = (1ULL << 48), + PTP_SOFT_CONFIG_TIME_NS_NEGATIVE = (1 << 30), + PTP_SOFT_CONFIG_TIME_S_NEGATIVE = (1ULL << 48), /* New Interrupt Bits */ INT_CFG0_ENABLE_8125 = (1 << 0), INT_CFG0_TIMEOUT0_BYPASS_8125 = (1 << 1), INT_CFG0_MITIGATION_BYPASS_8125 = (1 << 2), + INT_CFG0_RDU_BYPASS_8126 = (1 << 4), + INT_CFG0_MSIX_ENTRY_NUM_MODE = (1 << 5), ISRIMR_V2_ROK_Q0 = (1 << 0), ISRIMR_TOK_Q0 = (1 << 16), ISRIMR_TOK_Q1 = (1 << 18), ISRIMR_V2_LINKCHG = (1 << 21), + ISRIMR_V4_ROK_Q0 = (1 << 0), + ISRIMR_V4_LINKCHG = (1 << 29), + + ISRIMR_V5_ROK_Q0 = (1 << 0), + ISRIMR_V5_TOK_Q0 = (1 << 16), + ISRIMR_V5_TOK_Q1 = (1 << 17), + ISRIMR_V5_LINKCHG = (1 << 18), + /* Magic Number */ RTL8125_MAGIC_NUMBER = 0x0badbadbadbadbadull, }; @@ -1559,6 +1692,11 @@ enum _DescStatusBit { FirstFrag_V3 = (1 << 25), /* First segment of a packet */ LastFrag_V3 = (1 << 24), /* Final segment of a packet */ + DescOwn_V4 = (DescOwn), /* Descriptor is owned by NIC */ + RingEnd_V4 = (RingEnd), /* End of descriptor ring */ + FirstFrag_V4 = (FirstFrag), /* First segment of a packet */ + LastFrag_V4 = (LastFrag), /* Final segment of a packet */ + /* Tx private */ /*------ offset 0 of tx descriptor ------*/ LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ @@ -1617,7 +1755,7 @@ enum _DescStatusBit { RxIPF_v3 = (1 << 26), /* IP checksum failed */ RxUDPF_v3 = (1 << 25), /* UDP/IP checksum failed */ RxTCPF_v3 = (1 << 24), /* TCP/IP checksum failed */ - RxSCTPF_v3 = (1 << 23), /* TCP/IP checksum failed */ + RxSCTPF_v3 = (1 << 23), /* SCTP checksum failed */ RxVlanTag_v3 = (RxVlanTag), /* VLAN tag available */ /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ @@ -1630,6 +1768,23 @@ enum _DescStatusBit { RxV6F_v3 = (RxV6F), RxV4F_v3 = (RxV4F), /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + RxIPF_v4 = (1 << 17), /* IP checksum failed */ + RxUDPF_v4 = (1 << 16), /* UDP/IP checksum failed */ + RxTCPF_v4 = (1 << 15), /* TCP/IP checksum failed */ + RxSCTPF_v4 = (1 << 19), /* SCTP checksum failed */ + RxVlanTag_v4 = (RxVlanTag), /* VLAN tag available */ + + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxUDPT_v4 = (1 << 19), + RxTCPT_v4 = (1 << 18), + RxSCTP_v4 = (1 << 19), + /*@@@@@@ offset 0 of rx descriptor => bits for RTL8125 only end @@@@@@*/ + + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only begin @@@@@@*/ + RxV6F_v4 = (RxV6F), + RxV4F_v4 = (RxV4F), + /*@@@@@@ offset 4 of rx descriptor => bits for RTL8125 only end @@@@@@*/ }; enum features { @@ -1679,12 +1834,13 @@ enum bits { }; #define RTL8125_CP_NUM 4 -#define RTL8125_MAX_SUPPORT_cp_len 110 +#define RTL8125_MAX_SUPPORT_CP_LEN 110 enum rtl8125_cp_status { rtl8125_cp_normal = 0, rtl8125_cp_short, rtl8125_cp_open, + rtl8125_cp_mismatch, rtl8125_cp_unknown }; @@ -1697,6 +1853,7 @@ enum efuse { }; #define RsvdMask 0x3fffc000 #define RsvdMaskV3 0x3fff8000 +#define RsvdMaskV4 RsvdMaskV3 struct TxDesc { u32 opts1; @@ -1763,6 +1920,23 @@ struct RxDescV3 { }; }; +struct RxDescV4 { + union { + u64 addr; + + struct { + u32 rsv1: 27; + u32 RSSInfo: 5; + u32 RSSResult; + } RxDescNormalDDWord1; + }; + + struct { + u32 opts2; + u32 opts1; + } RxDescNormalDDWord2; +}; + enum rxdesc_type { RXDESC_TYPE_NORMAL=0, RXDESC_TYPE_NEXT, @@ -1776,17 +1950,21 @@ enum rx_desc_ring_type { RX_DESC_RING_TYPE_1, RX_DESC_RING_TYPE_2, RX_DESC_RING_TYPE_3, + RX_DESC_RING_TYPE_4, RX_DESC_RING_TYPE_MAX }; enum rx_desc_len { RX_DESC_LEN_TYPE_1 = (sizeof(struct RxDesc)), - RX_DESC_LEN_TYPE_3 = (sizeof(struct RxDescV3)) + RX_DESC_LEN_TYPE_3 = (sizeof(struct RxDescV3)), + RX_DESC_LEN_TYPE_4 = (sizeof(struct RxDescV4)) }; struct ring_info { struct sk_buff *skb; u32 len; + unsigned int bytecount; + unsigned short gso_segs; u8 __pad[sizeof(void *) - sizeof(u32)]; }; @@ -1818,8 +1996,14 @@ enum r8125_flag { R8125_FLAG_MAX }; +enum r8125_sysfs_flag { + R8125_SYSFS_RTL_ADV = 0, + R8125_SYSFS_FLAG_MAX +}; + struct rtl8125_tx_ring { void* priv; + struct net_device *netdev; u32 index; u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ u32 dirty_tx; @@ -1848,6 +2032,7 @@ struct rtl8125_rx_buffer { struct rtl8125_rx_ring { void* priv; + struct net_device *netdev; u32 index; u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ u32 dirty_rx; @@ -2096,6 +2281,13 @@ enum rtl8125_fc_mode { rtl8125_fc_default }; +enum rtl8125_state_t { + __RTL8125_TESTING = 0, + __RTL8125_RESETTING, + __RTL8125_DOWN, + __RTL8125_PTP_TX_IN_PROGRESS, +}; + struct rtl8125_private { void __iomem *mmio_addr; /* memory map physical address */ struct pci_dev *pci_dev; /* Index of PCI device */ @@ -2105,11 +2297,11 @@ struct rtl8125_private { unsigned int irq_nvecs; unsigned int max_irq_nvecs; unsigned int min_irq_nvecs; + unsigned int hw_supp_irq_nvecs; //struct msix_entry msix_entries[R8125_MAX_MSIX_VEC]; struct net_device_stats stats; /* statistics of net device */ -#ifdef ENABLE_PTP_SUPPORT - spinlock_t lock; /* spin lock flag */ -#endif + unsigned long state; + u32 msg_enable; u32 tx_tcp_csum_cmd; u32 tx_udp_csum_cmd; @@ -2141,7 +2333,7 @@ struct rtl8125_private { struct rtl8125_tx_ring tx_ring[R8125_MAX_TX_QUEUES]; struct rtl8125_rx_ring rx_ring[R8125_MAX_RX_QUEUES]; #ifdef ENABLE_LIB_SUPPORT - struct atomic_notifier_head lib_nh; + struct blocking_notifier_head lib_nh; struct rtl8125_ring lib_tx_ring[R8125_MAX_TX_QUEUES]; struct rtl8125_ring lib_rx_ring[R8125_MAX_RX_QUEUES]; #endif @@ -2208,7 +2400,7 @@ struct rtl8125_private { u8 org_pci_offset_80; u8 org_pci_offset_81; - u8 use_timer_interrrupt; + u8 use_timer_interrupt; u32 keep_intr_cnt; @@ -2220,17 +2412,12 @@ struct rtl8125_private { u16 sw_ram_code_ver; u16 hw_ram_code_ver; - u8 RequireRduNonStopPatch; - u8 rtk_enable_diag; u8 ShortPacketSwChecksum; u8 UseSwPaddingShortPkt; - void *ShortPacketEmptyBuffer; - dma_addr_t ShortPacketEmptyBufferPhy; - u8 RequireAdcBiasPatch; u16 AdcBiasPatchIoffset; @@ -2241,6 +2428,8 @@ struct rtl8125_private { u8 RequiredSecLanDonglePatch; + u8 RequiredPfmPatch; + u8 RequirePhyMdiSwapPatch; u8 RequireLSOPatch; @@ -2294,6 +2483,8 @@ struct rtl8125_private { u8 DASH; u8 dash_printer_enabled; u8 HwPkgDet; + u8 HwSuppOcpChannelVer; + u8 AllowAccessDashOcp; void __iomem *mapped_cmac_ioaddr; /* mapped cmac memory map physical address */ void __iomem *cmac_ioaddr; /* cmac memory map physical address */ @@ -2383,14 +2574,21 @@ struct rtl8125_private { #ifdef ENABLE_R8125_PROCFS //Procfs support struct proc_dir_entry *proc_dir; + struct proc_dir_entry *proc_dir_debug; + struct proc_dir_entry *proc_dir_test; +#endif +#ifdef ENABLE_R8125_SYSFS + //sysfs support + DECLARE_BITMAP(sysfs_flag, R8125_SYSFS_FLAG_MAX); + u32 testmode; #endif + u8 HwSuppRxDescType; u8 InitRxDescType; u16 RxDescLength; //V1 16 Byte V2 32 Bytes u8 HwSuppPtpVer; u8 EnablePtp; u8 ptp_master_mode; - s64 ptp_adjust; #ifdef ENABLE_PTP_SUPPORT u32 tx_hwtstamp_timeouts; u32 tx_hwtstamp_skipped; @@ -2415,6 +2613,13 @@ struct rtl8125_private { u8 HwSuppMacMcuVer; u16 MacMcuPageSize; + + u8 HwSuppTcamVer; + + u16 TcamNotValidReg; + u16 TcamValidReg; + u16 TcamMaAddrcOffset; + u16 TcamVlanTagOffset; }; #ifdef ENABLE_LIB_SUPPORT @@ -2468,6 +2673,11 @@ rtl8125_tot_rx_rings(struct rtl8125_private *tp) return tp->num_rx_rings + rtl8125_num_lib_rx_rings(tp); } +static inline struct netdev_queue *txring_txq(const struct rtl8125_tx_ring *ring) +{ + return netdev_get_tx_queue(ring->netdev, ring->index); +} + enum eetype { EEPROM_TYPE_NONE=0, EEPROM_TYPE_93C46, @@ -2483,6 +2693,9 @@ enum mcfg { CFG_METHOD_6, CFG_METHOD_7, CFG_METHOD_8, + CFG_METHOD_9, + CFG_METHOD_10, + CFG_METHOD_11, CFG_METHOD_DEFAULT, CFG_METHOD_MAX }; @@ -2516,8 +2729,11 @@ enum mcfg { #define NIC_RAMCODE_VERSION_CFG_METHOD_2 (0x0b11) #define NIC_RAMCODE_VERSION_CFG_METHOD_3 (0x0b33) #define NIC_RAMCODE_VERSION_CFG_METHOD_4 (0x0b17) -#define NIC_RAMCODE_VERSION_CFG_METHOD_5 (0x0b74) -#define NIC_RAMCODE_VERSION_CFG_METHOD_8 (0x0023) +#define NIC_RAMCODE_VERSION_CFG_METHOD_5 (0x0b99) +#define NIC_RAMCODE_VERSION_CFG_METHOD_8 (0x0013) +#define NIC_RAMCODE_VERSION_CFG_METHOD_9 (0x0001) +#define NIC_RAMCODE_VERSION_CFG_METHOD_10 (0x0007) +#define NIC_RAMCODE_VERSION_CFG_METHOD_11 (0x0001) //hwoptimize #define HW_PATCH_SOC_LAN (BIT_0) @@ -2533,13 +2749,12 @@ u32 rtl8125_mdio_prot_read(struct rtl8125_private *tp, u32 RegAddr); u32 rtl8125_mdio_prot_direct_read_phy_ocp(struct rtl8125_private *tp, u32 RegAddr); void rtl8125_ephy_write(struct rtl8125_private *tp, int RegAddr, int value); void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value); -u32 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr); +u16 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr); void rtl8125_clear_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask); void rtl8125_set_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask); void rtl8125_ocp_write(struct rtl8125_private *tp, u16 addr, u8 len, u32 data); void rtl8125_oob_notify(struct rtl8125_private *tp, u8 cmd); void rtl8125_init_ring_indexes(struct rtl8125_private *tp); -int rtl8125_eri_write(struct rtl8125_private *tp, int addr, int len, u32 value, int type); void rtl8125_oob_mutex_lock(struct rtl8125_private *tp); u32 rtl8125_ocp_read(struct rtl8125_private *tp, u16 addr, u8 len); u32 rtl8125_ocp_read_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, u32 base_address); @@ -2559,17 +2774,25 @@ void rtl8125_dash2_disable_rx(struct rtl8125_private *tp); void rtl8125_dash2_enable_rx(struct rtl8125_private *tp); void rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev); void rtl8125_mark_to_asic(struct rtl8125_private *tp, struct RxDesc *desc, u32 rx_buf_sz); +void rtl8125_mark_as_last_descriptor(struct rtl8125_private *tp, struct RxDesc *desc); static inline void rtl8125_make_unusable_by_asic(struct rtl8125_private *tp, struct RxDesc *desc) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) { + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: ((struct RxDescV3 *)desc)->addr = RTL8125_MAGIC_NUMBER; ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts1 &= ~cpu_to_le32(DescOwn | RsvdMaskV3); - } else { + break; + case RX_DESC_RING_TYPE_4: + ((struct RxDescV4 *)desc)->addr = RTL8125_MAGIC_NUMBER; + ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts1 &= ~cpu_to_le32(DescOwn | RsvdMaskV4); + break; + default: desc->addr = RTL8125_MAGIC_NUMBER; desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); + break; } } @@ -2598,6 +2821,7 @@ void rtl8125_hw_config(struct net_device *dev); void rtl8125_hw_set_timer_int_8125(struct rtl8125_private *tp, u32 message_id, u8 timer_intmiti_val); void rtl8125_set_rx_q_num(struct rtl8125_private *tp, unsigned int num_rx_queues); void rtl8125_set_tx_q_num(struct rtl8125_private *tp, unsigned int num_tx_queues); +void rtl8125_enable_mcu(struct rtl8125_private *tp, bool enable); void rtl8125_hw_start(struct net_device *dev); void rtl8125_hw_reset(struct net_device *dev); void rtl8125_tx_clear(struct rtl8125_private *tp); @@ -2614,14 +2838,14 @@ static inline void rtl8125_lib_reset_prepare(struct rtl8125_private *tp) { } static inline void rtl8125_lib_reset_complete(struct rtl8125_private *tp) { } #endif -#define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0 ) +#define HW_SUPPORT_CHECK_PHY_DISABLE_MODE(_M) ((_M)->HwSuppCheckPhyDisableModeVer > 0) #define HW_HAS_WRITE_PHY_MCU_RAM_CODE(_M) (((_M)->HwHasWrRamCodeToMicroP == TRUE) ? 1 : 0) #define HW_SUPPORT_D0_SPEED_UP(_M) ((_M)->HwSuppD0SpeedUpVer > 0) #define HW_SUPPORT_MAC_MCU(_M) ((_M)->HwSuppMacMcuVer > 0) +#define HW_SUPPORT_TCAM(_M) ((_M)->HwSuppTcamVer > 0) #define HW_SUPP_PHY_LINK_SPEED_GIGA(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 1000) #define HW_SUPP_PHY_LINK_SPEED_2500M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 2500) -#define HW_SUPP_PHY_LINK_SPEED_5000M(_M) ((_M)->HwSuppMaxPhyLinkSpeed >= 5000) #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34) #define netdev_mc_count(dev) ((dev)->mc_count) diff --git a/src/r8125_dash.h b/src/r8125_dash.h old mode 100755 new mode 100644 index 6819370..4402bc5 --- a/src/r8125_dash.h +++ b/src/r8125_dash.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -164,6 +164,7 @@ RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2; #define OCP_REG_CR (0x36) #define OCP_REG_DMEMSTA (0x38) #define OCP_REG_GPHYAR (0x60) +#define OCP_REG_FIRMWARE_MAJOR_VERSION (0x120) #define OCP_REG_CONFIG0_DASHEN BIT_15 @@ -175,10 +176,16 @@ RX_DASH_BUFFER_TYPE_2, *PRX_DASH_BUFFER_TYPE_2; #define OCP_REG_CONFIG0_DRV_WAIT_OOB BIT_8 #define OCP_REG_CONFIG0_TLSEN BIT_7 -#define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0 ) -#define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1 ) -#define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2 ) -#define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3 ) +#define HW_DASH_SUPPORT_DASH(_M) ((_M)->HwSuppDashVer > 0) +#define HW_DASH_SUPPORT_TYPE_1(_M) ((_M)->HwSuppDashVer == 1) +#define HW_DASH_SUPPORT_TYPE_2(_M) ((_M)->HwSuppDashVer == 2) +#define HW_DASH_SUPPORT_TYPE_3(_M) ((_M)->HwSuppDashVer == 3) +#define HW_DASH_SUPPORT_TYPE_4(_M) ((_M)->HwSuppDashVer == 4) +#define HW_DASH_SUPPORT_CMAC(_M) (HW_DASH_SUPPORT_TYPE_2(_M) || HW_DASH_SUPPORT_TYPE_3(_M)) +#define HW_DASH_SUPPORT_IPC2(_M) (HW_DASH_SUPPORT_TYPE_4(_M)) +#define HW_DASH_SUPPORT_GET_FIRMWARE_VERSION(_M) (HW_DASH_SUPPORT_TYPE_2(_M) || \ + HW_DASH_SUPPORT_TYPE_3(_M) || \ + HW_DASH_SUPPORT_TYPE_4(_M)) #define RECV_FROM_FW_BUF_SIZE (1520) #define SEND_TO_FW_BUF_SIZE (1520) diff --git a/src/r8125_firmware.c b/src/r8125_firmware.c old mode 100755 new mode 100644 index 61b92d1..71ef049 --- a/src/r8125_firmware.c +++ b/src/r8125_firmware.c @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8168 is the Linux device driver released for Realtek Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/r8125_firmware.h b/src/r8125_firmware.h old mode 100755 new mode 100644 index df97bf9..6ee0c41 --- a/src/r8125_firmware.h +++ b/src/r8125_firmware.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/r8125_n.c b/src/r8125_n.c old mode 100755 new mode 100644 index 6ca7201..90a8707 --- a/src/r8125_n.c +++ b/src/r8125_n.c @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -77,6 +77,10 @@ #include #endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,10) +#include +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(6,4,10) */ + #include #include @@ -92,11 +96,10 @@ #define FIRMWARE_8125A_3 "rtl_nic/rtl8125a-3.fw" #define FIRMWARE_8125B_2 "rtl_nic/rtl8125b-2.fw" -#define FIRMWARE_8126A_1 "rtl_nic/rtl8126a-1.fw" - -/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). - The RTL chips use a 64 element hash table based on the Ethernet CRC. */ -static const int multicast_filter_limit = 32; +#define FIRMWARE_8125BP_1 "rtl_nic/rtl8125bp-1.fw" +#define FIRMWARE_8125BP_2 "rtl_nic/rtl8125bp-2.fw" +#define FIRMWARE_8125D_1 "rtl_nic/rtl8125d-1.fw" +#define FIRMWARE_8125D_2 "rtl_nic/rtl8125d-2.fw" static const struct { const char *name; @@ -109,7 +112,10 @@ static const struct { [CFG_METHOD_5] = {"RTL8125B", FIRMWARE_8125B_2}, [CFG_METHOD_6] = {"RTL8168KB", FIRMWARE_8125A_3}, [CFG_METHOD_7] = {"RTL8168KB", FIRMWARE_8125B_2}, - [CFG_METHOD_8] = {"RTL8126A", FIRMWARE_8126A_1}, + [CFG_METHOD_8] = {"RTL8125BP", FIRMWARE_8125BP_1}, + [CFG_METHOD_9] = {"RTL8125BP", FIRMWARE_8125BP_2}, + [CFG_METHOD_10] = {"RTL8125D", FIRMWARE_8125D_1}, + [CFG_METHOD_11] = {"RTL8125D", FIRMWARE_8125D_2}, [CFG_METHOD_DEFAULT] = {"Unknown", }, }; @@ -125,49 +131,67 @@ static const struct { } rtl_chip_info[] = { _R("RTL8125A", CFG_METHOD_2, - BIT_30 | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), _R("RTL8125A", CFG_METHOD_3, - BIT_30 | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), _R("RTL8125B", CFG_METHOD_4, - BIT_30 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), _R("RTL8125B", CFG_METHOD_5, - BIT_30 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), _R("RTL8168KB", CFG_METHOD_6, - BIT_30 | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), _R("RTL8168KB", CFG_METHOD_7, - BIT_30 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), - _R("RTL8126A", + _R("RTL8125BP", CFG_METHOD_8, - BIT_30 | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST << RxCfgDMAShift), + Rx_Fetch_Number_8 | Rx_Close_Multiple | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + + _R("RTL8125BP", + CFG_METHOD_9, + Rx_Fetch_Number_8 | Rx_Close_Multiple | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + + _R("RTL8125D", + CFG_METHOD_10, + Rx_Fetch_Number_8 | Rx_Close_Multiple | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), + 0xff7e5880, + Jumbo_Frame_9k), + + _R("RTL8125D", + CFG_METHOD_11, + Rx_Fetch_Number_8 | Rx_Close_Multiple | RxCfg_pause_slot_en | EnableInnerVlan | EnableOuterVlan | (RX_DMA_BURST_256 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_9k), _R("Unknown", CFG_METHOD_DEFAULT, - (RX_DMA_BURST << RxCfgDMAShift), + (RX_DMA_BURST_512 << RxCfgDMAShift), 0xff7e5880, Jumbo_Frame_1k) }; @@ -182,8 +206,6 @@ static struct pci_device_id rtl8125_pci_tbl[] = { { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8125), }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8162), }, { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x3000), }, - { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8126), }, - { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x5000), }, {0,}, }; @@ -197,16 +219,9 @@ static struct { u32 msg_enable; } debug = { -1 }; -static unsigned int speed_mode = SPEED_5000; +static unsigned int speed_mode = SPEED_2500; static unsigned int duplex_mode = DUPLEX_FULL; static unsigned int autoneg_mode = AUTONEG_ENABLE; -static unsigned int advertising_mode = ADVERTISED_10baseT_Half | - ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | - ADVERTISED_100baseT_Full | - ADVERTISED_1000baseT_Half | - ADVERTISED_1000baseT_Full | - ADVERTISED_2500baseX_Full; #ifdef CONFIG_ASPM static int aspm = 1; #else @@ -247,10 +262,10 @@ static int enable_ptp_master_mode = 1; #else static int enable_ptp_master_mode = 0; #endif -#ifdef DISABLE_PM_SUPPORT -static int disable_pm_support = 1; +#ifdef DISABLE_WOL_SUPPORT +static int disable_wol_support = 1; #else -static int disable_pm_support = 0; +static int disable_wol_support = 0; #endif #ifdef ENABLE_DOUBLE_VLAN @@ -260,7 +275,7 @@ static int enable_double_vlan = 0; #endif MODULE_AUTHOR("Realtek and the Linux r8125 crew "); -MODULE_DESCRIPTION("Realtek RTL8125 2.5Gigabit Ethernet driver"); +MODULE_DESCRIPTION("Realtek r8125 Ethernet controller driver"); module_param(speed_mode, uint, 0); MODULE_PARM_DESC(speed_mode, "force phy operation. Deprecated by ethtool (8)."); @@ -271,9 +286,6 @@ MODULE_PARM_DESC(duplex_mode, "force phy operation. Deprecated by ethtool (8).") module_param(autoneg_mode, uint, 0); MODULE_PARM_DESC(autoneg_mode, "force phy operation. Deprecated by ethtool (8)."); -module_param(advertising_mode, uint, 0); -MODULE_PARM_DESC(advertising_mode, "force phy operation. Deprecated by ethtool (8)."); - module_param(aspm, int, 0); MODULE_PARM_DESC(aspm, "Enable ASPM."); @@ -304,8 +316,8 @@ MODULE_PARM_DESC(tx_no_close_enable, "Enable TX No Close."); module_param(enable_ptp_master_mode, int, 0); MODULE_PARM_DESC(enable_ptp_master_mode, "Enable PTP Master Mode."); -module_param(disable_pm_support, int, 0); -MODULE_PARM_DESC(disable_pm_support, "Disable PM support."); +module_param(disable_wol_support, int, 0); +MODULE_PARM_DESC(disable_wol_support, "Disable PM support."); module_param(enable_double_vlan, int, 0); MODULE_PARM_DESC(enable_double_vlan, "Enable Double VLAN."); @@ -319,6 +331,10 @@ MODULE_LICENSE("GPL"); #ifdef ENABLE_USE_FIRMWARE_FILE MODULE_FIRMWARE(FIRMWARE_8125A_3); MODULE_FIRMWARE(FIRMWARE_8125B_2); +MODULE_FIRMWARE(FIRMWARE_8125BP_1); +MODULE_FIRMWARE(FIRMWARE_8125BP_2); +MODULE_FIRMWARE(FIRMWARE_8125D_1); +MODULE_FIRMWARE(FIRMWARE_8125D_2); #endif MODULE_VERSION(RTL8125_VERSION); @@ -368,7 +384,11 @@ static void rtl8125_desc_addr_fill(struct rtl8125_private *); static void rtl8125_tx_desc_init(struct rtl8125_private *tp); static void rtl8125_rx_desc_init(struct rtl8125_private *tp); -static u32 mdio_direct_read_phy_ocp(struct rtl8125_private *tp, u16 RegAddr); +static void rtl8125_mdio_direct_write_phy_ocp(struct rtl8125_private *tp, u16 RegAddr,u16 value); +static u32 rtl8125_mdio_direct_read_phy_ocp(struct rtl8125_private *tp, u16 RegAddr); +static void rtl8125_clear_and_set_eth_phy_ocp_bit(struct rtl8125_private *tp, u16 addr, u16 clearmask, u16 setmask); +static void rtl8125_clear_eth_phy_ocp_bit(struct rtl8125_private *tp, u16 addr, u16 mask); +static void rtl8125_set_eth_phy_ocp_bit(struct rtl8125_private *tp, u16 addr, u16 mask); static u16 rtl8125_get_hw_phy_mcu_code_ver(struct rtl8125_private *tp); static void rtl8125_phy_power_up(struct net_device *dev); static void rtl8125_phy_power_down(struct net_device *dev); @@ -503,7 +523,7 @@ struct _kc_ethtool_ops { #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) #ifndef SET_ETHTOOL_OPS #define SET_ETHTOOL_OPS(netdev,ops) \ - ( (netdev)->ethtool_ops = (ops) ) + ((netdev)->ethtool_ops = (ops)) #endif //SET_ETHTOOL_OPS #endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,16,0) @@ -677,7 +697,9 @@ static u32 rtl8125_read_thermal_sensor(struct rtl8125_private *tp) case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: - ts_digout = mdio_direct_read_phy_ocp(tp, 0xBD84); + case CFG_METHOD_10: + case CFG_METHOD_11: + ts_digout = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBD84); ts_digout &= 0x3ff; break; default: @@ -714,14 +736,62 @@ int rtl8125_dump_tally_counter(struct rtl8125_private *tp, dma_addr_t paddr) return retval; } +static u32 +rtl8125_get_hw_clo_ptr(struct rtl8125_tx_ring *ring) +{ + struct rtl8125_private *tp = ring->priv; + + switch (tp->HwSuppTxNoCloseVer) { + case 3: + return RTL_R16(tp, ring->hw_clo_ptr_reg); + case 4: + case 5: + case 6: + return RTL_R32(tp, ring->hw_clo_ptr_reg); + default: +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + WARN_ON(1); +#endif + return 0; + } +} + +static u32 +rtl8125_get_sw_tail_ptr(struct rtl8125_tx_ring *ring) +{ + struct rtl8125_private *tp = ring->priv; + + switch (tp->HwSuppTxNoCloseVer) { + case 3: + return RTL_R16(tp, ring->sw_tail_ptr_reg); + case 4: + case 5: + case 6: + return RTL_R32(tp, ring->sw_tail_ptr_reg); + default: +#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) + WARN_ON(1); +#endif + return 0; + } +} + +static bool +rtl8125_sysfs_testmode_on(struct rtl8125_private *tp) +{ +#ifdef ENABLE_R8125_SYSFS + return !!tp->testmode; +#else + return 1; +#endif +} + static u32 rtl8125_convert_link_speed(u16 status) { u32 speed = SPEED_UNKNOWN; if (status & LinkStatus) { - if (status & _5000bpsF) - speed = SPEED_5000; - else if (status & _2500bpsF) + if (status & _2500bpsF) speed = SPEED_2500; else if (status & _1000bpsF) speed = SPEED_1000; @@ -734,95 +804,185 @@ static u32 rtl8125_convert_link_speed(u16 status) return speed; } +static void rtl8125_mdi_swap(struct rtl8125_private *tp) +{ + int i; + u16 reg, val, mdi_reverse; + u16 tps_p0, tps_p1, tps_p2, tps_p3, tps_p3_p0; + + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + reg = 0x8284; + break; + case CFG_METHOD_4: + case CFG_METHOD_5: + case CFG_METHOD_7: + reg = 0x81aa; + break; + default: + return; + }; + + tps_p3_p0 = rtl8125_mac_ocp_read(tp, 0xD440) & 0xF000; + tps_p3 = !!(tps_p3_p0 & BIT_15); + tps_p2 = !!(tps_p3_p0 & BIT_14); + tps_p1 = !!(tps_p3_p0 & BIT_13); + tps_p0 = !!(tps_p3_p0 & BIT_12); + mdi_reverse = rtl8125_mac_ocp_read(tp, 0xD442); + + if ((mdi_reverse & BIT_5) && tps_p3_p0 == 0xA000) + return; + + if (!(mdi_reverse & BIT_5)) + val = tps_p0 << 8 | + tps_p1 << 9 | + tps_p2 << 10 | + tps_p3 << 11; + else + val = tps_p3 << 8 | + tps_p2 << 9 | + tps_p1 << 10 | + tps_p0 << 11; + + for (i=8; i<12; i++) { + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, reg); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + BIT(i), + val & BIT(i)); + } +} + +static int _rtl8125_vcd_test(struct rtl8125_private *tp) +{ + u16 val; + u32 wait_cnt; + int ret = -1; + + rtl8125_mdi_swap(tp); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA422, BIT(0)); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA422, 0x00F0); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA422, BIT(0)); + + wait_cnt = 0; + do { + mdelay(1); + val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA422); + wait_cnt++; + } while (!(val & BIT_15) && (wait_cnt < 5000)); + + if (wait_cnt == 5000) + goto exit; + + ret = 0; + +exit: + return ret; +} + +static int rtl8125_vcd_test(struct rtl8125_private *tp, bool poe_mode) +{ + int ret; + + switch (tp->mcfg) { + case CFG_METHOD_4: + case CFG_METHOD_5: + case CFG_METHOD_7: + /* update rtct threshold for poe mode */ + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FE1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, poe_mode ? 0x0A44 : 0x0000); + + /* enable rtct poe mode */ + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FE3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, poe_mode ? 0x0100 : 0x0000); + + ret = _rtl8125_vcd_test(tp); + + /* disable rtct poe mode */ + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FE3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + + /* restore rtct threshold */ + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FE1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + break; + default: + ret = _rtl8125_vcd_test(tp); + break; + } + + return ret; +} + static void rtl8125_get_cp_len(struct rtl8125_private *tp, - u16 cp_len[RTL8125_CP_NUM]) + int cp_len[RTL8125_CP_NUM]) { int i; - int count; u16 status; - u16 tmp_cp_len = 0; + int tmp_cp_len; status = RTL_R16(tp, PHYstatus); if (status & LinkStatus) { if (status & _10bps) { - tmp_cp_len = 0; - goto no_cpdr; - } else if (status & _1000bpsF) { + tmp_cp_len = -1; + } else if (status & (_100bps | _1000bpsF)) { rtl8125_mdio_write(tp, 0x1f, 0x0a88); tmp_cp_len = rtl8125_mdio_read(tp, 0x10); - goto no_cpdr; } else if (status & _2500bpsF) { switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: case CFG_METHOD_6: rtl8125_mdio_write(tp, 0x1f, 0x0ac5); - tmp_cp_len = rtl8125_mdio_read(tp, 0x14) >> 4; + tmp_cp_len = rtl8125_mdio_read(tp, 0x14); + tmp_cp_len >>= 4; break; default: rtl8125_mdio_write(tp, 0x1f, 0x0acb); - tmp_cp_len = rtl8125_mdio_read(tp, 0x15) >> 2; + tmp_cp_len = rtl8125_mdio_read(tp, 0x15); + tmp_cp_len >>= 2; break; } - goto no_cpdr; - } - } - - rtl8125_mdio_write(tp, 0x1f, 0x0a42); - rtl8125_mdio_write(tp, 0x11, 0x0000); - rtl8125_set_eth_phy_bit(tp, 0x11, 0xf0); - rtl8125_set_eth_phy_bit(tp, 0x11, 0x01); - - count = 0; - while (!(rtl8125_mdio_read(tp, 0x11) & BIT_15) && - (count++ < 200)) - msleep(100); - - rtl8125_mdio_write(tp, 0x1f, 0x0a43); - for (i=0; i 200) + } else tmp_cp_len = 0; - cp_len[i] = tmp_cp_len; - } - - goto exit; + } else + tmp_cp_len = 0; -no_cpdr: - tmp_cp_len &= 0xff; + if (tmp_cp_len > 0) + tmp_cp_len &= 0xff; for (i=0; i RTL8125_MAX_SUPPORT_cp_len) - cp_len[i] = RTL8125_MAX_SUPPORT_cp_len; + if (cp_len[i] > RTL8125_MAX_SUPPORT_CP_LEN) + cp_len[i] = RTL8125_MAX_SUPPORT_CP_LEN; return; } -static int _rtl8125_get_cp_status(u16 val) +static int __rtl8125_get_cp_status(u16 val) { switch (val) { case 0x0060: return rtl8125_cp_normal; - case 0x0042: case 0x0048: return rtl8125_cp_open; - case 0x0044: case 0x0050: return rtl8125_cp_short; + case 0x0042: + case 0x0044: + return rtl8125_cp_mismatch; default: return rtl8125_cp_normal; } } -static int rtl8125_get_cp_status(struct rtl8125_private *tp, u8 pair_num) +static int _rtl8125_get_cp_status(struct rtl8125_private *tp, u8 pair_num) { u16 val; int cp_status = rtl8125_cp_unknown; @@ -830,12 +990,10 @@ static int rtl8125_get_cp_status(struct rtl8125_private *tp, u8 pair_num) if (pair_num > 3) goto exit; - rtl8125_mdio_write(tp, 0x1f, 0x0a43); - rtl8125_mdio_write(tp, 0x13, 0x8027 + 4 * pair_num); - val = rtl8125_mdio_read(tp, 0x14); - rtl8125_mdio_write(tp, 0x1f, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8027 + 4 * pair_num); + val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA438); - cp_status = _rtl8125_get_cp_status(val); + cp_status = __rtl8125_get_cp_status(val); exit: return cp_status; @@ -845,25 +1003,60 @@ static const char * rtl8125_get_cp_status_string(int cp_status) { switch(cp_status) { case rtl8125_cp_normal: - return "normal"; + return "normal "; case rtl8125_cp_short: - return "short"; + return "short "; case rtl8125_cp_open: - return "open"; + return "open "; + case rtl8125_cp_mismatch: + return "mismatch"; default: - return "unknown"; + return "unknown "; } } -static void rtl8125_get_cp(struct rtl8125_private *tp, - u16 cp_len[RTL8125_CP_NUM], - int cp_status[RTL8125_CP_NUM]) +static u16 rtl8125_get_cp_pp(struct rtl8125_private *tp, u8 pair_num) +{ + u16 pp = 0; + + if (pair_num > 3) + goto exit; + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8029 + 4 * pair_num); + pp = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA438); + + pp &= 0x3fff; + pp /= 80; + +exit: + return pp; +} + +static void rtl8125_get_cp_status(struct rtl8125_private *tp, + int cp_status[RTL8125_CP_NUM], + bool poe_mode) { + u16 status; int i; - rtl8125_get_cp_len(tp, cp_len); - for (i =0; iadvertising); seq_printf(m, "eeprom_len\t0x%x\n", tp->eeprom_len); seq_printf(m, "cur_page\t0x%x\n", tp->cur_page); - seq_printf(m, "bios_setting\t0x%x\n", tp->bios_setting); seq_printf(m, "features\t0x%x\n", tp->features); seq_printf(m, "org_pci_offset_99\t0x%x\n", tp->org_pci_offset_99); seq_printf(m, "org_pci_offset_180\t0x%x\n", tp->org_pci_offset_180); seq_printf(m, "issue_offset_99_event\t0x%x\n", tp->issue_offset_99_event); seq_printf(m, "org_pci_offset_80\t0x%x\n", tp->org_pci_offset_80); seq_printf(m, "org_pci_offset_81\t0x%x\n", tp->org_pci_offset_81); - seq_printf(m, "use_timer_interrrupt\t0x%x\n", tp->use_timer_interrrupt); + seq_printf(m, "use_timer_interrupt\t0x%x\n", tp->use_timer_interrupt); seq_printf(m, "HwIcVerUnknown\t0x%x\n", tp->HwIcVerUnknown); seq_printf(m, "NotWrRamCodeToMicroP\t0x%x\n", tp->NotWrRamCodeToMicroP); seq_printf(m, "NotWrMcuPatchCode\t0x%x\n", tp->NotWrMcuPatchCode); @@ -945,7 +1137,6 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "rtk_enable_diag\t0x%x\n", tp->rtk_enable_diag); seq_printf(m, "ShortPacketSwChecksum\t0x%x\n", tp->ShortPacketSwChecksum); seq_printf(m, "UseSwPaddingShortPkt\t0x%x\n", tp->UseSwPaddingShortPkt); - seq_printf(m, "RequireRduNonStopPatch\t0x%x\n", tp->RequireRduNonStopPatch); seq_printf(m, "RequireAdcBiasPatch\t0x%x\n", tp->RequireAdcBiasPatch); seq_printf(m, "AdcBiasPatchIoffset\t0x%x\n", tp->AdcBiasPatchIoffset); seq_printf(m, "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n", tp->RequireAdjustUpsTxLinkPulseTiming); @@ -956,6 +1147,7 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "HwSwitchMdiToFiber\t0x%x\n", tp->HwSwitchMdiToFiber); seq_printf(m, "NicCustLedValue\t0x%x\n", tp->NicCustLedValue); seq_printf(m, "RequiredSecLanDonglePatch\t0x%x\n", tp->RequiredSecLanDonglePatch); + seq_printf(m, "RequiredPfmPatch\t0x%x\n", tp->RequiredPfmPatch); seq_printf(m, "HwSuppDashVer\t0x%x\n", tp->HwSuppDashVer); seq_printf(m, "DASH\t0x%x\n", tp->DASH); seq_printf(m, "dash_printer_enabled\t0x%x\n", tp->dash_printer_enabled); @@ -963,7 +1155,6 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "speed_mode\t0x%x\n", speed_mode); seq_printf(m, "duplex_mode\t0x%x\n", duplex_mode); seq_printf(m, "autoneg_mode\t0x%x\n", autoneg_mode); - seq_printf(m, "advertising_mode\t0x%x\n", advertising_mode); seq_printf(m, "aspm\t0x%x\n", aspm); seq_printf(m, "s5wol\t0x%x\n", s5wol); seq_printf(m, "s5_keep_curr_mac\t0x%x\n", s5_keep_curr_mac); @@ -971,7 +1162,7 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "hwoptimize\t0x%lx\n", hwoptimize); seq_printf(m, "proc_init_num\t0x%x\n", proc_init_num); seq_printf(m, "s0_magic_packet\t0x%x\n", s0_magic_packet); - seq_printf(m, "disable_pm_support\t0x%x\n", disable_pm_support); + seq_printf(m, "disable_wol_support\t0x%x\n", disable_wol_support); seq_printf(m, "enable_double_vlan\t0x%x\n", enable_double_vlan); seq_printf(m, "HwSuppMagicPktVer\t0x%x\n", tp->HwSuppMagicPktVer); seq_printf(m, "HwSuppLinkChgWakeUpVer\t0x%x\n", tp->HwSuppLinkChgWakeUpVer); @@ -983,19 +1174,26 @@ static int proc_get_driver_variable(struct seq_file *m, void *v) seq_printf(m, "EnableTxNoClose\t0x%x\n", tp->EnableTxNoClose); seq_printf(m, "NextHwDesCloPtr0\t0x%x\n", tp->tx_ring[0].NextHwDesCloPtr); seq_printf(m, "BeginHwDesCloPtr0\t0x%x\n", tp->tx_ring[0].BeginHwDesCloPtr); + seq_printf(m, "hw_clo_ptr_reg0\t0x%x\n", rtl8125_get_hw_clo_ptr(&tp->tx_ring[0])); + seq_printf(m, "sw_tail_ptr_reg0\t0x%x\n", rtl8125_get_sw_tail_ptr(&tp->tx_ring[0])); seq_printf(m, "NextHwDesCloPtr1\t0x%x\n", tp->tx_ring[1].NextHwDesCloPtr); seq_printf(m, "BeginHwDesCloPtr1\t0x%x\n", tp->tx_ring[1].BeginHwDesCloPtr); + seq_printf(m, "hw_clo_ptr_reg1\t0x%x\n", rtl8125_get_hw_clo_ptr(&tp->tx_ring[1])); + seq_printf(m, "sw_tail_ptr_reg1\t0x%x\n", rtl8125_get_sw_tail_ptr(&tp->tx_ring[1])); seq_printf(m, "InitRxDescType\t0x%x\n", tp->InitRxDescType); seq_printf(m, "RxDescLength\t0x%x\n", tp->RxDescLength); seq_printf(m, "num_rx_rings\t0x%x\n", tp->num_rx_rings); seq_printf(m, "num_tx_rings\t0x%x\n", tp->num_tx_rings); seq_printf(m, "tot_rx_rings\t0x%x\n", rtl8125_tot_rx_rings(tp)); seq_printf(m, "tot_tx_rings\t0x%x\n", rtl8125_tot_tx_rings(tp)); + seq_printf(m, "HwSuppNumRxQueues\t0x%x\n", tp->HwSuppNumRxQueues); + seq_printf(m, "HwSuppNumTxQueues\t0x%x\n", tp->HwSuppNumTxQueues); seq_printf(m, "EnableRss\t0x%x\n", tp->EnableRss); seq_printf(m, "EnablePtp\t0x%x\n", tp->EnablePtp); seq_printf(m, "ptp_master_mode\t0x%x\n", tp->ptp_master_mode); seq_printf(m, "min_irq_nvecs\t0x%x\n", tp->min_irq_nvecs); seq_printf(m, "irq_nvecs\t0x%x\n", tp->irq_nvecs); + seq_printf(m, "hw_supp_irq_nvecs\t0x%x\n", tp->hw_supp_irq_nvecs); seq_printf(m, "ring_lib_enabled\t0x%x\n", tp->ring_lib_enabled); seq_printf(m, "HwSuppIsrVer\t0x%x\n", tp->HwSuppIsrVer); seq_printf(m, "HwCurrIsrVer\t0x%x\n", tp->HwCurrIsrVer); @@ -1100,7 +1298,69 @@ static int proc_get_registers(struct seq_file *m, void *v) rtnl_lock(); for (n = 0; n < max;) { - seq_printf(m, "\n0x%02x:\t", n); + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + max = 0xB00; + for (n = 0xA00; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + max = 0xD40; + for (n = 0xD00; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + max = 0x2840; + for (n = 0x2800; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + seq_printf(m, "%02x ", byte_rd); + } + } + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_get_all_registers(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + int i, n, max; + u8 byte_rd; + struct rtl8125_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; + struct pci_dev *pdev = tp->pci_dev; + + seq_puts(m, "\nDump All MAC Registers\n"); + seq_puts(m, "Offset\tValue\n------\t-----\n"); + + rtnl_lock(); + + max = pci_resource_len(pdev, 2); + max = min(max, 0x8000); + + for (n = 0; n < max;) { + seq_printf(m, "\n0x%04x:\t", n); for (i = 0; i < 16 && n < max; i++, n++) { byte_rd = readb(ioaddr + n); @@ -1110,6 +1370,8 @@ static int proc_get_registers(struct seq_file *m, void *v) rtnl_unlock(); + seq_printf(m, "\nTotal length:0x%X", max); + seq_putc(m, '\n'); return 0; } @@ -1164,6 +1426,45 @@ static int proc_get_eth_phy(struct seq_file *m, void *v) } } + seq_puts(m, "\n####################extra reg##################\n "); + n = 0xA400; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 8; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + n = 0xA410; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + n = 0xA434; + seq_printf(m, "\n0x%02x:\t", n); + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + + n = 0xA5D0; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 4; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + + n = 0xA61A; + seq_printf(m, "\n0x%02x:\t", n); + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + + n = 0xA6D0; + seq_printf(m, "\n0x%02x:\t", n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + seq_printf(m, "%04x ", word_rd); + } + rtnl_unlock(); seq_putc(m, '\n'); @@ -1241,6 +1542,8 @@ static int proc_get_temperature(struct seq_file *m, void *v) case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: + case CFG_METHOD_10: + case CFG_METHOD_11: seq_puts(m, "\nChip Temperature\n"); break; default: @@ -1248,7 +1551,17 @@ static int proc_get_temperature(struct seq_file *m, void *v) } rtnl_lock(); + + if (!rtl8125_sysfs_testmode_on(tp)) { + seq_puts(m, "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + rtnl_unlock(); + return 0; + } + + netif_testing_on(dev); ts_digout = rtl8125_read_thermal_sensor(tp); + netif_testing_off(dev); + rtnl_unlock(); tj = ts_digout / 2; @@ -1268,25 +1581,42 @@ static int proc_get_temperature(struct seq_file *m, void *v) return 0; } -static int proc_get_cable_info(struct seq_file *m, void *v) +static int _proc_get_cable_info(struct seq_file *m, void *v, bool poe_mode) { int i; u16 status; int cp_status[RTL8125_CP_NUM]; - u16 cp_len[RTL8125_CP_NUM] = {0}; + int cp_len[RTL8125_CP_NUM] = {0}; struct net_device *dev = m->private; struct rtl8125_private *tp = netdev_priv(dev); + const char *pair_str[RTL8125_CP_NUM] = {"1-2", "3-6", "4-5", "7-8"}; + int ret; switch (tp->mcfg) { case CFG_METHOD_2 ... CFG_METHOD_7: /* support */ break; default: - return -EOPNOTSUPP; + ret = -EOPNOTSUPP; + goto error_out; } rtnl_lock(); + if (!rtl8125_sysfs_testmode_on(tp)) { + seq_puts(m, "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + ret = 0; + goto error_unlock; + } + + rtl8125_mdio_write(tp, 0x1F, 0x0000); + if (rtl8125_mdio_read(tp, MII_BMCR) & BMCR_PDOWN) { + ret = -EIO; + goto error_unlock; + } + + netif_testing_on(dev); + status = RTL_R16(tp, PHYstatus); if (status & LinkStatus) seq_printf(m, "\nlink speed:%d", @@ -1294,35 +1624,195 @@ static int proc_get_cable_info(struct seq_file *m, void *v) else seq_puts(m, "\nlink status:off"); - rtl8125_get_cp(tp, cp_len, cp_status); + rtl8125_get_cp_len(tp, cp_len); + + rtl8125_get_cp_status(tp, cp_status, poe_mode); - rtnl_unlock(); + seq_puts(m, "\npair\tlength\tstatus \tpp\n"); - seq_puts(m, "\npair\tlength\tstaus\n"); + for (i=0; iprivate; + struct rtl8125_private *tp = netdev_priv(dev); + int i; + + rtnl_lock(); + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8125_rx_ring *ring = &tp->rx_ring[i]; + + if (!ring) + continue; + + seq_printf(m, "\ndump rx %d desc:%d\n", i, ring->num_rx_desc); + + _proc_dump_desc(m, (void*)ring->RxDescArray, ring->RxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8125_num_lib_rx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumRxQueues; i++) { + struct rtl8125_ring *lib_ring = &tp->lib_rx_ring[i]; + if (lib_ring->enabled) { + seq_printf(m, "\ndump lib rx %d desc:%d\n", i, + lib_ring->ring_size); + _proc_dump_desc(m, (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_dump_tx_desc(struct seq_file *m, void *v) +{ + struct net_device *dev = m->private; + struct rtl8125_private *tp = netdev_priv(dev); + int i; + + rtnl_lock(); + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8125_tx_ring *ring = &tp->tx_ring[i]; + + if (!ring) + continue; + + seq_printf(m, "\ndump tx %d desc:%d\n", i, ring->num_tx_desc); + + _proc_dump_desc(m, (void*)ring->TxDescArray, ring->TxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8125_num_lib_tx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + struct rtl8125_ring *lib_ring = &tp->lib_tx_ring[i]; + if (lib_ring->enabled) { + seq_printf(m, "\ndump lib tx %d desc:%d\n", i, + lib_ring->ring_size); + _proc_dump_desc(m, (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + seq_putc(m, '\n'); + return 0; +} + +static int proc_dump_msix_tbl(struct seq_file *m, void *v) +{ + int i, j; + void __iomem *ioaddr; + struct net_device *dev = m->private; + struct rtl8125_private *tp = netdev_priv(dev); + + /* ioremap MMIO region */ + ioaddr = ioremap(pci_resource_start(tp->pci_dev, 4), pci_resource_len(tp->pci_dev, 4)); + if (!ioaddr) + return -EFAULT; + + rtnl_lock(); + + seq_printf(m, "\ndump MSI-X Table. Total Entry %d. \n", tp->hw_supp_irq_nvecs); + + for (i=0; ihw_supp_irq_nvecs; i++) { + seq_printf(m, "\n%04x ", i); + for (j=0; j<4; j++) + seq_printf(m, "%08x ", + readl(ioaddr + i*0x10 + 4*j)); + } + + rtnl_unlock(); + + iounmap(ioaddr); + + seq_putc(m, '\n'); + return 0; +} + +#else //LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + +static int proc_get_driver_variable(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + struct rtl8125_private *tp = netdev_priv(dev); + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump Driver Driver\n"); + + rtnl_lock(); + + len += snprintf(page + len, count - len, "Variable\tValue\n----------\t-----\n"); len += snprintf(page + len, count - len, @@ -1368,14 +1858,13 @@ static int proc_get_driver_variable(char *page, char **start, "advertising\t0x%llx\n" "eeprom_len\t0x%x\n" "cur_page\t0x%x\n" - "bios_setting\t0x%x\n" "features\t0x%x\n" "org_pci_offset_99\t0x%x\n" "org_pci_offset_180\t0x%x\n" "issue_offset_99_event\t0x%x\n" "org_pci_offset_80\t0x%x\n" "org_pci_offset_81\t0x%x\n" - "use_timer_interrrupt\t0x%x\n" + "use_timer_interrupt\t0x%x\n" "HwIcVerUnknown\t0x%x\n" "NotWrRamCodeToMicroP\t0x%x\n" "NotWrMcuPatchCode\t0x%x\n" @@ -1385,7 +1874,6 @@ static int proc_get_driver_variable(char *page, char **start, "rtk_enable_diag\t0x%x\n" "ShortPacketSwChecksum\t0x%x\n" "UseSwPaddingShortPkt\t0x%x\n" - "RequireRduNonStopPatch\t0x%x\n" "RequireAdcBiasPatch\t0x%x\n" "AdcBiasPatchIoffset\t0x%x\n" "RequireAdjustUpsTxLinkPulseTiming\t0x%x\n" @@ -1396,6 +1884,7 @@ static int proc_get_driver_variable(char *page, char **start, "HwSwitchMdiToFiber\t0x%x\n" "NicCustLedValue\t0x%x\n" "RequiredSecLanDonglePatch\t0x%x\n" + "RequiredPfmPatch\t0x%x\n" "HwSuppDashVer\t0x%x\n" "DASH\t0x%x\n" "dash_printer_enabled\t0x%x\n" @@ -1403,7 +1892,6 @@ static int proc_get_driver_variable(char *page, char **start, "speed_mode\t0x%x\n" "duplex_mode\t0x%x\n" "autoneg_mode\t0x%x\n" - "advertising_mode\t0x%x\n" "aspm\t0x%x\n" "s5wol\t0x%x\n" "s5_keep_curr_mac\t0x%x\n" @@ -1411,7 +1899,7 @@ static int proc_get_driver_variable(char *page, char **start, "hwoptimize\t0x%lx\n" "proc_init_num\t0x%x\n" "s0_magic_packet\t0x%x\n" - "disable_pm_support\t0x%x\n" + "disable_wol_support\t0x%x\n" "enable_double_vlan\t0x%x\n" "HwSuppMagicPktVer\t0x%x\n" "HwSuppLinkChgWakeUpVer\t0x%x\n" @@ -1423,19 +1911,26 @@ static int proc_get_driver_variable(char *page, char **start, "EnableTxNoClose\t0x%x\n" "NextHwDesCloPtr0\t0x%x\n" "BeginHwDesCloPtr0\t0x%x\n" + "hw_clo_ptr_reg0\t0x%x\n" + "sw_tail_ptr_reg0\t0x%x\n" "NextHwDesCloPtr1\t0x%x\n" "BeginHwDesCloPtr1\t0x%x\n" + "hw_clo_ptr_reg1\t0x%x\n" + "sw_tail_ptr_reg1\t0x%x\n" "InitRxDescType\t0x%x\n" "RxDescLength\t0x%x\n" "num_rx_rings\t0x%x\n" "num_tx_rings\t0x%x\n" "tot_rx_rings\t0x%x\n" "tot_tx_rings\t0x%x\n" + "HwSuppNumRxQueues\t0x%x\n" + "HwSuppNumTxQueues\t0x%x\n" "EnableRss\t0x%x\n" "EnablePtp\t0x%x\n" "ptp_master_mode\t0x%x\n" "min_irq_nvecs\t0x%x\n" "irq_nvecs\t0x%x\n" + "hw_supp_irq_nvecs\t0x%x\n" "ring_lib_enabled\t0x%x\n" "HwSuppIsrVer\t0x%x\n" "HwCurrIsrVer\t0x%x\n" @@ -1491,14 +1986,13 @@ static int proc_get_driver_variable(char *page, char **start, tp->advertising, tp->eeprom_len, tp->cur_page, - tp->bios_setting, tp->features, tp->org_pci_offset_99, tp->org_pci_offset_180, tp->issue_offset_99_event, tp->org_pci_offset_80, tp->org_pci_offset_81, - tp->use_timer_interrrupt, + tp->use_timer_interrupt, tp->HwIcVerUnknown, tp->NotWrRamCodeToMicroP, tp->NotWrMcuPatchCode, @@ -1508,7 +2002,6 @@ static int proc_get_driver_variable(char *page, char **start, tp->rtk_enable_diag, tp->ShortPacketSwChecksum, tp->UseSwPaddingShortPkt, - tp->RequireRduNonStopPatch, tp->RequireAdcBiasPatch, tp->AdcBiasPatchIoffset, tp->RequireAdjustUpsTxLinkPulseTiming, @@ -1519,6 +2012,7 @@ static int proc_get_driver_variable(char *page, char **start, tp->HwSwitchMdiToFiber, tp->NicCustLedValue, tp->RequiredSecLanDonglePatch, + tp->RequiredPfmPatch, tp->HwSuppDashVer, tp->DASH, tp->dash_printer_enabled, @@ -1526,7 +2020,6 @@ static int proc_get_driver_variable(char *page, char **start, speed_mode, duplex_mode, autoneg_mode, - advertising_mode, aspm, s5wol, s5_keep_curr_mac, @@ -1534,7 +2027,7 @@ static int proc_get_driver_variable(char *page, char **start, hwoptimize, proc_init_num, s0_magic_packet, - disable_pm_support, + disable_wol_support, enable_double_vlan, tp->HwSuppMagicPktVer, tp->HwSuppLinkChgWakeUpVer, @@ -1546,19 +2039,26 @@ static int proc_get_driver_variable(char *page, char **start, tp->EnableTxNoClose, tp->tx_ring[0].NextHwDesCloPtr, tp->tx_ring[0].BeginHwDesCloPtr, + rtl8125_get_hw_clo_ptr(&tp->tx_ring[0]), + rtl8125_get_sw_tail_ptr(&tp->tx_ring[0]), tp->tx_ring[1].NextHwDesCloPtr, tp->tx_ring[1].BeginHwDesCloPtr, + rtl8125_get_hw_clo_ptr(&tp->tx_ring[1]), + rtl8125_get_sw_tail_ptr(&tp->tx_ring[1]), tp->InitRxDescType, tp->RxDescLength, tp->num_rx_rings, tp->num_tx_rings, - tp->tot_rx_rings, - tp->tot_tx_rings, + rtl8125_tot_rx_rings(tp), + rtl8125_tot_tx_rings(tp), + tp->HwSuppNumRxQueues, + tp->HwSuppNumTxQueues, tp->EnableRss, tp->EnablePtp, tp->ptp_master_mode, tp->min_irq_nvecs, tp->irq_nvecs, + tp->hw_supp_irq_nvecs, tp->ring_lib_enabled, tp->HwSuppIsrVer, tp->HwCurrIsrVer, @@ -1571,8 +2071,7 @@ static int proc_get_driver_variable(char *page, char **start, #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) dev->perm_addr, #endif - dev->dev_addr - ); + dev->dev_addr); rtnl_unlock(); @@ -1690,8 +2189,7 @@ static int proc_get_tally_counter(char *page, char **start, le32_to_cpu(counters->rx_mac_missed), le32_to_cpu(counters->rx_tcam_dropped), le32_to_cpu(counters->tdu), - le32_to_cpu(counters->rdu), - ); + le32_to_cpu(counters->rdu),); len += snprintf(page + len, count - len, "\n"); out_unlock: @@ -1720,7 +2218,91 @@ static int proc_get_registers(char *page, char **start, for (n = 0; n < max;) { len += snprintf(page + len, count - len, - "\n0x%02x:\t", + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + max = 0xB00; + for (n = 0xA00; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + max = 0xD40; + for (n = 0xD00; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + max = 0x2840; + for (n = 0x2800; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", + n); + + for (i = 0; i < 16 && n < max; i++, n++) { + byte_rd = readb(ioaddr + n); + len += snprintf(page + len, count - len, + "%02x ", + byte_rd); + } + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return len; +} + +static int proc_get_all_registers(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + struct net_device *dev = data; + int i, n, max; + u8 byte_rd; + struct rtl8125_private *tp = netdev_priv(dev); + void __iomem *ioaddr = tp->mmio_addr; + struct pci_dev *pdev = tp->pci_dev; + int len = 0; + + len += snprintf(page + len, count - len, + "\nDump All MAC Registers\n" + "Offset\tValue\n------\t-----\n"); + + rtnl_lock(); + + max = pci_resource_len(pdev, 2); + max = min(max, 0x8000); + + for (n = 0; n < max;) { + len += snprintf(page + len, count - len, + "\n0x%04x:\t", n); for (i = 0; i < 16 && n < max; i++, n++) { @@ -1733,6 +2315,8 @@ static int proc_get_registers(char *page, char **start, rtnl_unlock(); + len += snprintf(page + len, count - len, "\nTotal length:0x%X", max); + len += snprintf(page + len, count - len, "\n"); *eof = 1; @@ -1808,6 +2392,70 @@ static int proc_get_eth_phy(char *page, char **start, } } + len += snprintf(page + len, count - len, + "\n####################extra reg##################\n"); + n = 0xA400; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 8; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + n = 0xA410; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + n = 0xA434; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + + n = 0xA5D0; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 4; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + + n = 0xA61A; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + + n = 0xA6D0; + len += snprintf(page + len, count - len, + "\n0x%02x:\t", + n); + for (i = 0; i < 3; i++, n+=2) { + word_rd = rtl8125_mdio_direct_read_phy_ocp(tp, n); + len += snprintf(page + len, count - len, + "%04x ", + word_rd); + } + rtnl_unlock(); len += snprintf(page + len, count - len, "\n"); @@ -1916,6 +2564,8 @@ static int proc_get_temperature(char *page, char **start, case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: + case CFG_METHOD_10: + case CFG_METHOD_11: len += snprintf(page + len, count - len, "\nChip Temperature\n"); break; @@ -1924,8 +2574,14 @@ static int proc_get_temperature(char *page, char **start, } rtnl_lock(); + + if (!rtl8125_sysfs_testmode_on(tp)) { + len += snprintf(page + len, count - len, + "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + goto out_unlock; + } + ts_digout = rtl8125_read_thermal_sensor(tp); - rtnl_unlock(); tj = ts_digout / 2; if (ts_digout <= 512) { @@ -1951,21 +2607,26 @@ static int proc_get_temperature(char *page, char **start, len += snprintf(page + len, count - len, "\n"); +out_unlock: + rtnl_unlock(); + *eof = 1; return len; } -static int proc_get_cable_info(char *page, char **start, - off_t offset, int count, - int *eof, void *data) +static int _proc_get_cable_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data, + bool poe_mode) { int i; u16 status; int len = 0; struct net_device *dev = data; int cp_status[RTL8125_CP_NUM] = {0}; - u16 cp_len[RTL8125_CP_NUM] = {0}; + int cp_len[RTL8125_CP_NUM] = {0}; struct rtl8125_private *tp = netdev_priv(dev); + const char *pair_str[RTL8125_CP_NUM] = {"1-2", "3-6", "4-5", "7-8"}; switch (tp->mcfg) { case CFG_METHOD_2 ... CFG_METHOD_7: @@ -1977,6 +2638,12 @@ static int proc_get_cable_info(char *page, char **start, rtnl_lock(); + if (!rtl8125_sysfs_testmode_on(tp)) { + len += snprintf(page + len, count - len, + "\nPlease turn on ""/sys/class/net//rtk_adv/testmode"".\n\n"); + goto out_unlock; + } + status = RTL_R16(tp, PHYstatus); if (status & LinkStatus) len += snprintf(page + len, count - len, @@ -1986,60 +2653,259 @@ static int proc_get_cable_info(char *page, char **start, len += snprintf(page + len, count - len, "\nlink status:off"); - rtl8125_get_cp(tp, cp_len, cp_status); + rtl8125_get_cp_len(tp, cp_len); - rtnl_unlock(); + rtl8125_get_cp_status(tp, cp_status, poe_mode); len += snprintf(page + len, count - len, - "\npair\tlength\tstaus\n"); + "\npair\tlength\tstatus \tpp\n"); - for (i =0; i= KERNEL_VERSION(2,6,32) - rtl8125_proc = proc_mkdir(MODULENAME, init_net.proc_net); -#else - rtl8125_proc = proc_mkdir(MODULENAME, proc_net); -#endif - if (!rtl8125_proc) - dprintk("cannot create %s proc entry \n", MODULENAME); + return _proc_get_cable_info(page, start, offset, count, eof, data, 0); } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) -/* - * seq_file wrappers for procfile show routines. - */ -static int rtl8125_proc_open(struct inode *inode, struct file *file) +static int proc_get_poe_cable_info(char *page, char **start, + off_t offset, int count, + int *eof, void *data) { - struct net_device *dev = proc_get_parent_data(inode); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) - int (*show)(struct seq_file *, void *) = pde_data(inode); -#else - int (*show)(struct seq_file *, void *) = PDE_DATA(inode); -#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) - - return single_open(file, show, dev); + return _proc_get_cable_info(page, start, offset, count, eof, data, 1); } -#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) -static const struct proc_ops rtl8125_proc_fops = { - .proc_open = rtl8125_proc_open, - .proc_read = seq_read, - .proc_lseek = seq_lseek, - .proc_release = single_release, -}; +static void _proc_dump_desc(char *page, int *page_len, int *count, void *desc_base, + u32 alloc_size) +{ + u32 *pdword; + int i; + + if (desc_base == NULL || + alloc_size == 0) + return; + + len = *page_len; + pdword = (u32*)desc_base; + for (i=0; i<(alloc_size/4); i++) { + if (!(i % 4)) + len += snprintf(page + len, *count - len, + "\n%04x ", + i); + len += snprintf(page + len, *count - len, + "%08x ", + pdword[i]); + } + + len += snprintf(page + len, *count - len, "\n"); + + *page_len = len; + return; +} + +static int proc_dump_rx_desc(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + int len = 0; + struct net_device *dev = data; + struct rtl8125_private *tp = netdev_priv(dev); + + rtnl_lock(); + + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8125_rx_ring *ring = &tp->rx_ring[i]; + + if (!ring) + continue; + + len += snprintf(page + len, count - len, + "\ndump rx &d desc:%d", + i, ring->num_rx_desc); + + _proc_dump_desc(page, &len, &count, + ring->RxDescArray, + ring->RxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8125_num_lib_rx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumRxQueues; i++) { + struct rtl8125_ring *lib_ring = &tp->lib_rx_ring[i]; + if (lib_ring->enabled) { + len += snprintf(page + len, count - len, + "\ndump lib rx %d desc:%d", + i, + ring->ring_size); + _proc_dump_desc(page, &len, &count, + (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + + return len; +} + +static int proc_dump_tx_desc(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + int len = 0; + struct net_device *dev = data; + struct rtl8125_private *tp = netdev_priv(dev); + int i; + + rtnl_lock(); + + for (i = 0; i < tp->num_tx_rings; i++) { + struct rtl8125_tx_ring *ring = &tp->tx_ring[i]; + + if (!ring) + continue; + + len += snprintf(page + len, count - len, + "\ndump tx desc:%d", + ring->num_tx_desc); + + _proc_dump_desc(page, &len, &count, + ring->TxDescArray, + ring->TxDescAllocSize); + } + +#ifdef ENABLE_LIB_SUPPORT + if (rtl8125_num_lib_tx_rings(tp) > 0) { + for (i = 0; i < tp->HwSuppNumTxQueues; i++) { + struct rtl8125_ring *lib_ring = &tp->lib_tx_ring[i]; + if (lib_ring->enabled) { + len += snprintf(page + len, count - len, + "\ndump lib tx %d desc:%d", + i, + ring->ring_size); + _proc_dump_desc(page, &len, &count, + (void*)lib_ring->desc_addr, + lib_ring->desc_size); + } + } + } +#endif //ENABLE_LIB_SUPPORT + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + + return len; +} + +static int proc_dump_msix_tbl(char *page, char **start, + off_t offset, int count, + int *eof, void *data) +{ + int i, j; + int len = 0; + void __iomem *ioaddr; + struct net_device *dev = data; + struct rtl8125_private *tp = netdev_priv(dev); + + /* ioremap MMIO region */ + ioaddr = ioremap(pci_resource_start(tp->pci_dev, 4), pci_resource_len(tp->pci_dev, 4)); + if (!ioaddr) + return -EFAULT; + + rtnl_lock(); + + len += snprintf(page + len, count - len, + "\ndump MSI-X Table. Total Entry %d. \n", + tp->hw_supp_irq_nvecs); + + for (i=0; ihw_supp_irq_nvecs; i++) { + len += snprintf(page + len, count - len, + "\n%04x ", i); + for (j=0; j<4; j++) + len += snprintf(page + len, count - len, "%08x ", + readl(ioaddr + i*0x10 + 4*j)); + } + + rtnl_unlock(); + + len += snprintf(page + len, count - len, "\n"); + + *eof = 1; + return 0; +} + +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) + +static void rtl8125_proc_module_init(void) +{ + //create /proc/net/r8125 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32) + rtl8125_proc = proc_mkdir(MODULENAME, init_net.proc_net); +#else + rtl8125_proc = proc_mkdir(MODULENAME, proc_net); +#endif + if (!rtl8125_proc) + dprintk("cannot create %s proc entry \n", MODULENAME); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) +/* + * seq_file wrappers for procfile show routines. + */ +static int rtl8125_proc_open(struct inode *inode, struct file *file) +{ + struct net_device *dev = proc_get_parent_data(inode); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) + int (*show)(struct seq_file *, void *) = pde_data(inode); +#else + int (*show)(struct seq_file *, void *) = PDE_DATA(inode); +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0) + + return single_open(file, show, dev); +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) +static const struct proc_ops rtl8125_proc_fops = { + .proc_open = rtl8125_proc_open, + .proc_read = seq_read, + .proc_lseek = seq_lseek, + .proc_release = single_release, +}; #else static const struct file_operations rtl8125_proc_fops = { .open = rtl8125_proc_open, @@ -2055,7 +2921,7 @@ static const struct file_operations rtl8125_proc_fops = { * Table of proc files we need to create. */ struct rtl8125_proc_file { - char name[12]; + char name[16]; #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) int (*show)(struct seq_file *, void *); #else @@ -2063,68 +2929,143 @@ struct rtl8125_proc_file { #endif }; -static const struct rtl8125_proc_file rtl8125_proc_files[] = { +static const struct rtl8125_proc_file rtl8125_debug_proc_files[] = { { "driver_var", &proc_get_driver_variable }, { "tally", &proc_get_tally_counter }, { "registers", &proc_get_registers }, + { "registers2", &proc_get_all_registers }, { "pcie_phy", &proc_get_pcie_phy }, { "eth_phy", &proc_get_eth_phy }, { "ext_regs", &proc_get_extended_registers }, { "pci_regs", &proc_get_pci_registers }, + { "tx_desc", &proc_dump_tx_desc }, + { "rx_desc", &proc_dump_rx_desc }, + { "msix_tbl", &proc_dump_msix_tbl }, + { "", NULL } +}; + +static const struct rtl8125_proc_file rtl8125_test_proc_files[] = { { "temp", &proc_get_temperature }, { "cdt", &proc_get_cable_info }, + { "cdt_poe", &proc_get_poe_cable_info }, { "", NULL } }; +#define R8125_PROC_DEBUG_DIR "debug" +#define R8125_PROC_TEST_DIR "test" + static void rtl8125_proc_init(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); const struct rtl8125_proc_file *f; struct proc_dir_entry *dir; - if (rtl8125_proc && !tp->proc_dir) { + if (!rtl8125_proc) + return; + + if (tp->proc_dir_debug || tp->proc_dir_test) + return; + #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) - dir = proc_mkdir_data(dev->name, 0, rtl8125_proc, dev); - if (!dir) { - printk("Unable to initialize /proc/net/%s/%s\n", - MODULENAME, dev->name); + dir = proc_mkdir_data(dev->name, 0, rtl8125_proc, dev); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s\n", + MODULENAME, dev->name); + return; + } + tp->proc_dir = dir; + proc_init_num++; + + /* create debug entry */ + dir = proc_mkdir_data(R8125_PROC_DEBUG_DIR, 0, tp->proc_dir, dev); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_DEBUG_DIR); + return; + } + + tp->proc_dir_debug = dir; + for (f = rtl8125_debug_proc_files; f->name[0]; f++) { + if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir, + &rtl8125_proc_fops, f->show)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_DEBUG_DIR, + f->name); return; } + } - tp->proc_dir = dir; - proc_init_num++; + /* create test entry */ + dir = proc_mkdir_data(R8125_PROC_TEST_DIR, 0, tp->proc_dir, dev); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_TEST_DIR); + return; + } - for (f = rtl8125_proc_files; f->name[0]; f++) { - if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir, - &rtl8125_proc_fops, f->show)) { - printk("Unable to initialize " - "/proc/net/%s/%s/%s\n", - MODULENAME, dev->name, f->name); - return; - } + tp->proc_dir_test = dir; + for (f = rtl8125_test_proc_files; f->name[0]; f++) { + if (!proc_create_data(f->name, S_IFREG | S_IRUGO, dir, + &rtl8125_proc_fops, f->show)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_TEST_DIR, + f->name); + return; } + } #else - dir = proc_mkdir(dev->name, rtl8125_proc); - if (!dir) { - printk("Unable to initialize /proc/net/%s/%s\n", - MODULENAME, dev->name); + dir = proc_mkdir(dev->name, rtl8125_proc); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s\n", + MODULENAME, dev->name); + return; + } + + tp->proc_dir = dir; + proc_init_num++; + + /* create debug entry */ + dir = proc_mkdir(R8125_PROC_DEBUG_DIR, tp->proc_dir); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_DEBUG_DIR); + return; + } + + tp->proc_dir_debug = dir; + for (f = rtl8125_debug_proc_files; f->name[0]; f++) { + if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO, + dir, f->show, dev)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_DEBUG_DIR, + f->name); return; } + } - tp->proc_dir = dir; - proc_init_num++; + /* create test entry */ + dir = proc_mkdir(R8125_PROC_TEST_DIR, tp->proc_dir); + if (!dir) { + printk("Unable to initialize /proc/net/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_TEST_DIR); + return; + } - for (f = rtl8125_proc_files; f->name[0]; f++) { - if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO, - dir, f->show, dev)) { - printk("Unable to initialize " - "/proc/net/%s/%s/%s\n", - MODULENAME, dev->name, f->name); - return; - } + tp->proc_dir_test = dir; + for (f = rtl8125_test_proc_files; f->name[0]; f++) { + if (!create_proc_read_entry(f->name, S_IFREG | S_IRUGO, + dir, f->show, dev)) { + printk("Unable to initialize " + "/proc/net/%s/%s/%s/%s\n", + MODULENAME, dev->name, R8125_PROC_TEST_DIR, + f->name); + return; } -#endif } +#endif } static void rtl8125_proc_remove(struct net_device *dev) @@ -2134,33 +3075,119 @@ static void rtl8125_proc_remove(struct net_device *dev) if (tp->proc_dir) { #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,10,0) remove_proc_subtree(dev->name, rtl8125_proc); - proc_init_num--; - #else const struct rtl8125_proc_file *f; struct rtl8125_private *tp = netdev_priv(dev); - for (f = rtl8125_proc_files; f->name[0]; f++) - remove_proc_entry(f->name, tp->proc_dir); + if (tp->proc_dir_debug) { + for (f = rtl8125_debug_proc_files; f->name[0]; f++) + remove_proc_entry(f->name, tp->proc_dir_debug); + remove_proc_entry(R8125_PROC_DEBUG_DIR, tp->proc_dir); + } + + if (tp->proc_dir_test) { + for (f = rtl8125_test_proc_files; f->name[0]; f++) + remove_proc_entry(f->name, tp->proc_dir_test); + remove_proc_entry(R8125_PROC_TEST_DIR, tp->proc_dir); + } remove_proc_entry(dev->name, rtl8125_proc); - proc_init_num--; #endif + proc_init_num--; + + tp->proc_dir_debug = NULL; + tp->proc_dir_test = NULL; tp->proc_dir = NULL; } } #endif //ENABLE_R8125_PROCFS +#ifdef ENABLE_R8125_SYSFS +/**************************************************************************** +* -----------------------------SYSFS STUFF------------------------- +***************************************************************************** +*/ +static ssize_t testmode_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct net_device *netdev = to_net_dev(dev); + struct rtl8125_private *tp = netdev_priv(netdev); + + sprintf(buf, "%u\n", tp->testmode); + + return strlen(buf); +} + +static ssize_t testmode_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct net_device *netdev = to_net_dev(dev); + struct rtl8125_private *tp = netdev_priv(netdev); + u32 testmode; + + if (sscanf(buf, "%u\n", &testmode) != 1) + return -EINVAL; + + if (tp->testmode != testmode) { + rtnl_lock(); + tp->testmode = testmode; + rtnl_unlock(); + } + + return count; +} + +static DEVICE_ATTR_RW(testmode); + +static struct attribute *rtk_adv_attrs[] = { + &dev_attr_testmode.attr, + NULL +}; + +static struct attribute_group rtk_adv_grp = { + .name = "rtl_adv", + .attrs = rtk_adv_attrs, +}; + +static void rtl8125_sysfs_init(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + int ret; + + /* init rtl_adv */ +#ifdef ENABLE_LIB_SUPPORT + tp->testmode = 0; +#else + tp->testmode = 1; +#endif //ENABLE_LIB_SUPPORT + + ret = sysfs_create_group(&dev->dev.kobj, &rtk_adv_grp); + if (ret < 0) + netif_warn(tp, probe, dev, "create rtk_adv_grp fail\n"); + else + set_bit(R8125_SYSFS_RTL_ADV, tp->sysfs_flag); +} + +static void rtl8125_sysfs_remove(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + if (test_and_clear_bit(R8125_SYSFS_RTL_ADV, tp->sysfs_flag)) + sysfs_remove_group(&dev->dev.kobj, &rtk_adv_grp); +} +#endif //ENABLE_R8125_SYSFS + static inline u16 map_phy_ocp_addr(u16 PageNum, u8 RegNum) { u16 OcpPageNum = 0; u8 OcpRegNum = 0; u16 OcpPhyAddress = 0; - if ( PageNum == 0 ) { - OcpPageNum = OCP_STD_PHY_BASE_PAGE + ( RegNum / 8 ); - OcpRegNum = 0x10 + ( RegNum % 8 ); + if (PageNum == 0) { + OcpPageNum = OCP_STD_PHY_BASE_PAGE + (RegNum / 8); + OcpRegNum = 0x10 + (RegNum % 8); } else { OcpPageNum = PageNum; OcpRegNum = RegNum; @@ -2168,7 +3195,7 @@ static inline u16 map_phy_ocp_addr(u16 PageNum, u8 RegNum) OcpPageNum <<= 4; - if ( OcpRegNum < 16 ) { + if (OcpRegNum < 16) { OcpPhyAddress = 0; } else { OcpRegNum -= 16; @@ -2204,11 +3231,12 @@ static void mdio_real_direct_write_phy_ocp(struct rtl8125_private *tp, } } -static void mdio_direct_write_phy_ocp(struct rtl8125_private *tp, - u16 RegAddr, - u16 value) +static void rtl8125_mdio_direct_write_phy_ocp(struct rtl8125_private *tp, + u16 RegAddr, + u16 value) { - if (tp->rtk_enable_diag) return; + if (tp->rtk_enable_diag) + return; mdio_real_direct_write_phy_ocp(tp, RegAddr, value); } @@ -2223,7 +3251,7 @@ static void rtl8125_mdio_write_phy_ocp(struct rtl8125_private *tp, ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); - mdio_direct_write_phy_ocp(tp, ocp_addr, value); + rtl8125_mdio_direct_write_phy_ocp(tp, ocp_addr, value); } */ @@ -2254,7 +3282,8 @@ void rtl8125_mdio_write(struct rtl8125_private *tp, u16 RegAddr, u16 value) { - if (tp->rtk_enable_diag) return; + if (tp->rtk_enable_diag) + return; mdio_real_write(tp, RegAddr, value); } @@ -2297,10 +3326,11 @@ static u32 mdio_real_direct_read_phy_ocp(struct rtl8125_private *tp, return value; } -static u32 mdio_direct_read_phy_ocp(struct rtl8125_private *tp, - u16 RegAddr) +static u32 rtl8125_mdio_direct_read_phy_ocp(struct rtl8125_private *tp, + u16 RegAddr) { - if (tp->rtk_enable_diag) return 0xffffffff; + if (tp->rtk_enable_diag) + return 0xffffffff; return mdio_real_direct_read_phy_ocp(tp, RegAddr); } @@ -2314,7 +3344,7 @@ static u32 rtl8125_mdio_read_phy_ocp(struct rtl8125_private *tp, ocp_addr = map_phy_ocp_addr(PageNum, RegAddr); - return mdio_direct_read_phy_ocp(tp, ocp_addr); + return rtl8125_mdio_direct_read_phy_ocp(tp, ocp_addr); } */ @@ -2338,7 +3368,8 @@ static u32 mdio_real_read(struct rtl8125_private *tp, u32 rtl8125_mdio_read(struct rtl8125_private *tp, u16 RegAddr) { - if (tp->rtk_enable_diag) return 0xffffffff; + if (tp->rtk_enable_diag) + return 0xffffffff; return mdio_real_read(tp, RegAddr); } @@ -2355,7 +3386,7 @@ u32 rtl8125_mdio_prot_direct_read_phy_ocp(struct rtl8125_private *tp, return mdio_real_direct_read_phy_ocp(tp, RegAddr); } -static void ClearAndSetEthPhyBit(struct rtl8125_private *tp, u8 addr, u16 clearmask, u16 setmask) +static void rtl8125_clear_and_set_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 clearmask, u16 setmask) { u16 PhyRegValue; @@ -2367,48 +3398,44 @@ static void ClearAndSetEthPhyBit(struct rtl8125_private *tp, u8 addr, u16 clear void rtl8125_clear_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask) { - ClearAndSetEthPhyBit(tp, - addr, - mask, - 0 - ); + rtl8125_clear_and_set_eth_phy_bit(tp, + addr, + mask, + 0); } void rtl8125_set_eth_phy_bit(struct rtl8125_private *tp, u8 addr, u16 mask) { - ClearAndSetEthPhyBit(tp, - addr, - 0, - mask - ); + rtl8125_clear_and_set_eth_phy_bit(tp, + addr, + 0, + mask); } -static void ClearAndSetEthPhyOcpBit(struct rtl8125_private *tp, u16 addr, u16 clearmask, u16 setmask) +static void rtl8125_clear_and_set_eth_phy_ocp_bit(struct rtl8125_private *tp, u16 addr, u16 clearmask, u16 setmask) { u16 PhyRegValue; - PhyRegValue = mdio_direct_read_phy_ocp(tp, addr); + PhyRegValue = rtl8125_mdio_direct_read_phy_ocp(tp, addr); PhyRegValue &= ~clearmask; PhyRegValue |= setmask; - mdio_direct_write_phy_ocp(tp, addr, PhyRegValue); + rtl8125_mdio_direct_write_phy_ocp(tp, addr, PhyRegValue); } -void ClearEthPhyOcpBit(struct rtl8125_private *tp, u16 addr, u16 mask) +static void rtl8125_clear_eth_phy_ocp_bit(struct rtl8125_private *tp, u16 addr, u16 mask) { - ClearAndSetEthPhyOcpBit(tp, - addr, - mask, - 0 - ); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + addr, + mask, + 0); } -void SetEthPhyOcpBit(struct rtl8125_private *tp, u16 addr, u16 mask) +static void rtl8125_set_eth_phy_ocp_bit(struct rtl8125_private *tp, u16 addr, u16 mask) { - ClearAndSetEthPhyOcpBit(tp, - addr, - 0, - mask - ); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + addr, + 0, + mask); } void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value) @@ -2427,7 +3454,7 @@ void rtl8125_mac_ocp_write(struct rtl8125_private *tp, u16 reg_addr, u16 value) RTL_W32(tp, MACOCP, data32); } -u32 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr) +u16 rtl8125_mac_ocp_read(struct rtl8125_private *tp, u16 reg_addr) { u32 data32; u16 data16 = 0; @@ -2463,7 +3490,7 @@ static u32 mac_mcu_read(struct rtl8125_private *tp, u16 reg) #endif static void -ClearAndSetMcuAccessRegBit( +rtl8125_clear_set_mac_ocp_bit( struct rtl8125_private *tp, u16 addr, u16 clearmask, @@ -2479,31 +3506,29 @@ ClearAndSetMcuAccessRegBit( } static void -ClearMcuAccessRegBit( +rtl8125_clear_mac_ocp_bit( struct rtl8125_private *tp, u16 addr, u16 mask ) { - ClearAndSetMcuAccessRegBit(tp, - addr, - mask, - 0 - ); + rtl8125_clear_set_mac_ocp_bit(tp, + addr, + mask, + 0); } static void -SetMcuAccessRegBit( +rtl8125_set_mac_ocp_bit( struct rtl8125_private *tp, u16 addr, u16 mask ) { - ClearAndSetMcuAccessRegBit(tp, - addr, - 0, - mask - ); + rtl8125_clear_set_mac_ocp_bit(tp, + addr, + 0, + mask); } u32 rtl8125_ocp_read_with_oob_base_address(struct rtl8125_private *tp, u16 addr, u8 len, const u32 base_address) @@ -2515,9 +3540,12 @@ u32 rtl8125_ocp_read(struct rtl8125_private *tp, u16 addr, u8 len) { u32 value = 0; - if (HW_DASH_SUPPORT_TYPE_2(tp)) + if (!tp->AllowAccessDashOcp) + return 0xffffffff; + + if (tp->HwSuppOcpChannelVer == 2) value = rtl8125_ocp_read_with_oob_base_address(tp, addr, len, NO_BASE_ADDRESS); - else if (HW_DASH_SUPPORT_TYPE_3(tp)) + else if (tp->HwSuppOcpChannelVer == 3) value = rtl8125_ocp_read_with_oob_base_address(tp, addr, len, RTL8168FP_OOBMAC_BASE); return value; @@ -2530,9 +3558,12 @@ u32 rtl8125_ocp_write_with_oob_base_address(struct rtl8125_private *tp, u16 addr void rtl8125_ocp_write(struct rtl8125_private *tp, u16 addr, u8 len, u32 value) { - if (HW_DASH_SUPPORT_TYPE_2(tp)) + if (!tp->AllowAccessDashOcp) + return; + + if (tp->HwSuppOcpChannelVer == 2) rtl8125_ocp_write_with_oob_base_address(tp, addr, len, value, NO_BASE_ADDRESS); - else if (HW_DASH_SUPPORT_TYPE_3(tp)) + else if (tp->HwSuppOcpChannelVer == 3) rtl8125_ocp_write_with_oob_base_address(tp, addr, len, value, RTL8168FP_OOBMAC_BASE); } @@ -2544,12 +3575,15 @@ void rtl8125_oob_mutex_lock(struct rtl8125_private *tp) u16 ocp_reg_mutex_oob; u16 ocp_reg_mutex_prio; - if (!tp->DASH) return; + if (!tp->DASH) + return; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: case CFG_METHOD_6: + case CFG_METHOD_8: + case CFG_METHOD_9: ocp_reg_mutex_oob = 0x110; ocp_reg_mutex_ib = 0x114; ocp_reg_mutex_prio = 0x11C; @@ -2593,12 +3627,15 @@ void rtl8125_oob_mutex_unlock(struct rtl8125_private *tp) u16 ocp_reg_mutex_oob; u16 ocp_reg_mutex_prio; - if (!tp->DASH) return; + if (!tp->DASH) + return; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: case CFG_METHOD_6: + case CFG_METHOD_8: + case CFG_METHOD_9: ocp_reg_mutex_oob = 0x110; ocp_reg_mutex_ib = 0x114; ocp_reg_mutex_prio = 0x11C; @@ -2618,80 +3655,144 @@ void rtl8125_oob_notify(struct rtl8125_private *tp, u8 cmd) rtl8125_ocp_write(tp, 0x30, 1, 0x01); } -static int rtl8125_check_dash(struct rtl8125_private *tp) +static bool rtl8125_is_allow_access_dash_ocp(struct rtl8125_private *tp) { - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - if (rtl8125_ocp_read(tp, 0x128, 1) & BIT_0) - return 1; - } + bool allow_access = false; + u16 mac_ocp_data; - return 0; + if (!HW_DASH_SUPPORT_DASH(tp)) + goto exit; + + allow_access = true; + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xd460); + if (mac_ocp_data == 0xffff || !(mac_ocp_data & BIT_0)) + allow_access = false; + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xd4c0); + if (mac_ocp_data == 0xffff || (mac_ocp_data & BIT_3)) + allow_access = false; + break; + default: + goto exit; + } +exit: + return allow_access; } -void rtl8125_dash2_disable_tx(struct rtl8125_private *tp) +static u32 rtl8125_get_dash_fw_ver(struct rtl8125_private *tp) { - if (!tp->DASH) return; + u32 ver = 0xffffffff; - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - u16 WaitCnt; - u8 TmpUchar; + if (FALSE == HW_DASH_SUPPORT_GET_FIRMWARE_VERSION(tp)) + goto exit; - //Disable oob Tx - RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) & ~( BIT_0 )); - WaitCnt = 0; + ver = rtl8125_ocp_read(tp, OCP_REG_FIRMWARE_MAJOR_VERSION, 4); - //wait oob tx disable - do { - TmpUchar = RTL_CMAC_R8(tp, CMAC_IBISR0); +exit: + return ver; +} - if ( TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE ) { - break; - } +static int _rtl8125_check_dash(struct rtl8125_private *tp) +{ + if (!tp->AllowAccessDashOcp) + return 0; + + if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp) || + HW_DASH_SUPPORT_TYPE_4(tp)) { + if (rtl8125_ocp_read(tp, 0x128, 1) & BIT_0) + return 1; + } - udelay( 50 ); - WaitCnt++; - } while(WaitCnt < 2000); + return 0; +} - //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE - RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); +static int rtl8125_check_dash(struct rtl8125_private *tp) +{ + if (_rtl8125_check_dash(tp)) { + u32 ver = rtl8125_get_dash_fw_ver(tp); + if (!(ver == 0 || ver == 0xffffffff)) + return 1; } + + return 0; +} + +void rtl8125_dash2_disable_tx(struct rtl8125_private *tp) +{ + u16 WaitCnt; + u8 TmpUchar; + + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; + + if (!tp->DASH) + return; + + //Disable oob Tx + RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) & ~(BIT_0)); + WaitCnt = 0; + + //wait oob tx disable + do { + TmpUchar = RTL_CMAC_R8(tp, CMAC_IBISR0); + if (TmpUchar & ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE) + break; + + udelay(50); + WaitCnt++; + } while(WaitCnt < 2000); + + //Clear ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE + RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0) | ISRIMR_DASH_TYPE2_TX_DISABLE_IDLE); } void rtl8125_dash2_enable_tx(struct rtl8125_private *tp) { - if (!tp->DASH) return; + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) | BIT_0); - } + if (!tp->DASH) + return; + + RTL_CMAC_W8(tp, CMAC_IBCR2, RTL_CMAC_R8(tp, CMAC_IBCR2) | BIT_0); } void rtl8125_dash2_disable_rx(struct rtl8125_private *tp) { - if (!tp->DASH) return; + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) & ~( BIT_0 )); - } + if (!tp->DASH) + return; + + RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) & ~(BIT_0)); } void rtl8125_dash2_enable_rx(struct rtl8125_private *tp) { - if (!tp->DASH) return; + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) | BIT_0); - } + if (!tp->DASH) + return; + + RTL_CMAC_W8(tp, CMAC_IBCR0, RTL_CMAC_R8(tp, CMAC_IBCR0) | BIT_0); } static void rtl8125_dash2_disable_txrx(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - rtl8125_dash2_disable_tx( tp ); - rtl8125_dash2_disable_rx( tp ); - } + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; + + rtl8125_dash2_disable_tx(tp); + rtl8125_dash2_disable_rx(tp); } static int rtl8125_wait_dash_fw_ready(struct rtl8125_private *tp) @@ -2700,7 +3801,8 @@ static int rtl8125_wait_dash_fw_ready(struct rtl8125_private *tp) int timeout; if (HW_DASH_SUPPORT_TYPE_2(tp) == FALSE && - HW_DASH_SUPPORT_TYPE_3(tp) == FALSE) + HW_DASH_SUPPORT_TYPE_3(tp) == FALSE && + HW_DASH_SUPPORT_TYPE_4(tp) == FALSE) goto out; if (!tp->DASH) @@ -2720,37 +3822,66 @@ static int rtl8125_wait_dash_fw_ready(struct rtl8125_private *tp) return rc; } -static void rtl8125_driver_start(struct rtl8125_private *tp) +static void +rtl8125_notify_dash_oob_cmac(struct rtl8125_private *tp, u32 cmd) { u32 tmp_value; - if (HW_DASH_SUPPORT_TYPE_2(tp) == FALSE && - HW_DASH_SUPPORT_TYPE_3(tp) == FALSE) + if (!HW_DASH_SUPPORT_CMAC(tp)) return; - rtl8125_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_START); - tmp_value = rtl8125_ocp_read(tp, 0x30, 1); + rtl8125_ocp_write(tp, 0x180, 4, cmd); + tmp_value = rtl8125_ocp_read(tp, 0x30, 4); tmp_value |= BIT_0; - rtl8125_ocp_write(tp, 0x30, 1, tmp_value); + rtl8125_ocp_write(tp, 0x30, 4, tmp_value); +} + +static void +rtl8125_notify_dash_oob_ipc2(struct rtl8125_private *tp, u32 cmd) +{ + if (FALSE == HW_DASH_SUPPORT_TYPE_4(tp)) + return; + + rtl8125_ocp_write(tp, IB2SOC_DATA, 4, cmd); + rtl8125_ocp_write(tp, IB2SOC_CMD, 4, 0x00); + rtl8125_ocp_write(tp, IB2SOC_SET, 4, 0x01); +} + +static void +rtl8125_notify_dash_oob(struct rtl8125_private *tp, u32 cmd) +{ + switch (tp->HwSuppDashVer) { + case 2: + case 3: + return rtl8125_notify_dash_oob_cmac(tp, cmd); + case 4: + return rtl8125_notify_dash_oob_ipc2(tp, cmd); + default: + return; + } +} + +static void rtl8125_driver_start(struct rtl8125_private *tp) +{ + if (!tp->AllowAccessDashOcp) + return; + + rtl8125_notify_dash_oob(tp, OOB_CMD_DRIVER_START); rtl8125_wait_dash_fw_ready(tp); } static void rtl8125_driver_stop(struct rtl8125_private *tp) { - u32 tmp_value; struct net_device *dev = tp->dev; - if (HW_DASH_SUPPORT_TYPE_2(tp) == FALSE && - HW_DASH_SUPPORT_TYPE_3(tp) == FALSE) + if (!tp->AllowAccessDashOcp) return; - rtl8125_dash2_disable_txrx(dev); + if (HW_DASH_SUPPORT_CMAC(tp)) + rtl8125_dash2_disable_txrx(dev); - rtl8125_ocp_write(tp, 0x180, 1, OOB_CMD_DRIVER_STOP); - tmp_value = rtl8125_ocp_read(tp, 0x30, 1); - tmp_value |= BIT_0; - rtl8125_ocp_write(tp, 0x30, 1, tmp_value); + rtl8125_notify_dash_oob(tp, OOB_CMD_DRIVER_STOP); rtl8125_wait_dash_fw_ready(tp); } @@ -2810,20 +3941,18 @@ static void ClearAndSetPCIePhyBit(struct rtl8125_private *tp, u8 addr, u16 clear static void ClearPCIePhyBit(struct rtl8125_private *tp, u8 addr, u16 mask) { - ClearAndSetPCIePhyBit( tp, - addr, - mask, - 0 - ); + ClearAndSetPCIePhyBit(tp, + addr, + mask, + 0); } -static void SetPCIePhyBit( struct rtl8125_private *tp, u8 addr, u16 mask) +static void SetPCIePhyBit(struct rtl8125_private *tp, u8 addr, u16 mask) { - ClearAndSetPCIePhyBit( tp, - addr, - 0, - mask - ); + ClearAndSetPCIePhyBit(tp, + addr, + 0, + mask); } static u32 @@ -2877,7 +4006,7 @@ rtl8125_csi_other_fun_write(struct rtl8125_private *tp, if (tp->mcfg == CFG_METHOD_DEFAULT) multi_fun_sel_bit = 0; - if ( multi_fun_sel_bit > 7 ) + if (multi_fun_sel_bit > 7) return; cmd |= multi_fun_sel_bit << 16; @@ -2964,7 +4093,7 @@ rtl8125_csi_fun0_write_byte(struct rtl8125_private *tp, TmpUlong = rtl8125_csi_other_fun_read(tp, 0, RegAlignAddr); TmpUlong &= ~(0xFF << (8*ShiftByte)); TmpUlong |= (value << (8*ShiftByte)); - rtl8125_csi_other_fun_write( tp, 0, RegAlignAddr, TmpUlong ); + rtl8125_csi_other_fun_write(tp, 0, RegAlignAddr, TmpUlong); } udelay(R8125_CHANNEL_EXIT_DELAY_TIME); @@ -3113,6 +4242,9 @@ rtl8125_enable_rxdvgate(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) | BIT_3); mdelay(2); break; @@ -3132,6 +4264,9 @@ rtl8125_disable_rxdvgate(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_3); mdelay(2); break; @@ -3204,7 +4339,8 @@ rtl8125_stop_all_request(struct net_device *dev) case CFG_METHOD_6: for (i = 0; i < 20; i++) { udelay(10); - if (!(RTL_R8(tp, ChipCmd) & StopReq)) break; + if (!(RTL_R8(tp, ChipCmd) & StopReq)) + break; } if (i == 20) @@ -3226,6 +4362,9 @@ rtl8125_wait_txrx_fifo_empty(struct net_device *dev) case CFG_METHOD_5: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_stop_all_request(dev); break; } @@ -3238,6 +4377,9 @@ rtl8125_wait_txrx_fifo_empty(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: for (i = 0; i < 3000; i++) { udelay(50); if ((RTL_R8(tp, MCUCmd_reg) & (Txfifo_empty | Rxfifo_empty)) == (Txfifo_empty | Rxfifo_empty)) @@ -3251,6 +4393,9 @@ rtl8125_wait_txrx_fifo_empty(struct net_device *dev) case CFG_METHOD_5: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: for (i = 0; i < 3000; i++) { udelay(50); if ((RTL_R16(tp, IntrMitigate) & (BIT_0 | BIT_1 | BIT_8)) == (BIT_0 | BIT_1 | BIT_8)) @@ -3265,21 +4410,25 @@ rtl8125_wait_txrx_fifo_empty(struct net_device *dev) static inline void rtl8125_enable_dash2_interrupt(struct rtl8125_private *tp) { - if (!tp->DASH) return; + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(tp, CMAC_IBIMR0, ( ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE )); - } + if (!tp->DASH) + return; + + RTL_CMAC_W8(tp, CMAC_IBIMR0, (ISRIMR_DASH_TYPE2_ROK | ISRIMR_DASH_TYPE2_TOK | ISRIMR_DASH_TYPE2_TDU | ISRIMR_DASH_TYPE2_RDU | ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE)); } static inline void rtl8125_disable_dash2_interrupt(struct rtl8125_private *tp) { - if (!tp->DASH) return; + if (!HW_DASH_SUPPORT_CMAC(tp)) + return; - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - RTL_CMAC_W8(tp, CMAC_IBIMR0, 0); - } + if (!tp->DASH) + return; + + RTL_CMAC_W8(tp, CMAC_IBIMR0, 0); } #endif @@ -3287,7 +4436,14 @@ void rtl8125_enable_hw_linkchg_interrupt(struct rtl8125_private *tp) { switch (tp->HwCurrIsrVer) { + case 5: + RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V5_LINKCHG); + break; + case 4: + RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V4_LINKCHG); + break; case 2: + case 3: RTL_W32(tp, IMR_V2_SET_REG_8125, ISRIMR_V2_LINKCHG); break; case 1: @@ -3306,6 +4462,9 @@ rtl8125_enable_hw_interrupt(struct rtl8125_private *tp) { switch (tp->HwCurrIsrVer) { case 2: + case 3: + case 4: + case 5: RTL_W32(tp, IMR_V2_SET_REG_8125, tp->intr_mask); break; case 1: @@ -3334,8 +4493,10 @@ static inline void rtl8125_clear_hw_isr_v2(struct rtl8125_private *tp, static inline void rtl8125_disable_hw_interrupt(struct rtl8125_private *tp) { - if (tp->HwCurrIsrVer == 2) { + if (tp->HwCurrIsrVer > 1) { RTL_W32(tp, IMR_V2_CLEAR_REG_8125, 0xFFFFFFFF); + if (tp->HwCurrIsrVer > 3) + RTL_W32(tp, IMR_V4_L2_CLEAR_REG_8125, 0xFFFFFFFF); } else { RTL_W32(tp, tp->imr_reg[0], 0x0000); @@ -3363,7 +4524,7 @@ rtl8125_switch_to_hw_interrupt(struct rtl8125_private *tp) static inline void rtl8125_switch_to_timer_interrupt(struct rtl8125_private *tp) { - if (tp->use_timer_interrrupt) { + if (tp->use_timer_interrupt) { RTL_W32(tp, TIMER_INT0_8125, timer_count); RTL_W32(tp, TCTR0_8125, timer_count); RTL_W32(tp, tp->imr_reg[0], tp->timer_intr_mask); @@ -3382,8 +4543,10 @@ rtl8125_irq_mask_and_ack(struct rtl8125_private *tp) { rtl8125_disable_hw_interrupt(tp); - if (tp->HwCurrIsrVer == 2) { + if (tp->HwCurrIsrVer > 1) { RTL_W32(tp, ISR_V2_8125, 0xFFFFFFFF); + if (tp->HwCurrIsrVer > 3) + RTL_W32(tp, ISR_V4_L2_8125, 0xFFFFFFFF); } else { #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) { @@ -3391,9 +4554,8 @@ rtl8125_irq_mask_and_ack(struct rtl8125_private *tp) RTL_W32(tp, tp->isr_reg[0], RTL_R32(tp, tp->isr_reg[0]) & ~(ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); } else { - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { + if (HW_DASH_SUPPORT_CMAC(tp)) RTL_CMAC_W8(tp, CMAC_IBISR0, RTL_CMAC_R8(tp, CMAC_IBISR0)); - } } } else { RTL_W32(tp, tp->isr_reg[0], RTL_R32(tp, tp->isr_reg[0])); @@ -3443,6 +4605,9 @@ rtl8125_nic_reset(struct net_device *dev) if ((RTL_R8(tp, ChipCmd) & CmdReset) == 0) break; } + + /* reset rcr */ + RTL_W32(tp, RxConfig, (RX_DMA_BURST_512 << RxCfgDMAShift)); } static void @@ -3450,15 +4615,27 @@ rtl8125_hw_set_interrupt_type(struct rtl8125_private *tp, u8 isr_ver) { u8 tmp; + if (tp->HwSuppIsrVer < 2) + return; + + tmp = RTL_R8(tp, INT_CFG0_8125); + switch (tp->HwSuppIsrVer) { + case 4: + case 5: + tmp &= ~INT_CFG0_MSIX_ENTRY_NUM_MODE; + fallthrough; case 2: - tmp = RTL_R8(tp, INT_CFG0_8125); + case 3: tmp &= ~(INT_CFG0_ENABLE_8125); - if (isr_ver == 2) + if (isr_ver > 1) tmp |= INT_CFG0_ENABLE_8125; - RTL_W8(tp, INT_CFG0_8125, tmp); break; + default: + return; } + + RTL_W8(tp, INT_CFG0_8125, tmp); } static void @@ -3474,6 +4651,9 @@ rtl8125_hw_clear_timer_int(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W32(tp, TIMER_INT0_8125, 0x0000); RTL_W32(tp, TIMER_INT1_8125, 0x0000); RTL_W32(tp, TIMER_INT2_8125, 0x0000); @@ -3490,17 +4670,26 @@ rtl8125_hw_clear_int_miti(struct net_device *dev) switch (tp->HwSuppIntMitiVer) { case 3: + case 6: + case 7: //IntMITI_0-IntMITI_31 for (i=0xA00; i<0xB00; i+=4) RTL_W32(tp, i, 0x0000); break; case 4: + case 5: //IntMITI_0-IntMITI_15 for (i = 0xA00; i < 0xA80; i += 4) RTL_W32(tp, i, 0x0000); - RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) & - ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | INT_CFG0_MITIGATION_BYPASS_8125)); + if (tp->HwSuppIntMitiVer == 5) + RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) & + ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | + INT_CFG0_MITIGATION_BYPASS_8125 | + INT_CFG0_RDU_BYPASS_8126)); + else + RTL_W8(tp, INT_CFG0_8125, RTL_R8(tp, INT_CFG0_8125) & + ~(INT_CFG0_TIMEOUT0_BYPASS_8125 | INT_CFG0_MITIGATION_BYPASS_8125)); RTL_W16(tp, INT_CFG1_8125, 0x0000); break; @@ -3514,18 +4703,40 @@ rtl8125_hw_set_timer_int_8125(struct rtl8125_private *tp, { switch (tp->HwSuppIntMitiVer) { case 4: + case 6: + case 7: #ifdef ENABLE_LIB_SUPPORT if (message_id < R8125_MAX_RX_QUEUES_VEC_V3) timer_intmiti_val = 0; #else - if (tp->EnableRss && (message_id < R8125_MAX_RX_QUEUES_VEC_V3)) + if ((tp->HwCurrIsrVer == 2) && (message_id < R8125_MAX_RX_QUEUES_VEC_V3)) timer_intmiti_val = 0; #endif //ENABLE_LIB_SUPPORT + //ROK + if (message_id < R8125_MAX_RX_QUEUES_VEC_V3) + RTL_W8(tp,INT_MITI_V2_0_RX + 8 * message_id, timer_intmiti_val); + //TOK + if (tp->HwSuppIntMitiVer == 4) { + if (message_id == 16) + RTL_W8(tp,INT_MITI_V2_0_TX, timer_intmiti_val); + if (message_id == 18 && tp->num_tx_rings > 1) + RTL_W8(tp,INT_MITI_V2_1_TX, timer_intmiti_val); + } else if (tp->HwSuppIntMitiVer == 6) { + if (message_id < tp->num_tx_rings) + RTL_W8(tp,INT_MITI_V2_0_TX + 8 * message_id, timer_intmiti_val); + } else if (tp->HwSuppIntMitiVer == 4) { + if (message_id == 16) + RTL_W8(tp,INT_MITI_V2_0_TX, timer_intmiti_val); + if (message_id == 17 && tp->num_tx_rings > 1) + RTL_W8(tp,INT_MITI_V2_1_TX, timer_intmiti_val); + } + break; + case 5: if (message_id < R8125_MAX_RX_QUEUES_VEC_V3) //ROK RTL_W8(tp,INT_MITI_V2_0_RX + 8 * message_id, timer_intmiti_val); - else if (message_id == 16) //TOK + if (message_id == 0) //TOK RTL_W8(tp,INT_MITI_V2_0_TX, timer_intmiti_val); - else if (message_id == 18) //TOK + if (message_id == 1 && tp->num_tx_rings > 1) //TOK RTL_W8(tp,INT_MITI_V2_1_TX, timer_intmiti_val); break; } @@ -3562,11 +4773,13 @@ static unsigned int rtl8125_xmii_link_ok(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - unsigned int retval; + u16 status; - retval = (RTL_R16(tp, PHYstatus) & LinkStatus) ? 1 : 0; + status = RTL_R16(tp, PHYstatus); + if (status == 0xffff) + return 0; - return retval; + return (status & LinkStatus) ? 1 : 0; } static int @@ -3590,9 +4803,8 @@ rtl8125_xmii_reset_enable(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (rtl8125_is_in_phy_disable_mode(dev)) { + if (rtl8125_is_in_phy_disable_mode(dev)) return; - } rtl8125_mdio_write(tp, 0x1f, 0x0000); rtl8125_mdio_write(tp, MII_ADVERTISE, rtl8125_mdio_read(tp, MII_ADVERTISE) & @@ -3600,10 +4812,12 @@ rtl8125_xmii_reset_enable(struct net_device *dev) ADVERTISE_100HALF | ADVERTISE_100FULL)); rtl8125_mdio_write(tp, MII_CTRL1000, rtl8125_mdio_read(tp, MII_CTRL1000) & ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL)); - mdio_direct_write_phy_ocp(tp, 0xA5D4, mdio_direct_read_phy_ocp(tp, 0xA5D4) & ~(RTK_ADVERTISE_2500FULL)); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA5D4, rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5D4) & + ~RTK_ADVERTISE_2500FULL); rtl8125_mdio_write(tp, MII_BMCR, BMCR_RESET | BMCR_ANENABLE); - if (rtl8125_wait_phy_reset_complete(tp) == 0) return; + if (rtl8125_wait_phy_reset_complete(tp) == 0) + return; if (netif_msg_link(tp)) printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); @@ -3621,6 +4835,10 @@ rtl8125_init_ring_indexes(struct rtl8125_private *tp) ring->BeginHwDesCloPtr = 0; ring->index = i; ring->priv = tp; + ring->netdev = tp->dev; + + /* reset BQL for queue */ + netdev_tx_reset_queue(txring_txq(ring)); } for (i = 0; i < tp->HwSuppNumRxQueues; i++) { @@ -3628,6 +4846,7 @@ rtl8125_init_ring_indexes(struct rtl8125_private *tp) ring->dirty_rx = ring->cur_rx = 0; ring->index = i; ring->priv = tp; + ring->netdev = tp->dev; } #ifdef ENABLE_LIB_SUPPORT @@ -3658,6 +4877,9 @@ rtl8125_issue_offset_99_event(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xE09A, rtl8125_mac_ocp_read(tp, 0xE09A) | BIT_0); break; } @@ -3667,14 +4889,15 @@ rtl8125_issue_offset_99_event(struct rtl8125_private *tp) static void NICChkTypeEnableDashInterrupt(struct rtl8125_private *tp) { - if (tp->DASH) { + if (!tp->DASH) + return; + + if (HW_DASH_SUPPORT_CMAC(tp)) { // // even disconnected, enable 3 dash interrupt mask bits for in-band/out-band communication // - if (HW_DASH_SUPPORT_TYPE_2(tp) || HW_DASH_SUPPORT_TYPE_3(tp)) { - rtl8125_enable_dash2_interrupt(tp); - RTL_W16(tp, IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); - } + rtl8125_enable_dash2_interrupt(tp); + RTL_W16(tp, IntrMask, (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET)); } } #endif @@ -3692,9 +4915,11 @@ static int rtl8125_enable_eee_plus(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xE080, rtl8125_mac_ocp_read(tp, 0xE080)|BIT_1); break; - default: // dev_printk(KERN_DEBUG, tp_to_dev(tp), "Not Support EEEPlus\n"); ret = -EOPNOTSUPP; @@ -3717,6 +4942,9 @@ static int rtl8125_disable_eee_plus(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xE080, rtl8125_mac_ocp_read(tp, 0xE080)&~BIT_1); break; default: @@ -3738,6 +4966,9 @@ static void rtl8125_enable_double_vlan(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W16(tp, DOUBLE_VLAN_CONFIG, 0xf002); break; default: @@ -3755,6 +4986,9 @@ static void rtl8125_disable_double_vlan(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W16(tp, DOUBLE_VLAN_CONFIG, 0); break; default: @@ -3762,6 +4996,26 @@ static void rtl8125_disable_double_vlan(struct rtl8125_private *tp) } } +static void +rtl8125_set_pfm_patch(struct rtl8125_private *tp, bool enable) +{ + if (!tp->RequiredPfmPatch) + goto exit; + + if (enable) { + rtl8125_set_mac_ocp_bit(tp, 0xD3F0, BIT_0); + rtl8125_set_mac_ocp_bit(tp, 0xD3F2, BIT_0); + rtl8125_set_mac_ocp_bit(tp, 0xE85A, BIT_6); + } else { + rtl8125_clear_mac_ocp_bit(tp, 0xD3F0, BIT_0); + rtl8125_clear_mac_ocp_bit(tp, 0xD3F2, BIT_0); + rtl8125_clear_mac_ocp_bit(tp, 0xE85A, BIT_6); + } + +exit: + return; +} + static void rtl8125_link_on_patch(struct net_device *dev) { @@ -3785,6 +5039,7 @@ rtl8125_link_on_patch(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: if (RTL_R8(tp, PHYstatus) & _10bps) rtl8125_enable_eee_plus(tp); break; @@ -3792,6 +5047,9 @@ rtl8125_link_on_patch(struct net_device *dev) break; } + if (tp->RequiredPfmPatch) + rtl8125_set_pfm_patch(tp, (RTL_R8(tp, PHYstatus) & _10bps) ? 1 : 0); + rtl8125_hw_start(dev); netif_carrier_on(dev); @@ -3801,7 +5059,7 @@ rtl8125_link_on_patch(struct net_device *dev) tp->phy_reg_aner = rtl8125_mdio_read(tp, MII_EXPANSION); tp->phy_reg_anlpar = rtl8125_mdio_read(tp, MII_LPA); tp->phy_reg_gbsr = rtl8125_mdio_read(tp, MII_STAT1000); - tp->phy_reg_status_2500 = mdio_direct_read_phy_ocp(tp, 0xA5D6); + tp->phy_reg_status_2500 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5D6); } static void @@ -3822,12 +5080,16 @@ rtl8125_link_down_patch(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: rtl8125_disable_eee_plus(tp); break; default: break; } + if (tp->RequiredPfmPatch) + rtl8125_set_pfm_patch(tp, 1); + netif_carrier_off(dev); netif_tx_disable(dev); @@ -3845,9 +5107,8 @@ rtl8125_link_down_patch(struct net_device *dev) //rtl8125_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); #ifdef ENABLE_DASH_SUPPORT - if (tp->DASH) { + if (tp->DASH) NICChkTypeEnableDashInterrupt(tp); - } #endif } @@ -3879,69 +5140,81 @@ rtl8125_check_link_status(struct net_device *dev) tp->resume_not_chg_speed = 0; } -static void -rtl8125_link_option_giga(u8 *aut, - u32 *spd, - u8 *dup, - u32 *adv) -{ - if ((*spd != SPEED_1000) && - (*spd != SPEED_100) && - (*spd != SPEED_10)) - *spd = SPEED_1000; - - if ((*dup != DUPLEX_FULL) && (*dup != DUPLEX_HALF)) - *dup = DUPLEX_FULL; - - if ((*aut != AUTONEG_ENABLE) && (*aut != AUTONEG_DISABLE)) - *aut = AUTONEG_ENABLE; - - *adv &= (ADVERTISED_10baseT_Half | - ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | - ADVERTISED_100baseT_Full | - ADVERTISED_1000baseT_Half | - ADVERTISED_1000baseT_Full); - if (*adv == 0) - *adv = (ADVERTISED_10baseT_Half | - ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | - ADVERTISED_100baseT_Full | - ADVERTISED_1000baseT_Half | - ADVERTISED_1000baseT_Full); +static bool +rtl8125_is_autoneg_mode_valid(u32 autoneg) +{ + switch(autoneg) { + case AUTONEG_ENABLE: + case AUTONEG_DISABLE: + return true; + default: + return false; + } +} + +static bool +rtl8125_is_speed_mode_valid(u32 speed) +{ + switch(speed) { + case SPEED_2500: + case SPEED_1000: + case SPEED_100: + case SPEED_10: + return true; + default: + return false; + } +} + +static bool +rtl8125_is_duplex_mode_valid(u8 duplex) +{ + switch(duplex) { + case DUPLEX_FULL: + case DUPLEX_HALF: + return true; + default: + return false; + } } static void -rtl8125_link_option(u8 *aut, - u32 *spd, - u8 *dup, - u32 *adv) -{ - if ((*spd != SPEED_2500) && (*spd != SPEED_1000) && - (*spd != SPEED_100) && (*spd != SPEED_10)) - *spd = SPEED_2500; - - if ((*dup != DUPLEX_FULL) && (*dup != DUPLEX_HALF)) - *dup = DUPLEX_FULL; - - if ((*aut != AUTONEG_ENABLE) && (*aut != AUTONEG_DISABLE)) - *aut = AUTONEG_ENABLE; - - *adv &= (ADVERTISED_10baseT_Half | - ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | - ADVERTISED_100baseT_Full | - ADVERTISED_1000baseT_Half | - ADVERTISED_1000baseT_Full | - ADVERTISED_2500baseX_Full); - if (*adv == 0) - *adv = (ADVERTISED_10baseT_Half | - ADVERTISED_10baseT_Full | - ADVERTISED_100baseT_Half | - ADVERTISED_100baseT_Full | - ADVERTISED_1000baseT_Half | - ADVERTISED_1000baseT_Full | - ADVERTISED_2500baseX_Full); +rtl8125_set_link_option(struct rtl8125_private *tp, + u8 autoneg, + u32 speed, + u8 duplex, + enum rtl8125_fc_mode fc) +{ + u64 adv; + + if (!rtl8125_is_speed_mode_valid(speed)) + speed = SPEED_2500; + + if (!rtl8125_is_duplex_mode_valid(duplex)) + duplex = DUPLEX_FULL; + + if (!rtl8125_is_autoneg_mode_valid(autoneg)) + autoneg = AUTONEG_ENABLE; + + speed = min(speed, tp->HwSuppMaxPhyLinkSpeed); + + adv = 0; + switch(speed) { + case SPEED_2500: + adv |= ADVERTISED_2500baseX_Full; + fallthrough; + default: + adv |= (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | + ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full); + break; + } + + tp->autoneg = autoneg; + tp->speed = speed; + tp->duplex = duplex; + tp->advertising = adv; + tp->fcpause = fc; } /* @@ -3953,16 +5226,12 @@ rtl8125_enable_ocp_phy_power_saving(struct net_device *dev) if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { - val = mdio_direct_read_phy_ocp(tp, 0xC416); + tp->mcfg == CFG_METHOD_6) { + val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xC416); if (val != 0x0050) { rtl8125_set_phy_mcu_patch_request(tp); - mdio_direct_write_phy_ocp(tp, 0xC416, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xC416, 0x0050); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xC416, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xC416, 0x0050); rtl8125_clear_phy_mcu_patch_request(tp); } } @@ -3977,16 +5246,12 @@ rtl8125_disable_ocp_phy_power_saving(struct net_device *dev) if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { - val = mdio_direct_read_phy_ocp(tp, 0xC416); + tp->mcfg == CFG_METHOD_6) { + val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xC416); if (val != 0x0500) { rtl8125_set_phy_mcu_patch_request(tp); - mdio_direct_write_phy_ocp(tp, 0xC416, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xC416, 0x0500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xC416, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xC416, 0x0500); rtl8125_clear_phy_mcu_patch_request(tp); } } @@ -4016,6 +5281,9 @@ rtl8125_disable_pci_offset_99(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xE032, rtl8125_mac_ocp_read(tp, 0xE032) & ~(BIT_0 | BIT_1)); break; } @@ -4028,6 +5296,9 @@ rtl8125_disable_pci_offset_99(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_csi_fun0_write_byte(tp, 0x99, 0x00); break; } @@ -4046,6 +5317,9 @@ rtl8125_enable_pci_offset_99(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_csi_fun0_write_byte(tp, 0x99, tp->org_pci_offset_99); break; } @@ -4058,6 +5332,9 @@ rtl8125_enable_pci_offset_99(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE032); csi_tmp &= ~(BIT_0 | BIT_1); if (tp->org_pci_offset_99 & (BIT_5 | BIT_6)) @@ -4082,6 +5359,9 @@ rtl8125_init_pci_offset_99(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xCDD0, 0x9003); csi_tmp = rtl8125_mac_ocp_read(tp, 0xE034); csi_tmp |= (BIT_15 | BIT_14); @@ -4123,6 +5403,9 @@ rtl8125_disable_pci_offset_180(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE092); csi_tmp &= 0xFF00; rtl8125_mac_ocp_write(tp, 0xE092, csi_tmp); @@ -4143,6 +5426,9 @@ rtl8125_enable_pci_offset_180(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE094); csi_tmp &= 0x00FF; rtl8125_mac_ocp_write(tp, 0xE094, csi_tmp); @@ -4157,6 +5443,9 @@ rtl8125_enable_pci_offset_180(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: csi_tmp = rtl8125_mac_ocp_read(tp, 0xE092); csi_tmp &= 0xFF00; csi_tmp |= BIT_2; @@ -4184,6 +5473,9 @@ rtl8125_set_pci_99_180_exit_driver_para(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: if (tp->org_pci_offset_99 & BIT_2) rtl8125_issue_offset_99_event(tp); rtl8125_disable_pci_offset_99(tp); @@ -4198,6 +5490,9 @@ rtl8125_set_pci_99_180_exit_driver_para(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_disable_pci_offset_180(tp); break; } @@ -4219,14 +5514,14 @@ static void rtl8125_enable_exit_l1_mask(struct rtl8125_private *tp) { //(1)ERI(0xD4)(OCP 0xC0AC).bit[7:12]=6'b111111, L1 Mask - SetMcuAccessRegBit(tp, 0xC0AC, (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); + rtl8125_set_mac_ocp_bit(tp, 0xC0AC, (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); } static void rtl8125_disable_exit_l1_mask(struct rtl8125_private *tp) { //(1)ERI(0xD4)(OCP 0xC0AC).bit[7:12]=6'b000000, L1 Mask - ClearMcuAccessRegBit(tp, 0xC0AC, (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); + rtl8125_clear_mac_ocp_bit(tp, 0xC0AC, (BIT_7 | BIT_8 | BIT_9 | BIT_10 | BIT_11 | BIT_12)); } static void @@ -4234,7 +5529,7 @@ rtl8125_enable_extend_tally_couter(struct rtl8125_private *tp) { switch (tp->HwSuppExtendTallyCounterVer) { case 1: - SetMcuAccessRegBit(tp, 0xEA84, (BIT_1 | BIT_0)); + rtl8125_set_mac_ocp_bit(tp, 0xEA84, (BIT_1 | BIT_0)); break; } } @@ -4244,18 +5539,23 @@ rtl8125_disable_extend_tally_couter(struct rtl8125_private *tp) { switch (tp->HwSuppExtendTallyCounterVer) { case 1: - ClearMcuAccessRegBit(tp, 0xEA84, (BIT_1 | BIT_0)); + rtl8125_clear_mac_ocp_bit(tp, 0xEA84, (BIT_1 | BIT_0)); break; } } static void -rtl8125_hw_d3_para(struct net_device *dev) +rtl8125_enable_force_clkreq(struct rtl8125_private *tp, bool enable) { - struct rtl8125_private *tp = netdev_priv(dev); - - RTL_W16(tp, RxMaxSize, RX_BUF_SIZE); + if (enable) + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) | BIT_7); + else + RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); +} +static void +rtl8125_enable_aspm_clkreq_lock(struct rtl8125_private *tp, bool enable) +{ switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: @@ -4264,19 +5564,28 @@ rtl8125_hw_d3_para(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_enable_cfg9346_write(tp); - RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); - RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); + if (enable) { + RTL_W8(tp, Config2, RTL_R8(tp, Config2) | BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) | BIT_0); + } else { + RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); + RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); + } rtl8125_disable_cfg9346_write(tp); break; } +} - rtl8125_disable_exit_l1_mask(tp); +static void +rtl8125_hw_d3_para(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); -#ifdef ENABLE_REALWOW_SUPPORT - rtl8125_set_realwow_d3_para(dev); -#endif + RTL_W16(tp, RxMaxSize, RX_BUF_SIZE); switch (tp->mcfg) { case CFG_METHOD_2: @@ -4286,20 +5595,26 @@ rtl8125_hw_d3_para(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - rtl8125_mac_ocp_write(tp, 0xEA18, 0x0064); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_enable_force_clkreq(tp, 0); + rtl8125_enable_aspm_clkreq_lock(tp, 0); break; } + rtl8125_disable_exit_l1_mask(tp); + +#ifdef ENABLE_REALWOW_SUPPORT + rtl8125_set_realwow_d3_para(dev); +#endif + rtl8125_set_pci_99_180_exit_driver_para(dev); /*disable ocp phy power saving*/ if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) + tp->mcfg == CFG_METHOD_6) rtl8125_disable_ocp_phy_power_saving(dev); rtl8125_disable_rxdvgate(dev); @@ -4338,7 +5653,7 @@ rtl8125_enable_linkchg_wakeup(struct net_device *dev) switch (tp->HwSuppLinkChgWakeUpVer) { case 3: RTL_W8(tp, Config3, RTL_R8(tp, Config3) | LinkUp); - ClearAndSetMcuAccessRegBit(tp, 0xE0C6, (BIT_5 | BIT_3 | BIT_2), (BIT_4 | BIT_1 | BIT_0)); + rtl8125_clear_set_mac_ocp_bit(tp, 0xE0C6, (BIT_5 | BIT_3 | BIT_2), (BIT_4 | BIT_1 | BIT_0)); break; } } @@ -4351,7 +5666,7 @@ rtl8125_disable_linkchg_wakeup(struct net_device *dev) switch (tp->HwSuppLinkChgWakeUpVer) { case 3: RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~LinkUp); - ClearMcuAccessRegBit(tp, 0xE0C6, (BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)); + rtl8125_clear_mac_ocp_bit(tp, 0xE0C6, (BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0)); break; } } @@ -4365,7 +5680,7 @@ rtl8125_get_hw_wol(struct rtl8125_private *tp) u32 csi_tmp; u32 wol_opts = 0; - if (disable_pm_support) + if (disable_wol_support) goto out; options = RTL_R8(tp, Config1); @@ -4399,36 +5714,48 @@ rtl8125_get_hw_wol(struct rtl8125_private *tp) static void rtl8125_enable_d0_speedup(struct rtl8125_private *tp) { - if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) return; - if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_DISABLE) return; + u16 clearmask; + u16 setmask; - if (tp->HwSuppD0SpeedUpVer == 1) { - u16 mac_ocp_data; + if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) + return; - RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_3); + if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_DISABLE) + return; + if (tp->HwSuppD0SpeedUpVer == 1 || tp->HwSuppD0SpeedUpVer == 2) { //speed up speed - mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE10A); - mac_ocp_data &= ~(BIT_10 | BIT_9 | BIT_8 | BIT_7); - if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_2500) { - mac_ocp_data |= BIT_7; - } - rtl8125_mac_ocp_write(tp, 0xE10A, mac_ocp_data); + clearmask = (BIT_10 | BIT_9 | BIT_8 | BIT_7); + if (tp->D0SpeedUpSpeed == D0_SPEED_UP_SPEED_2500) + setmask = BIT_7; + else + setmask = 0; + rtl8125_clear_set_mac_ocp_bit(tp, 0xE10A, clearmask, setmask); //speed up flowcontrol - mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE860); - mac_ocp_data |= (BIT_15 | BIT_14); - rtl8125_mac_ocp_write(tp, 0xE860, mac_ocp_data); + clearmask = (BIT_15 | BIT_14); + if (tp->HwSuppD0SpeedUpVer == 2) + clearmask |= BIT_13; + + if (tp->fcpause == rtl8125_fc_full) { + setmask = (BIT_15 | BIT_14); + if (tp->HwSuppD0SpeedUpVer == 2) + setmask |= BIT_13; + } else + setmask = 0; + rtl8125_clear_set_mac_ocp_bit(tp, 0xE860, clearmask, setmask); } + + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_3); } static void rtl8125_disable_d0_speedup(struct rtl8125_private *tp) { - if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) return; + if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) + return; - if (tp->HwSuppD0SpeedUpVer == 1) - RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_7); + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~BIT_3); } static void @@ -4487,7 +5814,8 @@ rtl8125_phy_restart_nway(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (rtl8125_is_in_phy_disable_mode(dev)) return; + if (rtl8125_is_in_phy_disable_mode(dev)) + return; rtl8125_mdio_write(tp, 0x1F, 0x0000); rtl8125_mdio_write(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); @@ -4499,7 +5827,8 @@ rtl8125_phy_setup_force_mode(struct net_device *dev, u32 speed, u8 duplex) struct rtl8125_private *tp = netdev_priv(dev); u16 bmcr_true_force = 0; - if (rtl8125_is_in_phy_disable_mode(dev)) return; + if (rtl8125_is_in_phy_disable_mode(dev)) + return; if ((speed == SPEED_10) && (duplex == DUPLEX_HALF)) { bmcr_true_force = BMCR_SPEED10; @@ -4536,14 +5865,14 @@ rtl8125_set_pci_pme(struct rtl8125_private *tp, int set) pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, pmc); } -static void +static int rtl8125_set_wol_link_speed(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - int auto_nego; + int auto_nego = 0; int giga_ctrl; int ctrl_2500; - u32 adv; + u64 adv; u16 anlpar; u16 gbsr; u16 status_2500; @@ -4561,8 +5890,8 @@ rtl8125_set_wol_link_speed(struct net_device *dev) giga_ctrl = rtl8125_mdio_read(tp, MII_CTRL1000); giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); - ctrl_2500 = mdio_direct_read_phy_ocp(tp, 0xA5D4); - ctrl_2500 &= ~(RTK_ADVERTISE_2500FULL); + ctrl_2500 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5D4); + ctrl_2500 &= ~RTK_ADVERTISE_2500FULL; aner = tp->phy_reg_aner; anlpar = tp->phy_reg_anlpar; @@ -4572,7 +5901,7 @@ rtl8125_set_wol_link_speed(struct net_device *dev) aner = rtl8125_mdio_read(tp, MII_EXPANSION); anlpar = rtl8125_mdio_read(tp, MII_LPA); gbsr = rtl8125_mdio_read(tp, MII_STAT1000); - status_2500 = mdio_direct_read_phy_ocp(tp, 0xA5D6); + status_2500 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5D6); } adv = tp->advertising; @@ -4593,7 +5922,8 @@ rtl8125_set_wol_link_speed(struct net_device *dev) auto_nego |= auto_nego_tmp; goto skip_check_lpa; } - if (!(aner & EXPANSION_NWAY)) goto exit; + if (!(aner & EXPANSION_NWAY)) + goto exit; if ((adv & ADVERTISED_10baseT_Half) && (anlpar & LPA_10HALF)) auto_nego |= ADVERTISE_10HALF; @@ -4622,12 +5952,12 @@ rtl8125_set_wol_link_speed(struct net_device *dev) rtl8125_mdio_write(tp, MII_ADVERTISE, auto_nego); rtl8125_mdio_write(tp, MII_CTRL1000, giga_ctrl); - mdio_direct_write_phy_ocp(tp, 0xA5D4, ctrl_2500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA5D4, ctrl_2500); rtl8125_phy_restart_nway(dev); exit: - return; + return auto_nego; } static bool @@ -4648,19 +5978,19 @@ rtl8125_powerdown_pll(struct net_device *dev, u8 from_suspend) tp->check_keep_link_speed = 0; if (tp->wol_enabled == WOL_ENABLED || tp->DASH || tp->EnableKCPOffload) { + int auto_nego; + rtl8125_set_hw_wol(dev, tp->wol_opts); - if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_11: rtl8125_enable_cfg9346_write(tp); RTL_W8(tp, Config2, RTL_R8(tp, Config2) | PMSTS_En); rtl8125_disable_cfg9346_write(tp); - } + break; + default: + break; + }; /* Enable the PME and clear the status */ rtl8125_set_pci_pme(tp, 1); @@ -4674,7 +6004,12 @@ rtl8125_powerdown_pll(struct net_device *dev, u8 from_suspend) tp->check_keep_link_speed = 1; } - rtl8125_set_wol_link_speed(dev); + auto_nego = rtl8125_set_wol_link_speed(dev); + + if (tp->RequiredPfmPatch) + rtl8125_set_pfm_patch(tp, + (auto_nego & (ADVERTISE_10HALF | ADVERTISE_10FULL)) ? + 1 : 0); } RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); @@ -4696,6 +6031,9 @@ rtl8125_powerdown_pll(struct net_device *dev, u8 from_suspend) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~BIT_7); break; } @@ -4709,6 +6047,9 @@ rtl8125_powerdown_pll(struct net_device *dev, u8 from_suspend) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W8(tp, 0xF2, RTL_R8(tp, 0xF2) & ~BIT_6); break; } @@ -4726,11 +6067,15 @@ static void rtl8125_powerup_pll(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | BIT_7 | BIT_6); break; } - if (tp->resume_not_chg_speed) return; + if (tp->resume_not_chg_speed) + return; rtl8125_phy_power_up(dev); } @@ -4745,7 +6090,7 @@ rtl8125_get_wol(struct net_device *dev, wol->wolopts = 0; - if (tp->mcfg == CFG_METHOD_DEFAULT || disable_pm_support) { + if (tp->mcfg == CFG_METHOD_DEFAULT || disable_wol_support) { wol->supported = 0; return; } else { @@ -4765,7 +6110,7 @@ rtl8125_set_wol(struct net_device *dev, { struct rtl8125_private *tp = netdev_priv(dev); - if (tp->mcfg == CFG_METHOD_DEFAULT || disable_pm_support) + if (tp->mcfg == CFG_METHOD_DEFAULT || disable_wol_support) return -EOPNOTSUPP; tp->wol_opts = wol->wolopts; @@ -4784,14 +6129,14 @@ rtl8125_get_drvinfo(struct net_device *dev, struct rtl8125_private *tp = netdev_priv(dev); struct rtl8125_fw *rtl_fw = tp->rtl_fw; - strcpy(info->driver, MODULENAME); - strcpy(info->version, RTL8125_VERSION); - strcpy(info->bus_info, pci_name(tp->pci_dev)); + strscpy(info->driver, MODULENAME, sizeof(info->driver)); + strscpy(info->version, RTL8125_VERSION, sizeof(info->version)); + strscpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info)); info->regdump_len = R8125_REGS_DUMP_SIZE; info->eedump_len = tp->eeprom_len; BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); if (rtl_fw) - strlcpy(info->fw_version, rtl_fw->version, + strscpy(info->fw_version, rtl_fw->version, sizeof(info->fw_version)); } @@ -4805,13 +6150,14 @@ rtl8125_get_regs_len(struct net_device *dev) static void rtl8125_set_d0_speedup_speed(struct rtl8125_private *tp) { - if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) return; + if (FALSE == HW_SUPPORT_D0_SPEED_UP(tp)) + return; tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_DISABLE; if (tp->autoneg == AUTONEG_ENABLE) { if (tp->speed == SPEED_2500) tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_2500; - else if(tp->speed == SPEED_1000) + else if (tp->speed == SPEED_1000) tp->D0SpeedUpSpeed = D0_SPEED_UP_SPEED_1000; } } @@ -4830,22 +6176,19 @@ rtl8125_set_speed_xmii(struct net_device *dev, int rc = -EINVAL; //Disable Giga Lite - ClearEthPhyOcpBit(tp, 0xA428, BIT_9); - ClearEthPhyOcpBit(tp, 0xA5EA, BIT_0); - - if (speed != SPEED_5000 && - speed != SPEED_2500 && - (speed != SPEED_1000) && - (speed != SPEED_100) && - (speed != SPEED_10)) { + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_9); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA5EA, BIT_0); + + if (!rtl8125_is_speed_mode_valid(speed)) { speed = SPEED_2500; duplex = DUPLEX_FULL; + adv |= tp->advertising; } giga_ctrl = rtl8125_mdio_read(tp, MII_CTRL1000); giga_ctrl &= ~(ADVERTISE_1000HALF | ADVERTISE_1000FULL); - ctrl_2500 = mdio_direct_read_phy_ocp(tp, 0xA5D4); - ctrl_2500 &= ~(RTK_ADVERTISE_2500FULL | RTK_ADVERTISE_5000FULL); + ctrl_2500 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5D4); + ctrl_2500 &= ~RTK_ADVERTISE_2500FULL; if (autoneg == AUTONEG_ENABLE) { /*n-way force*/ @@ -4868,13 +6211,9 @@ rtl8125_set_speed_xmii(struct net_device *dev, giga_ctrl |= ADVERTISE_1000FULL; if (adv & ADVERTISED_2500baseX_Full) ctrl_2500 |= RTK_ADVERTISE_2500FULL; - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { - if (adv & RTK_ADVERTISED_5000baseX_Full) - ctrl_2500 |= RTK_ADVERTISE_5000FULL; - } //flow control - if (dev->mtu <= ETH_DATA_LEN && tp->fcpause == rtl8125_fc_full) + if (tp->fcpause == rtl8125_fc_full) auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; tp->phy_auto_nego_reg = auto_nego; @@ -4885,7 +6224,7 @@ rtl8125_set_speed_xmii(struct net_device *dev, rtl8125_mdio_write(tp, 0x1f, 0x0000); rtl8125_mdio_write(tp, MII_ADVERTISE, auto_nego); rtl8125_mdio_write(tp, MII_CTRL1000, giga_ctrl); - mdio_direct_write_phy_ocp(tp, 0xA5D4, ctrl_2500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA5D4, ctrl_2500); rtl8125_phy_restart_nway(dev); mdelay(20); } else { @@ -4918,8 +6257,9 @@ rtl8125_set_speed(struct net_device *dev, struct rtl8125_private *tp = netdev_priv(dev); int ret; - if (tp->resume_not_chg_speed) return 0; - + if (tp->resume_not_chg_speed) + return 0; + ret = tp->set_speed(dev, autoneg, speed, duplex, adv); return ret; @@ -4948,7 +6288,6 @@ rtl8125_set_settings(struct net_device *dev, supported = cmd->supported; advertising = cmd->advertising; #else - struct rtl8125_private *tp = netdev_priv(dev); const struct ethtool_link_settings *base = &cmd->base; autoneg = base->autoneg; speed = base->speed; @@ -4963,14 +6302,6 @@ rtl8125_set_settings(struct net_device *dev, if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, cmd->link_modes.advertising)) advertising |= ADVERTISED_2500baseX_Full; - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { - if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - cmd->link_modes.supported)) - supported |= RTK_ADVERTISED_5000baseX_Full; - if (test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - cmd->link_modes.advertising)) - advertising |= RTK_ADVERTISED_5000baseX_Full; - } #endif if (advertising & ~supported) return -EINVAL; @@ -5056,20 +6387,28 @@ static u32 rtl8125_rx_desc_opts1(struct rtl8125_private *tp, struct RxDesc *desc) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: return ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts1; - else + case RX_DESC_RING_TYPE_4: + return ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts1; + default: return desc->opts1; + } } static u32 rtl8125_rx_desc_opts2(struct rtl8125_private *tp, struct RxDesc *desc) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: return ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts2; - else + case RX_DESC_RING_TYPE_4: + return ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts2; + default: return desc->opts2; + } } #ifdef CONFIG_R8125_VLAN @@ -5078,10 +6417,17 @@ static void rtl8125_clear_rx_desc_opts2(struct rtl8125_private *tp, struct RxDesc *desc) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: ((struct RxDescV3 *)desc)->RxDescNormalDDWord4.opts2 = 0; - else + break; + case RX_DESC_RING_TYPE_4: + ((struct RxDescV4 *)desc)->RxDescNormalDDWord2.opts2 = 0; + break; + default: desc->opts2 = 0; + break; + } } static inline u32 @@ -5111,13 +6457,18 @@ rtl8125_vlan_rx_register(struct net_device *dev, struct rtl8125_private *tp = netdev_priv(dev); tp->vlgrp = grp; - if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { + + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: + case CFG_METHOD_6: + case CFG_METHOD_7: + case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: if (tp->vlgrp) { tp->rtl8125_rx_config |= (EnableInnerVlan | EnableOuterVlan); RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) | (EnableInnerVlan | EnableOuterVlan)) @@ -5125,6 +6476,7 @@ rtl8125_vlan_rx_register(struct net_device *dev, tp->rtl8125_rx_config &= ~(EnableInnerVlan | EnableOuterVlan); RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~(EnableInnerVlan | EnableOuterVlan)) } + break; } } @@ -5257,6 +6609,17 @@ static int rtl8125_set_features(struct net_device *dev, #endif +static u8 rtl8125_get_mdi_status(struct rtl8125_private *tp) +{ + if (!tp->link_ok(tp->dev)) + return ETH_TP_MDI_INVALID; + + if (rtl8125_mdio_direct_read_phy_ocp(tp, 0xA444) & BIT_1) + return ETH_TP_MDI; + else + return ETH_TP_MDI_X; +} + static void rtl8125_gset_xmii(struct net_device *dev, #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0) struct ethtool_cmd *cmd @@ -5270,7 +6633,7 @@ static void rtl8125_gset_xmii(struct net_device *dev, u16 anlpar = tp->phy_reg_anlpar; u16 gbsr = tp->phy_reg_gbsr; u16 status_2500 = tp->phy_reg_status_2500; - u32 lpa_adv = 0; + u64 lpa_adv = 0; u16 status; u8 autoneg, duplex; u32 speed = 0; @@ -5286,21 +6649,16 @@ static void rtl8125_gset_xmii(struct net_device *dev, SUPPORTED_2500baseX_Full | SUPPORTED_Autoneg | SUPPORTED_TP | - SUPPORTED_Pause | + SUPPORTED_Pause | SUPPORTED_Asym_Pause; if (!HW_SUPP_PHY_LINK_SPEED_2500M(tp)) supported &= ~SUPPORTED_2500baseX_Full; - advertising = ADVERTISED_TP; - - rtl8125_mdio_write(tp, 0x1F, 0x0000); - bmcr = rtl8125_mdio_read(tp, MII_BMCR); - - if (bmcr & BMCR_ANENABLE) { - advertising |= ADVERTISED_Autoneg; - autoneg = AUTONEG_ENABLE; - + advertising = tp->advertising; + if (tp->phy_auto_nego_reg || tp->phy_1000_ctrl_reg || + tp->phy_2500_ctrl_reg) { + advertising = 0; if (tp->phy_auto_nego_reg & ADVERTISE_10HALF) advertising |= ADVERTISED_10baseT_Half; if (tp->phy_auto_nego_reg & ADVERTISE_10FULL) @@ -5311,10 +6669,21 @@ static void rtl8125_gset_xmii(struct net_device *dev, advertising |= ADVERTISED_100baseT_Full; if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL) advertising |= ADVERTISED_1000baseT_Full; + if (tp->phy_2500_ctrl_reg & RTK_ADVERTISE_2500FULL) + advertising |= ADVERTISED_2500baseX_Full; + } + + rtl8125_mdio_write(tp, 0x1F, 0x0000); + bmcr = rtl8125_mdio_read(tp, MII_BMCR); + if (bmcr & BMCR_ANENABLE) { + autoneg = AUTONEG_ENABLE; + advertising |= ADVERTISED_Autoneg; } else { autoneg = AUTONEG_DISABLE; } + advertising |= ADVERTISED_TP; + status = RTL_R16(tp, PHYstatus); if (netif_running(dev) && (status & LinkStatus)) report_lpa = 1; @@ -5329,7 +6698,7 @@ static void rtl8125_gset_xmii(struct net_device *dev, if (status & RxFlowCtrl) advertising |= ADVERTISED_Pause; - duplex = ((status & (_1000bpsF | _2500bpsF | _5000bpsF)) || + duplex = ((status & (_1000bpsF | _2500bpsF)) || (status & FullDup)) ? DUPLEX_FULL : DUPLEX_HALF; @@ -5368,7 +6737,8 @@ static void rtl8125_gset_xmii(struct net_device *dev, cmd->speed = speed; cmd->duplex = duplex; cmd->port = PORT_TP; - cmd->lp_advertising = lpa_adv; + cmd->lp_advertising = (u32)lpa_adv; + cmd->eth_tp_mdix = rtl8125_get_mdi_status(tp); #else ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, supported); @@ -5389,12 +6759,6 @@ static void rtl8125_gset_xmii(struct net_device *dev, linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, cmd->link_modes.advertising, 1); } - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { - linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - cmd->link_modes.supported, 1); - linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - cmd->link_modes.advertising, tp->phy_2500_ctrl_reg & RTK_ADVERTISE_5000FULL); - } if (report_lpa) { if (lpa_adv & ADVERTISED_2500baseX_Full) { linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseX_Full_BIT, @@ -5402,18 +6766,13 @@ static void rtl8125_gset_xmii(struct net_device *dev, linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, cmd->link_modes.lp_advertising, 1); } - if (status_2500 & RTK_LPA_ADVERTISE_5000FULL) - linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - cmd->link_modes.lp_advertising, 1); - if (status_2500 & RTK_LPA_ADVERTISE_10000FULL) - linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, - cmd->link_modes.lp_advertising, 1); } #endif cmd->base.autoneg = autoneg; cmd->base.speed = speed; cmd->base.duplex = duplex; cmd->base.port = PORT_TP; + cmd->base.eth_tp_mdix = rtl8125_get_mdi_status(tp); #endif } @@ -5472,6 +6831,9 @@ static void rtl8125_get_regs(struct net_device *dev, struct ethtool_regs *regs, case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: default: for (i = 0; i < R8125_ERI_REGS_SIZE; i+=4) { *(u32*)data = rtl8125_eri_read(tp, i , 4, ERIAR_ExGMAC); @@ -5605,10 +6967,10 @@ rtl8125_set_ring_size(struct rtl8125_private *tp, u32 rx, u32 tx) { int i; - for (i = 0; i < tp->num_rx_rings; i++) + for (i = 0; i < R8125_MAX_RX_QUEUES; i++) tp->rx_ring[i].num_rx_desc = rx; - for (i = 0; i < tp->num_tx_rings; i++) + for (i = 0; i < R8125_MAX_TX_QUEUES; i++) tp->tx_ring[i].num_tx_desc = tx; } @@ -5780,6 +7142,9 @@ static int rtl_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: default: VPD_addr = 0xD2; VPD_data = 0xD4; @@ -5861,63 +7226,33 @@ static int _kc_ethtool_op_set_sg(struct net_device *dev, u32 data) } #endif -static int rtl8125_enable_eee(struct rtl8125_private *tp) +static void +rtl8125_set_eee_lpi_timer(struct rtl8125_private *tp) { - struct ethtool_eee *eee = &tp->eee; - u16 eee_adv_t = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); - int ret; + u16 dev_lpi_timer; + + dev_lpi_timer = tp->eee.tx_lpi_timer; - ret = 0; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - case CFG_METHOD_6: - RTL_W16(tp, EEE_TXIDLE_TIMER_8125, eee->tx_lpi_timer); - - SetMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); - SetMcuAccessRegBit(tp, 0xEB62, (BIT_2|BIT_1)); - - SetEthPhyOcpBit(tp, 0xA432, BIT_4); - ClearAndSetEthPhyOcpBit(tp, - 0xA5D0, - MDIO_EEE_100TX | MDIO_EEE_1000T, - eee_adv_t); - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); - - ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); - ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); - break; case CFG_METHOD_4: case CFG_METHOD_5: + case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - RTL_W16(tp, EEE_TXIDLE_TIMER_8125, eee->tx_lpi_timer); - - SetMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); - - ClearAndSetEthPhyOcpBit(tp, - 0xA5D0, - MDIO_EEE_100TX | MDIO_EEE_1000T, - eee_adv_t); - if (eee->advertised & SUPPORTED_2500baseX_Full) - SetEthPhyOcpBit(tp, 0xA6D4, BIT_0); - else - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_1); - - ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); - ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + RTL_W16(tp, EEE_TXIDLE_TIMER_8125, dev_lpi_timer); break; default: -// dev_printk(KERN_DEBUG, tp_to_dev(tp), "Not Support EEE\n"); - ret = -EOPNOTSUPP; break; } +} - /*Advanced EEE*/ +static bool rtl8125_is_adv_eee_enabled(struct rtl8125_private *tp) +{ switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: @@ -5926,19 +7261,68 @@ static int rtl8125_enable_eee(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + //case CFG_METHOD_10: + //case CFG_METHOD_11: + if (rtl8125_mdio_direct_read_phy_ocp(tp, 0xA430) & BIT_15) + return true; + break; + default: + break; + } + + return false; +} + +static void _rtl8125_disable_adv_eee(struct rtl8125_private *tp) +{ + bool lock; + + if (rtl8125_is_adv_eee_enabled(tp)) + lock = true; + else + lock = false; + + if (lock) rtl8125_set_phy_mcu_patch_request(tp); - ClearMcuAccessRegBit(tp, 0xE052, BIT_0); - ClearEthPhyOcpBit(tp, 0xA442, BIT_12 | BIT_13); - ClearEthPhyOcpBit(tp, 0xA430, BIT_15); + + rtl8125_clear_mac_ocp_bit(tp, 0xE052, BIT_0); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA442, BIT_12 | BIT_13); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA430, BIT_15); + + if (lock) rtl8125_clear_phy_mcu_patch_request(tp); +} + +static void rtl8125_disable_adv_eee(struct rtl8125_private *tp) +{ + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + case CFG_METHOD_8: + case CFG_METHOD_9: + rtl8125_oob_mutex_lock(tp); break; } - return ret; + _rtl8125_disable_adv_eee(tp); + + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + case CFG_METHOD_8: + case CFG_METHOD_9: + rtl8125_oob_mutex_unlock(tp); + break; + } } -static int rtl8125_disable_eee(struct rtl8125_private *tp) +static int rtl8125_enable_eee(struct rtl8125_private *tp) { + struct ethtool_eee *eee = &tp->eee; + u16 eee_adv_t = ethtool_adv_to_mmd_eee_adv_t(eee->advertised); int ret; ret = 0; @@ -5946,55 +7330,101 @@ static int rtl8125_disable_eee(struct rtl8125_private *tp) case CFG_METHOD_2: case CFG_METHOD_3: case CFG_METHOD_6: - ClearMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); - ClearMcuAccessRegBit(tp, 0xEB62, (BIT_2|BIT_1)); - - ClearEthPhyOcpBit(tp, 0xA432, BIT_4); - ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); - - ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); - ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); + rtl8125_set_mac_ocp_bit(tp, 0xE040, (BIT_1|BIT_0)); + rtl8125_set_mac_ocp_bit(tp, 0xEB62, (BIT_2|BIT_1)); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA432, BIT_4); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA5D0, + MDIO_EEE_100TX | MDIO_EEE_1000T, + eee_adv_t); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D4, MDIO_EEE_2_5GT); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D8, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_7); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA4A2, BIT_9); break; case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: case CFG_METHOD_8: - ClearMcuAccessRegBit(tp, 0xE040, (BIT_1|BIT_0)); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_set_mac_ocp_bit(tp, 0xE040, (BIT_1|BIT_0)); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA432, BIT_4); - ClearEthPhyOcpBit(tp, 0xA5D0, (BIT_2 | BIT_1)); - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_0); - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) - ClearEthPhyOcpBit(tp, 0xA6D4, BIT_1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA5D0, + MDIO_EEE_100TX | MDIO_EEE_1000T, + eee_adv_t); + if (eee->advertised & SUPPORTED_2500baseX_Full) + rtl8125_set_eth_phy_ocp_bit(tp, 0xA6D4, MDIO_EEE_2_5GT); + else + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D4, MDIO_EEE_2_5GT); - ClearEthPhyOcpBit(tp, 0xA6D8, BIT_4); - ClearEthPhyOcpBit(tp, 0xA428, BIT_7); - ClearEthPhyOcpBit(tp, 0xA4A2, BIT_9); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D8, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_7); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA4A2, BIT_9); break; default: -// dev_printk(KERN_DEBUG, tp_to_dev(tp), "Not Support EEE\n"); ret = -EOPNOTSUPP; break; } /*Advanced EEE*/ + rtl8125_disable_adv_eee(tp); + + return ret; +} + +static int rtl8125_disable_eee(struct rtl8125_private *tp) +{ + int ret; + + ret = 0; switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: + case CFG_METHOD_6: + rtl8125_clear_mac_ocp_bit(tp, 0xE040, (BIT_1|BIT_0)); + rtl8125_clear_mac_ocp_bit(tp, 0xEB62, (BIT_2|BIT_1)); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA432, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA5D0, (MDIO_EEE_100TX | MDIO_EEE_1000T)); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D4, BIT_0); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D8, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_7); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA4A2, BIT_9); + break; case CFG_METHOD_4: case CFG_METHOD_5: - case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - rtl8125_set_phy_mcu_patch_request(tp); - ClearMcuAccessRegBit(tp, 0xE052, BIT_0); - ClearEthPhyOcpBit(tp, 0xA442, BIT_12 | BIT_13); - ClearEthPhyOcpBit(tp, 0xA430, BIT_15); - rtl8125_clear_phy_mcu_patch_request(tp); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_clear_mac_ocp_bit(tp, 0xE040, (BIT_1|BIT_0)); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA432, BIT_4); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA5D0, (MDIO_EEE_100TX | MDIO_EEE_1000T)); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D4, MDIO_EEE_2_5GT); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA6D8, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA428, BIT_7); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA4A2, BIT_9); + break; + default: + ret = -EOPNOTSUPP; break; } + /*Advanced EEE*/ + rtl8125_disable_adv_eee(tp); + return ret; } @@ -6023,35 +7453,22 @@ static int rtl_nway_reset(struct net_device *dev) #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) static u32 -rtl8125_tx_lpi_timer_to_us(struct rtl8125_private *tp , u32 tx_lpi_timer) +rtl8125_device_lpi_t_to_ethtool_lpi_t(struct rtl8125_private *tp , u32 lpi_timer) { u32 to_us; u16 status; - to_us = tx_lpi_timer * 80; + to_us = lpi_timer * 80; status = RTL_R16(tp, PHYstatus); if (status & LinkStatus) { /*link on*/ - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) { - //5G : tx_lpi_timer * 12.8ns - //2.5G : tx_lpi_timer * 25.6ns - //Giga: tx_lpi_timer * 8ns - //100M : tx_lpi_timer * 80ns - if (status & (_5000bpsF)) - to_us = (tx_lpi_timer * 128) / 10; - else if (status & _2500bpsF) - to_us = (tx_lpi_timer * 256) / 10; - else if (status & _1000bpsF) - to_us = tx_lpi_timer * 8; - } else { - //2.5G : tx_lpi_timer * 3.2ns - //Giga: tx_lpi_timer * 8ns - //100M : tx_lpi_timer * 80ns - if (status & _2500bpsF) - to_us = (tx_lpi_timer * 32) / 10; - else if (status & _1000bpsF) - to_us = tx_lpi_timer * 8; - } + //2.5G : lpi_timer * 3.2ns + //Giga: lpi_timer * 8ns + //100M : lpi_timer * 80ns + if (status & _2500bpsF) + to_us = (lpi_timer * 32) / 10; + else if (status & _1000bpsF) + to_us = lpi_timer * 8; } //ns to us @@ -6072,26 +7489,22 @@ rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) return -EBUSY; /* Get Supported EEE */ - //val = mdio_direct_read_phy_ocp(tp, 0xA5C4); + //val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5C4); //supported = mmd_eee_cap_to_ethtool_sup_t(val); supported = eee->supported; /* Get advertisement EEE */ - val = mdio_direct_read_phy_ocp(tp, 0xA5D0); - adv = mmd_eee_adv_to_ethtool_adv_t(val); - val = mdio_direct_read_phy_ocp(tp, 0xA6D4); - if (val & RTK_EEE_ADVERTISE_2500FULL) - adv |= ADVERTISED_2500baseX_Full; + adv = eee->advertised; /* Get LP advertisement EEE */ - val = mdio_direct_read_phy_ocp(tp, 0xA5D2); + val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA5D2); lp = mmd_eee_adv_to_ethtool_adv_t(val); - val = mdio_direct_read_phy_ocp(tp, 0xA6D0); + val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA6D0); if (val & RTK_LPA_EEE_ADVERTISE_2500FULL) lp |= ADVERTISED_2500baseX_Full; /* Get EEE Tx LPI timer*/ - tx_lpi_timer = RTL_R16(tp, EEE_TXIDLE_TIMER_8125); + tx_lpi_timer = rtl8125_device_lpi_t_to_ethtool_lpi_t(tp, eee->tx_lpi_timer); val = rtl8125_mac_ocp_read(tp, 0xE040); val &= BIT_1 | BIT_0; @@ -6102,7 +7515,7 @@ rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata) edata->advertised = adv; edata->lp_advertised = lp; edata->tx_lpi_enabled = edata->eee_enabled; - edata->tx_lpi_timer = rtl8125_tx_lpi_timer_to_us(tp, tx_lpi_timer); + edata->tx_lpi_timer = tx_lpi_timer; return 0; } @@ -6112,7 +7525,7 @@ rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) { struct rtl8125_private *tp = netdev_priv(net); struct ethtool_eee *eee = &tp->eee; - u32 advertising; + u64 advertising; int rc = 0; if (!HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp) || @@ -6131,21 +7544,23 @@ rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) goto out; } + /* if (edata->tx_lpi_enabled) { - if (edata->tx_lpi_timer > tp->max_jumbo_frame_size || - edata->tx_lpi_timer < ETH_MIN_MTU) { - dev_printk(KERN_WARNING, tp_to_dev(tp), "Valid LPI timer range is %d to %d. \n", - ETH_MIN_MTU, tp->max_jumbo_frame_size); - rc = -EINVAL; - goto out; - } + if (edata->tx_lpi_timer > tp->max_jumbo_frame_size || + edata->tx_lpi_timer < ETH_MIN_MTU) { + dev_printk(KERN_WARNING, tp_to_dev(tp), "Valid LPI timer range is %d to %d. \n", + ETH_MIN_MTU, tp->max_jumbo_frame_size); + rc = -EINVAL; + goto out; + } } + */ advertising = tp->advertising; if (!edata->advertised) { edata->advertised = advertising & eee->supported; } else if (edata->advertised & ~advertising) { - dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE advertised %x must be a subset of autoneg advertised speeds %x\n", + dev_printk(KERN_WARNING, tp_to_dev(tp), "EEE advertised %x must be a subset of autoneg advertised speeds %llu\n", edata->advertised, advertising); rc = -EINVAL; goto out; @@ -6165,8 +7580,8 @@ rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) edata->tx_lpi_timer, eee->tx_lpi_timer); eee->advertised = edata->advertised; - eee->tx_lpi_enabled = edata->tx_lpi_enabled; - eee->tx_lpi_timer = edata->tx_lpi_timer; + //eee->tx_lpi_enabled = edata->tx_lpi_enabled; + //eee->tx_lpi_timer = edata->tx_lpi_timer; eee->eee_enabled = edata->eee_enabled; if (eee->eee_enabled) @@ -6184,6 +7599,19 @@ rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata) } #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) +static void rtl8125_get_channels(struct net_device *dev, + struct ethtool_channels *channel) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + channel->max_rx = tp->HwSuppNumRxQueues; + channel->max_tx = tp->HwSuppNumTxQueues; + channel->rx_count = tp->num_rx_rings; + channel->tx_count = tp->num_tx_rings; +} +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) */ + #if LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) static const struct ethtool_ops rtl8125_ethtool_ops = { .get_drvinfo = rtl8125_get_drvinfo, @@ -6254,63 +7682,14 @@ static const struct ethtool_ops rtl8125_ethtool_ops = { .get_eee = rtl_ethtool_get_eee, .set_eee = rtl_ethtool_set_eee, #endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,6,0) */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) + .get_channels = rtl8125_get_channels, +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0) */ .nway_reset = rtl_nway_reset, }; #endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,4,22) -#if 0 - -static int rtl8125_enable_green_feature(struct rtl8125_private *tp) -{ - u16 gphy_val; - - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_6: - case CFG_METHOD_7: - case CFG_METHOD_8: - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8011); - SetEthPhyOcpBit(tp, 0xA438, BIT_15); - rtl8125_mdio_write(tp, 0x00, 0x9200); - break; - default: - dev_printk(KERN_DEBUG, tp_to_dev(tp), "Not Support Green Feature\n"); - break; - } - - return 0; -} - -static int rtl8125_disable_green_feature(struct rtl8125_private *tp) -{ - u16 gphy_val; - - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_6: - case CFG_METHOD_7: - case CFG_METHOD_8: - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8011); - ClearEthPhyOcpBit(tp, 0xA438, BIT_15); - rtl8125_mdio_write(tp, 0x00, 0x9200); - break; - default: - dev_printk(KERN_DEBUG, tp_to_dev(tp), "Not Support Green Feature\n"); - break; - } - - return 0; -} - -#endif - static void rtl8125_get_mac_version(struct rtl8125_private *tp) { u32 reg,val32; @@ -6346,8 +7725,27 @@ static void rtl8125_get_mac_version(struct rtl8125_private *tp) tp->efuse_ver = EFUSE_SUPPORT_V4; break; - case 0x64800000: - tp->mcfg = CFG_METHOD_8; + case 0x68000000: + if (ICVerID == 0x00000000) { + tp->mcfg = CFG_METHOD_8; + } else if (ICVerID == 0x100000) { + tp->mcfg = CFG_METHOD_9; + } else { + tp->mcfg = CFG_METHOD_9; + tp->HwIcVerUnknown = TRUE; + } + + tp->efuse_ver = EFUSE_SUPPORT_V4; + break; + case 0x68800000: + if (ICVerID == 0x00000000) { + tp->mcfg = CFG_METHOD_10; + } else if (ICVerID == 0x100000) { + tp->mcfg = CFG_METHOD_11; + } else { + tp->mcfg = CFG_METHOD_11; + tp->HwIcVerUnknown = TRUE; + } tp->efuse_ver = EFUSE_SUPPORT_V4; break; @@ -6359,7 +7757,7 @@ static void rtl8125_get_mac_version(struct rtl8125_private *tp) break; } - if (pdev->subsystem_vendor == 0x8162) { + if (pdev->device == 0x8162) { if (tp->mcfg == CFG_METHOD_3) tp->mcfg = CFG_METHOD_6; else if (tp->mcfg == CFG_METHOD_5) @@ -6373,8 +7771,8 @@ rtl8125_print_mac_version(struct rtl8125_private *tp) int i; for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) { if (tp->mcfg == rtl_chip_info[i].mcfg) { - dprintk("Realtek PCIe 2.5GbE Family Controller mcfg = %04d\n", - rtl_chip_info[i].mcfg); + dprintk("Realtek %s Ethernet controller mcfg = %04d\n", + MODULENAME, rtl_chip_info[i].mcfg); return; } } @@ -6412,10 +7810,13 @@ rtl8125_clear_phy_ups_reg(struct net_device *dev) case CFG_METHOD_5: case CFG_METHOD_7: case CFG_METHOD_8: - ClearEthPhyOcpBit(tp, 0xA466, BIT_0); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA466, BIT_0); break; }; - ClearEthPhyOcpBit(tp, 0xA468, BIT_3 | BIT_1); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA468, BIT_3 | BIT_1); } static int @@ -6423,16 +7824,12 @@ rtl8125_is_ups_resume(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_11: return (rtl8125_mac_ocp_read(tp, 0xD42C) & BIT_8); - - return 0; + default: + return 0; + }; } static void @@ -6440,56 +7837,62 @@ rtl8125_clear_ups_resume_bit(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7) - rtl8125_mac_ocp_write(tp, 0xD408, rtl8125_mac_ocp_read(tp, 0xD408) & ~(BIT_8)); + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_11: + rtl8125_clear_mac_ocp_bit(tp, 0xD42C, BIT_8); + break; + default: + return; + }; +} + +static u8 +rtl8125_get_phy_state(struct rtl8125_private *tp) +{ + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_11: + return (rtl8125_mdio_direct_read_phy_ocp(tp, 0xA420) & 0x7); + default: + return 0xff; + }; } static void rtl8125_wait_phy_ups_resume(struct net_device *dev, u16 PhyState) { struct rtl8125_private *tp = netdev_priv(dev); - u16 TmpPhyState; - int i=0; + int i; - if (tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { - do { - TmpPhyState = mdio_direct_read_phy_ocp(tp, 0xA420); - TmpPhyState &= 0x7; - mdelay(1); - i++; - } while ((i < 100) && (TmpPhyState != PhyState)); - } + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_11: + for (i=0; i< 100; i++) { + if (rtl8125_get_phy_state(tp) == PhyState) + break; + else + mdelay(1); + } #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,18) - WARN_ON_ONCE(i == 100); + WARN_ON_ONCE(i == 100); #endif + break; + default: + break; + }; } void rtl8125_enable_now_is_oob(struct rtl8125_private *tp) { - if ( tp->HwSuppNowIsOobVer == 1 ) { + if (tp->HwSuppNowIsOobVer == 1) RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) | Now_is_oob); - } } void rtl8125_disable_now_is_oob(struct rtl8125_private *tp) { - if ( tp->HwSuppNowIsOobVer == 1 ) { + if (tp->HwSuppNowIsOobVer == 1) RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) & ~Now_is_oob); - } } static void @@ -6520,6 +7923,9 @@ rtl8125_exit_oob(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xC0BC, 0x00FF); break; } @@ -6535,6 +7941,9 @@ rtl8125_exit_oob(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_disable_now_is_oob(tp); data16 = rtl8125_mac_ocp_read(tp, 0xE8DE) & ~BIT_14; @@ -6542,7 +7951,11 @@ rtl8125_exit_oob(struct net_device *dev) rtl8125_wait_ll_share_fifo_ready(dev); rtl8125_mac_ocp_write(tp, 0xC0AA, 0x07D0); +#ifdef ENABLE_LIB_SUPPORT + rtl8125_mac_ocp_write(tp, 0xC0A6, 0x04E2); +#else rtl8125_mac_ocp_write(tp, 0xC0A6, 0x01B5); +#endif rtl8125_mac_ocp_write(tp, 0xC01E, 0x5555); rtl8125_wait_ll_share_fifo_ready(dev); @@ -6558,6 +7971,9 @@ rtl8125_exit_oob(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: if (rtl8125_is_ups_resume(dev)) { rtl8125_wait_phy_ups_resume(dev, 2); rtl8125_clear_ups_resume_bit(dev); @@ -6582,10 +7998,10 @@ rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - rtl8125_enable_cfg9346_write(tp); - RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); - RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); - rtl8125_disable_cfg9346_write(tp); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_enable_aspm_clkreq_lock(tp, 0); break; } @@ -6597,6 +8013,9 @@ rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xFC48, 0x0000); break; } @@ -6609,6 +8028,9 @@ rtl8125_hw_disable_mac_mcu_bps(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: for (regAddr = 0xFC28; regAddr < 0xFC48; regAddr += 2) { rtl8125_mac_ocp_write(tp, regAddr, 0x0000); } @@ -6638,9 +8060,8 @@ _rtl8125_write_mac_mcu_ram_code(struct rtl8125_private *tp, const u16 *entry, u1 { u16 i; - for (i = 0; i < entry_cnt; i++) { + for (i = 0; i < entry_cnt; i++) rtl8125_mac_ocp_write(tp, 0xF800 + i * 2, entry[i]); - } } static void @@ -6649,7 +8070,8 @@ _rtl8125_write_mac_mcu_ram_code_with_page(struct rtl8125_private *tp, const u16 u16 i; u16 offset; - if (page_size == 0) return; + if (page_size == 0) + return; for (i = 0; i < entry_cnt; i++) { offset = i % page_size; @@ -6664,8 +8086,11 @@ _rtl8125_write_mac_mcu_ram_code_with_page(struct rtl8125_private *tp, const u16 static void rtl8125_write_mac_mcu_ram_code(struct rtl8125_private *tp, const u16 *entry, u16 entry_cnt) { - if (FALSE == HW_SUPPORT_MAC_MCU(tp)) return; - if (entry == NULL || entry_cnt == 0) return; + if (FALSE == HW_SUPPORT_MAC_MCU(tp)) + return; + + if (entry == NULL || entry_cnt == 0) + return; if (tp->MacMcuPageSize > 0) _rtl8125_write_mac_mcu_ram_code_with_page(tp, entry, entry_cnt, tp->MacMcuPageSize); @@ -6683,7 +8108,7 @@ static void rtl8125_set_mac_mcu_8125a_2(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - static const u16 mcu_patch_code_8125a_2[] = { + static const u16 mcu_patch_code_8125a_2[] = { 0xE010, 0xE012, 0xE022, 0xE024, 0xE029, 0xE02B, 0xE094, 0xE09D, 0xE09F, 0xE0AA, 0xE0B5, 0xE0C6, 0xE0CC, 0xE0D1, 0xE0D6, 0xE0D8, 0xC602, 0xBE00, 0x0000, 0xC60F, 0x73C4, 0x49B3, 0xF106, 0x73C2, 0xC608, 0xB406, 0xC609, @@ -6768,96 +8193,363 @@ rtl8125_set_mac_mcu_8125a_2(struct net_device *dev) 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6486, - 0x0B15, 0x090E, 0x1139 - }; - - rtl8125_hw_disable_mac_mcu_bps(dev); - - rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125a_2, ARRAY_SIZE(mcu_patch_code_8125a_2)); - - rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); - - rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0540); - rtl8125_mac_ocp_write(tp, 0xFC2E, 0x0A06); - rtl8125_mac_ocp_write(tp, 0xFC30, 0x0EB8); - rtl8125_mac_ocp_write(tp, 0xFC32, 0x3A5C); - rtl8125_mac_ocp_write(tp, 0xFC34, 0x10A8); - rtl8125_mac_ocp_write(tp, 0xFC40, 0x0D54); - rtl8125_mac_ocp_write(tp, 0xFC42, 0x0E24); - - rtl8125_mac_ocp_write(tp, 0xFC48, 0x307A); -} - -static void -rtl8125_set_mac_mcu_8125b_1(struct net_device *dev) -{ - rtl8125_hw_disable_mac_mcu_bps(dev); -} - -static void -rtl8125_set_mac_mcu_8125b_2(struct net_device *dev) -{ - struct rtl8125_private *tp = netdev_priv(dev); - static const u16 mcu_patch_code_8125b_2[] = { - 0xE010, 0xE01B, 0xE026, 0xE037, 0xE03D, 0xE057, 0xE05B, 0xE060, 0xE062, - 0xE064, 0xE066, 0xE068, 0xE06A, 0xE06C, 0xE06E, 0xE070, 0x740A, 0x4846, - 0x4847, 0x9C0A, 0xC607, 0x74C0, 0x48C6, 0x9CC0, 0xC602, 0xBE00, 0x13F0, - 0xE054, 0x72CA, 0x4826, 0x4827, 0x9ACA, 0xC607, 0x72C0, 0x48A6, 0x9AC0, - 0xC602, 0xBE00, 0x081C, 0xE054, 0xC60F, 0x74C4, 0x49CC, 0xF109, 0xC60C, - 0x74CA, 0x48C7, 0x9CCA, 0xC609, 0x74C0, 0x4846, 0x9CC0, 0xC602, 0xBE00, - 0x2494, 0xE092, 0xE0C0, 0xE054, 0x7420, 0x48C0, 0x9C20, 0x7444, 0xC602, - 0xBE00, 0x12DC, 0x733A, 0x21B5, 0x25BC, 0x1304, 0xF111, 0x1B12, 0x1D2A, - 0x3168, 0x3ADA, 0x31AB, 0x1A00, 0x9AC0, 0x1300, 0xF1FB, 0x7620, 0x236E, - 0x276F, 0x1A3C, 0x22A1, 0x41B5, 0x9EE2, 0x76E4, 0x486F, 0x9EE4, 0xC602, - 0xBE00, 0x4A26, 0x733A, 0x49BB, 0xC602, 0xBE00, 0x47A2, 0x48C1, 0x48C2, - 0x9C46, 0xC402, 0xBC00, 0x0A52, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, - 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, - 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, - 0x0000, 0xC602, 0xBE00, 0x0000 + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6486, + 0x0B15, 0x090E, 0x1139 + }; + + rtl8125_hw_disable_mac_mcu_bps(dev); + + rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125a_2, ARRAY_SIZE(mcu_patch_code_8125a_2)); + + rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0540); + rtl8125_mac_ocp_write(tp, 0xFC2E, 0x0A06); + rtl8125_mac_ocp_write(tp, 0xFC30, 0x0EB8); + rtl8125_mac_ocp_write(tp, 0xFC32, 0x3A5C); + rtl8125_mac_ocp_write(tp, 0xFC34, 0x10A8); + rtl8125_mac_ocp_write(tp, 0xFC40, 0x0D54); + rtl8125_mac_ocp_write(tp, 0xFC42, 0x0E24); + + rtl8125_mac_ocp_write(tp, 0xFC48, 0x307A); +} + +static void +rtl8125_set_mac_mcu_8125b_1(struct net_device *dev) +{ + rtl8125_hw_disable_mac_mcu_bps(dev); +} + +static void +rtl8125_set_mac_mcu_8125b_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + static const u16 mcu_patch_code_8125b_2[] = { + 0xE010, 0xE01B, 0xE026, 0xE037, 0xE03D, 0xE057, 0xE05B, 0xE060, 0xE062, + 0xE064, 0xE066, 0xE068, 0xE06A, 0xE06C, 0xE06E, 0xE070, 0x740A, 0x4846, + 0x4847, 0x9C0A, 0xC607, 0x74C0, 0x48C6, 0x9CC0, 0xC602, 0xBE00, 0x13F0, + 0xE054, 0x72CA, 0x4826, 0x4827, 0x9ACA, 0xC607, 0x72C0, 0x48A6, 0x9AC0, + 0xC602, 0xBE00, 0x081C, 0xE054, 0xC60F, 0x74C4, 0x49CC, 0xF109, 0xC60C, + 0x74CA, 0x48C7, 0x9CCA, 0xC609, 0x74C0, 0x4846, 0x9CC0, 0xC602, 0xBE00, + 0x2494, 0xE092, 0xE0C0, 0xE054, 0x7420, 0x48C0, 0x9C20, 0x7444, 0xC602, + 0xBE00, 0x12DC, 0x733A, 0x21B5, 0x25BC, 0x1304, 0xF111, 0x1B12, 0x1D2A, + 0x3168, 0x3ADA, 0x31AB, 0x1A00, 0x9AC0, 0x1300, 0xF1FB, 0x7620, 0x236E, + 0x276F, 0x1A3C, 0x22A1, 0x41B5, 0x9EE2, 0x76E4, 0x486F, 0x9EE4, 0xC602, + 0xBE00, 0x4A26, 0x733A, 0x49BB, 0xC602, 0xBE00, 0x47A2, 0x48C1, 0x48C2, + 0x9C46, 0xC402, 0xBC00, 0x0A52, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, + 0x0000, 0xC602, 0xBE00, 0x0000 + }; + + rtl8125_hw_disable_mac_mcu_bps(dev); + + rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125b_2, ARRAY_SIZE(mcu_patch_code_8125b_2)); + + rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8125_mac_ocp_write(tp, 0xFC28, 0x13E6); + rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0812); + rtl8125_mac_ocp_write(tp, 0xFC2C, 0x248C); + rtl8125_mac_ocp_write(tp, 0xFC2E, 0x12DA); + rtl8125_mac_ocp_write(tp, 0xFC30, 0x4A20); + rtl8125_mac_ocp_write(tp, 0xFC32, 0x47A0); + //rtl8125_mac_ocp_write(tp, 0xFC34, 0x0A46); + + rtl8125_mac_ocp_write(tp, 0xFC48, 0x003F); +} + +static void +rtl8125_set_mac_mcu_8125bp_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + static const u16 mcu_patch_code_8125bp_1[] = { + 0xE003, 0xE007, 0xE01A, 0x1BC8, 0x46EB, 0xC302, 0xBB00, 0x0F14, 0xC211, + 0x400A, 0xF00A, 0xC20F, 0x400A, 0xF007, 0x73A4, 0xC20C, 0x400A, 0xF102, + 0x48B0, 0x9B20, 0x1B00, 0x9BA0, 0xC602, 0xBE00, 0x4364, 0xE6E0, 0xE6E2, + 0xC01C, 0xB406, 0x1000, 0xF016, 0xC61F, 0x400E, 0xF012, 0x218E, 0x25BE, + 0x1300, 0xF007, 0x7340, 0xC618, 0x400E, 0xF102, 0x48B0, 0x8320, 0xB400, + 0x2402, 0x1000, 0xF003, 0x7342, 0x8322, 0xB000, 0xE007, 0x7322, 0x9B42, + 0x7320, 0x9B40, 0x0300, 0x0300, 0xB006, 0xC302, 0xBB00, 0x413E, 0xE6E0, + 0xC01C, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x1171, 0x0B17, 0x0816, 0x1108 + }; + + rtl8125_hw_disable_mac_mcu_bps(dev); + + rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125bp_1, ARRAY_SIZE(mcu_patch_code_8125bp_1)); + + rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8125_mac_ocp_write(tp, 0xFC28, 0x0f10); + rtl8125_mac_ocp_write(tp, 0xFC2A, 0x435c); + rtl8125_mac_ocp_write(tp, 0xFC2C, 0x4112); + + rtl8125_mac_ocp_write(tp, 0xFC48, 0x0007); +} + +static void +rtl8125_set_mac_mcu_8125bp_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + static const u16 mcu_patch_code_8125bp_2[] = { + 0xE010, 0xE033, 0xE046, 0xE04A, 0xE04C, 0xE04E, 0xE050, 0xE052, 0xE054, + 0xE056, 0xE058, 0xE05A, 0xE05C, 0xE05E, 0xE060, 0xE062, 0xB406, 0x1000, + 0xF016, 0xC61F, 0x400E, 0xF012, 0x218E, 0x25BE, 0x1300, 0xF007, 0x7340, + 0xC618, 0x400E, 0xF102, 0x48B0, 0x8320, 0xB400, 0x2402, 0x1000, 0xF003, + 0x7342, 0x8322, 0xB000, 0xE007, 0x7322, 0x9B42, 0x7320, 0x9B40, 0x0300, + 0x0300, 0xB006, 0xC302, 0xBB00, 0x4168, 0xE6E0, 0xC01C, 0xC211, 0x400A, + 0xF00A, 0xC20F, 0x400A, 0xF007, 0x73A4, 0xC20C, 0x400A, 0xF102, 0x48B0, + 0x9B20, 0x1B00, 0x9BA0, 0xC602, 0xBE00, 0x4392, 0xE6E0, 0xE6E2, 0xC01C, + 0x4166, 0x9CF6, 0xC002, 0xB800, 0x143C, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC102, + 0xB900, 0x0000, 0xC002, 0xB800, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, + 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1171, + 0x0B18, 0x030D, 0x0A2A + }; + + rtl8125_hw_disable_mac_mcu_bps(dev); + + rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125bp_2, ARRAY_SIZE(mcu_patch_code_8125bp_2)); + + rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); + + rtl8125_mac_ocp_write(tp, 0xFC28, 0x413C); + rtl8125_mac_ocp_write(tp, 0xFC2A, 0x438A); + rtl8125_mac_ocp_write(tp, 0xFC2C, 0x143A); + + rtl8125_mac_ocp_write(tp, 0xFC48, 0x0007); +} + +static void +rtl8125_set_mac_mcu_8125d_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + static const u16 mcu_patch_code_8125d_1[] = { + 0xE002, 0xE006, 0x4166, 0x9CF6, 0xC002, 0xB800, 0x14A4, 0xC102, 0xB900, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x6938, + 0x0A18, 0x0217, 0x0D2A }; rtl8125_hw_disable_mac_mcu_bps(dev); - rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125b_2, ARRAY_SIZE(mcu_patch_code_8125b_2)); + rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8125d_1, ARRAY_SIZE(mcu_patch_code_8125d_1)); rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); - rtl8125_mac_ocp_write(tp, 0xFC28, 0x13E6); - rtl8125_mac_ocp_write(tp, 0xFC2A, 0x0812); - rtl8125_mac_ocp_write(tp, 0xFC2C, 0x248C); - rtl8125_mac_ocp_write(tp, 0xFC2E, 0x12DA); - rtl8125_mac_ocp_write(tp, 0xFC30, 0x4A20); - rtl8125_mac_ocp_write(tp, 0xFC32, 0x47A0); - //rtl8125_mac_ocp_write(tp, 0xFC34, 0x0A46); + rtl8125_mac_ocp_write(tp, 0xFC28, 0x14A2); - rtl8125_mac_ocp_write(tp, 0xFC48, 0x003F); + rtl8125_mac_ocp_write(tp, 0xFC48, 0x0001); } static void -rtl8125_set_mac_mcu_8126a_1(struct net_device *dev) +rtl8125_set_mac_mcu_8125d_2(struct net_device *dev) { - struct rtl8125_private *tp = netdev_priv(dev); - static const u16 mcu_patch_code_8126a_1[] = { - 0xE010, 0xE019, 0xE01B, 0xE01D, 0xE01F, 0xE021, 0xE023, 0xE025, 0xE027, - 0xE029, 0xE02B, 0xE02D, 0xE02F, 0xE031, 0xE033, 0xE035, 0x48C0, 0x9C66, - 0x7446, 0x4840, 0x48C1, 0x48C2, 0x9C46, 0xC402, 0xBC00, 0x0AD6, 0xC602, - 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, - 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, - 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, - 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, - 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000, 0xC602, 0xBE00, 0x0000 - }; - rtl8125_hw_disable_mac_mcu_bps(dev); - - rtl8125_write_mac_mcu_ram_code(tp, mcu_patch_code_8126a_1, ARRAY_SIZE(mcu_patch_code_8126a_1)); - - rtl8125_mac_ocp_write(tp, 0xFC26, 0x8000); - - rtl8125_mac_ocp_write(tp, 0xFC28, 0x0AAA); - - rtl8125_mac_ocp_write(tp, 0xFC48, 0x0001); } static void @@ -6865,7 +8557,8 @@ rtl8125_hw_mac_mcu_config(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (tp->NotWrMcuPatchCode == TRUE) return; + if (tp->NotWrMcuPatchCode == TRUE) + return; switch (tp->mcfg) { case CFG_METHOD_2: @@ -6883,7 +8576,16 @@ rtl8125_hw_mac_mcu_config(struct net_device *dev) rtl8125_set_mac_mcu_8125b_2(dev); break; case CFG_METHOD_8: - rtl8125_set_mac_mcu_8126a_1(dev); + rtl8125_set_mac_mcu_8125bp_1(dev); + break; + case CFG_METHOD_9: + rtl8125_set_mac_mcu_8125bp_2(dev); + break; + case CFG_METHOD_10: + rtl8125_set_mac_mcu_8125d_1(dev); + break; + case CFG_METHOD_11: + rtl8125_set_mac_mcu_8125d_2(dev); break; } } @@ -6899,7 +8601,7 @@ static void rtl8125_release_firmware(struct rtl8125_private *tp) } } -void rtl8125_apply_firmware(struct rtl8125_private *tp) +static void rtl8125_apply_firmware(struct rtl8125_private *tp) { /* TODO: release firmware if rtl_fw_write_firmware signals failure. */ if (tp->rtl_fw) { @@ -6934,11 +8636,11 @@ rtl8125_hw_init(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - rtl8125_enable_cfg9346_write(tp); - RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); - RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); - rtl8125_disable_cfg9346_write(tp); - RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_enable_aspm_clkreq_lock(tp, 0); + rtl8125_enable_force_clkreq(tp, 0); break; } @@ -6951,7 +8653,10 @@ rtl8125_hw_init(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - rtl8125_mac_ocp_write(tp, 0xD40A, rtl8125_mac_ocp_read( tp, 0xD40A) & ~(BIT_4)); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_mac_ocp_write(tp, 0xD40A, rtl8125_mac_ocp_read(tp, 0xD40A) & ~(BIT_4)); break; } @@ -6963,11 +8668,7 @@ rtl8125_hw_init(struct net_device *dev) /*disable ocp phy power saving*/ if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) + tp->mcfg == CFG_METHOD_6) rtl8125_disable_ocp_phy_power_saving(dev); //Set PCIE uncorrectable error status mask pcie 0x108 @@ -7045,8 +8746,7 @@ rtl8125_hw_ephy_config(struct net_device *dev) ClearAndSetPCIePhyBit(tp, 0x2A, (BIT_14 | BIT_13 | BIT_12), - (BIT_13 | BIT_12) - ); + (BIT_13 | BIT_12)); ClearPCIePhyBit(tp, 0x19, BIT_6); SetPCIePhyBit(tp, 0x1B, (BIT_11 | BIT_10 | BIT_9)); ClearPCIePhyBit(tp, 0x1B, (BIT_14 | BIT_13 | BIT_12)); @@ -7056,8 +8756,7 @@ rtl8125_hw_ephy_config(struct net_device *dev) ClearAndSetPCIePhyBit(tp, 0x6A, (BIT_14 | BIT_13 | BIT_12), - (BIT_13 | BIT_12) - ); + (BIT_13 | BIT_12)); ClearPCIePhyBit(tp, 0x59, BIT_6); SetPCIePhyBit(tp, 0x5B, (BIT_11 | BIT_10 | BIT_9)); ClearPCIePhyBit(tp, 0x5B, (BIT_14 | BIT_13 | BIT_12)); @@ -7108,6 +8807,10 @@ rtl8125_hw_ephy_config(struct net_device *dev) rtl8125_ephy_write(tp, 0x69, 0xFF00); break; case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + /* nothing to do */ break; } } @@ -7125,8 +8828,11 @@ rtl8125_get_hw_phy_mcu_code_ver(struct rtl8125_private *tp) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); - hw_ram_code_ver = mdio_direct_read_phy_ocp(tp, 0xA438); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); + hw_ram_code_ver = rtl8125_mdio_direct_read_phy_ocp(tp, 0xA438); break; } @@ -7137,16 +8843,16 @@ static int rtl8125_check_hw_phy_mcu_code_ver(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - int ram_code_ver_match = 0; tp->hw_ram_code_ver = rtl8125_get_hw_phy_mcu_code_ver(tp); if (tp->hw_ram_code_ver == tp->sw_ram_code_ver) { - ram_code_ver_match = 1; tp->HwHasWrRamCodeToMicroP = TRUE; + return 1; + } else { + tp->HwHasWrRamCodeToMicroP = FALSE; + return 0; } - - return ram_code_ver_match; } bool @@ -7156,16 +8862,17 @@ rtl8125_set_phy_mcu_patch_request(struct rtl8125_private *tp) u16 WaitCount; bool bSuccess = TRUE; - SetEthPhyOcpBit(tp, 0xB820, BIT_4); + rtl8125_set_eth_phy_ocp_bit(tp, 0xB820, BIT_4); WaitCount = 0; do { - gphy_val = mdio_direct_read_phy_ocp(tp, 0xB800); + gphy_val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xB800); udelay(100); WaitCount++; } while (!(gphy_val & BIT_6) && (WaitCount < 1000)); - if (!(gphy_val & BIT_6) && (WaitCount == 1000)) bSuccess = FALSE; + if (!(gphy_val & BIT_6) && (WaitCount == 1000)) + bSuccess = FALSE; if (!bSuccess) dprintk("rtl8125_set_phy_mcu_patch_request fail.\n"); @@ -7180,16 +8887,17 @@ rtl8125_clear_phy_mcu_patch_request(struct rtl8125_private *tp) u16 WaitCount; bool bSuccess = TRUE; - ClearEthPhyOcpBit(tp, 0xB820, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB820, BIT_4); WaitCount = 0; do { - gphy_val = mdio_direct_read_phy_ocp(tp, 0xB800); + gphy_val = rtl8125_mdio_direct_read_phy_ocp(tp, 0xB800); udelay(100); WaitCount++; } while ((gphy_val & BIT_6) && (WaitCount < 1000)); - if ((gphy_val & BIT_6) && (WaitCount == 1000)) bSuccess = FALSE; + if ((gphy_val & BIT_6) && (WaitCount == 1000)) + bSuccess = FALSE; if (!bSuccess) dprintk("rtl8125_clear_phy_mcu_patch_request fail.\n"); @@ -7211,8 +8919,11 @@ rtl8125_write_hw_phy_mcu_code_ver(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); - mdio_direct_write_phy_ocp(tp, 0xA438, tp->sw_ram_code_ver); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x801E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, tp->sw_ram_code_ver); tp->hw_ram_code_ver = tp->sw_ram_code_ver; break; } @@ -7241,10 +8952,10 @@ rtl8125_acquire_phy_mcu_patch_key_lock(struct rtl8125_private *tp) default: return; } - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8024); - mdio_direct_write_phy_ocp(tp, 0xA438, PatchKey); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xB82E); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0001); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, PatchKey); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xB82E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0001); } static void @@ -7257,11 +8968,11 @@ rtl8125_release_phy_mcu_patch_key_lock(struct rtl8125_private *tp) case CFG_METHOD_5: case CFG_METHOD_6: case CFG_METHOD_7: - mdio_direct_write_phy_ocp(tp, 0xA436, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - ClearEthPhyOcpBit(tp, 0xB82E, BIT_0); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8024); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB82E, BIT_0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); break; default: break; @@ -7286,7 +8997,7 @@ rtl8125_set_phy_mcu_ram_code(struct net_device *dev, const u16 *ramcode, u16 cod if (addr == 0xFFFF && val == 0xFFFF) { break; } - mdio_direct_write_phy_ocp(tp, addr, val); + rtl8125_mdio_direct_write_phy_ocp(tp, addr, val); } out: @@ -7331,27 +9042,27 @@ rtl8125_set_hw_phy_before_init_phy_mcu(struct net_device *dev) switch (tp->mcfg) { case CFG_METHOD_4: - mdio_direct_write_phy_ocp(tp, 0xBF86, 0x9000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBF86, 0x9000); - SetEthPhyOcpBit(tp, 0xC402, BIT_10); - ClearEthPhyOcpBit(tp, 0xC402, BIT_10); + rtl8125_set_eth_phy_ocp_bit(tp, 0xC402, BIT_10); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xC402, BIT_10); - PhyRegValue = mdio_direct_read_phy_ocp(tp, 0xBF86); + PhyRegValue = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBF86); PhyRegValue &= (BIT_1 | BIT_0); if (PhyRegValue != 0) dprintk("PHY watch dog not clear, value = 0x%x \n", PhyRegValue); - mdio_direct_write_phy_ocp(tp, 0xBD86, 0x1010); - mdio_direct_write_phy_ocp(tp, 0xBD88, 0x1010); - - ClearAndSetEthPhyOcpBit(tp, - 0xBD4E, - BIT_11 | BIT_10, - BIT_11); - ClearAndSetEthPhyOcpBit(tp, - 0xBF46, - BIT_11 | BIT_10 | BIT_9 | BIT_8, - BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBD86, 0x1010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBD88, 0x1010); + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBD4E, + BIT_11 | BIT_10, + BIT_11); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBF46, + BIT_11 | BIT_10 | BIT_9 | BIT_8, + BIT_10 | BIT_9 | BIT_8); break; } } @@ -7364,826 +9075,826 @@ rtl8125_real_set_phy_mcu_8125a_1(struct net_device *dev) rtl8125_acquire_phy_mcu_patch_key_lock(tp); - SetEthPhyOcpBit(tp, 0xB820, BIT_7); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8013); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8021); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x802f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x803d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8042); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8051); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8051); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa088); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a50); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8008); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1a3); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x401a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd707); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40c2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f8b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a6c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8080); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd019); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1a2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x401a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd707); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40c4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f8b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a84); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8970); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c07); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0901); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcf09); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd705); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xceff); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf0a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1213); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8401); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8580); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1253); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd064); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd181); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4018); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc50f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd706); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2c59); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x804d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc60f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc605); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x10fd); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA026); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA024); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA022); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x10f4); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA020); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1252); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA006); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1206); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA004); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a78); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a60); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a4f); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA008); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3f00); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0010); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8066); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x807c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8089); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x808e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80b2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80c2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x62db); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x655c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0505); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0509); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x653c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0502); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0506); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x050a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0505); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0506); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x050c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0509); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x050a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x050c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0508); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0502); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0508); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0346); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8208); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x609d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x001a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x001a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x607d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ab); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60fd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaa0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x017b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a05); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x017b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60fd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaa0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x01e0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a05); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x01e0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60fd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaa0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0231); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a05); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0231); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08E); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08C); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0221); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08A); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x01ce); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA088); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0169); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA086); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00a6); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA084); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x000d); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA082); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0308); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA080); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x029f); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA090); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x007f); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0020); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8017); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8029); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8054); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x805a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8064); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80a7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9430); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9480); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb408); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd120); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd057); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb80); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9906); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0567); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb94); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8406); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8dff); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa840); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0773); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb91); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd139); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd140); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07dc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa110); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa2a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4045); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa180); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07ec); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f74); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07dc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07c0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fa7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0481); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x94bc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x870c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa00a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa280); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8220); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x078e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb92); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa840); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd140); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd150); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd703); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6121); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x61a2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6223); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d10); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d20); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d30); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf005); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d40); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa008); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4046); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07f7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f74); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3ad4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0537); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8840); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8301); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa70c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9402); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x890c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8840); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10E); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0642); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10C); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0686); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10A); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0788); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA108); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x047b); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA106); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x065c); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA104); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0769); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA102); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0565); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA100); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x06f9); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA110); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ff); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8530); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3caf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8593); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9caf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x85a5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5afb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe083); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfb0c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x020d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x021b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x10bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86d7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbe0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x83fc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1b10); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xda02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xdd02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5afb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe083); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfd0c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x020d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x021b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x10bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86dd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbe0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x83fe); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1b10); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf2f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2cac); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0286); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x65af); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x212b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x022c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86b6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf21); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cd1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x03bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8710); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x870d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8719); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8716); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x871f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x871c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8728); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8725); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8707); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbad); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x281c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd100); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1302); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2202); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2b02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae1a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd101); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1302); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2202); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2b02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd101); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3402); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3102); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3d02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3a02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4302); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4c02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4902); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd100); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2e02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4602); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4f02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf35); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7ff8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfaef); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x69bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e3); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86fb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86fe); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86ec); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86ef); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86f2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86f5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cbf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x86f8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cef); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x96fe); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfc04); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf8fa); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xef69); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xef02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf202); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf502); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf802); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xef96); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfefc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0420); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb540); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x53b5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4086); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb540); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb9b5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40c8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb03a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8b0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbac8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb13a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8b1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xba77); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd26); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffbd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2677); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd28); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffbd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2840); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd26); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8bd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2640); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd28); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8bd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x28bb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa430); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x98b0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1eba); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb01e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xdcb0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e98); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbab0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9edc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x98b1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1eba); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb11e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xdcb1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e98); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbab1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9edc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x11b0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e22); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb01e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x33b0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e11); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x22b0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9e33); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x11b1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e22); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb11e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x33b1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e11); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x22b1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9e33); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb85e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2f71); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb860); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x20d9); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb862); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2109); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb864); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x34e7); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb878); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x000f); - - - ClearEthPhyOcpBit(tp, 0xB820, BIT_7); + rtl8125_set_eth_phy_ocp_bit(tp, 0xB820, BIT_7); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8013); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8021); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x802f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x803d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8042); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8051); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8051); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa088); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a50); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8008); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1a3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x401a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd707); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40c2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f8b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a6c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8080); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd019); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1a2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x401a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd707); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40c4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f8b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a84); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8970); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c07); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0901); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcf09); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd705); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xceff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf0a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1213); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8401); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8580); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1253); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd064); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd181); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4018); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc50f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd706); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2c59); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x804d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc60f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc605); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x10fd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA026); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA022); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x10f4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA020); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1252); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA006); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1206); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA004); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a78); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a60); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a4f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA008); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3f00); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8066); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x807c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8089); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x808e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80b2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80c2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x62db); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x655c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0505); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0509); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x653c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0502); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0506); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x050a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0505); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0506); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x050c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0509); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x050a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x050c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0508); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0304); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd73e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60e9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x614a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x61ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0502); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0508); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0321); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0346); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8208); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x609d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x001a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x001a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x607d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ab); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60fd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaa0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x017b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a05); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x017b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60fd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaa0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x01e0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a05); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x01e0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60fd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa50f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaa0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0231); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0503); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a05); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0231); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0221); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x01ce); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA088); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0169); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA086); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00a6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA084); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x000d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA082); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0308); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA080); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x029f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA090); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x007f); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0020); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8017); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8029); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8054); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x805a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8064); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80a7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9430); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9480); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb408); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd120); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd057); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb80); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9906); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0567); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb94); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8406); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8dff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa840); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0773); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb91); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd139); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd140); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07dc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa110); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa2a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4045); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa180); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07ec); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f74); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07dc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07c0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fa7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0481); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x94bc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x870c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa00a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa280); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8220); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x078e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb92); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa840); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd140); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd150); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd703); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6121); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x61a2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6223); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d10); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d20); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d30); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf005); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d40); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa008); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4046); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07f7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f74); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0742); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3ad4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0537); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8840); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8301); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa70c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9402); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x890c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8840); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x064b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0642); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0686); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0788); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA108); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x047b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA106); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x065c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA104); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0769); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA102); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0565); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x06f9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA110); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ff); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8530); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3caf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8593); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9caf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x85a5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5afb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe083); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfb0c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x020d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x021b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x10bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86d7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbe0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x83fc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1b10); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xda02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xdd02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5afb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe083); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfd0c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x020d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x021b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x10bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86dd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbe0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x83fe); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1b10); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf2f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2cac); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0286); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x65af); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x212b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x022c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86b6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf21); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cd1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x03bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8710); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x870d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8719); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8716); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x871f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x871c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8728); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8725); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8707); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbad); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x281c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1302); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2202); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2b02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae1a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd101); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1302); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2202); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2b02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd101); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3402); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3102); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3d02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3a02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4302); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4c02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4902); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2e02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4602); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf87); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4f02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ab7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf35); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7ff8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfaef); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x69bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86fb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86fe); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86e9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86ec); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfbbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x025a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7bf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86ef); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86f2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86f5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cbf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x86f8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0262); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7cef); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x96fe); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfc04); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf8fa); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xef69); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xef02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf202); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf502); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbf86); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf802); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6273); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xef96); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfefc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0420); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb540); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x53b5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4086); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb540); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb9b5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40c8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb03a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8b0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbac8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb13a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8b1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xba77); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd26); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffbd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2677); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd28); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffbd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2840); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd26); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8bd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2640); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbd28); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc8bd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x28bb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa430); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x98b0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1eba); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb01e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xdcb0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e98); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbab0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9edc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x98b1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1eba); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb11e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xdcb1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e98); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbab1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9edc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x11b0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e22); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb01e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x33b0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e11); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x22b0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9e33); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb09e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x11b1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e22); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb11e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x33b1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1e11); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x22b1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9e33); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb19e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb85e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2f71); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb860); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x20d9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb862); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2109); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb864); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x34e7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb878); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x000f); + + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB820, BIT_7); rtl8125_release_phy_mcu_patch_key_lock(tp); @@ -8209,568 +9920,568 @@ rtl8125_real_set_phy_mcu_8125a_2(struct net_device *dev) rtl8125_acquire_phy_mcu_patch_key_lock(tp); - SetEthPhyOcpBit(tp, 0xB820, BIT_7); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x808b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x808f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8093); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8097); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x809d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80a1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80aa); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x607b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x42da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf01e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x615b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf01c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf024); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf034); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac11); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa410); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4779); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf034); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac22); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa420); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4559); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf023); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac44); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa440); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4339); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac88); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa480); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4119); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf001); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fac); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc48f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x141b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x121a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd0b4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1bb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0898); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd0b4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1bb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a0e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd064); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd18a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0b7e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x401c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa804); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8804); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x053b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa301); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0648); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc520); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa201); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x252d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1646); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd708); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4006); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1646); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0308); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA026); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0307); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA024); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1645); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA022); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0647); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA020); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x053a); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA006); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0b7c); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA004); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a0c); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0896); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x11a1); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA008); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xff00); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0010); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8015); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xad02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x02d7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ed); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0509); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xc100); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x008f); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08E); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08C); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08A); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA088); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA086); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA084); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA082); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x008d); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA080); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00eb); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA090); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0103); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0020); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8014); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8018); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8024); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8051); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8055); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8072); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x80dc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfffd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfffd); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8301); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa70c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x9402); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x890c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8840); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa380); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x066e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb91); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd139); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd140); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa110); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa2a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4085); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa180); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8280); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07f0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f74); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x066e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd158); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd04d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x03d4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x94bc); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x870c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8380); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd10d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07c4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fb4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa190); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa00a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa280); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa220); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd130); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07c4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fb4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xbb80); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1c4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd074); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa301); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x604b); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa90c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0556); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb92); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd116); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd119); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd703); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6241); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x63e2); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6583); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf054); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d10); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d50); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d20); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf021); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d60); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf01c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d30); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf013); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d70); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d40); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf005); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d80); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ff4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa008); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x4046); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07fb); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd703); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f6f); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f4e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f2d); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f0c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3ad4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0556); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x066e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1f5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xd049); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x01ec); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10E); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x01ea); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10C); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x06a9); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10A); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x078a); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA108); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x03d2); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA106); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x067f); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA104); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0665); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA102); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA100); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xA110); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00fc); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8530); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x3caf); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8545); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x45af); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8545); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xee82); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf900); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0103); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf03); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7f8); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe0a6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00e1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa601); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xef01); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x58f0); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa080); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x37a1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8402); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae16); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa185); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x02ae); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x11a1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8702); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae0c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xa188); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x02ae); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x07a1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8902); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae02); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xae1c); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe0b4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6901); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe4b4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe0b4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6901); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xe4b4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xfc04); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb85e); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x03b3); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb860); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb862); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb864); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); - mdio_direct_write_phy_ocp(tp, 0xA436, 0xb878); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0001); - - - ClearEthPhyOcpBit(tp, 0xB820, BIT_7); + rtl8125_set_eth_phy_ocp_bit(tp, 0xB820, BIT_7); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x808b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x808f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8093); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8097); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x809d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80a1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80aa); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x607b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x42da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf01e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x615b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf01c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14a4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x14bc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f2e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf034); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac11); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa410); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4779); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf034); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac22); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa420); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4559); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf023); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac44); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa440); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4339); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd719); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4118); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac88); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa480); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xce00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4119); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xac0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1444); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf001); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1456); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd718); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fac); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc48f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x141b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd504); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x121a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd0b4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1bb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0898); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd0b4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1bb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a0e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd064); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd18a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0b7e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x401c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd501); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa804); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8804); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x053b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa301); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0648); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc520); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa201); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x252d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1646); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd708); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4006); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1646); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0308); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA026); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0307); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1645); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA022); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0647); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA020); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x053a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA006); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0b7c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA004); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0a0c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0896); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x11a1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA008); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xff00); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8015); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x801a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xad02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x02d7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ed); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0509); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xc100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x008f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA08A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA088); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA086); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA084); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA082); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x008d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA080); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00eb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA090); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0103); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA016); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0020); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8014); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8018); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8051); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8055); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8072); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x80dc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfffd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfffd); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8301); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa70c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x9402); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x890c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8840); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa380); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x066e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb91); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd139); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd140); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa110); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa2a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4085); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa180); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8280); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07f0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5f74); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x82a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0c0f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x066e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd158); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd04d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x03d4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x94bc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x870c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8380); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd10d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07c4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fb4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa190); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa00a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa280); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa404); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa220); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd130); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07c4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5fb4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xbb80); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1c4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd074); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa301); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x604b); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa90c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0556); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xcb92); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4063); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd116); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd119); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd040); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd703); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x60a0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6241); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x63e2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6583); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf054); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d10); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d50); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf02a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d20); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf021); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d60); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf01c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d30); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf013); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d70); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf00e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x611e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x40da); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d40); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf005); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d80); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x405d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa720); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5ff4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa008); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd704); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4046); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07fb); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd703); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f6f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f4e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f2d); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7f0c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x800a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0cf0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0d00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07e8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8010); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa740); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0743); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7fb5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd701); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3ad4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0556); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8610); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x066e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd1f5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xd049); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x1800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x01ec); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x01ea); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x06a9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA10A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x078a); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA108); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x03d2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA106); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x067f); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA104); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0665); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA102); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xA110); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00fc); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8530); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb87e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x3caf); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8545); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf85); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x45af); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8545); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xee82); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf900); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0103); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xaf03); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb7f8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe0a6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00e1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa601); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xef01); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x58f0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa080); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x37a1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8402); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae16); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa185); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x02ae); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x11a1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8702); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae0c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xa188); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x02ae); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x07a1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8902); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae02); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xae1c); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe0b4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6901); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe4b4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe0b4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6901); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xe4b4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x62e5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xb463); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xfc04); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb85e); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x03b3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb860); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb862); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb864); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xffff); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0xb878); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0001); + + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB820, BIT_7); rtl8125_release_phy_mcu_patch_key_lock(tp); @@ -9492,8 +11203,8 @@ static const u16 phy_mcu_ram_code_8125b_2[] = { 0xa438, 0x077e, 0xa436, 0xA110, 0xa438, 0x000f, 0xa436, 0xb87c, 0xa438, 0x8625, 0xa436, 0xb87e, 0xa438, 0xaf86, 0xa438, 0x3daf, 0xa438, 0x8689, 0xa438, 0xaf88, 0xa438, 0x69af, 0xa438, 0x8887, - 0xa438, 0xaf88, 0xa438, 0x9caf, 0xa438, 0x889c, 0xa438, 0xaf88, - 0xa438, 0x9caf, 0xa438, 0x889c, 0xa438, 0xbf86, 0xa438, 0x49d7, + 0xa438, 0xaf88, 0xa438, 0x9caf, 0xa438, 0x88be, 0xa438, 0xaf88, + 0xa438, 0xbeaf, 0xa438, 0x88be, 0xa438, 0xbf86, 0xa438, 0x49d7, 0xa438, 0x0040, 0xa438, 0x0277, 0xa438, 0x7daf, 0xa438, 0x2727, 0xa438, 0x0000, 0xa438, 0x7205, 0xa438, 0x0000, 0xa438, 0x7208, 0xa438, 0x0000, 0xa438, 0x71f3, 0xa438, 0x0000, 0xa438, 0x71f6, @@ -9569,639 +11280,713 @@ static const u16 phy_mcu_ram_code_8125b_2[] = { 0xa438, 0xaf26, 0xa438, 0xf520, 0xa438, 0xac86, 0xa438, 0xbf88, 0xa438, 0x3f02, 0xa438, 0x6e9c, 0xa438, 0xad28, 0xa438, 0x03af, 0xa438, 0x3324, 0xa438, 0xad38, 0xa438, 0x03af, 0xa438, 0x32e6, - 0xa438, 0xaf32, 0xa438, 0xfb00, 0xa436, 0xb87c, 0xa438, 0x8ff6, - 0xa436, 0xb87e, 0xa438, 0x0705, 0xa436, 0xb87c, 0xa438, 0x8ff8, - 0xa436, 0xb87e, 0xa438, 0x19cc, 0xa436, 0xb87c, 0xa438, 0x8ffa, - 0xa436, 0xb87e, 0xa438, 0x28e3, 0xa436, 0xb87c, 0xa438, 0x8ffc, - 0xa436, 0xb87e, 0xa438, 0x1047, 0xa436, 0xb87c, 0xa438, 0x8ffe, - 0xa436, 0xb87e, 0xa438, 0x0a45, 0xa436, 0xb85e, 0xa438, 0x271E, - 0xa436, 0xb860, 0xa438, 0x3846, 0xa436, 0xb862, 0xa438, 0x26E6, - 0xa436, 0xb864, 0xa438, 0x32E3, 0xa436, 0xb886, 0xa438, 0xffff, - 0xa436, 0xb888, 0xa438, 0xffff, 0xa436, 0xb88a, 0xa438, 0xffff, - 0xa436, 0xb88c, 0xa438, 0xffff, 0xa436, 0xb838, 0xa438, 0x000f, - 0xb820, 0x0010, 0xa436, 0x846e, 0xa438, 0xaf84, 0xa438, 0x86af, - 0xa438, 0x8690, 0xa438, 0xaf86, 0xa438, 0xa4af, 0xa438, 0x86a4, - 0xa438, 0xaf86, 0xa438, 0xa4af, 0xa438, 0x86a4, 0xa438, 0xaf86, - 0xa438, 0xa4af, 0xa438, 0x86a4, 0xa438, 0xee82, 0xa438, 0x5f00, - 0xa438, 0x0284, 0xa438, 0x90af, 0xa438, 0x0441, 0xa438, 0xf8e0, - 0xa438, 0x8ff3, 0xa438, 0xa000, 0xa438, 0x0502, 0xa438, 0x84a4, - 0xa438, 0xae06, 0xa438, 0xa001, 0xa438, 0x0302, 0xa438, 0x84c8, - 0xa438, 0xfc04, 0xa438, 0xf8f9, 0xa438, 0xef59, 0xa438, 0xe080, - 0xa438, 0x15ad, 0xa438, 0x2702, 0xa438, 0xae03, 0xa438, 0xaf84, - 0xa438, 0xc3bf, 0xa438, 0x53ca, 0xa438, 0x0252, 0xa438, 0xc8ad, - 0xa438, 0x2807, 0xa438, 0x0285, 0xa438, 0x2cee, 0xa438, 0x8ff3, - 0xa438, 0x01ef, 0xa438, 0x95fd, 0xa438, 0xfc04, 0xa438, 0xf8f9, - 0xa438, 0xfaef, 0xa438, 0x69bf, 0xa438, 0x53ca, 0xa438, 0x0252, - 0xa438, 0xc8ac, 0xa438, 0x2822, 0xa438, 0xd480, 0xa438, 0x00bf, + 0xa438, 0xaf32, 0xa438, 0xfbee, 0xa438, 0x826a, 0xa438, 0x0002, + 0xa438, 0x88a6, 0xa438, 0xaf04, 0xa438, 0x78f8, 0xa438, 0xfaef, + 0xa438, 0x69e0, 0xa438, 0x8015, 0xa438, 0xad20, 0xa438, 0x06bf, + 0xa438, 0x88bb, 0xa438, 0x0275, 0xa438, 0xb1ef, 0xa438, 0x96fe, + 0xa438, 0xfc04, 0xa438, 0x00b8, 0xa438, 0x7a00, 0xa436, 0xb87c, + 0xa438, 0x8ff6, 0xa436, 0xb87e, 0xa438, 0x0705, 0xa436, 0xb87c, + 0xa438, 0x8ff8, 0xa436, 0xb87e, 0xa438, 0x19cc, 0xa436, 0xb87c, + 0xa438, 0x8ffa, 0xa436, 0xb87e, 0xa438, 0x28e3, 0xa436, 0xb87c, + 0xa438, 0x8ffc, 0xa436, 0xb87e, 0xa438, 0x1047, 0xa436, 0xb87c, + 0xa438, 0x8ffe, 0xa436, 0xb87e, 0xa438, 0x0a45, 0xa436, 0xb85e, + 0xa438, 0x271E, 0xa436, 0xb860, 0xa438, 0x3846, 0xa436, 0xb862, + 0xa438, 0x26E6, 0xa436, 0xb864, 0xa438, 0x32E3, 0xa436, 0xb886, + 0xa438, 0x0474, 0xa436, 0xb888, 0xa438, 0xffff, 0xa436, 0xb88a, + 0xa438, 0xffff, 0xa436, 0xb88c, 0xa438, 0xffff, 0xa436, 0xb838, + 0xa438, 0x001f, 0xb820, 0x0010, 0xa436, 0x846e, 0xa438, 0xaf84, + 0xa438, 0x86af, 0xa438, 0x8690, 0xa438, 0xaf86, 0xa438, 0xa4af, + 0xa438, 0x8934, 0xa438, 0xaf89, 0xa438, 0x60af, 0xa438, 0x897e, + 0xa438, 0xaf89, 0xa438, 0xa9af, 0xa438, 0x89a9, 0xa438, 0xee82, + 0xa438, 0x5f00, 0xa438, 0x0284, 0xa438, 0x90af, 0xa438, 0x0441, + 0xa438, 0xf8e0, 0xa438, 0x8ff3, 0xa438, 0xa000, 0xa438, 0x0502, + 0xa438, 0x84a4, 0xa438, 0xae06, 0xa438, 0xa001, 0xa438, 0x0302, + 0xa438, 0x84c8, 0xa438, 0xfc04, 0xa438, 0xf8f9, 0xa438, 0xef59, + 0xa438, 0xe080, 0xa438, 0x15ad, 0xa438, 0x2702, 0xa438, 0xae03, + 0xa438, 0xaf84, 0xa438, 0xc3bf, 0xa438, 0x53ca, 0xa438, 0x0252, + 0xa438, 0xc8ad, 0xa438, 0x2807, 0xa438, 0x0285, 0xa438, 0x2cee, + 0xa438, 0x8ff3, 0xa438, 0x01ef, 0xa438, 0x95fd, 0xa438, 0xfc04, + 0xa438, 0xf8f9, 0xa438, 0xfaef, 0xa438, 0x69bf, 0xa438, 0x53ca, + 0xa438, 0x0252, 0xa438, 0xc8ac, 0xa438, 0x2822, 0xa438, 0xd480, + 0xa438, 0x00bf, 0xa438, 0x8684, 0xa438, 0x0252, 0xa438, 0xa9bf, + 0xa438, 0x8687, 0xa438, 0x0252, 0xa438, 0xa9bf, 0xa438, 0x868a, + 0xa438, 0x0252, 0xa438, 0xa9bf, 0xa438, 0x868d, 0xa438, 0x0252, + 0xa438, 0xa9ee, 0xa438, 0x8ff3, 0xa438, 0x00af, 0xa438, 0x8526, + 0xa438, 0xe08f, 0xa438, 0xf4e1, 0xa438, 0x8ff5, 0xa438, 0xe28f, + 0xa438, 0xf6e3, 0xa438, 0x8ff7, 0xa438, 0x1b45, 0xa438, 0xac27, + 0xa438, 0x0eee, 0xa438, 0x8ff4, 0xa438, 0x00ee, 0xa438, 0x8ff5, + 0xa438, 0x0002, 0xa438, 0x852c, 0xa438, 0xaf85, 0xa438, 0x26e0, + 0xa438, 0x8ff4, 0xa438, 0xe18f, 0xa438, 0xf52c, 0xa438, 0x0001, + 0xa438, 0xe48f, 0xa438, 0xf4e5, 0xa438, 0x8ff5, 0xa438, 0xef96, + 0xa438, 0xfefd, 0xa438, 0xfc04, 0xa438, 0xf8f9, 0xa438, 0xef59, + 0xa438, 0xbf53, 0xa438, 0x2202, 0xa438, 0x52c8, 0xa438, 0xa18b, + 0xa438, 0x02ae, 0xa438, 0x03af, 0xa438, 0x85da, 0xa438, 0xbf57, + 0xa438, 0x7202, 0xa438, 0x52c8, 0xa438, 0xe48f, 0xa438, 0xf8e5, + 0xa438, 0x8ff9, 0xa438, 0xbf57, 0xa438, 0x7502, 0xa438, 0x52c8, + 0xa438, 0xe48f, 0xa438, 0xfae5, 0xa438, 0x8ffb, 0xa438, 0xbf57, + 0xa438, 0x7802, 0xa438, 0x52c8, 0xa438, 0xe48f, 0xa438, 0xfce5, + 0xa438, 0x8ffd, 0xa438, 0xbf57, 0xa438, 0x7b02, 0xa438, 0x52c8, + 0xa438, 0xe48f, 0xa438, 0xfee5, 0xa438, 0x8fff, 0xa438, 0xbf57, + 0xa438, 0x6c02, 0xa438, 0x52c8, 0xa438, 0xa102, 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0xa438, 0xe38f, + 0xa438, 0xe61b, 0xa438, 0x659e, 0xa438, 0x10e4, 0xa438, 0x8fe5, + 0xa438, 0xe58f, 0xa438, 0xe6e2, 0xa438, 0x83c9, 0xa438, 0xf636, + 0xa438, 0xe683, 0xa438, 0xc9ae, 0xa438, 0x13e2, 0xa438, 0x83c9, + 0xa438, 0xf736, 0xa438, 0xe683, 0xa438, 0xc902, 0xa438, 0x5820, + 0xa438, 0xef57, 0xa438, 0xe68f, 0xa438, 0xe7e7, 0xa438, 0x8fe8, + 0xa438, 0xffef, 0xa438, 0x97ff, 0xa438, 0xfefd, 0xa438, 0xfc04, + 0xa438, 0xf8f9, 0xa438, 0xfafb, 0xa438, 0xef79, 0xa438, 0xfbe2, + 0xa438, 0x8fe7, 0xa438, 0xe38f, 0xa438, 0xe8ef, 0xa438, 0x65e2, + 0xa438, 0x81b8, 0xa438, 0xe381, 0xa438, 0xb9ef, 0xa438, 0x7502, + 0xa438, 0x583b, 0xa438, 0xac50, 0xa438, 0x1abf, 0xa438, 0x5718, + 0xa438, 0x0252, 0xa438, 0xc8ef, 0xa438, 0x64e2, 0xa438, 0x8fe5, + 0xa438, 0xe38f, 0xa438, 0xe61b, 0xa438, 0x659e, 0xa438, 0x1ce4, + 0xa438, 0x8fe5, 0xa438, 0xe58f, 0xa438, 0xe6ae, 0xa438, 0x0cbf, + 0xa438, 0x5715, 0xa438, 0x0258, 0xa438, 0xb1bf, 0xa438, 0x5715, + 0xa438, 0x0258, 0xa438, 0xa8e2, 0xa438, 0x83c9, 0xa438, 0xf636, + 0xa438, 0xe683, 0xa438, 0xc9ff, 0xa438, 0xef97, 0xa438, 0xfffe, + 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xf9fa, 0xa438, 0xef69, + 0xa438, 0xe080, 0xa438, 0x15ad, 0xa438, 0x264b, 0xa438, 0xbf53, + 0xa438, 0xca02, 0xa438, 0x52c8, 0xa438, 0xad28, 0xa438, 0x42bf, + 0xa438, 0x8931, 0xa438, 0x0252, 0xa438, 0xc8ef, 0xa438, 0x54bf, + 0xa438, 0x576c, 0xa438, 0x0252, 0xa438, 0xc8a1, 0xa438, 0x001b, + 0xa438, 0xbf53, 0xa438, 0x4c02, 0xa438, 0x52c8, 0xa438, 0xac29, + 0xa438, 0x0dac, 0xa438, 0x2805, 0xa438, 0xa302, 0xa438, 0x16ae, + 0xa438, 0x20a3, 0xa438, 0x0311, 0xa438, 0xae1b, 0xa438, 0xa304, + 0xa438, 0x0cae, 0xa438, 0x16a3, 0xa438, 0x0802, 0xa438, 0xae11, + 0xa438, 0xa309, 0xa438, 0x02ae, 0xa438, 0x0cbf, 0xa438, 0x5715, + 0xa438, 0x0258, 0xa438, 0xb1bf, 0xa438, 0x5715, 0xa438, 0x0258, + 0xa438, 0xa8ef, 0xa438, 0x96fe, 0xa438, 0xfdfc, 0xa438, 0x04f0, + 0xa438, 0xa300, 0xa438, 0xf0a3, 0xa438, 0x02f0, 0xa438, 0xa304, + 0xa438, 0xf0a3, 0xa438, 0x06f0, 0xa438, 0xa308, 0xa438, 0xf0a2, + 0xa438, 0x8074, 0xa438, 0xa600, 0xa438, 0xac4f, 0xa438, 0x02ae, + 0xa438, 0x0bef, 0xa438, 0x46f6, 0xa438, 0x273c, 0xa438, 0x1000, + 0xa438, 0xab1b, 0xa438, 0xae16, 0xa438, 0xe081, 0xa438, 0xabe1, + 0xa438, 0x81ac, 0xa438, 0x1b46, 0xa438, 0xab0c, 0xa438, 0xac32, + 0xa438, 0x04ef, 0xa438, 0x32ae, 0xa438, 0x02d3, 0xa438, 0x04af, + 0xa438, 0x486c, 0xa438, 0xaf48, 0xa438, 0x82af, 0xa438, 0x4888, + 0xa438, 0xe081, 0xa438, 0x9be1, 0xa438, 0x819c, 0xa438, 0xe28f, + 0xa438, 0xe3ad, 0xa438, 0x3009, 0xa438, 0x1f55, 0xa438, 0xe38f, + 0xa438, 0xe20c, 0xa438, 0x581a, 0xa438, 0x45e4, 0xa438, 0x83a6, + 0xa438, 0xe583, 0xa438, 0xa7af, 0xa438, 0x2a75, 0xa438, 0xe08f, + 0xa438, 0xe3ad, 0xa438, 0x201c, 0xa438, 0x1f44, 0xa438, 0xe18f, + 0xa438, 0xe10c, 0xa438, 0x44ef, 0xa438, 0x64e0, 0xa438, 0x8232, + 0xa438, 0xe182, 0xa438, 0x331b, 0xa438, 0x649f, 0xa438, 0x091f, + 0xa438, 0x44e1, 0xa438, 0x8fe2, 0xa438, 0x0c48, 0xa438, 0x1b54, + 0xa438, 0xe683, 0xa438, 0xa6e7, 0xa438, 0x83a7, 0xa438, 0xaf2b, + 0xa438, 0xd900, 0xa436, 0xb818, 0xa438, 0x043d, 0xa436, 0xb81a, + 0xa438, 0x06a3, 0xa436, 0xb81c, 0xa438, 0x476d, 0xa436, 0xb81e, + 0xa438, 0x4852, 0xa436, 0xb850, 0xa438, 0x2A69, 0xa436, 0xb852, + 0xa438, 0x2BD3, 0xa436, 0xb878, 0xa438, 0xffff, 0xa436, 0xb884, + 0xa438, 0xffff, 0xa436, 0xb832, 0xa438, 0x003f, 0xb844, 0xffff, + 0xa436, 0x8fe9, 0xa438, 0x0000, 0xa436, 0x8feb, 0xa438, 0x02fe, + 0xa436, 0x8fed, 0xa438, 0x0019, 0xa436, 0x8fef, 0xa438, 0x0bdb, + 0xa436, 0x8ff1, 0xa438, 0x0ca4, 0xa436, 0x0000, 0xa438, 0x0000, + 0xa436, 0xB82E, 0xa438, 0x0000, 0xa436, 0x8024, 0xa438, 0x0000, + 0xa436, 0x801E, 0xa438, 0x0024, 0xb820, 0x0000, 0xFFFF, 0xFFFF }; -static const u16 phy_mcu_ram_code_8126a_1_1[] = { - 0xa436, 0x8023, 0xa438, 0x4900, 0xa436, 0xB82E, 0xa438, 0x0001, - 0xBFBA, 0xE000, 0xBF1A, 0xC1B9, 0xBFA8, 0x10F0, 0xBFB0, 0x0210, - 0xBFB4, 0xE7E4, 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, - 0xa436, 0xA012, 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, - 0xa438, 0x8010, 0xa438, 0x1800, 0xa438, 0x8062, 0xa438, 0x1800, - 0xa438, 0x8069, 0xa438, 0x1800, 0xa438, 0x80e2, 0xa438, 0x1800, - 0xa438, 0x80eb, 0xa438, 0x1800, 0xa438, 0x80f5, 0xa438, 0x1800, - 0xa438, 0x811b, 0xa438, 0x1800, 0xa438, 0x8120, 0xa438, 0xd500, - 0xa438, 0xd049, 0xa438, 0xd1b9, 0xa438, 0xa208, 0xa438, 0x8208, - 0xa438, 0xd503, 0xa438, 0xa104, 0xa438, 0x0c07, 0xa438, 0x0902, - 0xa438, 0xd500, 0xa438, 0xbc10, 0xa438, 0xc484, 0xa438, 0xd503, - 0xa438, 0xcc02, 0xa438, 0xcd0d, 0xa438, 0xaf01, 0xa438, 0xd500, - 0xa438, 0xd703, 0xa438, 0x4531, 0xa438, 0xbd08, 0xa438, 0x1000, - 0xa438, 0x16bb, 0xa438, 0xd75e, 0xa438, 0x5fb3, 0xa438, 0xd503, - 0xa438, 0xd04d, 0xa438, 0xd1c7, 0xa438, 0x0cf0, 0xa438, 0x0e10, - 0xa438, 0xd704, 0xa438, 0x5ffc, 0xa438, 0xd04d, 0xa438, 0xd1c7, - 0xa438, 0x0cf0, 0xa438, 0x0e20, 0xa438, 0xd704, 0xa438, 0x5ffc, - 0xa438, 0xd04d, 0xa438, 0xd1c7, 0xa438, 0x0cf0, 0xa438, 0x0e40, - 0xa438, 0xd704, 0xa438, 0x5ffc, 0xa438, 0xd04d, 0xa438, 0xd1c7, - 0xa438, 0x0cf0, 0xa438, 0x0e80, 0xa438, 0xd704, 0xa438, 0x5ffc, - 0xa438, 0xd07b, 0xa438, 0xd1c5, 0xa438, 0x8ef0, 0xa438, 0xd704, - 0xa438, 0x5ffc, 0xa438, 0x9d08, 0xa438, 0x1000, 0xa438, 0x16bb, - 0xa438, 0xd75e, 0xa438, 0x7fb3, 0xa438, 0x1000, 0xa438, 0x16bb, - 0xa438, 0xd75e, 0xa438, 0x5fad, 0xa438, 0x1000, 0xa438, 0x181f, - 0xa438, 0xd703, 0xa438, 0x3181, 0xa438, 0x8059, 0xa438, 0x60ad, - 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd703, 0xa438, 0x5fbb, - 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd719, 0xa438, 0x7fa8, - 0xa438, 0xd500, 0xa438, 0xd049, 0xa438, 0xd1b9, 0xa438, 0x1800, - 0xa438, 0x0f0b, 0xa438, 0xd500, 0xa438, 0xd07b, 0xa438, 0xd1b5, - 0xa438, 0xd0f6, 0xa438, 0xd1c5, 0xa438, 0x1800, 0xa438, 0x1049, - 0xa438, 0xd707, 0xa438, 0x4121, 0xa438, 0xd706, 0xa438, 0x40fa, - 0xa438, 0xd099, 0xa438, 0xd1c6, 0xa438, 0x1000, 0xa438, 0x16bb, - 0xa438, 0xd704, 0xa438, 0x5fbc, 0xa438, 0xbc80, 0xa438, 0xc489, - 0xa438, 0xd503, 0xa438, 0xcc08, 0xa438, 0xcd46, 0xa438, 0xaf01, - 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x0903, 0xa438, 0x1000, - 0xa438, 0x16bb, 0xa438, 0xd75e, 0xa438, 0x5f6d, 0xa438, 0x1000, - 0xa438, 0x181f, 0xa438, 0xd504, 0xa438, 0xa210, 0xa438, 0xd500, - 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd719, 0xa438, 0x5fbc, - 0xa438, 0xd504, 0xa438, 0x8210, 0xa438, 0xd503, 0xa438, 0xc6d0, - 0xa438, 0xa521, 0xa438, 0xcd49, 0xa438, 0xaf01, 0xa438, 0xd504, - 0xa438, 0xa220, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x16bb, - 0xa438, 0xd75e, 0xa438, 0x5fad, 0xa438, 0x1000, 0xa438, 0x181f, - 0xa438, 0xd503, 0xa438, 0xa704, 0xa438, 0x0c07, 0xa438, 0x0904, - 0xa438, 0xd504, 0xa438, 0xa102, 0xa438, 0xd500, 0xa438, 0x1000, - 0xa438, 0x16bb, 0xa438, 0xd718, 0xa438, 0x5fab, 0xa438, 0xd503, - 0xa438, 0xc6f0, 0xa438, 0xa521, 0xa438, 0xd505, 0xa438, 0xa404, - 0xa438, 0xd500, 0xa438, 0xd701, 0xa438, 0x6085, 0xa438, 0xd504, - 0xa438, 0xc9f1, 0xa438, 0xf003, 0xa438, 0xd504, 0xa438, 0xc9f0, - 0xa438, 0xd503, 0xa438, 0xcd4a, 0xa438, 0xaf01, 0xa438, 0xd500, - 0xa438, 0xd504, 0xa438, 0xa802, 0xa438, 0xd500, 0xa438, 0x1000, - 0xa438, 0x16bb, 0xa438, 0xd707, 0xa438, 0x5fb1, 0xa438, 0xd707, - 0xa438, 0x5f10, 0xa438, 0xd505, 0xa438, 0xa402, 0xa438, 0xd503, - 0xa438, 0xd707, 0xa438, 0x41a1, 0xa438, 0xd706, 0xa438, 0x60ba, - 0xa438, 0x60fc, 0xa438, 0x0c07, 0xa438, 0x0204, 0xa438, 0xf009, - 0xa438, 0x0c07, 0xa438, 0x0202, 0xa438, 0xf006, 0xa438, 0x0c07, - 0xa438, 0x0206, 0xa438, 0xf003, 0xa438, 0x0c07, 0xa438, 0x0202, - 0xa438, 0xd500, 0xa438, 0xd703, 0xa438, 0x3181, 0xa438, 0x80e0, - 0xa438, 0x616d, 0xa438, 0xd701, 0xa438, 0x6065, 0xa438, 0x1800, - 0xa438, 0x1229, 0xa438, 0x1000, 0xa438, 0x16bb, 0xa438, 0xd707, - 0xa438, 0x6061, 0xa438, 0xd704, 0xa438, 0x5f7c, 0xa438, 0x1800, - 0xa438, 0x124a, 0xa438, 0xd504, 0xa438, 0x8c0f, 0xa438, 0xd505, - 0xa438, 0xa20e, 0xa438, 0xd500, 0xa438, 0x1000, 0xa438, 0x1871, - 0xa438, 0x1800, 0xa438, 0x1899, 0xa438, 0xd70b, 0xa438, 0x60b0, - 0xa438, 0xd05a, 0xa438, 0xd19a, 0xa438, 0x1800, 0xa438, 0x1aef, - 0xa438, 0xd0ef, 0xa438, 0xd19a, 0xa438, 0x1800, 0xa438, 0x1aef, - 0xa438, 0x1000, 0xa438, 0x1d09, 0xa438, 0xd708, 0xa438, 0x3399, - 0xa438, 0x1b63, 0xa438, 0xd709, 0xa438, 0x5f5d, 0xa438, 0xd70b, - 0xa438, 0x6130, 0xa438, 0xd70d, 0xa438, 0x6163, 0xa438, 0xd709, - 0xa438, 0x430b, 0xa438, 0xd71e, 0xa438, 0x62c2, 0xa438, 0xb401, - 0xa438, 0xf014, 0xa438, 0xc901, 0xa438, 0x1000, 0xa438, 0x810e, - 0xa438, 0xf010, 0xa438, 0xc902, 0xa438, 0x1000, 0xa438, 0x810e, - 0xa438, 0xf00c, 0xa438, 0xce04, 0xa438, 0xcf01, 0xa438, 0xd70a, - 0xa438, 0x5fe2, 0xa438, 0xce04, 0xa438, 0xcf02, 0xa438, 0xc900, - 0xa438, 0xd70a, 0xa438, 0x4057, 0xa438, 0xb401, 0xa438, 0x0800, - 0xa438, 0x1800, 0xa438, 0x1b5d, 0xa438, 0xa480, 0xa438, 0xa2b0, - 0xa438, 0xa806, 0xa438, 0x1800, 0xa438, 0x225c, 0xa438, 0xa7e8, - 0xa438, 0xac08, 0xa438, 0x1800, 0xa438, 0x1a4e, 0xa436, 0xA026, - 0xa438, 0x1a4d, 0xa436, 0xA024, 0xa438, 0x225a, 0xa436, 0xA022, - 0xa438, 0x1b53, 0xa436, 0xA020, 0xa438, 0x1aed, 0xa436, 0xA006, - 0xa438, 0x1892, 0xa436, 0xA004, 0xa438, 0x11a4, 0xa436, 0xA002, - 0xa438, 0x103c, 0xa436, 0xA000, 0xa438, 0x0ea6, 0xa436, 0xA008, - 0xa438, 0xff00, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, - 0xa438, 0x0ff8, 0xa436, 0xA014, 0xa438, 0x0000, 0xa438, 0xD098, - 0xa438, 0xc483, 0xa438, 0xc483, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa436, 0xA152, 0xa438, 0x3fff, - 0xa436, 0xA154, 0xa438, 0x0413, 0xa436, 0xA156, 0xa438, 0x1A32, - 0xa436, 0xA158, 0xa438, 0x1CC0, 0xa436, 0xA15A, 0xa438, 0x3fff, +static const u16 phy_mcu_ram_code_8125d_1_1[] = { + 0xa436, 0x8023, 0xa438, 0x3800, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8018, 0xa438, 0x1800, 0xa438, 0x8021, + 0xa438, 0x1800, 0xa438, 0x8029, 0xa438, 0x1800, 0xa438, 0x8031, + 0xa438, 0x1800, 0xa438, 0x8035, 0xa438, 0x1800, 0xa438, 0x8035, + 0xa438, 0x1800, 0xa438, 0x8035, 0xa438, 0xd711, 0xa438, 0x6081, + 0xa438, 0x8904, 0xa438, 0x1800, 0xa438, 0x2021, 0xa438, 0xa904, + 0xa438, 0x1800, 0xa438, 0x2021, 0xa438, 0xd75f, 0xa438, 0x4083, + 0xa438, 0xd503, 0xa438, 0xa908, 0xa438, 0x87f0, 0xa438, 0x1000, + 0xa438, 0x17e0, 0xa438, 0x1800, 0xa438, 0x13c3, 0xa438, 0xd707, + 0xa438, 0x2005, 0xa438, 0x8027, 0xa438, 0xd75e, 0xa438, 0x1800, + 0xa438, 0x1434, 0xa438, 0x1800, 0xa438, 0x14a5, 0xa438, 0xc504, + 0xa438, 0xce20, 0xa438, 0xcf01, 0xa438, 0xd70a, 0xa438, 0x4005, + 0xa438, 0xcf02, 0xa438, 0x1800, 0xa438, 0x1c50, 0xa438, 0xa980, + 0xa438, 0xd500, 0xa438, 0x1800, 0xa438, 0x14f3, 0xa436, 0xA026, + 0xa438, 0xffff, 0xa436, 0xA024, 0xa438, 0xffff, 0xa436, 0xA022, + 0xa438, 0xffff, 0xa436, 0xA020, 0xa438, 0x14f2, 0xa436, 0xA006, + 0xa438, 0x1c4f, 0xa436, 0xA004, 0xa438, 0x1433, 0xa436, 0xA002, + 0xa438, 0x13c1, 0xa436, 0xA000, 0xa438, 0x2020, 0xa436, 0xA008, + 0xa438, 0x1f00, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x07f8, 0xa436, 0xA014, 0xa438, 0xd04d, 0xa438, 0x8904, + 0xa438, 0x813C, 0xa438, 0xA13D, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x0000, 0xa438, 0x0000, 0xa436, 0xA152, 0xa438, 0x1384, + 0xa436, 0xA154, 0xa438, 0x1fa8, 0xa436, 0xA156, 0xa438, 0x218B, + 0xa436, 0xA158, 0xa438, 0x21B8, 0xa436, 0xA15A, 0xa438, 0x3fff, 0xa436, 0xA15C, 0xa438, 0x3fff, 0xa436, 0xA15E, 0xa438, 0x3fff, - 0xa436, 0xA160, 0xa438, 0x3fff, 0xa436, 0xA150, 0xa438, 0x000E, - 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, - 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, - 0xa438, 0x8021, 0xa438, 0x1800, 0xa438, 0x8037, 0xa438, 0x1800, - 0xa438, 0x803f, 0xa438, 0x1800, 0xa438, 0x8084, 0xa438, 0x1800, - 0xa438, 0x80c5, 0xa438, 0x1800, 0xa438, 0x80cc, 0xa438, 0x1800, - 0xa438, 0x80d5, 0xa438, 0xa00a, 0xa438, 0xa280, 0xa438, 0xa404, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x1800, 0xa438, 0x099b, 0xa438, 0x1000, 0xa438, 0x1021, - 0xa438, 0xd700, 0xa438, 0x5fab, 0xa438, 0xa208, 0xa438, 0x8204, - 0xa438, 0xcb38, 0xa438, 0xaa40, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x0000, - 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x0b2a, - 0xa438, 0x82a0, 0xa438, 0x8404, 0xa438, 0xa110, 0xa438, 0xd706, - 0xa438, 0x4041, 0xa438, 0xa180, 0xa438, 0x1800, 0xa438, 0x0e7f, - 0xa438, 0x8190, 0xa438, 0xcb93, 0xa438, 0x1000, 0xa438, 0x0ef4, - 0xa438, 0xd704, 0xa438, 0x7fb8, 0xa438, 0xa008, 0xa438, 0xd706, - 0xa438, 0x4040, 0xa438, 0xa002, 0xa438, 0xd705, 0xa438, 0x4079, - 0xa438, 0x1000, 0xa438, 0x10ad, 0xa438, 0x0c03, 0xa438, 0x1502, - 0xa438, 0x85f0, 0xa438, 0x9503, 0xa438, 0xd705, 0xa438, 0x40d9, - 0xa438, 0xd70c, 0xa438, 0x6083, 0xa438, 0x0c1f, 0xa438, 0x0d09, - 0xa438, 0xf003, 0xa438, 0x0c1f, 0xa438, 0x0d0a, 0xa438, 0x0cc0, - 0xa438, 0x0d80, 0xa438, 0x1000, 0xa438, 0x104f, 0xa438, 0x1000, - 0xa438, 0x0ef4, 0xa438, 0x8020, 0xa438, 0xd705, 0xa438, 0x40d9, - 0xa438, 0xd704, 0xa438, 0x609f, 0xa438, 0xd70c, 0xa438, 0x6043, - 0xa438, 0x8504, 0xa438, 0xcb94, 0xa438, 0x1000, 0xa438, 0x0ef4, - 0xa438, 0xd706, 0xa438, 0x7fa2, 0xa438, 0x800a, 0xa438, 0x0c03, - 0xa438, 0x1502, 0xa438, 0x0cf0, 0xa438, 0x05a0, 0xa438, 0x9503, - 0xa438, 0xd705, 0xa438, 0x40b9, 0xa438, 0x0c1f, 0xa438, 0x0d00, - 0xa438, 0x8dc0, 0xa438, 0xf005, 0xa438, 0xa190, 0xa438, 0x0c1f, - 0xa438, 0x0d17, 0xa438, 0x8dc0, 0xa438, 0x1000, 0xa438, 0x104f, - 0xa438, 0xd705, 0xa438, 0x39cc, 0xa438, 0x0c7d, 0xa438, 0x1800, - 0xa438, 0x0e67, 0xa438, 0xcb96, 0xa438, 0x0c03, 0xa438, 0x1502, - 0xa438, 0xab05, 0xa438, 0xac04, 0xa438, 0xac08, 0xa438, 0x9503, - 0xa438, 0x0c1f, 0xa438, 0x0d00, 0xa438, 0x8dc0, 0xa438, 0x1000, - 0xa438, 0x104f, 0xa438, 0x1000, 0xa438, 0x1021, 0xa438, 0xd706, - 0xa438, 0x2215, 0xa438, 0x8099, 0xa438, 0x0c03, 0xa438, 0x1502, - 0xa438, 0xae02, 0xa438, 0x9503, 0xa438, 0xd706, 0xa438, 0x6451, - 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0xa438, 0x025f, 0xa438, 0x33ee, 0xa438, 0x8fea, + 0xa438, 0x04bf, 0xa438, 0x5e4e, 0xa438, 0x025f, 0xa438, 0x7ead, + 0xa438, 0x281f, 0xa438, 0x024b, 0xa438, 0x12ae, 0xa438, 0x1abf, + 0xa438, 0x8735, 0xa438, 0x025f, 0xa438, 0x3cbf, 0xa438, 0x8738, + 0xa438, 0x025f, 0xa438, 0x3cee, 0xa438, 0x8fea, 0xa438, 0x03bf, + 0xa438, 0x5e2a, 0xa438, 0x025f, 0xa438, 0x33ee, 0xa438, 0x84e7, + 0xa438, 0x01af, 0xa438, 0x4a74, 0xa438, 0x44ac, 0xa438, 0x0e55, + 0xa438, 0xac0e, 0xa438, 0xbf5e, 0xa438, 0x7502, 0xa438, 0x5f7e, + 0xa438, 0xad2d, 0xa438, 0x0bbf, 0xa438, 0x5e36, 0xa438, 0xe18f, + 0xa438, 0xe902, 0xa438, 0x5f5f, 0xa438, 0xae09, 0xa438, 0xbf5e, + 0xa438, 0x36e1, 0xa438, 0x84e1, 0xa438, 0x025f, 0xa438, 0x5faf, + 0xa438, 0x49cd, 0xa436, 0xb85e, 0xa438, 0x5082, 0xa436, 0xb860, + 0xa438, 0x4575, 0xa436, 0xb862, 0xa438, 0x425F, 0xa436, 0xb864, + 0xa438, 0x0096, 0xa436, 0xb886, 0xa438, 0x4A44, 0xa436, 0xb888, + 0xa438, 0x49c4, 0xa436, 0xb88a, 0xa438, 0xffff, 0xa436, 0xb88c, + 0xa438, 0xffff, 0xa436, 0xb838, 0xa438, 0x003f, 0xb820, 0x0010, + 0xa466, 0x0001, 0xa436, 0x836a, 0xa438, 0x0001, 0xa436, 0x843d, + 0xa438, 0xaf84, 0xa438, 0xafaf, 0xa438, 0x8549, 0xa438, 0xaf85, + 0xa438, 0xb7af, 0xa438, 0x85be, 0xa438, 0xaf87, 0xa438, 0x86af, + 0xa438, 0x878d, 0xa438, 0xaf87, 0xa438, 0x90af, 0xa438, 0x87ee, + 0xa438, 0x0066, 0xa438, 0x0a03, 0xa438, 0x6607, 0xa438, 0x2666, + 0xa438, 0x1c00, 0xa438, 0x660d, 0xa438, 0x0166, 0xa438, 0x1004, + 0xa438, 0x6616, 0xa438, 0x0566, 0xa438, 0x1f06, 0xa438, 0x6a5d, + 0xa438, 0x2766, 0xa438, 0x1900, 0xa438, 0x6625, 0xa438, 0x2466, + 0xa438, 0x2820, 0xa438, 0x662b, 0xa438, 0x0066, 0xa438, 0x3d01, + 0xa438, 0x6640, 0xa438, 0x0266, 0xa438, 0x4324, 0xa438, 0x6646, + 0xa438, 0x0066, 0xa438, 0x4c01, 0xa438, 0x6649, 0xa438, 0x0288, + 0xa438, 0x6a03, 0xa438, 0x8867, 0xa438, 0x0588, 0xa438, 0x7605, + 0xa438, 0x8879, 0xa438, 0x0588, 0xa438, 0x7c05, 0xa438, 0x887f, + 0xa438, 0x0588, 0xa438, 0x8205, 0xa438, 0x8885, 0xa438, 0x0588, + 0xa438, 0x8805, 0xa438, 0x888b, 0xa438, 0x0588, 0xa438, 0x8e05, + 0xa438, 0x8891, 0xa438, 0x1e13, 0xa438, 0xad28, 0xa438, 0x41bf, + 0xa438, 0x64f1, 0xa438, 0x026b, 0xa438, 0x9dad, 0xa438, 0x2803, + 0xa438, 0xaf15, 0xa438, 0xfcbf, 0xa438, 0x65cb, 0xa438, 0x026b, + 0xa438, 0x9d0d, 0xa438, 0x11f6, 0xa438, 0x2fef, 0xa438, 0x31d2, + 0xa438, 0x02bf, 0xa438, 0x886d, 0xa438, 0x026b, 0xa438, 0x52e0, + 0xa438, 0x8202, 0xa438, 0x0d01, 0xa438, 0xf627, 0xa438, 0x1b03, + 0xa438, 0xaa01, 0xa438, 0x82e0, 0xa438, 0x8201, 0xa438, 0x0d01, + 0xa438, 0xf627, 0xa438, 0x1b03, 0xa438, 0xaa07, 0xa438, 0x82bf, + 0xa438, 0x886d, 0xa438, 0x026b, 0xa438, 0x5baf, 0xa438, 0x15f9, + 0xa438, 0xbf65, 0xa438, 0xcb02, 0xa438, 0x6b9d, 0xa438, 0x0d11, + 0xa438, 0xf62f, 0xa438, 0xef31, 0xa438, 0xe08f, 0xa438, 0xf70d, + 0xa438, 0x01f6, 0xa438, 0x271b, 0xa438, 0x03aa, 0xa438, 0x20e1, + 0xa438, 0x8ff4, 0xa438, 0xd000, 0xa438, 0xbf65, 0xa438, 0x8702, + 0xa438, 0x6b7e, 0xa438, 0xe18f, 0xa438, 0xf5bf, 0xa438, 0x658a, + 0xa438, 0x026b, 0xa438, 0x7ee1, 0xa438, 0x8ff6, 0xa438, 0xbf65, + 0xa438, 0x8402, 0xa438, 0x6b7e, 0xa438, 0xaf15, 0xa438, 0xfce1, + 0xa438, 0x8ff1, 0xa438, 0xd000, 0xa438, 0xbf65, 0xa438, 0x8702, + 0xa438, 0x6b7e, 0xa438, 0xe18f, 0xa438, 0xf2bf, 0xa438, 0x658a, + 0xa438, 0x026b, 0xa438, 0x7ee1, 0xa438, 0x8ff3, 0xa438, 0xbf65, + 0xa438, 0x84af, 0xa438, 0x15fc, 0xa438, 0xd107, 0xa438, 0xbf65, + 0xa438, 0xce02, 0xa438, 0x6b7e, 0xa438, 0xd10c, 0xa438, 0xbf65, + 0xa438, 0xd102, 0xa438, 0x6b7e, 0xa438, 0xd103, 0xa438, 0xbf88, + 0xa438, 0x6702, 0xa438, 0x6b7e, 0xa438, 0xd105, 0xa438, 0xbf88, + 0xa438, 0x7002, 0xa438, 0x6b7e, 0xa438, 0xd107, 0xa438, 0xbf88, + 0xa438, 0x7302, 0xa438, 0x6b7e, 0xa438, 0xbf6a, 0xa438, 0x6c02, + 0xa438, 0x6b5b, 0xa438, 0x0262, 0xa438, 0xb5bf, 0xa438, 0x6a00, + 0xa438, 0x026b, 0xa438, 0x5bbf, 0xa438, 0x644e, 0xa438, 0x026b, + 0xa438, 0x9dac, 0xa438, 0x280b, 0xa438, 0xbf64, 0xa438, 0x1202, + 0xa438, 0x6b9d, 0xa438, 0xa105, 0xa438, 0x02ae, 0xa438, 0xecd1, + 0xa438, 0x04bf, 0xa438, 0x65ce, 0xa438, 0x026b, 0xa438, 0x7ed1, + 0xa438, 0x04bf, 0xa438, 0x65d1, 0xa438, 0x026b, 0xa438, 0x7ed1, + 0xa438, 0x02bf, 0xa438, 0x8870, 0xa438, 0x026b, 0xa438, 0x7ed1, + 0xa438, 0x04bf, 0xa438, 0x8873, 0xa438, 0x026b, 0xa438, 0x7eaf, + 0xa438, 0x6272, 0xa438, 0xf60a, 0xa438, 0xf609, 0xa438, 0xaf34, + 0xa438, 0xe302, 0xa438, 0x85c7, 0xa438, 0x0210, 0xa438, 0x6caf, + 0xa438, 0x106b, 0xa438, 0xf8fa, 0xa438, 0xef69, 0xa438, 0xe080, + 0xa438, 0x4cac, 0xa438, 0x2517, 0xa438, 0xe080, 0xa438, 0x40ad, + 0xa438, 0x251a, 0xa438, 0x0285, 0xa438, 0xf6e0, 0xa438, 0x8040, + 0xa438, 0xac25, 0xa438, 0x11bf, 0xa438, 0x876e, 0xa438, 0x026b, + 0xa438, 0x5bae, 0xa438, 0x0902, 0xa438, 0x872d, 0xa438, 0x0287, + 0xa438, 0x6302, 0xa438, 0x8758, 0xa438, 0xef96, 0xa438, 0xfefc, + 0xa438, 0x04f8, 0xa438, 0xe080, 0xa438, 0x19ad, 0xa438, 0x2011, + 0xa438, 0xe08f, 0xa438, 0xe3ac, 0xa438, 0x2005, 0xa438, 0x0286, + 0xa438, 0x13ae, 0xa438, 0x0302, 0xa438, 0x8681, 0xa438, 0x0286, + 0xa438, 0xca02, 0xa438, 0x8758, 0xa438, 0xfc04, 0xa438, 0xf8f9, + 0xa438, 0xef79, 0xa438, 0xfbbf, 0xa438, 0x8771, 0xa438, 0x026b, + 0xa438, 0x9d5c, 0xa438, 0x2000, 0xa438, 0x0d4d, 0xa438, 0xa101, + 0xa438, 0x51bf, 0xa438, 0x8771, 0xa438, 0x026b, 0xa438, 0x9d5c, + 0xa438, 0x07ff, 0xa438, 0xe38f, 0xa438, 0xe41b, 0xa438, 0x319f, + 0xa438, 0x410d, 0xa438, 0x48e3, 0xa438, 0x8fe5, 0xa438, 0x1b31, + 0xa438, 0x9f38, 0xa438, 0xbf87, 0xa438, 0x7402, 0xa438, 0x6b9d, + 0xa438, 0x5c07, 0xa438, 0xffe3, 0xa438, 0x8fe6, 0xa438, 0x1b31, + 0xa438, 0x9f28, 0xa438, 0x0d48, 0xa438, 0xe38f, 0xa438, 0xe71b, + 0xa438, 0x319f, 0xa438, 0x1fbf, 0xa438, 0x8777, 0xa438, 0x026b, + 0xa438, 0x9d5c, 0xa438, 0x07ff, 0xa438, 0xe38f, 0xa438, 0xe81b, + 0xa438, 0x319f, 0xa438, 0x0f0d, 0xa438, 0x48e3, 0xa438, 0x8fe9, + 0xa438, 0x1b31, 0xa438, 0x9f06, 0xa438, 0xee8f, 0xa438, 0xe301, + 0xa438, 0xae04, 0xa438, 0xee8f, 0xa438, 0xe300, 0xa438, 0xffef, + 0xa438, 0x97fd, 0xa438, 0xfc04, 0xa438, 0xf8f9, 0xa438, 0xef79, + 0xa438, 0xfbbf, 0xa438, 0x8771, 0xa438, 0x026b, 0xa438, 0x9d5c, + 0xa438, 0x2000, 0xa438, 0x0d4d, 0xa438, 0xa100, 0xa438, 0x20bf, + 0xa438, 0x8771, 0xa438, 0x026b, 0xa438, 0x9d5c, 0xa438, 0x0600, + 0xa438, 0x0d49, 0xa438, 0xe38f, 0xa438, 0xea1b, 0xa438, 0x319f, + 0xa438, 0x0ebf, 0xa438, 0x877a, 0xa438, 0x026b, 0xa438, 0x5bbf, + 0xa438, 0x8780, 0xa438, 0x026b, 0xa438, 0x5bae, 0xa438, 0x0cbf, + 0xa438, 0x877a, 0xa438, 0x026b, 0xa438, 0x52bf, 0xa438, 0x8780, + 0xa438, 0x026b, 0xa438, 0x52ee, 0xa438, 0x8fe3, 0xa438, 0x00ff, + 0xa438, 0xef97, 0xa438, 0xfdfc, 0xa438, 0x04f8, 0xa438, 0xf9ef, + 0xa438, 0x79fb, 0xa438, 0xbf87, 0xa438, 0x7102, 0xa438, 0x6b9d, + 0xa438, 0x5c20, 0xa438, 0x000d, 0xa438, 0x4da1, 0xa438, 0x014a, + 0xa438, 0xbf87, 0xa438, 0x7102, 0xa438, 0x6b9d, 0xa438, 0x5c07, + 0xa438, 0xffe3, 0xa438, 0x8feb, 0xa438, 0x1b31, 0xa438, 0x9f3a, + 0xa438, 0x0d48, 0xa438, 0xe38f, 0xa438, 0xec1b, 0xa438, 0x319f, + 0xa438, 0x31bf, 0xa438, 0x8774, 0xa438, 0x026b, 0xa438, 0x9de3, + 0xa438, 0x8fed, 0xa438, 0x1b31, 0xa438, 0x9f24, 0xa438, 0x0d48, + 0xa438, 0xe38f, 0xa438, 0xee1b, 0xa438, 0x319f, 0xa438, 0x1bbf, + 0xa438, 0x8777, 0xa438, 0x026b, 0xa438, 0x9de3, 0xa438, 0x8fef, + 0xa438, 0x1b31, 0xa438, 0x9f0e, 0xa438, 0xbf87, 0xa438, 0x7d02, + 0xa438, 0x6b5b, 0xa438, 0xbf87, 0xa438, 0x8302, 0xa438, 0x6b5b, + 0xa438, 0xae00, 0xa438, 0xffef, 0xa438, 0x97fd, 0xa438, 0xfc04, + 0xa438, 0xf8ef, 0xa438, 0x79fb, 0xa438, 0xe080, 0xa438, 0x19ad, + 0xa438, 0x201c, 0xa438, 0xee8f, 0xa438, 0xe300, 0xa438, 0xbf87, + 0xa438, 0x7a02, 0xa438, 0x6b52, 0xa438, 0xbf87, 0xa438, 0x8002, + 0xa438, 0x6b52, 0xa438, 0xbf87, 0xa438, 0x7d02, 0xa438, 0x6b52, + 0xa438, 0xbf87, 0xa438, 0x8302, 0xa438, 0x6b52, 0xa438, 0xffef, + 0xa438, 0x97fc, 0xa438, 0x04f8, 0xa438, 0xe080, 0xa438, 0x40f6, + 0xa438, 0x25e4, 0xa438, 0x8040, 0xa438, 0xfc04, 0xa438, 0xf8e0, + 0xa438, 0x804c, 0xa438, 0xf625, 0xa438, 0xe480, 0xa438, 0x4cfc, + 0xa438, 0x0455, 0xa438, 0xa4ba, 0xa438, 0xf0a6, 0xa438, 0x4af0, + 0xa438, 0xa64c, 0xa438, 0xf0a6, 0xa438, 0x4e66, 0xa438, 0xa4b6, + 0xa438, 0x55a4, 0xa438, 0xb600, 0xa438, 0xac0e, 0xa438, 0x11ac, + 0xa438, 0x0eee, 0xa438, 0x804c, 0xa438, 0x3aaf, 0xa438, 0x07d0, + 0xa438, 0xaf26, 0xa438, 0xd0a2, 0xa438, 0x010e, 0xa438, 0xbf66, + 0xa438, 0x3d02, 0xa438, 0x6b52, 0xa438, 0xbf66, 0xa438, 0x4302, + 0xa438, 0x6b52, 0xa438, 0xae11, 0xa438, 0xbf66, 0xa438, 0x4302, + 0xa438, 0x6b5b, 0xa438, 0xd400, 0xa438, 0x54b4, 0xa438, 0xfebf, + 0xa438, 0x663d, 0xa438, 0x026b, 0xa438, 0x5bd3, 0xa438, 0x0002, + 0xa438, 0x0df6, 0xa438, 0xa204, 0xa438, 0x05e0, 0xa438, 0x8147, + 0xa438, 0xae03, 0xa438, 0xe081, 0xa438, 0x48ac, 0xa438, 0x2302, + 0xa438, 0xae02, 0xa438, 0x68f0, 0xa438, 0x1a10, 0xa438, 0xad2f, + 0xa438, 0x04d1, 0xa438, 0x00ae, 0xa438, 0x05ad, 0xa438, 0x2c02, + 0xa438, 0xd10f, 0xa438, 0x1f00, 0xa438, 0xa204, 0xa438, 0x0739, + 0xa438, 0x08ad, 0xa438, 0x2f02, 0xa438, 0xd100, 0xa438, 0x020e, + 0xa438, 0x1c2b, 0xa438, 0x01ad, 0xa438, 0x3ac9, 0xa438, 0xaf0d, + 0xa438, 0xeea0, 0xa438, 0x0027, 0xa438, 0x021b, 0xa438, 0xebe1, + 0xa438, 0x8fe1, 0xa438, 0xac28, 0xa438, 0x19ee, 0xa438, 0x8fe1, + 0xa438, 0x011f, 0xa438, 0x44bf, 0xa438, 0x6593, 0xa438, 0x026b, + 0xa438, 0x9de5, 0xa438, 0x8fe2, 0xa438, 0x1f44, 0xa438, 0xd102, + 0xa438, 0xbf65, 0xa438, 0x9302, 0xa438, 0x6b7e, 0xa438, 0xe082, + 0xa438, 0xb1ae, 0xa438, 0x49a0, 0xa438, 0x0105, 0xa438, 0x021c, + 0xa438, 0x4dae, 0xa438, 0x41a0, 0xa438, 0x0205, 0xa438, 0x021c, + 0xa438, 0x90ae, 0xa438, 0x39a0, 0xa438, 0x0305, 0xa438, 0x021c, + 0xa438, 0x9dae, 0xa438, 0x31a0, 0xa438, 0x0405, 0xa438, 0x021c, + 0xa438, 0xbcae, 0xa438, 0x29a0, 0xa438, 0x051e, 0xa438, 0x021c, + 0xa438, 0xc9e0, 0xa438, 0x80df, 0xa438, 0xac20, 0xa438, 0x13ac, + 0xa438, 0x2110, 0xa438, 0xac22, 0xa438, 0x0de1, 0xa438, 0x8fe2, + 0xa438, 0xbf65, 0xa438, 0x9302, 0xa438, 0x6b7e, 0xa438, 0xee8f, + 0xa438, 0xe100, 0xa438, 0xae08, 0xa438, 0xa006, 0xa438, 0x0502, + 0xa438, 0x1d07, 0xa438, 0xae00, 0xa438, 0xe082, 0xa438, 0xb1af, + 0xa438, 0x1be9, 0xa438, 0x10bf, 0xa438, 0x4a99, 0xa438, 0xbf4a, + 0xa438, 0x00a8, 0xa438, 0x6afd, 0xa438, 0xad5e, 0xa438, 0xcaad, + 0xa438, 0x5e88, 0xa438, 0xbd2c, 0xa438, 0x99bd, 0xa438, 0x2c33, + 0xa438, 0xbd32, 0xa438, 0x22bd, 0xa438, 0x3211, 0xa438, 0xbd32, + 0xa438, 0x00bd, 0xa438, 0x3277, 0xa438, 0xbd32, 0xa438, 0x66bd, + 0xa438, 0x3255, 0xa438, 0xbd32, 0xa438, 0x44bd, 0xa438, 0x3200, + 0xa436, 0xb818, 0xa438, 0x15c5, 0xa436, 0xb81a, 0xa438, 0x6255, + 0xa436, 0xb81c, 0xa438, 0x34e1, 0xa436, 0xb81e, 0xa438, 0x1068, + 0xa436, 0xb850, 0xa438, 0x07cc, 0xa436, 0xb852, 0xa438, 0x26ca, + 0xa436, 0xb878, 0xa438, 0x0dbf, 0xa436, 0xb884, 0xa438, 0x1BB1, + 0xa436, 0xb832, 0xa438, 0x00ff, 0xa436, 0x0000, 0xa438, 0x0000, + 0xb82e, 0x0000, 0xa436, 0x8023, 0xa438, 0x0000, 0xa436, 0x801E, + 0xa438, 0x0020, 0xB820, 0x0000, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125d_1_2[] = { + 0xb892, 0x0000, 0xB88E, 0xC28F, 0xB890, 0x252D, 0xB88E, 0xC290, + 0xB890, 0xC924, 0xB88E, 0xC291, 0xB890, 0xC92E, 0xB88E, 0xC292, + 0xB890, 0xF626, 0xB88E, 0xC293, 0xB890, 0xF630, 0xB88E, 0xC294, + 0xB890, 0xA328, 0xB88E, 0xC295, 0xB890, 0xA332, 0xB88E, 0xC296, + 0xB890, 0xD72B, 0xB88E, 0xC297, 0xB890, 0xD735, 0xB88E, 0xC298, + 0xB890, 0x8A2E, 0xB88E, 0xC299, 0xB890, 0x8A38, 0xB88E, 0xC29A, + 0xB890, 0xBE32, 0xB88E, 0xC29B, 0xB890, 0xBE3C, 0xB88E, 0xC29C, + 0xB890, 0x7436, 0xB88E, 0xC29D, 0xB890, 0x7440, 0xB88E, 0xC29E, + 0xB890, 0xAD3B, 0xB88E, 0xC29F, 0xB890, 0xAD45, 0xB88E, 0xC2A0, + 0xB890, 0x6640, 0xB88E, 0xC2A1, 0xB890, 0x664A, 0xB88E, 0xC2A2, + 0xB890, 0xA646, 0xB88E, 0xC2A3, 0xB890, 0xA650, 0xB88E, 0xC2A4, + 0xB890, 0x624C, 0xB88E, 0xC2A5, 0xB890, 0x6256, 0xB88E, 0xC2A6, + 0xB890, 0xA453, 0xB88E, 0xC2A7, 0xB890, 0xA45D, 0xB88E, 0xC2A8, + 0xB890, 0x665A, 0xB88E, 0xC2A9, 0xB890, 0x6664, 0xB88E, 0xC2AA, + 0xB890, 0xAC62, 0xB88E, 0xC2AB, 0xB890, 0xAC6C, 0xB88E, 0xC2AC, + 0xB890, 0x746A, 0xB88E, 0xC2AD, 0xB890, 0x7474, 0xB88E, 0xC2AE, + 0xB890, 0xBCFA, 0xB88E, 0xC2AF, 0xB890, 0xBCFD, 0xB88E, 0xC2B0, + 0xB890, 0x79FF, 0xB88E, 0xC2B1, 0xB890, 0x7901, 0xB88E, 0xC2B2, + 0xB890, 0xF703, 0xB88E, 0xC2B3, 0xB890, 0xF706, 0xB88E, 0xC2B4, + 0xB890, 0x7408, 0xB88E, 0xC2B5, 0xB890, 0x740A, 0xB88E, 0xC2B6, + 0xB890, 0xF10C, 0xB88E, 0xC2B7, 0xB890, 0xF10F, 0xB88E, 0xC2B8, + 0xB890, 0x6F10, 0xB88E, 0xC2B9, 0xB890, 0x6F13, 0xB88E, 0xC2BA, + 0xB890, 0xEC15, 0xB88E, 0xC2BB, 0xB890, 0xEC18, 0xB88E, 0xC2BC, + 0xB890, 0x6A1A, 0xB88E, 0xC2BD, 0xB890, 0x6A1C, 0xB88E, 0xC2BE, + 0xB890, 0xE71E, 0xB88E, 0xC2BF, 0xB890, 0xE721, 0xB88E, 0xC2C0, + 0xB890, 0x6424, 0xB88E, 0xC2C1, 0xB890, 0x6425, 0xB88E, 0xC2C2, + 0xB890, 0xE228, 0xB88E, 0xC2C3, 0xB890, 0xE22A, 0xB88E, 0xC2C4, + 0xB890, 0x5F2B, 0xB88E, 0xC2C5, 0xB890, 0x5F2E, 0xB88E, 0xC2C6, + 0xB890, 0xDC31, 0xB88E, 0xC2C7, 0xB890, 0xDC33, 0xB88E, 0xC2C8, + 0xB890, 0x2035, 0xB88E, 0xC2C9, 0xB890, 0x2036, 0xB88E, 0xC2CA, + 0xB890, 0x9F3A, 0xB88E, 0xC2CB, 0xB890, 0x9F3A, 0xB88E, 0xC2CC, + 0xB890, 0x4430, 0xFFFF, 0xFFFF +}; + +static const u16 phy_mcu_ram_code_8125d_1_3[] = { + 0xa436, 0xacca, 0xa438, 0x0104, 0xa436, 0xaccc, 0xa438, 0x8000, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x0fff, + 0xa436, 0xacce, 0xa438, 0xfff8, 0xa436, 0xacd0, 0xa438, 0x0fff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xffff, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xfb47, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xfb4f, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0x6087, 0xa436, 0xacd0, 0xa438, 0x0180, + 0xa436, 0xacce, 0xa438, 0x600f, 0xa436, 0xacd0, 0xa438, 0x0108, + 0xa436, 0xacce, 0xa438, 0x6807, 0xa436, 0xacd0, 0xa438, 0x0100, + 0xa436, 0xacce, 0xa438, 0x688f, 0xa436, 0xacd0, 0xa438, 0x0188, + 0xa436, 0xacce, 0xa438, 0x7027, 0xa436, 0xacd0, 0xa438, 0x0120, + 0xa436, 0xacce, 0xa438, 0x702f, 0xa436, 0xacd0, 0xa438, 0x0128, + 0xa436, 0xacce, 0xa438, 0x7847, 0xa436, 0xacd0, 0xa438, 0x0140, + 0xa436, 0xacce, 0xa438, 0x784f, 0xa436, 0xacd0, 0xa438, 0x0148, + 0xa436, 0xacce, 0xa438, 0x80a7, 0xa436, 0xacd0, 0xa438, 0x01a0, + 0xa436, 0xacce, 0xa438, 0x88af, 0xa436, 0xacd0, 0xa438, 0x01a8, + 0xa436, 0xacce, 0xa438, 0x8067, 0xa436, 0xacd0, 0xa438, 0x0161, + 0xa436, 0xacce, 0xa438, 0x886f, 0xa436, 0xacd0, 0xa438, 0x0169, + 0xa436, 0xacce, 0xa438, 0xfb57, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0xfb5f, 0xa436, 0xacd0, 0xa438, 0x07ff, + 0xa436, 0xacce, 0xa438, 0x6017, 0xa436, 0xacd0, 0xa438, 0x0110, + 0xa436, 0xacce, 0xa438, 0x601f, 0xa436, 0xacd0, 0xa438, 0x0118, + 0xa436, 0xacce, 0xa438, 0x6837, 0xa436, 0xacd0, 0xa438, 0x0130, + 0xa436, 0xacce, 0xa438, 0x683f, 0xa436, 0xacd0, 0xa438, 0x0138, + 0xa436, 0xacce, 0xa438, 0x7097, 0xa436, 0xacd0, 0xa438, 0x0190, + 0xa436, 0xacce, 0xa438, 0x705f, 0xa436, 0xacd0, 0xa438, 0x0158, + 0xa436, 0xacce, 0xa438, 0x7857, 0xa436, 0xacd0, 0xa438, 0x0150, + 0xa436, 0xacce, 0xa438, 0x789f, 0xa436, 0xacd0, 0xa438, 0x0198, + 0xa436, 0xacce, 0xa438, 0x90b7, 0xa436, 0xacd0, 0xa438, 0x01b0, + 0xa436, 0xacce, 0xa438, 0x98bf, 0xa436, 0xacd0, 0xa438, 0x01b8, + 0xa436, 0xacce, 0xa438, 0x9077, 0xa436, 0xacd0, 0xa438, 0x1171, + 0xa436, 0xacce, 0xa438, 0x987f, 0xa436, 0xacd0, 0xa438, 0x1179, + 0xa436, 0xacca, 0xa438, 0x0004, 0xa436, 0xacc6, 0xa438, 0x0015, + 0xa436, 0xacc8, 0xa438, 0xc000, 0xa436, 0xacc8, 0xa438, 0x0000, 0xFFFF, 0xFFFF }; -static const u16 phy_mcu_ram_code_8126a_1_2[] = { - 0xB87C, 0x8a32, 0xB87E, 0x0400, 0xB87C, 0x8376, 0xB87E, 0x0300, - 0xce00, 0x6CAF, 0xB87C, 0x8301, 0xB87E, 0x1133, 0xB87C, 0x8105, - 0xB87E, 0xa000, 0xB87C, 0x8148, 0xB87E, 0xa000, 0xa436, 0x81d8, - 0xa438, 0x5865, 0xacf8, 0xCCC0, 0xac90, 0x52B0, 0xad2C, 0x8000, - 0xB87C, 0x83e6, 0xB87E, 0x4A0E, 0xB87C, 0x83d2, 0xB87E, 0x0A0E, - 0xB87C, 0x80a0, 0xB87E, 0xB8B6, 0xB87C, 0x805e, 0xB87E, 0xB8B6, - 0xB87C, 0x8057, 0xB87E, 0x305A, 0xB87C, 0x8099, 0xB87E, 0x305A, - 0xB87C, 0x8052, 0xB87E, 0x3333, 0xB87C, 0x8094, 0xB87E, 0x3333, - 0xB87C, 0x807F, 0xB87E, 0x7975, 0xB87C, 0x803D, 0xB87E, 0x7975, - 0xB87C, 0x8036, 0xB87E, 0x305A, 0xB87C, 0x8078, 0xB87E, 0x305A, - 0xB87C, 0x8031, 0xB87E, 0x3335, 0xB87C, 0x8073, 0xB87E, 0x3335, - 0xa436, 0x81D8, 0xa438, 0x5865, 0xB87C, 0x867c, 0xB87E, 0x0617, - 0xad94, 0x0092, 0xB87C, 0x89B1, 0xB87E, 0x5050, 0xB87C, 0x86E0, - 0xB87E, 0x809A, 0xB87C, 0x86E2, 0xB87E, 0xB34D, 0xB87C, 0x8FD2, - 0xB87E, 0x004B, 0xB87C, 0x8691, 0xB87E, 0x007D, 0xB87E, 0x00AF, - 0xB87E, 0x00E1, 0xB87E, 0x00FF, 0xB87C, 0x867F, 0xB87E, 0x0201, - 0xB87E, 0x0201, 0xB87E, 0x0201, 0xB87E, 0x0201, 0xB87E, 0x0201, - 0xB87E, 0x0201, 0xB87C, 0x86DA, 0xB87E, 0xCDCD, 0xB87E, 0xE6CD, - 0xB87E, 0xCDCD, 0xB87C, 0x8FE8, 0xB87E, 0x0368, 0xB87E, 0x033F, - 0xB87E, 0x1046, 0xB87E, 0x147D, 0xB87E, 0x147D, 0xB87E, 0x147D, - 0xB87E, 0x0368, 0xB87E, 0x033F, 0xB87E, 0x1046, 0xB87E, 0x147D, - 0xB87E, 0x147D, 0xB87E, 0x147D, 0xa436, 0x80dd, 0xa438, 0xf0AB, - 0xa436, 0x80df, 0xa438, 0xC009, 0xa436, 0x80e7, 0xa438, 0x401E, - 0xa436, 0x80e1, 0xa438, 0x120A, 0xa436, 0x86f2, 0xa438, 0x5094, - 0xa436, 0x8701, 0xa438, 0x5094, 0xa436, 0x80f1, 0xa438, 0x30CC, - 0xa436, 0x80f3, 0xa438, 0x0001, 0xa436, 0x80f5, 0xa438, 0x330B, - 0xa436, 0x80f8, 0xa438, 0xCB76, 0xa436, 0x8105, 0xa438, 0xf0D3, - 0xa436, 0x8107, 0xa438, 0x0002, 0xa436, 0x8109, 0xa438, 0xff0B, - 0xa436, 0x810c, 0xa438, 0xC86D, 0xB87C, 0x8a32, 0xB87E, 0x0400, - 0xa6f8, 0x0000, 0xa6f8, 0x0000, 0xa436, 0x81bc, 0xa438, 0x1300, - 0xa846, 0x2410, 0xa86A, 0x0801, 0xa85C, 0x9680, 0xa436, 0x841D, - 0xa438, 0x4A28, 0xa436, 0x8016, 0xa438, 0xBE05, 0xBF9C, 0x004A, - 0xBF96, 0x41FA, 0xBF9A, 0xDC81, 0xa436, 0x8018, 0xa438, 0x0700, - 0xa436, 0x8ff4, 0xa438, 0x01AE, 0xa436, 0x8fef, 0xa438, 0x0172, - 0xa438, 0x00dc, 0xc842, 0x0002, 0xFFFF, 0xFFFF +static const u16 phy_mcu_ram_code_8125bp_1_1[] = { + 0xa436, 0x8024, 0xa438, 0x3600, 0xa436, 0xB82E, 0xa438, 0x0001, + 0xb820, 0x0090, 0xa436, 0xA016, 0xa438, 0x0000, 0xa436, 0xA012, + 0xa438, 0x0000, 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, + 0xa438, 0x1800, 0xa438, 0x8014, 0xa438, 0x1800, 0xa438, 0x8018, + 0xa438, 0x1800, 0xa438, 0x801c, 0xa438, 0x1800, 0xa438, 0x8020, + 0xa438, 0x1800, 0xa438, 0x8024, 0xa438, 0x1800, 0xa438, 0x8028, + 0xa438, 0x1800, 0xa438, 0x8028, 0xa438, 0xdb20, 0xa438, 0xd501, + 0xa438, 0x1800, 0xa438, 0x034c, 0xa438, 0xdb10, 0xa438, 0xd501, + 0xa438, 0x1800, 0xa438, 0x032c, 0xa438, 0x8620, 0xa438, 0xa480, + 0xa438, 0x1800, 0xa438, 0x1cfe, 0xa438, 0xbf40, 0xa438, 0xd703, + 0xa438, 0x1800, 0xa438, 0x0ce9, 0xa438, 0x9c10, 0xa438, 0x9f40, + 0xa438, 0x1800, 0xa438, 0x137a, 0xa438, 0x9f20, 0xa438, 0x9f40, + 0xa438, 0x1800, 0xa438, 0x16c4, 0xa436, 0xA026, 0xa438, 0xffff, + 0xa436, 0xA024, 0xa438, 0xffff, 0xa436, 0xA022, 0xa438, 0x16c3, + 0xa436, 0xA020, 0xa438, 0x1379, 0xa436, 0xA006, 0xa438, 0x0ce8, + 0xa436, 0xA004, 0xa438, 0x1cfd, 0xa436, 0xA002, 0xa438, 0x032b, + 0xa436, 0xA000, 0xa438, 0x034b, 0xa436, 0xA008, 0xa438, 0x3f00, + 0xa436, 0xA016, 0xa438, 0x0020, 0xa436, 0xA012, 0xa438, 0x0000, + 0xa436, 0xA014, 0xa438, 0x1800, 0xa438, 0x8010, 0xa438, 0x1800, + 0xa438, 0x8018, 0xa438, 0x1800, 0xa438, 0x8021, 0xa438, 0x1800, + 0xa438, 0x802b, 0xa438, 0x1800, 0xa438, 0x8055, 0xa438, 0x1800, + 0xa438, 0x805a, 0xa438, 0x1800, 0xa438, 0x805e, 0xa438, 0x1800, + 0xa438, 0x8062, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0xcb11, + 0xa438, 0xd1b9, 0xa438, 0xd05b, 0xa438, 0x0000, 0xa438, 0x1800, + 0xa438, 0x0284, 0xa438, 0x0000, 0xa438, 0x0000, 0xa438, 0xd700, + 0xa438, 0x5fb4, 0xa438, 0x5f95, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0x1800, 0xa438, 0x02b7, 0xa438, 0x0000, 0xa438, 0x0000, + 0xa438, 0xcb21, 0xa438, 0x1000, 0xa438, 0x0b34, 0xa438, 0xd71f, + 0xa438, 0x5f5e, 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x0322, + 0xa438, 0xd700, 0xa438, 0xd113, 0xa438, 0xd040, 0xa438, 0x1000, + 0xa438, 0x0a57, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xd700, + 0xa438, 0x6065, 0xa438, 0xd122, 0xa438, 0xf002, 0xa438, 0xd122, + 0xa438, 0xd040, 0xa438, 0x1000, 0xa438, 0x0b53, 0xa438, 0xa008, + 0xa438, 0xd704, 0xa438, 0x4052, 0xa438, 0xa002, 0xa438, 0xd704, + 0xa438, 0x4054, 0xa438, 0xa740, 0xa438, 0x1000, 0xa438, 0x0a57, + 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0xcb9b, 0xa438, 0xd110, + 0xa438, 0xd040, 0xa438, 0x1000, 0xa438, 0x0c01, 0xa438, 0x1000, + 0xa438, 0x0a57, 0xa438, 0xd700, 0xa438, 0x5fb4, 0xa438, 0x801a, + 0xa438, 0x1000, 0xa438, 0x0a57, 0xa438, 0xd704, 0xa438, 0x7fb9, + 0xa438, 0x1800, 0xa438, 0x088d, 0xa438, 0xcb62, 0xa438, 0xd700, + 0xa438, 0x8880, 0xa438, 0x1800, 0xa438, 0x06cb, 0xa438, 0xbe02, + 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x002c, 0xa438, 0xbe04, + 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x002c, 0xa438, 0xbe08, + 0xa438, 0x0000, 0xa438, 0x1800, 0xa438, 0x002c, 0xa436, 0xA10E, + 0xa438, 0x802a, 0xa436, 0xA10C, 0xa438, 0x8026, 0xa436, 0xA10A, + 0xa438, 0x8022, 0xa436, 0xA108, 0xa438, 0x06ca, 0xa436, 0xA106, + 0xa438, 0x086f, 0xa436, 0xA104, 0xa438, 0x0321, 0xa436, 0xA102, + 0xa438, 0x02b5, 0xa436, 0xA100, 0xa438, 0x0283, 0xa436, 0xA110, + 0xa438, 0x001f, 0xb820, 0x0010, 0xb82e, 0x0000, 0xa436, 0x8024, + 0xa438, 0x0000, 0xB820, 0x0000, 0xFFFF, 0xFFFF }; -static const u16 phy_mcu_ram_code_8126a_1_3[] = { - 0xb892, 0x0000, 0xB88E, 0xC236, 0xB890, 0x1A1C, 0xB88E, 0xC238, - 0xB890, 0x1C1C, 0xB890, 0x1C1C, 0xB890, 0x2D2D, 0xB890, 0x2D2D, - 0xB890, 0x2D2A, 0xB890, 0x2A2A, 0xB890, 0x2A2A, 0xB890, 0x2A19, - 0xB88E, 0xC272, 0xB890, 0x8484, 0xB890, 0x8484, 0xB890, 0x84B4, - 0xB890, 0xB4B4, 0xB890, 0xB4B4, 0xB890, 0xF8F8, 0xB890, 0xF8F8, - 0xB890, 0xF8F8, 0xB88E, 0xC000, 0xB890, 0x0303, 0xB890, 0x0405, - 0xB890, 0x0608, 0xB890, 0x0A0B, 0xB890, 0x0E11, 0xB890, 0x1519, - 0xB890, 0x2028, 0xB890, 0x3503, 0xB890, 0x0304, 0xB890, 0x0405, - 0xB890, 0x0606, 0xB890, 0x0708, 0xB890, 0x090A, 0xB890, 0x0B0D, - 0xB890, 0x0F11, 0xB890, 0x1315, 0xB890, 0x181A, 0xB890, 0x2029, - 0xB890, 0x2F36, 0xB890, 0x3D43, 0xB890, 0x0101, 0xB890, 0x0102, - 0xB890, 0x0202, 0xB890, 0x0303, 0xB890, 0x0405, 0xB890, 0x0607, - 0xB890, 0x090A, 0xB890, 0x0C0E, 0xB88E, 0xC038, 0xB890, 0x6AE1, - 0xB890, 0x8E6B, 0xB890, 0xA767, 0xB890, 0x01EF, 0xB890, 0x5A63, - 0xB890, 0x2B99, 0xB890, 0x7F5D, 0xB890, 0x361F, 0xB890, 0xA127, - 0xB890, 0xB558, 0xB890, 0x11C3, 0xB890, 0x7D85, 0xB890, 0xBAC5, - 0xB890, 0xE691, 0xB890, 0x8F79, 0xB890, 0x3164, 0xB890, 0x3293, - 0xB890, 0xB80D, 0xB890, 0xE2B7, 0xB890, 0x0D62, 0xB890, 0x4F85, - 0xB890, 0xC919, 0xB890, 0x78F3, 0xB890, 0x77FF, 0xB890, 0xBD9E, - 0xB890, 0x69D6, 0xB890, 0x6DA4, 0xB890, 0x0CC5, 0xB88E, 0xC1D2, - 0xB890, 0x2425, 0xB890, 0x2627, 0xB890, 0x2829, 0xB890, 0x2A2B, - 0xB890, 0x2C2D, 0xB890, 0x2E2F, 0xB890, 0x3031, 0xB890, 0x3233, - 0xB890, 0x2323, 0xB890, 0x2424, 0xB890, 0x2525, 0xB890, 0x2626, - 0xB890, 0x2727, 0xB890, 0x2828, 0xB890, 0x2929, 0xB890, 0x2A2A, - 0xB890, 0x2B2C, 0xB890, 0x2C2D, 0xB890, 0x2D2E, 0xB890, 0x2E2F, - 0xB890, 0x2F30, 0xB890, 0x1A1B, 0xB890, 0x1D1E, 0xB890, 0x1F20, - 0xB890, 0x2123, 0xB890, 0x2425, 0xB890, 0x2628, 0xB890, 0x292A, - 0xB890, 0x2B2C, 0xB890, 0x2E12, 0xB88E, 0xC09A, 0xB890, 0xD3D3, - 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xB890, 0xD3D3, - 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xB890, 0xD3D3, 0xFFFF, 0xFFFF +static const u16 phy_mcu_ram_code_8125bp_1_2[] = { + 0xb892, 0x0000, 0xb88e, 0xC201, 0xb890, 0x2C01, 0xb890, 0xCD02, + 0xb890, 0x0602, 0xb890, 0x5502, 0xb890, 0xB903, 0xb890, 0x3303, + 0xb890, 0xC204, 0xb890, 0x6605, 0xb890, 0x1F05, 0xb890, 0xEE06, + 0xb890, 0xD207, 0xb890, 0xCC08, 0xb890, 0xDA09, 0xb890, 0xFF0B, + 0xb890, 0x380C, 0xb890, 0x87F3, 0xb88e, 0xC27F, 0xb890, 0x2B66, + 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x6666, + 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x6666, 0xb890, 0x66C2, + 0xb88e, 0xC26F, 0xb890, 0x751D, 0xb890, 0x1D1F, 0xb890, 0x2022, + 0xb890, 0x2325, 0xb890, 0x2627, 0xb890, 0x2829, 0xb890, 0x2929, + 0xb890, 0x2A2A, 0xb890, 0x2B66, 0xB820, 0x0000, 0xFFFF, 0xFFFF }; static void @@ -10209,8 +11994,7 @@ rtl8125_real_set_phy_mcu_8125b_1(struct net_device *dev) { rtl8125_set_phy_mcu_ram_code(dev, phy_mcu_ram_code_8125b_1, - ARRAY_SIZE(phy_mcu_ram_code_8125b_1) - ); + ARRAY_SIZE(phy_mcu_ram_code_8125b_1)); } static void @@ -10230,8 +12014,7 @@ rtl8125_real_set_phy_mcu_8125b_2(struct net_device *dev) { rtl8125_set_phy_mcu_ram_code(dev, phy_mcu_ram_code_8125b_2, - ARRAY_SIZE(phy_mcu_ram_code_8125b_2) - ); + ARRAY_SIZE(phy_mcu_ram_code_8125b_2)); } static void @@ -10247,52 +12030,83 @@ rtl8125_set_phy_mcu_8125b_2(struct net_device *dev) } static void -rtl8125_real_set_phy_mcu_8126a_1_1(struct net_device *dev) +rtl8125_real_set_phy_mcu_8125d_1_1(struct net_device *dev) { rtl8125_set_phy_mcu_ram_code(dev, - phy_mcu_ram_code_8126a_1_1, - ARRAY_SIZE(phy_mcu_ram_code_8126a_1_1) - ); + phy_mcu_ram_code_8125d_1_1, + ARRAY_SIZE(phy_mcu_ram_code_8125d_1_1)); } static void -rtl8125_real_set_phy_mcu_8126a_1_2(struct net_device *dev) +rtl8125_real_set_phy_mcu_8125d_1_2(struct net_device *dev) { rtl8125_set_phy_mcu_ram_code(dev, - phy_mcu_ram_code_8126a_1_2, - ARRAY_SIZE(phy_mcu_ram_code_8126a_1_2) - ); + phy_mcu_ram_code_8125d_1_2, + ARRAY_SIZE(phy_mcu_ram_code_8125d_1_2)); } static void -rtl8125_real_set_phy_mcu_8126a_1_3(struct net_device *dev) +rtl8125_real_set_phy_mcu_8125d_1_3(struct net_device *dev) { rtl8125_set_phy_mcu_ram_code(dev, - phy_mcu_ram_code_8126a_1_3, - ARRAY_SIZE(phy_mcu_ram_code_8126a_1_3) - ); + phy_mcu_ram_code_8125d_1_3, + ARRAY_SIZE(phy_mcu_ram_code_8125d_1_3)); } static void -rtl8125_set_phy_mcu_8126a_1(struct net_device *dev) +rtl8125_set_phy_mcu_8125d_1(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); rtl8125_set_phy_mcu_patch_request(tp); - rtl8125_real_set_phy_mcu_8126a_1_1(dev); + rtl8125_real_set_phy_mcu_8125d_1_1(dev); + + rtl8125_clear_phy_mcu_patch_request(tp); + + rtl8125_set_phy_mcu_patch_request(tp); + + rtl8125_real_set_phy_mcu_8125d_1_2(dev); + + rtl8125_clear_phy_mcu_patch_request(tp); + + rtl8125_set_phy_mcu_patch_request(tp); + + rtl8125_real_set_phy_mcu_8125d_1_3(dev); rtl8125_clear_phy_mcu_patch_request(tp); +} + +static void +rtl8125_real_set_phy_mcu_8125bp_1_1(struct net_device *dev) +{ + rtl8125_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8125bp_1_1, + ARRAY_SIZE(phy_mcu_ram_code_8125bp_1_1)); +} + +static void +rtl8125_real_set_phy_mcu_8125bp_1_2(struct net_device *dev) +{ + rtl8125_set_phy_mcu_ram_code(dev, + phy_mcu_ram_code_8125bp_1_2, + ARRAY_SIZE(phy_mcu_ram_code_8125bp_1_2)); +} + +static void +rtl8125_set_phy_mcu_8125bp_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); rtl8125_set_phy_mcu_patch_request(tp); - rtl8125_real_set_phy_mcu_8126a_1_2(dev); + rtl8125_real_set_phy_mcu_8125bp_1_1(dev); rtl8125_clear_phy_mcu_patch_request(tp); rtl8125_set_phy_mcu_patch_request(tp); - rtl8125_real_set_phy_mcu_8126a_1_3(dev); + rtl8125_real_set_phy_mcu_8125bp_1_2(dev); rtl8125_clear_phy_mcu_patch_request(tp); } @@ -10303,8 +12117,11 @@ rtl8125_init_hw_phy_mcu(struct net_device *dev) struct rtl8125_private *tp = netdev_priv(dev); u8 require_disable_phy_disable_mode = FALSE; - if (tp->NotWrRamCodeToMicroP == TRUE) return; - if (rtl8125_check_hw_phy_mcu_code_ver(dev)) return; + if (tp->NotWrRamCodeToMicroP == TRUE) + return; + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + return; if (HW_SUPPORT_CHECK_PHY_DISABLE_MODE(tp) && rtl8125_is_in_phy_disable_mode(dev)) require_disable_phy_disable_mode = TRUE; @@ -10328,7 +12145,16 @@ rtl8125_init_hw_phy_mcu(struct net_device *dev) rtl8125_set_phy_mcu_8125b_2(dev); break; case CFG_METHOD_8: - rtl8125_set_phy_mcu_8126a_1(dev); + rtl8125_set_phy_mcu_8125bp_1(dev); + break; + case CFG_METHOD_9: + /* nothing to do */ + break; + case CFG_METHOD_10: + rtl8125_set_phy_mcu_8125d_1(dev); + break; + case CFG_METHOD_11: + /* nothing to do */ break; } @@ -10348,7 +12174,7 @@ rtl8125_enable_phy_aldps(struct rtl8125_private *tp) { //enable aldps //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) - SetEthPhyOcpBit(tp, 0xA430, BIT_2); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA430, BIT_2); } static void @@ -10356,133 +12182,113 @@ rtl8125_hw_phy_config_8125a_1(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - ClearAndSetEthPhyOcpBit(tp, - 0xAD40, - 0x03FF, - 0x84 - ); - - SetEthPhyOcpBit(tp, 0xAD4E, BIT_4); - ClearAndSetEthPhyOcpBit(tp, - 0xAD16, - 0x03FF, - 0x0006 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD32, - 0x003F, - 0x0006 - ); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_12); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xAC8A, - BIT_15|BIT_14|BIT_13|BIT_12, - BIT_14|BIT_13|BIT_12 - ); - SetEthPhyOcpBit(tp, 0xAD18, BIT_10); - SetEthPhyOcpBit(tp, 0xAD1A, 0x3FF); - SetEthPhyOcpBit(tp, 0xAD1C, 0x3FF); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xC400 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EB); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0x0700, - 0x0300 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F8); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x1C00 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F1); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x3000 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80FE); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xA500 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8102); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x5000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8105); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x3300 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8100); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x7000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8104); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xF000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8106); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x6500 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xED00 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); - SetEthPhyOcpBit(tp, 0xA438, BIT_8); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80E1); - ClearEthPhyOcpBit(tp, 0xA438, BIT_8); - - ClearAndSetEthPhyOcpBit(tp, - 0xBF06, - 0x003F, - 0x38 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x819F); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xD0B6); - - mdio_direct_write_phy_ocp(tp, 0xBC34, 0x5555); - ClearAndSetEthPhyOcpBit(tp, - 0xBF0A, - BIT_11|BIT_10|BIT_9, - BIT_11|BIT_9 - ); - - ClearEthPhyOcpBit(tp, 0xA5C0, BIT_10); - - SetEthPhyOcpBit(tp, 0xA442, BIT_11); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD40, + 0x03FF, + 0x84); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xAD4E, BIT_4); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD16, + 0x03FF, + 0x0006); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD32, + 0x003F, + 0x0006); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAC08, BIT_12); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAC08, BIT_8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAC8A, + BIT_15|BIT_14|BIT_13|BIT_12, + BIT_14|BIT_13|BIT_12); + rtl8125_set_eth_phy_ocp_bit(tp, 0xAD18, BIT_10); + rtl8125_set_eth_phy_ocp_bit(tp, 0xAD1A, 0x3FF); + rtl8125_set_eth_phy_ocp_bit(tp, 0xAD1C, 0x3FF); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xC400); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EB); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x0700, + 0x0300); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1C00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80F1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x3000); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80FE); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xA500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8102); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8105); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x3300); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8100); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x7000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8104); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xF000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8106); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x6500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xED00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA438, BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80E1); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_8); + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBF06, + 0x003F, + 0x38); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x819F); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xD0B6); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBC34, 0x5555); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBF0A, + BIT_11|BIT_10|BIT_9, + BIT_11|BIT_9); + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA5C0, BIT_10); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); //enable aldps //GPHY OCP 0xA430 bit[2] = 0x1 (en_aldps) - if (aspm) { - if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - rtl8125_enable_phy_aldps(tp); - } - } + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); } static void @@ -10490,198 +12296,189 @@ rtl8125_hw_phy_config_8125a_2(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - SetEthPhyOcpBit(tp, 0xAD4E, BIT_4); - ClearAndSetEthPhyOcpBit(tp, - 0xAD16, - 0x03FF, - 0x03FF - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD32, - 0x003F, - 0x0006 - ); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_12); - ClearEthPhyOcpBit(tp, 0xAC08, BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xACC0, - BIT_1|BIT_0, - BIT_1 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD40, - BIT_7|BIT_6|BIT_5, - BIT_6 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD40, - BIT_2|BIT_1|BIT_0, - BIT_2 - ); - ClearEthPhyOcpBit(tp, 0xAC14, BIT_7); - ClearEthPhyOcpBit(tp, 0xAC80, BIT_9|BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xAC5E, - BIT_2|BIT_1|BIT_0, - BIT_1 - ); - mdio_direct_write_phy_ocp(tp, 0xAD4C, 0x00A8); - mdio_direct_write_phy_ocp(tp, 0xAC5C, 0x01FF); - ClearAndSetEthPhyOcpBit(tp, - 0xAC8A, - BIT_7|BIT_6|BIT_5|BIT_4, - BIT_5|BIT_4 - ); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8157); - ClearAndSetEthPhyOcpBit(tp, - 0xB87E, - 0xFF00, - 0x0500 - ); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8159); - ClearAndSetEthPhyOcpBit(tp, - 0xB87E, - 0xFF00, - 0x0700 - ); - - - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80A2); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x809C); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B3); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0043); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00A7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00D6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00EC); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00F6); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FB); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FD); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FF); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x00BB); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0058); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0029); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0013); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0009); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0004); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0002); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8257); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x020F); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x7843); + rtl8125_set_eth_phy_ocp_bit(tp, 0xAD4E, BIT_4); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD16, + 0x03FF, + 0x03FF); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD32, + 0x003F, + 0x0006); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAC08, BIT_12); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAC08, BIT_8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xACC0, + BIT_1|BIT_0, + BIT_1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD40, + BIT_7|BIT_6|BIT_5, + BIT_6); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD40, + BIT_2|BIT_1|BIT_0, + BIT_2); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAC14, BIT_7); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAC80, BIT_9|BIT_8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAC5E, + BIT_2|BIT_1|BIT_0, + BIT_1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAD4C, 0x00A8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC5C, 0x01FF); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAC8A, + BIT_7|BIT_6|BIT_5|BIT_4, + BIT_5|BIT_4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8157); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8159); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0700); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80A2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x809C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0153); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81B3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0043); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00A7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00D6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00EC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00F6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FB); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FD); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00FF); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00BB); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0058); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0029); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0013); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0009); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0004); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8257); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x020F); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80EA); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7843); rtl8125_set_phy_mcu_patch_request(tp); - ClearEthPhyOcpBit(tp, 0xB896, BIT_0); - ClearEthPhyOcpBit(tp, 0xB892, 0xFF00); - - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC091); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC092); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1214); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC094); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1516); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC096); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x171B); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC098); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1B1C); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1F1F); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09C); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2021); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2224); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A0); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A2); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A4); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC018); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0AF2); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0D4A); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01C); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0F26); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x118D); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC020); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x14F3); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC022); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x175A); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC024); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x19C0); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC026); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1C26); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC089); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6050); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x5F6E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08C); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC090); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); - - SetEthPhyOcpBit(tp, 0xB896, BIT_0); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB896, BIT_0); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB892, 0xFF00); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC091); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC092); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1214); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC094); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1516); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC096); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x171B); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC098); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1B1C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1F1F); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x2021); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC09E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x2224); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC0A4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x2424); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC018); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0AF2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0D4A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0F26); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC01E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x118D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC020); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x14F3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC022); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x175A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC024); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x19C0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC026); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1C26); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC089); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x6050); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x5F6E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC08E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E6E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC090); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x6E12); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xB896, BIT_0); rtl8125_clear_phy_mcu_patch_request(tp); - SetEthPhyOcpBit(tp, 0xD068, BIT_13); + rtl8125_set_eth_phy_ocp_bit(tp, 0xD068, BIT_13); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A2); - SetEthPhyOcpBit(tp, 0xA438, BIT_8); - ClearAndSetEthPhyOcpBit(tp, - 0xB54C, - 0xFF00, - 0xDB00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81A2); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA438, BIT_8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB54C, + 0xFF00, + 0xDB00); - ClearEthPhyOcpBit(tp, 0xA454, BIT_0); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA454, BIT_0); - SetEthPhyOcpBit(tp, 0xA5D4, BIT_5); - ClearEthPhyOcpBit(tp, 0xAD4E, BIT_4); - ClearEthPhyOcpBit(tp, 0xA86A, BIT_0); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA5D4, BIT_5); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAD4E, BIT_4); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA86A, BIT_0); - SetEthPhyOcpBit(tp, 0xA442, BIT_11); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); if (tp->RequirePhyMdiSwapPatch) { @@ -10698,152 +12495,128 @@ rtl8125_hw_phy_config_8125a_2(struct net_device *dev) u16 rg_lpf_cap_p2; u16 rg_lpf_cap_p3; - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0007, - 0x0001 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0000 - ); - adccal_offset_p0 = mdio_direct_read_phy_ocp(tp, 0xD06A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0007, + 0x0001); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0000); + adccal_offset_p0 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xD06A); adccal_offset_p0 &= 0x07FF; - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0008 - ); - adccal_offset_p1 = mdio_direct_read_phy_ocp(tp, 0xD06A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0008); + adccal_offset_p1 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xD06A); adccal_offset_p1 &= 0x07FF; - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0010 - ); - adccal_offset_p2 = mdio_direct_read_phy_ocp(tp, 0xD06A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0010); + adccal_offset_p2 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xD06A); adccal_offset_p2 &= 0x07FF; - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0018 - ); - adccal_offset_p3 = mdio_direct_read_phy_ocp(tp, 0xD06A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0018); + adccal_offset_p3 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xD06A); adccal_offset_p3 &= 0x07FF; - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0000 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD06A, - 0x07FF, - adccal_offset_p3 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0008 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD06A, - 0x07FF, - adccal_offset_p2 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0010 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD06A, - 0x07FF, - adccal_offset_p1 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD068, - 0x0018, - 0x0018 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xD06A, - 0x07FF, - adccal_offset_p0 - ); - - - rg_lpf_cap_xg_p0 = mdio_direct_read_phy_ocp(tp, 0xBD5A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0000); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p3); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0008); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p2); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0010); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD068, + 0x0018, + 0x0018); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xD06A, + 0x07FF, + adccal_offset_p0); + + + rg_lpf_cap_xg_p0 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBD5A); rg_lpf_cap_xg_p0 &= 0x001F; - rg_lpf_cap_xg_p1 = mdio_direct_read_phy_ocp(tp, 0xBD5A); + rg_lpf_cap_xg_p1 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBD5A); rg_lpf_cap_xg_p1 &= 0x1F00; - rg_lpf_cap_xg_p2 = mdio_direct_read_phy_ocp(tp, 0xBD5C); + rg_lpf_cap_xg_p2 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBD5C); rg_lpf_cap_xg_p2 &= 0x001F; - rg_lpf_cap_xg_p3 = mdio_direct_read_phy_ocp(tp, 0xBD5C); + rg_lpf_cap_xg_p3 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBD5C); rg_lpf_cap_xg_p3 &= 0x1F00; - rg_lpf_cap_p0 = mdio_direct_read_phy_ocp(tp, 0xBC18); + rg_lpf_cap_p0 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBC18); rg_lpf_cap_p0 &= 0x001F; - rg_lpf_cap_p1 = mdio_direct_read_phy_ocp(tp, 0xBC18); + rg_lpf_cap_p1 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBC18); rg_lpf_cap_p1 &= 0x1F00; - rg_lpf_cap_p2 = mdio_direct_read_phy_ocp(tp, 0xBC1A); + rg_lpf_cap_p2 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBC1A); rg_lpf_cap_p2 &= 0x001F; - rg_lpf_cap_p3 = mdio_direct_read_phy_ocp(tp, 0xBC1A); + rg_lpf_cap_p3 = rtl8125_mdio_direct_read_phy_ocp(tp, 0xBC1A); rg_lpf_cap_p3 &= 0x1F00; - ClearAndSetEthPhyOcpBit(tp, - 0xBD5A, - 0x001F, - rg_lpf_cap_xg_p3 >> 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBD5A, - 0x1F00, - rg_lpf_cap_xg_p2 << 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBD5C, - 0x001F, - rg_lpf_cap_xg_p1 >> 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBD5C, - 0x1F00, - rg_lpf_cap_xg_p0 << 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBC18, - 0x001F, - rg_lpf_cap_p3 >> 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBC18, - 0x1F00, - rg_lpf_cap_p2 << 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBC1A, - 0x001F, - rg_lpf_cap_p1 >> 8 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xBC1A, - 0x1F00, - rg_lpf_cap_p0 << 8 - ); - } - - - SetEthPhyOcpBit(tp, 0xA424, BIT_3); - - - if (aspm) { - if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - rtl8125_enable_phy_aldps(tp); - } - } + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBD5A, + 0x001F, + rg_lpf_cap_xg_p3 >> 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBD5A, + 0x1F00, + rg_lpf_cap_xg_p2 << 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBD5C, + 0x001F, + rg_lpf_cap_xg_p1 >> 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBD5C, + 0x1F00, + rg_lpf_cap_xg_p0 << 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC18, + 0x001F, + rg_lpf_cap_p3 >> 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC18, + 0x1F00, + rg_lpf_cap_p2 << 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC1A, + 0x001F, + rg_lpf_cap_p1 >> 8); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC1A, + 0x1F00, + rg_lpf_cap_p0 << 8); + } + + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA424, BIT_3); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); } static void @@ -10851,284 +12624,269 @@ rtl8125_hw_phy_config_8125b_1(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - SetEthPhyOcpBit(tp, 0xA442, BIT_11); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); - SetEthPhyOcpBit(tp, 0xBC08, (BIT_3 | BIT_2)); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBC08, (BIT_3 | BIT_2)); if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FFF); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x0400 - ); - } - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8560); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8562); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8564); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8566); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8568); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x856A); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FFF); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0400); + } + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8560); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8562); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8564); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x19CC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8566); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8568); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x856A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x147D); if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FFE); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0907); - } - ClearAndSetEthPhyOcpBit(tp, - 0xACDA, - 0xFF00, - 0xFF00 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xACDE, - 0xF000, - 0xF000 - ); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80D6); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F2); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F4); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x6077); - mdio_direct_write_phy_ocp(tp, 0xB506, 0x01E7); - mdio_direct_write_phy_ocp(tp, 0xAC8C, 0x0FFC); - mdio_direct_write_phy_ocp(tp, 0xAC46, 0xB7B4); - mdio_direct_write_phy_ocp(tp, 0xAC50, 0x0FBC); - mdio_direct_write_phy_ocp(tp, 0xAC3C, 0x9240); - mdio_direct_write_phy_ocp(tp, 0xAC4E, 0x0DB4); - mdio_direct_write_phy_ocp(tp, 0xACC6, 0x0707); - mdio_direct_write_phy_ocp(tp, 0xACC8, 0xA0D3); - mdio_direct_write_phy_ocp(tp, 0xAD08, 0x0007); - - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8013); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0700); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FB9); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBA); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0100); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBC); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x1900); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBE); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xE100); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC0); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0800); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC2); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xE500); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC4); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0F00); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC6); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF100); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC8); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0400); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCa); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF300); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCc); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFD00); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCe); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFF00); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD0); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFB00); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD2); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0100); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD4); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF400); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD6); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFF00); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD8); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF600); - - - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x813D); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x390E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x814F); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x790E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80B0); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0F31); - SetEthPhyOcpBit(tp, 0xBF4C, BIT_1); - SetEthPhyOcpBit(tp, 0xBCCA, (BIT_9 | BIT_8)); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8141); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x320E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8153); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x720E); - ClearEthPhyOcpBit(tp, 0xA432, BIT_6); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8529); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x050E); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x816C); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xC4A0); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8170); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xC4A0); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8174); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x04A0); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8178); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x04A0); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x817C); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0719); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FFE); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0907); + } + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xACDA, + 0xFF00, + 0xFF00); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xACDE, + 0xF000, + 0xF000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80D6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x6077); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB506, 0x01E7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC8C, 0x0FFC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC46, 0xB7B4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC50, 0x0FBC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC3C, 0x9240); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC4E, 0x0DB4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xACC6, 0x0707); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xACC8, 0xA0D3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAD08, 0x0007); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8013); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0700); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FB9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x2801); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBA); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBC); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x1900); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FBE); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xE100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0800); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xE500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0F00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FC8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0400); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCa); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF300); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCc); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFD00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FCe); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFF00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFB00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD2); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF400); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFF00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8FD8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xF600); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x813D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x390E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x814F); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x790E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80B0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0F31); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBF4C, BIT_1); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBCCA, (BIT_9 | BIT_8)); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8141); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x320E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8153); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x720E); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA432, BIT_6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8529); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x050E); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x816C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xC4A0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8170); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xC4A0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8174); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x04A0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8178); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x04A0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x817C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0719); if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF4); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0400); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0404); - } - mdio_direct_write_phy_ocp(tp, 0xBF4A, 0x001B); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8033); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8037); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x803B); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFC32); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x803F); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8043); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8047); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); - - - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8145); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x370E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8157); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x770E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8169); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0D0A); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x817B); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x1D0A); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8217); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x5000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x821A); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x5000 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DA); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0403); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x1000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B3); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x0384); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2007); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BA); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x6C00 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xF009); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BD); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x9F00 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C7); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xf083); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DD); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x03f0); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x1000 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CB); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x2007); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CE); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x6C00 - ); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C9); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x8009); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80D1); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0x8000 - ); - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A3); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x200A); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A5); - mdio_direct_write_phy_ocp(tp, 0xA438, 0xF0AD); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x809F); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x6073); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A1); - mdio_direct_write_phy_ocp(tp, 0xA438, 0x000B); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A9); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - 0xFF00, - 0xC000 - ); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF4); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0400); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0404); + } + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBF4A, 0x001B); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8033); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8037); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x803B); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0xFC32); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x803F); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8043); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8047); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x7C13); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8145); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x370E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8157); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x770E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8169); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x0D0A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x817B); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x1D0A); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8217); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x821A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5000); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DA); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0403); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DC); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0384); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2007); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BA); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x6C00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xF009); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BD); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x9F00); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C7); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xf083); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DD); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x03f0); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DF); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CB); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x2007); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CE); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x6C00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80C9); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8009); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80D1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x8000); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x200A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xF0AD); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x809F); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x6073); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x000B); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A9); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xC000); rtl8125_set_phy_mcu_patch_request(tp); - ClearEthPhyOcpBit(tp, 0xB896, BIT_0); - ClearEthPhyOcpBit(tp, 0xB892, 0xFF00); - - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC23E); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0000); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC240); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0103); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC242); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0507); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC244); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x090B); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC246); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x0C0E); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC248); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1012); - mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC24A); - mdio_direct_write_phy_ocp(tp, 0xB890, 0x1416); - - SetEthPhyOcpBit(tp, 0xB896, BIT_0); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB896, BIT_0); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xB892, 0xFF00); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC23E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC240); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0103); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC242); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0507); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC244); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x090B); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC246); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x0C0E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC248); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1012); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB88E, 0xC24A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB890, 0x1416); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xB896, BIT_0); rtl8125_clear_phy_mcu_patch_request(tp); - SetEthPhyOcpBit(tp, 0xA86A, BIT_0); - SetEthPhyOcpBit(tp, 0xA6F0, BIT_0); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA86A, BIT_0); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA6F0, BIT_0); - mdio_direct_write_phy_ocp(tp, 0xBFA0, 0xD70D); - mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x4100); - mdio_direct_write_phy_ocp(tp, 0xBFA4, 0xE868); - mdio_direct_write_phy_ocp(tp, 0xBFA6, 0xDC59); - mdio_direct_write_phy_ocp(tp, 0xB54C, 0x3C18); - ClearEthPhyOcpBit(tp, 0xBFA4, BIT_5); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); - SetEthPhyOcpBit(tp, 0xA438, BIT_12); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA0, 0xD70D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x4100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA4, 0xE868); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA6, 0xDC59); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB54C, 0x3C18); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xBFA4, BIT_5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA438, BIT_12); - if (aspm) { - if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - rtl8125_enable_phy_aldps(tp); - } - } + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); } static void @@ -11136,119 +12894,478 @@ rtl8125_hw_phy_config_8125b_2(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - SetEthPhyOcpBit(tp, 0xA442, BIT_11); - - - ClearAndSetEthPhyOcpBit(tp, - 0xAC46, - 0x00F0, - 0x0090 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xAD30, - 0x0003, - 0x0001 - ); - - - RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->eee.tx_lpi_timer); - - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F5); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x760E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8107); - mdio_direct_write_phy_ocp(tp, 0xB87E, 0x360E); - mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8551); - ClearAndSetEthPhyOcpBit(tp, - 0xB87E, - BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8, - BIT_11 - ); - - ClearAndSetEthPhyOcpBit(tp, - 0xbf00, - 0xE000, - 0xA000 - ); - ClearAndSetEthPhyOcpBit(tp, - 0xbf46, - 0x0F00, - 0x0300 - ); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x8044); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x804A); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x8050); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x8056); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x805C); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x8062); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x8068); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x806E); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x8074); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - mdio_direct_write_phy_ocp(tp, 0xa436, 0x807A); - mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); - - - SetEthPhyOcpBit(tp, 0xA4CA, BIT_6); - - - ClearAndSetEthPhyOcpBit(tp, - 0xBF84, - BIT_15 | BIT_14 | BIT_13, - BIT_15 | BIT_13 - ); - - - mdio_direct_write_phy_ocp(tp, 0xA436, 0x8170); - ClearAndSetEthPhyOcpBit(tp, - 0xA438, - BIT_13 | BIT_10 | BIT_9 | BIT_8, - BIT_15 | BIT_14 | BIT_12 | BIT_11 - ); - - - SetEthPhyOcpBit(tp, 0xA424, BIT_3); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); + + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAC46, + 0x00F0, + 0x0090); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD30, + 0x0003, + 0x0001); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80F5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x760E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8107); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87E, 0x360E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8551); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + BIT_15 | BIT_14 | BIT_13 | BIT_12 | BIT_11 | BIT_10 | BIT_9 | BIT_8, + BIT_11); + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xbf00, + 0xE000, + 0xA000); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xbf46, + 0x0F00, + 0x0300); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8044); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x804A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8050); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8056); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x805C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8062); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8068); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x806E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x8074); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa436, 0x807A); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xa438, 0x2417); + + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA4CA, BIT_6); + + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBF84, + BIT_15 | BIT_14 | BIT_13, + BIT_15 | BIT_13); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8170); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + BIT_13 | BIT_10 | BIT_9 | BIT_8, + BIT_15 | BIT_14 | BIT_12 | BIT_11); + + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA424, BIT_3); /* - mdio_direct_write_phy_ocp(tp, 0xBFA0, 0xD70D); - mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x4100); - mdio_direct_write_phy_ocp(tp, 0xBFA4, 0xE868); - mdio_direct_write_phy_ocp(tp, 0xBFA6, 0xDC59); - mdio_direct_write_phy_ocp(tp, 0xB54C, 0x3C18); - ClearEthPhyOcpBit(tp, 0xBFA4, BIT_5); - mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); - SetEthPhyOcpBit(tp, 0xA438, BIT_12); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA0, 0xD70D); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x4100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA4, 0xE868); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA6, 0xDC59); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB54C, 0x3C18); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xBFA4, BIT_5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x817D); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA438, BIT_12); */ - if (aspm) { - if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - rtl8125_enable_phy_aldps(tp); - } - } + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); } static void -rtl8125_hw_phy_config_8126a_1(struct net_device *dev) +rtl8125_hw_phy_config_8125bp_1(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - SetEthPhyOcpBit(tp, 0xA442, BIT_11); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); - RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->eee.tx_lpi_timer); - if (aspm) { - if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { - rtl8125_enable_phy_aldps(tp); - } + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA80C, + BIT_14, + BIT_15 | BIT_11 | BIT_10); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8010); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_11); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8088); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x9000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x808F); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x9000); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8174); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + BIT_13, + BIT_12 | BIT_11); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); +} + +static void +rtl8125_hw_phy_config_8125bp_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8010); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_11); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8088); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x9000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x808F); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x9000); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8174); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + BIT_13, + BIT_12 | BIT_11); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); +} + +static void +rtl8125_hw_phy_config_8125d_1(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); + + + rtl8125_set_phy_mcu_patch_request(tp); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xBF96, BIT_15); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBF94, + 0x0007, + 0x0005); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBF8E, + 0x3C00, + 0x2800); + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBCD8, + 0xC000, + 0x4000); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBCD8, BIT_15 | BIT_14); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBCD8, + 0xC000, + 0x4000); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC80, + 0x001F, + 0x0004); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBC82, BIT_15 | BIT_14 | BIT_13); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBC82, BIT_12 | BIT_11 | BIT_10); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC80, + 0x001F, + 0x0005); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC82, + 0x00E0, + 0x0040); + rtl8125_set_eth_phy_ocp_bit(tp, 0xBC82, BIT_4 | BIT_3 | BIT_2); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xBCD8, BIT_15 | BIT_14); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBCD8, + 0xC000, + 0x8000); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xBCD8, BIT_15 | BIT_14); + + rtl8125_clear_phy_mcu_patch_request(tp); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x832C); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0500); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB106, + 0x0700, + 0x0100); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB206, + 0x0700, + 0x0200); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB306, + 0x0700, + 0x0300); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x80CB); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0300); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBCF4, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBCF6, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBC12, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x844d); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0200); + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8feb); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0100); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xB87C, 0x8fe9); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xB87E, + 0xFF00, + 0x0600); + } + + + rtl8125_clear_eth_phy_ocp_bit(tp, 0xAD40, BIT_5 | BIT_4); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD66, + 0x000F, + 0x0007); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD68, + 0xF000, + 0x8000); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD68, + 0x0F00, + 0x0500); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD68, + 0x000F, + 0x0002); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xAD6A, + 0xF000, + 0x7000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xAC50, 0x01E8); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x81FA); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5400); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA864, + 0x00F0, + 0x00C0); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA42C, + 0x00FF, + 0x0002); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80E1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0F00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80DE); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xF000, + 0x0700); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA846, BIT_7); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BA); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8A04); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80BD); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xCA00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80B7); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xB300); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CE); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8A04); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80D1); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xCA00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80CB); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0xBB00); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A6); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x4909); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x80A8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x05B8); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8200); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x5800); + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF1); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7078); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x5D78); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF5); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x7862); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FF7); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1400); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x814C); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x8455); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x814E); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x84AF); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8163); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0600); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x816A); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x0500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8171); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1f00); + + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBC3A, + 0x000F, + 0x0006); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8064); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8067); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x806A); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x806D); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8070); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8073); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8076); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8079); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x807C); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x807F); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA438, BIT_10 | BIT_9 | BIT_8); + + + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xBFA0, + 0xFF70, + 0x5500); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xBFA2, 0x9D00); + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8165); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0x0700, + 0x0200); + + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8019); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA438, BIT_8); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8FE3); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0005); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0000); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x00ED); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0502); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0x0B00); + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA438, 0xD401); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x2900); + } + + + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x8018); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1700); + + + if (HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) { + rtl8125_mdio_direct_write_phy_ocp(tp, 0xA436, 0x815B); + rtl8125_clear_and_set_eth_phy_ocp_bit(tp, + 0xA438, + 0xFF00, + 0x1700); } + + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA430, BIT_12 | BIT_0); + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_7); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); +} + +static void +rtl8125_hw_phy_config_8125d_2(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + rtl8125_set_eth_phy_ocp_bit(tp, 0xA442, BIT_11); + + + if (aspm && HW_HAS_WRITE_PHY_MCU_RAM_CODE(tp)) + rtl8125_enable_phy_aldps(tp); } static void @@ -11256,11 +13373,13 @@ rtl8125_hw_phy_config(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (tp->resume_not_chg_speed) return; + if (tp->resume_not_chg_speed) + return; tp->phy_reset_enable(dev); - if (HW_DASH_SUPPORT_TYPE_3(tp) && tp->HwPkgDet == 0x06) return; + if (HW_DASH_SUPPORT_TYPE_3(tp) && tp->HwPkgDet == 0x06) + return; #ifndef ENABLE_USE_FIRMWARE_FILE if (!tp->rtl_fw) { @@ -11286,7 +13405,16 @@ rtl8125_hw_phy_config(struct net_device *dev) rtl8125_hw_phy_config_8125b_2(dev); break; case CFG_METHOD_8: - rtl8125_hw_phy_config_8126a_1(dev); + rtl8125_hw_phy_config_8125bp_1(dev); + break; + case CFG_METHOD_9: + rtl8125_hw_phy_config_8125bp_2(dev); + break; + case CFG_METHOD_10: + rtl8125_hw_phy_config_8125d_1(dev); + break; + case CFG_METHOD_11: + rtl8125_hw_phy_config_8125d_2(dev); break; } @@ -11299,10 +13427,11 @@ rtl8125_hw_phy_config(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: default: - rtl8125_mdio_write(tp, 0x1F, 0x0A5B); - rtl8125_clear_eth_phy_bit(tp, 0x12, BIT_15); - rtl8125_mdio_write(tp, 0x1F, 0x0000); + rtl8125_clear_eth_phy_ocp_bit(tp, 0xA5B4, BIT_15); break; } @@ -11400,50 +13529,57 @@ rtl8125_netpoll(struct net_device *dev) irq->handler(irq->vector, r8125napi); #endif - enable_irq(irq->vector); - } -} -#endif //CONFIG_NET_POLL_CONTROLLER - -static void -rtl8125_get_bios_setting(struct net_device *dev) -{ - struct rtl8125_private *tp = netdev_priv(dev); - - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_6: - case CFG_METHOD_7: - case CFG_METHOD_8: - tp->bios_setting = RTL_R32(tp, TimeInt2); - break; + enable_irq(irq->vector); } } +#endif //CONFIG_NET_POLL_CONTROLLER static void -rtl8125_set_bios_setting(struct net_device *dev) +rtl8125_setup_interrupt_mask(struct rtl8125_private *tp) { - struct rtl8125_private *tp = netdev_priv(dev); + int i; - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_6: - case CFG_METHOD_7: - case CFG_METHOD_8: - RTL_W32(tp, TimeInt2, tp->bios_setting); - break; + if (tp->HwCurrIsrVer == 5) { + tp->intr_mask = ISRIMR_V5_LINKCHG | ISRIMR_V5_TOK_Q0; + if (tp->num_tx_rings > 1) + tp->intr_mask |= ISRIMR_V5_TOK_Q1; + for (i = 0; i < tp->num_rx_rings; i++) + tp->intr_mask |= ISRIMR_V5_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 4) { + tp->intr_mask = ISRIMR_V4_LINKCHG; + for (i = 0; i < max(tp->num_tx_rings, tp->num_rx_rings); i++) + tp->intr_mask |= ISRIMR_V4_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 3) { + tp->intr_mask = ISRIMR_V2_LINKCHG; + for (i = 0; i < max(tp->num_tx_rings, tp->num_rx_rings); i++) + tp->intr_mask |= ISRIMR_V2_ROK_Q0 << i; + } else if (tp->HwCurrIsrVer == 2) { + tp->intr_mask = ISRIMR_V2_LINKCHG | ISRIMR_TOK_Q0; + if (tp->num_tx_rings > 1) + tp->intr_mask |= ISRIMR_TOK_Q1; + + for (i = 0; i < tp->num_rx_rings; i++) + tp->intr_mask |= ISRIMR_V2_ROK_Q0 << i; + } else { + tp->intr_mask = LinkChg | RxDescUnavail | TxOK | RxOK | SWInt; + tp->timer_intr_mask = LinkChg | PCSTimeout; + +#ifdef ENABLE_DASH_SUPPORT + if (tp->DASH) { + if (HW_DASH_SUPPORT_TYPE_3(tp)) { + tp->timer_intr_mask |= (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); + tp->intr_mask |= (ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); + } + } +#endif } } static void rtl8125_setup_mqs_reg(struct rtl8125_private *tp) { + u16 hw_clo_ptr0_reg, sw_tail_ptr0_reg; + u16 reg_len; int i; //tx @@ -11452,31 +13588,42 @@ rtl8125_setup_mqs_reg(struct rtl8125_private *tp) tp->tx_ring[i].tdsar_reg = (u16)(TNPDS_Q1_LOW_8125 + (i - 1) * 8); } + switch (tp->HwSuppTxNoCloseVer) { + case 4: + case 5: + hw_clo_ptr0_reg = HW_CLO_PTR0_8126; + sw_tail_ptr0_reg = SW_TAIL_PTR0_8126; + reg_len = 4; + break; + case 6: + hw_clo_ptr0_reg = HW_CLO_PTR0_8125BP; + sw_tail_ptr0_reg = SW_TAIL_PTR0_8125BP; + reg_len = 8; + break; + default: + hw_clo_ptr0_reg = HW_CLO_PTR0_8125; + sw_tail_ptr0_reg = SW_TAIL_PTR0_8125; + reg_len = 4; + break; + } + for (i = 0; i < R8125_MAX_TX_QUEUES; i++) { - if (tp->HwSuppTxNoCloseVer == 4) { - tp->tx_ring[i].hw_clo_ptr_reg = (u16)(HW_CLO_PTR0_8126 + i * 4); - tp->tx_ring[i].sw_tail_ptr_reg = (u16)(SW_TAIL_PTR0_8126 + i * 4); - } else { - tp->tx_ring[i].hw_clo_ptr_reg = (u16)(HW_CLO_PTR0_8125 + i * 4); - tp->tx_ring[i].sw_tail_ptr_reg = (u16)(SW_TAIL_PTR0_8125 + i * 4); - } + tp->tx_ring[i].hw_clo_ptr_reg = (u16)(hw_clo_ptr0_reg + i * reg_len); + tp->tx_ring[i].sw_tail_ptr_reg = (u16)(sw_tail_ptr0_reg + i * reg_len); } //rx tp->rx_ring[0].rdsar_reg = RxDescAddrLow; - for (i = 1; i < R8125_MAX_RX_QUEUES; i++) { + for (i = 1; i < R8125_MAX_RX_QUEUES; i++) tp->rx_ring[i].rdsar_reg = (u16)(RDSAR_Q1_LOW_8125 + (i - 1) * 8); - } tp->isr_reg[0] = ISR0_8125; - for (i = 1; i < R8125_MAX_QUEUES; i++) { + for (i = 1; i < R8125_MAX_QUEUES; i++) tp->isr_reg[i] = (u16)(ISR1_8125 + (i - 1) * 4); - } tp->imr_reg[0] = IMR0_8125; - for (i = 1; i < R8125_MAX_QUEUES; i++) { + for (i = 1; i < R8125_MAX_QUEUES; i++) tp->imr_reg[i] = (u16)(IMR1_8125 + (i - 1) * 4); - } } static void @@ -11485,22 +13632,40 @@ rtl8125_init_software_variable(struct net_device *dev) struct rtl8125_private *tp = netdev_priv(dev); struct pci_dev *pdev = tp->pci_dev; - rtl8125_get_bios_setting(dev); - #ifdef ENABLE_LIB_SUPPORT tp->ring_lib_enabled = 1; #endif switch (tp->mcfg) { case CFG_METHOD_2: - case CFG_METHOD_3: - //tp->HwSuppDashVer = 3; + case CFG_METHOD_3: { + u8 tmp = (u8)rtl8125_mac_ocp_read(tp, 0xD006); + if (tmp == 0x02 || tmp == 0x04) + tp->HwSuppDashVer = 3; + } + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + tp->HwSuppDashVer = 4; break; default: tp->HwSuppDashVer = 0; break; } + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + if (HW_DASH_SUPPORT_DASH(tp)) + tp->HwSuppOcpChannelVer = 2; + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + tp->HwSuppOcpChannelVer = 2; + break; + } + tp->AllowAccessDashOcp = rtl8125_is_allow_access_dash_ocp(tp); + switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: @@ -11509,6 +13674,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwPkgDet = rtl8125_mac_ocp_read(tp, 0xDC00); tp->HwPkgDet = (tp->HwPkgDet >> 3) & 0x07; break; @@ -11525,6 +13693,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppNowIsOobVer = 1; break; } @@ -11536,9 +13707,14 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_5: case CFG_METHOD_6: case CFG_METHOD_7: - case CFG_METHOD_8: tp->HwPcieSNOffset = 0x16C; break; + case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwPcieSNOffset = 0x168; + break; } #ifdef ENABLE_REALWOW_SUPPORT @@ -11573,11 +13749,10 @@ rtl8125_init_software_variable(struct net_device *dev) #endif //LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) } - if (cmac_ioaddr == NULL) { + if (cmac_ioaddr == NULL) tp->DASH = 0; - } else { + else tp->mapped_cmac_ioaddr = cmac_ioaddr; - } } eee_enable = 0; @@ -11595,6 +13770,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->org_pci_offset_99 = rtl8125_csi_fun0_read_byte(tp, 0x99); tp->org_pci_offset_99 &= ~(BIT_5|BIT_6); break; @@ -11612,7 +13790,10 @@ rtl8125_init_software_variable(struct net_device *dev) tp->org_pci_offset_180 = rtl8125_csi_fun0_read_byte(tp, 0x214); break; case CFG_METHOD_8: - tp->org_pci_offset_180 = rtl8125_csi_fun0_read_byte(tp, 0x22c); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->org_pci_offset_180 = rtl8125_csi_fun0_read_byte(tp, 0x210); break; } } @@ -11628,8 +13809,11 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: default: - tp->use_timer_interrrupt = TRUE; + tp->use_timer_interrupt = TRUE; break; } @@ -11638,10 +13822,11 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_3: case CFG_METHOD_4: case CFG_METHOD_5: - tp->HwSuppMaxPhyLinkSpeed = 2500; - break; case CFG_METHOD_8: - tp->HwSuppMaxPhyLinkSpeed = 5000; + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppMaxPhyLinkSpeed = 2500; break; default: tp->HwSuppMaxPhyLinkSpeed = 1000; @@ -11649,7 +13834,7 @@ rtl8125_init_software_variable(struct net_device *dev) } if (timer_count == 0 || tp->mcfg == CFG_METHOD_DEFAULT) - tp->use_timer_interrrupt = FALSE; + tp->use_timer_interrupt = FALSE; switch (tp->mcfg) { case CFG_METHOD_2: @@ -11659,6 +13844,25 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->ShortPacketSwChecksum = TRUE; + tp->UseSwPaddingShortPkt = TRUE; + break; + default: + break; + } + + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_4: + case CFG_METHOD_5: + case CFG_METHOD_6: + case CFG_METHOD_7: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppMagicPktVer = WAKEUP_MAGIC_PACKET_V3; break; default: @@ -11674,6 +13878,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppLinkChgWakeUpVer = 3; break; } @@ -11685,8 +13892,13 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: tp->HwSuppD0SpeedUpVer = 1; break; + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppD0SpeedUpVer = 2; + break; } switch (tp->mcfg) { @@ -11697,6 +13909,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppCheckPhyDisableModeVer = 3; break; } @@ -11711,16 +13926,28 @@ rtl8125_init_software_variable(struct net_device *dev) tp->HwSuppTxNoCloseVer = 3; break; case CFG_METHOD_8: - tp->HwSuppTxNoCloseVer = 4; + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppTxNoCloseVer = 6; break; } - if (tp->HwSuppTxNoCloseVer == 4) + switch (tp->HwSuppTxNoCloseVer) { + case 5: + case 6: + tp->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V4; + break; + case 4: tp->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V3; - else if (tp->HwSuppTxNoCloseVer == 3) + break; + case 3: tp->MaxTxDescPtrMask = MAX_TX_NO_CLOSE_DESC_PTR_MASK_V2; - else + break; + default: tx_no_close_enable = 0; + break; + } if (tp->HwSuppTxNoCloseVer > 0 && tx_no_close_enable == 1) tp->EnableTxNoClose = TRUE; @@ -11751,6 +13978,15 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_8: tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_8; break; + case CFG_METHOD_9: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_9; + break; + case CFG_METHOD_10: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_10; + break; + case CFG_METHOD_11: + tp->sw_ram_code_ver = NIC_RAMCODE_VERSION_CFG_METHOD_11; + break; } if (tp->HwIcVerUnknown) { @@ -11758,11 +13994,13 @@ rtl8125_init_software_variable(struct net_device *dev) tp->NotWrMcuPatchCode = TRUE; } + rtl8125_check_hw_phy_mcu_code_ver(dev); + switch (tp->mcfg) { case CFG_METHOD_3: case CFG_METHOD_6: if ((rtl8125_mac_ocp_read(tp, 0xD442) & BIT_5) && - (mdio_direct_read_phy_ocp(tp, 0xD068) & BIT_1)) + (rtl8125_mdio_direct_read_phy_ocp(tp, 0xD068) & BIT_1)) tp->RequirePhyMdiSwapPatch = TRUE; break; } @@ -11775,6 +14013,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppMacMcuVer = 2; break; } @@ -11787,6 +14028,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->MacMcuPageSize = RTL8125_MAC_MCU_PAGE_SIZE; break; } @@ -11796,6 +14040,9 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_5: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppNumTxQueues = 2; tp->HwSuppNumRxQueues = 4; break; @@ -11805,18 +14052,65 @@ rtl8125_init_software_variable(struct net_device *dev) break; } + switch (tp->mcfg) { + case CFG_METHOD_4: + case CFG_METHOD_5: + case CFG_METHOD_7: + tp->HwSuppPtpVer = 1; + break; + } +#ifdef ENABLE_PTP_SUPPORT + if (tp->HwSuppPtpVer > 0) + tp->EnablePtp = 1; +#endif + + //init interrupt + switch (tp->mcfg) { + case CFG_METHOD_4: + case CFG_METHOD_5: + case CFG_METHOD_7: + tp->HwSuppIsrVer = 2; + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + tp->HwSuppIsrVer = 4; + break; + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppIsrVer = 5; + break; + default: + tp->HwSuppIsrVer = 1; + break; + } + + tp->HwCurrIsrVer = tp->HwSuppIsrVer; + if (tp->HwCurrIsrVer > 1) { + if (!(tp->features & RTL_FEATURE_MSIX) || + tp->irq_nvecs < tp->min_irq_nvecs || + (tp->DASH && HW_DASH_SUPPORT_TYPE_4(tp))) + tp->HwCurrIsrVer = 1; + } + tp->num_tx_rings = 1; #ifdef ENABLE_MULTIPLE_TX_QUEUE #ifndef ENABLE_LIB_SUPPORT tp->num_tx_rings = tp->HwSuppNumTxQueues; #endif #endif + if (tp->HwCurrIsrVer < 2 || + (tp->HwCurrIsrVer == 2 && tp->irq_nvecs < 19)) + tp->num_tx_rings = 1; + //RSS switch (tp->mcfg) { case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppRssVer = 5; tp->HwSuppIndirTblEntries = 128; break; @@ -11828,7 +14122,7 @@ rtl8125_init_software_variable(struct net_device *dev) if (tp->HwSuppRssVer > 0) tp->EnableRss = 1; #else - if (tp->HwSuppRssVer > 0) { + if (tp->HwSuppRssVer > 0 && tp->HwCurrIsrVer > 1) { u8 rss_queue_num = netif_get_num_default_rss_queues(); tp->num_rx_rings = (tp->HwSuppNumRxQueues > rss_queue_num)? rss_queue_num : tp->HwSuppNumRxQueues; @@ -11842,79 +14136,51 @@ rtl8125_init_software_variable(struct net_device *dev) #endif #endif + //interrupt mask + rtl8125_setup_interrupt_mask(tp); + rtl8125_setup_mqs_reg(tp); rtl8125_set_ring_size(tp, NUM_RX_DESC, NUM_TX_DESC); switch (tp->mcfg) { - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_7: - tp->HwSuppPtpVer = 1; + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + tp->HwSuppIntMitiVer = 3; break; - } -#ifdef ENABLE_PTP_SUPPORT - if (tp->HwSuppPtpVer > 0) - tp->EnablePtp = 1; -#endif - - //init interrupt - switch (tp->mcfg) { case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: + tp->HwSuppIntMitiVer = 4; + break; case CFG_METHOD_8: - tp->HwSuppIsrVer = 2; + case CFG_METHOD_9: + tp->HwSuppIntMitiVer = 6; break; - default: - tp->HwSuppIsrVer = 1; + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppIntMitiVer = 7; break; } - tp->HwCurrIsrVer = tp->HwSuppIsrVer; - if (tp->HwSuppIsrVer == 2) { - if (!(tp->features & RTL_FEATURE_MSIX) || - tp->irq_nvecs < R8125_MIN_MSIX_VEC_8125B) - tp->HwCurrIsrVer = 1; - } - - if (tp->HwCurrIsrVer < 2 || tp->irq_nvecs < 19) - tp->num_tx_rings = 1; - - if (tp->HwCurrIsrVer == 2) { - int i; - - tp->intr_mask = ISRIMR_V2_LINKCHG | ISRIMR_TOK_Q0; - if (tp->num_tx_rings > 1) - tp->intr_mask |= ISRIMR_TOK_Q1; - - for (i = 0; i < tp->num_rx_rings; i++) - tp->intr_mask |= ISRIMR_V2_ROK_Q0 << i; - } else { - tp->intr_mask = LinkChg | RxDescUnavail | TxOK | RxOK | SWInt; - tp->timer_intr_mask = LinkChg | PCSTimeout; - -#ifdef ENABLE_DASH_SUPPORT - if (tp->DASH) { - if (HW_DASH_SUPPORT_TYPE_3(tp)) { - tp->timer_intr_mask |= ( ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); - tp->intr_mask |= ( ISRIMR_DASH_INTR_EN | ISRIMR_DASH_INTR_CMAC_RESET); - } - } -#endif - } - switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: - case CFG_METHOD_6: - tp->HwSuppIntMitiVer = 3; - break; case CFG_METHOD_4: case CFG_METHOD_5: + case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - tp->HwSuppIntMitiVer = 4; + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppTcamVer = 1; + + tp->TcamNotValidReg = TCAM_NOTVALID_ADDR; + tp->TcamValidReg = TCAM_VALID_ADDR; + tp->TcamMaAddrcOffset = TCAM_MAC_ADDR; + tp->TcamVlanTagOffset = TCAM_VLAN_TAG; break; } @@ -11926,54 +14192,81 @@ rtl8125_init_software_variable(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: tp->HwSuppExtendTallyCounterVer = 1; break; } timer_count_v2 = (timer_count / 0x100); + /* timer unit is double */ + switch (tp->mcfg) { + case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + timer_count_v2 /= 2; + break; + } + + switch (tp->mcfg) { + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->RequiredPfmPatch = TRUE; + break; + } -#ifndef ENABLE_LIB_SUPPORT switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: case CFG_METHOD_4: case CFG_METHOD_5: + case CFG_METHOD_6: case CFG_METHOD_7: - if (tp->HwSuppIsrVer == 2) { - tp->RequireRduNonStopPatch = 1; - tp->EnableRss = 0; - } + tp->HwSuppRxDescType = RX_DESC_RING_TYPE_3; + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->HwSuppRxDescType = RX_DESC_RING_TYPE_4; + break; + default: + tp->HwSuppRxDescType = RX_DESC_RING_TYPE_1; break; } -#endif tp->InitRxDescType = RX_DESC_RING_TYPE_1; - if (tp->EnableRss || tp->EnablePtp) - tp->InitRxDescType = RX_DESC_RING_TYPE_3; - tp->RxDescLength = RX_DESC_LEN_TYPE_1; - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) - tp->RxDescLength = RX_DESC_LEN_TYPE_3; + switch (tp->HwSuppRxDescType) { + case RX_DESC_RING_TYPE_3: + if (tp->EnableRss || tp->EnablePtp) { + tp->InitRxDescType = RX_DESC_RING_TYPE_3; + tp->RxDescLength = RX_DESC_LEN_TYPE_3; + } + break; + case RX_DESC_RING_TYPE_4: + if (tp->EnableRss) { + tp->InitRxDescType = RX_DESC_RING_TYPE_4; + tp->RxDescLength = RX_DESC_LEN_TYPE_4; + } + break; + } tp->rtl8125_rx_config = rtl_chip_info[tp->chipset].RCR_Cfg; if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) tp->rtl8125_rx_config |= EnableRxDescV3; + else if (tp->InitRxDescType == RX_DESC_RING_TYPE_4) + tp->rtl8125_rx_config &= ~EnableRxDescV4_1; tp->NicCustLedValue = RTL_R16(tp, CustomLED); tp->wol_opts = rtl8125_get_hw_wol(tp); tp->wol_enabled = (tp->wol_opts) ? WOL_ENABLED : WOL_DISABLED; - if (HW_SUPP_PHY_LINK_SPEED_2500M(tp)) - rtl8125_link_option((u8*)&autoneg_mode, (u32*)&speed_mode, (u8*)&duplex_mode, (u32*)&advertising_mode); - else - rtl8125_link_option_giga((u8*)&autoneg_mode, (u32*)&speed_mode, (u8*)&duplex_mode, (u32*)&advertising_mode); - - tp->autoneg = autoneg_mode; - tp->speed = speed_mode; - tp->duplex = duplex_mode; - tp->advertising = advertising_mode; - if (HW_SUPP_PHY_LINK_SPEED_5000M(tp)) - tp->advertising |= RTK_ADVERTISED_5000baseX_Full; - tp->fcpause = rtl8125_fc_full; + rtl8125_set_link_option(tp, autoneg_mode, speed_mode, duplex_mode, + rtl8125_fc_full); tp->max_jumbo_frame_size = rtl_chip_info[tp->chipset].jumbo_frame_sz; #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) @@ -11988,14 +14281,20 @@ rtl8125_init_software_variable(struct net_device *dev) eee->eee_enabled = eee_enable; eee->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full; + eee->advertised = mmd_eee_adv_to_ethtool_adv_t(MDIO_EEE_1000T | MDIO_EEE_100TX); switch (tp->mcfg) { - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_8: - eee->supported |= SUPPORTED_2500baseX_Full; + case CFG_METHOD_2: + case CFG_METHOD_3: + /* nothing to do */ + break; + default: + if (HW_SUPP_PHY_LINK_SPEED_2500M(tp)) { + eee->supported |= SUPPORTED_2500baseX_Full; + eee->advertised |= SUPPORTED_2500baseX_Full; + } break; } - eee->advertised = mmd_eee_adv_to_ethtool_adv_t(MDIO_EEE_1000T | MDIO_EEE_100TX); + eee->tx_lpi_enabled = eee_enable; eee->tx_lpi_timer = dev->mtu + ETH_HLEN + 0x20; } @@ -12014,7 +14313,6 @@ rtl8125_release_board(struct pci_dev *pdev, struct rtl8125_private *tp = netdev_priv(dev); void __iomem *ioaddr = tp->mmio_addr; - rtl8125_set_bios_setting(dev); rtl8125_rar_set(tp, tp->org_mac_addr); tp->wol_enabled = WOL_DISABLED; @@ -12056,16 +14354,14 @@ rtl8125_get_mac_address(struct net_device *dev) for (i = 0; i < MAC_ADDR_LEN; i++) mac_addr[i] = RTL_R8(tp, MAC0 + i); - if(tp->mcfg == CFG_METHOD_2 || - tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_4 || - tp->mcfg == CFG_METHOD_5 || - tp->mcfg == CFG_METHOD_6 || - tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_11: *(u32*)&mac_addr[0] = RTL_R32(tp, BACKUP_ADDR0_8125); *(u16*)&mac_addr[4] = RTL_R16(tp, BACKUP_ADDR1_8125); - } + break; + default: + break; + }; if (!is_valid_ether_addr(mac_addr)) { netif_err(tp, probe, dev, "Invalid ether addr %pM\n", @@ -12083,7 +14379,7 @@ rtl8125_get_mac_address(struct net_device *dev) /* keep the original MAC address */ memcpy(tp->org_mac_addr, dev->dev_addr, MAC_ADDR_LEN); #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,13) - memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); + memcpy(dev->perm_addr, dev->dev_addr, MAC_ADDR_LEN); #endif return 0; } @@ -12947,9 +15243,8 @@ rtl8125_phy_power_up(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); - if (rtl8125_is_in_phy_disable_mode(dev)) { + if (rtl8125_is_in_phy_disable_mode(dev)) return; - } rtl8125_mdio_write(tp, 0x1F, 0x0000); rtl8125_mdio_write(tp, MII_BMCR, BMCR_ANENABLE); @@ -12963,6 +15258,9 @@ rtl8125_phy_power_up(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_wait_phy_ups_resume(dev, 3); break; }; @@ -13345,8 +15643,7 @@ rtl8125_link_timer(struct timer_list *t) } */ -int -rtl8125_enable_msix(struct rtl8125_private *tp) +static int rtl8125_enable_msix(struct rtl8125_private *tp) { int i, nvecs = 0; struct msix_entry msix_ent[R8125_MAX_MSIX_VEC]; @@ -13367,52 +15664,66 @@ rtl8125_enable_msix(struct rtl8125_private *tp) struct r8125_irq *irq = &tp->irq_tbl[i]; irq->vector = msix_ent[i].vector; //snprintf(irq->name, len, "%s-%d", dev->name, i); - //irq->handler = rtl8125_interrupt_msix; - } - -out: - return nvecs; -} - -void rtl8125_dump_msix_tbl(struct rtl8125_private *tp) -{ - void __iomem *ioaddr; - - /* ioremap MMIO region */ - ioaddr = ioremap(pci_resource_start(tp->pci_dev, 4), pci_resource_len(tp->pci_dev, 4)); - if (ioaddr) { - int i = 0; - for (i=0; iirq_nvecs; i++) { - printk("entry 0x%d %08X %08X %08X %08X \n", - i, - readl(ioaddr + 16 * i), - readl(ioaddr + 16 * i + 4), - readl(ioaddr + 16 * i + 8), - readl(ioaddr + 16 * i + 12)); - } - iounmap(ioaddr); + //irq->handler = rtl8125_interrupt_msix; } + +out: + return nvecs; } /* Cfg9346_Unlock assumed. */ static int rtl8125_try_msi(struct rtl8125_private *tp) { struct pci_dev *pdev = tp->pci_dev; + unsigned int hw_supp_irq_nvecs; unsigned msi = 0; int nvecs = 1; - tp->max_irq_nvecs = 1; - tp->min_irq_nvecs = 1; -#ifndef DISABLE_MULTI_MSIX_VECTOR + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + hw_supp_irq_nvecs = R8125_MAX_MSIX_VEC_8125A; + break; + case CFG_METHOD_4 ... CFG_METHOD_7: + hw_supp_irq_nvecs = R8125_MAX_MSIX_VEC_8125B; + break; + case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + hw_supp_irq_nvecs = R8125_MAX_MSIX_VEC_8125D; + break; + default: + hw_supp_irq_nvecs = 1; + break; + } + tp->hw_supp_irq_nvecs = clamp_val(hw_supp_irq_nvecs, 1, + R8125_MAX_MSIX_VEC); + switch (tp->mcfg) { case CFG_METHOD_4: case CFG_METHOD_5: case CFG_METHOD_7: - case CFG_METHOD_8: - tp->max_irq_nvecs = R8125_MAX_MSIX_VEC_8125B; + tp->max_irq_nvecs = tp->hw_supp_irq_nvecs; tp->min_irq_nvecs = R8125_MIN_MSIX_VEC_8125B; break; + case CFG_METHOD_8: + case CFG_METHOD_9: + tp->max_irq_nvecs = tp->hw_supp_irq_nvecs; + tp->min_irq_nvecs = R8125_MIN_MSIX_VEC_8125BP; + break; + case CFG_METHOD_10: + case CFG_METHOD_11: + tp->max_irq_nvecs = tp->hw_supp_irq_nvecs; + tp->min_irq_nvecs = R8125_MIN_MSIX_VEC_8125D; + break; + default: + tp->max_irq_nvecs = 1; + tp->min_irq_nvecs = 1; + break; } +#ifdef DISABLE_MULTI_MSIX_VECTOR + tp->max_irq_nvecs = 1; #endif #if defined(RTL_USE_NEW_INTR_API) @@ -13485,7 +15796,7 @@ rtl8125_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) stats->tx_errors = le64_to_cpu(counters->tx_errors); stats->collisions = le32_to_cpu(counters->tx_multi_collision); - stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) ; + stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted); stats->rx_missed_errors = le16_to_cpu(counters->rx_missed); } #else @@ -13570,7 +15881,8 @@ static int rtl8125_poll(napi_ptr napi, napi_budget budget) #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) - if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) return RTL_NAPI_RETURN_VALUE; + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; #else RTL_NETIF_RX_COMPLETE(dev, napi, work_done); #endif @@ -13588,7 +15900,6 @@ static int rtl8125_poll(napi_ptr napi, napi_budget budget) return RTL_NAPI_RETURN_VALUE; } -#if 0 static int rtl8125_poll_msix_ring(napi_ptr napi, napi_budget budget) { struct r8125_napi *r8125napi = RTL_GET_PRIV(napi, struct r8125_napi); @@ -13611,7 +15922,8 @@ static int rtl8125_poll_msix_ring(napi_ptr napi, napi_budget budget) #endif #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) - if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) return RTL_NAPI_RETURN_VALUE; + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; #else RTL_NETIF_RX_COMPLETE(dev, napi, work_done); #endif @@ -13628,7 +15940,6 @@ static int rtl8125_poll_msix_ring(napi_ptr napi, napi_budget budget) return RTL_NAPI_RETURN_VALUE; } -#endif static int rtl8125_poll_msix_tx(napi_ptr napi, napi_budget budget) { @@ -13648,7 +15959,8 @@ static int rtl8125_poll_msix_tx(napi_ptr napi, napi_budget budget) if (work_done < work_to_do) { #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) - if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) return RTL_NAPI_RETURN_VALUE; + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; #else RTL_NETIF_RX_COMPLETE(dev, napi, work_done); #endif @@ -13703,7 +16015,8 @@ static int rtl8125_poll_msix_rx(napi_ptr napi, napi_budget budget) if (work_done < work_to_do) { #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,10,0) - if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) return RTL_NAPI_RETURN_VALUE; + if (RTL_NETIF_RX_COMPLETE(dev, napi, work_done) == FALSE) + return RTL_NAPI_RETURN_VALUE; #else RTL_NETIF_RX_COMPLETE(dev, napi, work_done); #endif @@ -13761,16 +16074,33 @@ static void rtl8125_init_napi(struct rtl8125_private *tp) #ifdef CONFIG_R8125_NAPI int (*poll)(struct napi_struct *, int); - if (tp->features & RTL_FEATURE_MSIX && - tp->HwCurrIsrVer == 2) { - if (i < R8125_MAX_RX_QUEUES_VEC_V3) - poll = rtl8125_poll_msix_rx; - else if (i == 16 || i == 18) - poll = rtl8125_poll_msix_tx; - else - poll = rtl8125_poll_msix_other; - } else { - poll = rtl8125_poll; + poll = rtl8125_poll; + if (tp->features & RTL_FEATURE_MSIX) { + switch (tp->HwCurrIsrVer) { + case 5: + if (i < R8125_MAX_RX_QUEUES_VEC_V3) + poll = rtl8125_poll_msix_rx; + else if (i == 16 || i == 17) + poll = rtl8125_poll_msix_tx; + else + poll = rtl8125_poll_msix_other; + break; + case 2: + if (i < R8125_MAX_RX_QUEUES_VEC_V3) + poll = rtl8125_poll_msix_rx; + else if (i == 16 || i == 18) + poll = rtl8125_poll_msix_tx; + else + poll = rtl8125_poll_msix_other; + break; + case 3: + case 4: + if (i < R8125_MAX_RX_QUEUES_VEC_V3) + poll = rtl8125_poll_msix_ring; + else + poll = rtl8125_poll_msix_other; + break; + } } RTL_NAPI_CONFIG(tp->dev, r8125napi, poll, R8125_NAPI_WEIGHT); @@ -13798,6 +16128,18 @@ rtl8125_set_real_num_queue(struct rtl8125_private *tp) return retval; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) +void netdev_sw_irq_coalesce_default_on(struct net_device *dev) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0) + WARN_ON(dev->reg_state == NETREG_REGISTERED); + + dev->gro_flush_timeout = 20000; + dev->napi_defer_hard_irqs = 1; +#endif //LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0) +} +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) + static int __devinit rtl8125_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) @@ -13815,7 +16157,7 @@ rtl8125_init_one(struct pci_dev *pdev, board_idx++; if (netif_msg_drv(&debug)) - printk(KERN_INFO "%s 2.5Gigabit Ethernet driver %s loaded\n", + printk(KERN_INFO "%s Ethernet controller driver %s loaded\n", MODULENAME, RTL8125_VERSION); rc = rtl8125_init_board(pdev, &dev, &ioaddr); @@ -13843,9 +16185,7 @@ rtl8125_init_one(struct pci_dev *pdev, dev_err(&pdev->dev, "Can't allocate interrupt\n"); goto err_out_1; } -#ifdef ENABLE_PTP_SUPPORT - spin_lock_init(&tp->lock); -#endif + rtl8125_init_software_variable(dev); RTL_NET_DEVICE_OPS(rtl8125_netdev_ops); @@ -13881,6 +16221,16 @@ rtl8125_init_one(struct pci_dev *pdev, tp->cp_cmd |= RxChkSum; #else dev->features |= NETIF_F_RXCSUM; + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + /* nothing to do */ + break; + default: + dev->features |= NETIF_F_SG | NETIF_F_TSO; + break; + }; dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | @@ -13892,7 +16242,17 @@ rtl8125_init_one(struct pci_dev *pdev, dev->hw_features |= NETIF_F_RXFCS; #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22) dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6; - dev->features |= NETIF_F_IPV6_CSUM; + dev->features |= NETIF_F_IPV6_CSUM; + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + /* nothing to do */ + break; + default: + dev->features |= NETIF_F_TSO6; + break; + }; #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,19,0) netif_set_tso_max_size(dev, LSO_64K); netif_set_tso_max_segs(dev, NIC_MAX_PHYS_BUF_COUNT_LSO2); @@ -13912,18 +16272,20 @@ rtl8125_init_one(struct pci_dev *pdev, #ifdef ENABLE_RSS_SUPPORT if (tp->EnableRss) { dev->hw_features |= NETIF_F_RXHASH; - dev->features |= NETIF_F_RXHASH; + dev->features |= NETIF_F_RXHASH; } #endif } + netdev_sw_irq_coalesce_default_on(dev); + #ifdef ENABLE_DASH_SUPPORT if (tp->DASH) AllocateDashShareMemory(dev); #endif #ifdef ENABLE_LIB_SUPPORT - ATOMIC_INIT_NOTIFIER_HEAD(&tp->lib_nh); + BLOCKING_INIT_NOTIFIER_HEAD(&tp->lib_nh); #endif rtl8125_init_all_schedule_work(tp); @@ -13972,6 +16334,8 @@ rtl8125_init_one(struct pci_dev *pdev, netif_carrier_off(dev); + rtl8125_sysfs_init(dev); + printk("%s", GPL_CLAIM); out: @@ -14014,6 +16378,10 @@ rtl8125_remove_one(struct pci_dev *pdev) if (HW_DASH_SUPPORT_DASH(tp)) rtl8125_driver_stop(tp); +#ifdef ENABLE_R8125_SYSFS + rtl8125_sysfs_remove(dev); +#endif //ENABLE_R8125_SYSFS + unregister_netdev(dev); rtl8125_disable_msi(pdev, tp); #ifdef ENABLE_R8125_PROCFS @@ -14049,7 +16417,9 @@ rtl8125_set_rxbufsize(struct rtl8125_private *tp, { unsigned int mtu = dev->mtu; - tp->rms = (mtu > ETH_DATA_LEN) ? mtu + ETH_HLEN + 8 + 1 : RX_BUF_SIZE; + tp->rms = (mtu > ETH_DATA_LEN) ? + mtu + ETH_HLEN + RT_VALN_HLEN + ETH_FCS_LEN: + RX_BUF_SIZE; tp->rx_buf_sz = tp->rms; #ifdef ENABLE_RX_PACKET_FRAGMENT tp->rx_buf_sz = SKB_DATA_ALIGN(RX_BUF_SIZE); @@ -14092,7 +16462,7 @@ static int rtl8125_alloc_irq(struct rtl8125_private *tp) for (i=0; iirq_nvecs; i++) { irq = &tp->irq_tbl[i]; if (tp->features & RTL_FEATURE_MSIX && - tp->HwCurrIsrVer == 2) + tp->HwCurrIsrVer > 1) irq->handler = rtl8125_interrupt_msix; else irq->handler = rtl8125_interrupt; @@ -14113,7 +16483,7 @@ static int rtl8125_alloc_irq(struct rtl8125_private *tp) irq_flags |= IRQF_NO_SUSPEND; #endif if (tp->features & RTL_FEATURE_MSIX && - tp->HwCurrIsrVer == 2) { + tp->HwCurrIsrVer > 1) { for (i=0; iirq_nvecs; i++) { irq = &tp->irq_tbl[i]; irq->handler = rtl8125_interrupt_msix; @@ -14188,24 +16558,6 @@ static int rtl8125_alloc_rx_desc(struct rtl8125_private *tp) return 0; } -static int rtl8125_alloc_patch_mem(struct rtl8125_private *tp) -{ - struct pci_dev *pdev = tp->pci_dev; - - if (tp->RequireRduNonStopPatch) { - tp->ShortPacketEmptyBuffer = dma_alloc_coherent(&pdev->dev, - SHORT_PACKET_PADDING_BUF_SIZE, - &tp->ShortPacketEmptyBufferPhy, - GFP_KERNEL); - if (!tp->ShortPacketEmptyBuffer) - return -1; - - memset(tp->ShortPacketEmptyBuffer, 0x0, SHORT_PACKET_PADDING_BUF_SIZE); - } - - return 0; -} - static void rtl8125_free_tx_desc(struct rtl8125_private *tp) { struct rtl8125_tx_ring *ring; @@ -14242,26 +16594,11 @@ static void rtl8125_free_rx_desc(struct rtl8125_private *tp) } } -static void rtl8125_free_patch_mem(struct rtl8125_private *tp) -{ - struct pci_dev *pdev = tp->pci_dev; - - if (tp->ShortPacketEmptyBuffer) { - dma_free_coherent(&pdev->dev, - SHORT_PACKET_PADDING_BUF_SIZE, - tp->ShortPacketEmptyBuffer, - tp->ShortPacketEmptyBufferPhy); - tp->ShortPacketEmptyBuffer = NULL; - } -} - static void rtl8125_free_alloc_resources(struct rtl8125_private *tp) { rtl8125_free_rx_desc(tp); rtl8125_free_tx_desc(tp); - - rtl8125_free_patch_mem(tp); } #ifdef ENABLE_USE_FIRMWARE_FILE @@ -14313,10 +16650,6 @@ int rtl8125_open(struct net_device *dev) if (retval < 0) goto err_free_all_allocated_mem; - retval = rtl8125_alloc_patch_mem(tp); - if (retval < 0) - goto err_free_all_allocated_mem; - retval = rtl8125_alloc_irq(tp); if (retval < 0) goto err_free_all_allocated_mem; @@ -14397,7 +16730,8 @@ set_offset79(struct rtl8125_private *tp, u8 setting) struct pci_dev *pdev = tp->pci_dev; u8 device_control; - if (hwoptimize & HW_PATCH_SOC_LAN) return; + if (hwoptimize & HW_PATCH_SOC_LAN) + return; pci_read_config_byte(pdev, 0x79, &device_control); device_control &= ~0x70; @@ -14423,9 +16757,8 @@ rtl8125_hw_set_rx_packet_filter(struct net_device *dev) AcceptBroadcast | AcceptMulticast | AcceptMyPhys | AcceptAllPhys; mc_filter[1] = mc_filter[0] = 0xffffffff; - } else if ((netdev_mc_count(dev) > multicast_filter_limit) - || (dev->flags & IFF_ALLMULTI)) { - /* Too many to filter perfectly -- accept all multicasts. */ + } else if (dev->flags & IFF_ALLMULTI) { + /* accept all multicasts. */ rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; mc_filter[1] = mc_filter[0] = 0xffffffff; } else { @@ -14503,32 +16836,72 @@ rtl8125_set_tx_q_num(struct rtl8125_private *tp, } void -rtl8125_hw_config(struct net_device *dev) +rtl8125_enable_mcu(struct rtl8125_private *tp, bool enable) { - struct rtl8125_private *tp = netdev_priv(dev); - struct pci_dev *pdev = tp->pci_dev; - u16 mac_ocp_data; + if (FALSE == HW_SUPPORT_MAC_MCU(tp)) + return; - RTL_W32(tp, RxConfig, (RX_DMA_BURST << RxCfgDMAShift)); + if (enable) + rtl8125_set_mac_ocp_bit(tp, 0xC0B4, BIT_0); + else + rtl8125_clear_mac_ocp_bit(tp, 0xC0B4, BIT_0); +} - rtl8125_hw_reset(dev); +static void +rtl8125_clear_tcam_entries(struct rtl8125_private *tp) +{ + if (FALSE == HW_SUPPORT_TCAM(tp)) + return; - rtl8125_enable_cfg9346_write(tp); + rtl8125_set_mac_ocp_bit(tp, 0xEB54, BIT_0); + udelay(1); + rtl8125_clear_mac_ocp_bit(tp, 0xEB54, BIT_0); +} + +static void +rtl8125_enable_tcam(struct rtl8125_private *tp) +{ + if (tp->HwSuppTcamVer != 1) + return; + + RTL_W16(tp, 0x382, 0x221B); +} + +static u8 +rtl8125_get_l1off_cap_bits(struct rtl8125_private *tp) +{ + u8 l1offCapBits = 0; + + l1offCapBits = (BIT_0 | BIT_1); switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: case CFG_METHOD_4: case CFG_METHOD_5: - case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - RTL_W8(tp, 0xF1, RTL_R8(tp, 0xF1) & ~BIT_7); - RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); - RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + l1offCapBits |= (BIT_2 | BIT_3); + break; + default: break; } - //clear io_rdy_l23 + return l1offCapBits; +} + +void +rtl8125_hw_config(struct net_device *dev) +{ + struct rtl8125_private *tp = netdev_priv(dev); + struct pci_dev *pdev = tp->pci_dev; + u16 mac_ocp_data; + + rtl8125_disable_rx_packet_filter(tp); + + rtl8125_hw_reset(dev); + + rtl8125_enable_cfg9346_write(tp); switch (tp->mcfg) { case CFG_METHOD_2: case CFG_METHOD_3: @@ -14536,10 +16909,17 @@ rtl8125_hw_config(struct net_device *dev) case CFG_METHOD_5: case CFG_METHOD_6: case CFG_METHOD_7: - RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~BIT_1); + case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_enable_force_clkreq(tp, 0); + rtl8125_enable_aspm_clkreq_lock(tp, 0); break; } + rtl8125_set_eee_lpi_timer(tp); + //keep magic packet only switch (tp->mcfg) { case CFG_METHOD_2: @@ -14549,6 +16929,9 @@ rtl8125_hw_config(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xC0B6); mac_ocp_data &= BIT_0; rtl8125_mac_ocp_write(tp, 0xC0B6, mac_ocp_data); @@ -14573,17 +16956,24 @@ rtl8125_hw_config(struct net_device *dev) else rtl8125_disable_double_vlan(tp); + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_7: + rtl8125_enable_tcam(tp); + break; + } + if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || tp->mcfg == CFG_METHOD_4 || tp->mcfg == CFG_METHOD_5 || tp->mcfg == CFG_METHOD_6 || tp->mcfg == CFG_METHOD_7 || - tp->mcfg == CFG_METHOD_8) { + tp->mcfg == CFG_METHOD_8 || + tp->mcfg == CFG_METHOD_9 || + tp->mcfg == CFG_METHOD_10 || + tp->mcfg == CFG_METHOD_11) { set_offset70F(tp, 0x27); - set_offset79(tp, 0x50); - - RTL_W16(tp, 0x382, 0x221B); + set_offset79(tp, 0x40); #ifdef ENABLE_RSS_SUPPORT rtl8125_config_rss(tp); @@ -14603,12 +16993,10 @@ rtl8125_hw_config(struct net_device *dev) rtl8125_mac_ocp_write(tp, 0xEB58, mac_ocp_data); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE614); - mac_ocp_data &= ~( BIT_10 | BIT_9 | BIT_8); + mac_ocp_data &= ~(BIT_10 | BIT_9 | BIT_8); if (tp->mcfg == CFG_METHOD_4 || tp->mcfg == CFG_METHOD_5 || tp->mcfg == CFG_METHOD_7) mac_ocp_data |= ((2 & 0x07) << 8); - else if (tp->mcfg == CFG_METHOD_8) - mac_ocp_data |= ((4 & 0x07) << 8); else mac_ocp_data |= ((3 & 0x07) << 8); rtl8125_mac_ocp_write(tp, 0xE614, mac_ocp_data); @@ -14618,18 +17006,15 @@ rtl8125_hw_config(struct net_device *dev) mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE63E); mac_ocp_data &= ~(BIT_5 | BIT_4); if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || - tp->mcfg == CFG_METHOD_6 || tp->mcfg == CFG_METHOD_8) + tp->mcfg == CFG_METHOD_6) mac_ocp_data |= ((0x02 & 0x03) << 4); rtl8125_mac_ocp_write(tp, 0xE63E, mac_ocp_data); - mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xC0B4); - mac_ocp_data &= ~BIT_0; - rtl8125_mac_ocp_write(tp, 0xC0B4, mac_ocp_data); - mac_ocp_data |= BIT_0; - rtl8125_mac_ocp_write(tp, 0xC0B4, mac_ocp_data); + rtl8125_enable_mcu(tp, 0); + rtl8125_enable_mcu(tp, 1); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xC0B4); - mac_ocp_data |= (BIT_3|BIT_2); + mac_ocp_data |= (BIT_3 | BIT_2); rtl8125_mac_ocp_write(tp, 0xC0B4, mac_ocp_data); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xEB6A); @@ -14649,8 +17034,6 @@ rtl8125_hw_config(struct net_device *dev) RTL_W8(tp, TDFNR, 0x10); - RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_7); - mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xE040); mac_ocp_data &= ~(BIT_12); rtl8125_mac_ocp_write(tp, 0xE040, mac_ocp_data); @@ -14660,10 +17043,33 @@ rtl8125_hw_config(struct net_device *dev) mac_ocp_data |= (BIT_0); rtl8125_mac_ocp_write(tp, 0xEA1C, mac_ocp_data); - rtl8125_mac_ocp_write(tp, 0xE0C0, 0x4000); + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + case CFG_METHOD_8: + case CFG_METHOD_9: + rtl8125_oob_mutex_lock(tp); + break; + } + + if (tp->mcfg == CFG_METHOD_10 || tp->mcfg == CFG_METHOD_11) + rtl8125_mac_ocp_write(tp, 0xE0C0, 0x4403); + else + rtl8125_mac_ocp_write(tp, 0xE0C0, 0x4000); + + rtl8125_set_mac_ocp_bit(tp, 0xE052, (BIT_6 | BIT_5)); + rtl8125_clear_mac_ocp_bit(tp, 0xE052, BIT_3 | BIT_7); - SetMcuAccessRegBit(tp, 0xE052, (BIT_6 | BIT_5)); - ClearMcuAccessRegBit(tp, 0xE052, BIT_3 | BIT_7); + switch (tp->mcfg) { + case CFG_METHOD_2: + case CFG_METHOD_3: + case CFG_METHOD_6: + case CFG_METHOD_8: + case CFG_METHOD_9: + rtl8125_oob_mutex_unlock(tp); + break; + } mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xD430); mac_ocp_data &= ~(BIT_11 | BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | BIT_4 | BIT_3 | BIT_2 | BIT_1 | BIT_0); @@ -14674,22 +17080,31 @@ rtl8125_hw_config(struct net_device *dev) if (!tp->DASH) RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) | BIT_6 | BIT_7); else - RTL_W8(tp, 0xD0, (RTL_R8(tp, 0xD0) & ~BIT_6) | BIT_7); + RTL_W8(tp, 0xD0, RTL_R8(tp, 0xD0) & ~(BIT_6 | BIT_7)); if (tp->mcfg == CFG_METHOD_2 || tp->mcfg == CFG_METHOD_3 || tp->mcfg == CFG_METHOD_6) RTL_W8(tp, MCUCmd_reg, RTL_R8(tp, MCUCmd_reg) | BIT_0); - rtl8125_disable_eee_plus(tp); + if (tp->mcfg != CFG_METHOD_10 && tp->mcfg != CFG_METHOD_11) + rtl8125_disable_eee_plus(tp); mac_ocp_data = rtl8125_mac_ocp_read(tp, 0xEA1C); mac_ocp_data &= ~(BIT_2); rtl8125_mac_ocp_write(tp, 0xEA1C, mac_ocp_data); - SetMcuAccessRegBit(tp, 0xEB54, BIT_0); - udelay(1); - ClearMcuAccessRegBit(tp, 0xEB54, BIT_0); + rtl8125_clear_tcam_entries(tp); + RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~(BIT_4 | BIT_5)); + + if (tp->HwSuppRxDescType == RX_DESC_RING_TYPE_4) { + if (tp->InitRxDescType == RX_DESC_RING_TYPE_4) + RTL_W8(tp, 0xd8, RTL_R8(tp, 0xd8) | + EnableRxDescV4_0); + else + RTL_W8(tp, 0xd8, RTL_R8(tp, 0xd8) & + ~EnableRxDescV4_0); + } } /* csum offload command for RTL8125 */ @@ -14699,7 +17114,7 @@ rtl8125_hw_config(struct net_device *dev) tp->tx_ipv6_csum_cmd = TxIPV6F_C; /* config interrupt type for RTL8125B */ - if (tp->HwSuppIsrVer == 2) + if (tp->HwSuppIsrVer > 1) rtl8125_hw_set_interrupt_type(tp, tp->HwCurrIsrVer); //other hw parameters @@ -14707,15 +17122,9 @@ rtl8125_hw_config(struct net_device *dev) rtl8125_hw_clear_int_miti(dev); - if (tp->RequireRduNonStopPatch && - tp->ShortPacketEmptyBuffer) { - RTL_W32(tp, RSS_INDIRECTION_TBL_8125_V2, ((u64)tp->ShortPacketEmptyBufferPhy & DMA_BIT_MASK(32))); - RTL_W32(tp, RSS_INDIRECTION_TBL_8125_V2 + 4, ((u64)tp->ShortPacketEmptyBufferPhy >> 32)); - } - - if (tp->use_timer_interrrupt && - (tp->HwCurrIsrVer == 2) && - (tp->HwSuppIntMitiVer == 4) && + if (tp->use_timer_interrupt && + (tp->HwCurrIsrVer > 1) && + (tp->HwSuppIntMitiVer > 3) && (tp->features & RTL_FEATURE_MSIX)) { int i; for (i = 0; i < tp->irq_nvecs; i++) @@ -14732,6 +17141,9 @@ rtl8125_hw_config(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_mac_ocp_write(tp, 0xE098, 0xC302); break; } @@ -14744,6 +17156,9 @@ rtl8125_hw_config(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_disable_pci_offset_99(tp); if (aspm) { if (tp->org_pci_offset_99 & (BIT_2 | BIT_5 | BIT_6)) @@ -14759,14 +17174,20 @@ rtl8125_hw_config(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: rtl8125_disable_pci_offset_180(tp); if (aspm) { - if (tp->org_pci_offset_180 & (BIT_0|BIT_1)) + if (tp->org_pci_offset_180 & rtl8125_get_l1off_cap_bits(tp)) rtl8125_init_pci_offset_180(tp); } break; } + if (tp->RequiredPfmPatch) + rtl8125_set_pfm_patch(tp, 0); + tp->cp_cmd &= ~(EnableBist | Macdbgo_oe | Force_halfdup | Force_rxflow_en | Force_txflow_en | Cxpl_dbg_sel | ASF | Macdbgo_sel); @@ -14776,24 +17197,6 @@ rtl8125_hw_config(struct net_device *dev) #else rtl8125_hw_set_features(dev, dev->features); #endif - - switch (tp->mcfg) { - case CFG_METHOD_2: - case CFG_METHOD_3: - case CFG_METHOD_4: - case CFG_METHOD_5: - case CFG_METHOD_6: - case CFG_METHOD_7: { - int timeout; - for (timeout = 0; timeout < 10; timeout++) { - if ((rtl8125_mac_ocp_read(tp, 0xE00E) & BIT_13)==0) - break; - mdelay(1); - } - } - break; - } - RTL_W16(tp, RxMaxSize, tp->rms); rtl8125_disable_rxdvgate(dev); @@ -14837,13 +17240,10 @@ rtl8125_hw_config(struct net_device *dev) case CFG_METHOD_6: case CFG_METHOD_7: case CFG_METHOD_8: - if (aspm) { - RTL_W8(tp, Config5, RTL_R8(tp, Config5) | BIT_0); - RTL_W8(tp, Config2, RTL_R8(tp, Config2) | BIT_7); - } else { - RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~BIT_7); - RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~BIT_0); - } + case CFG_METHOD_9: + case CFG_METHOD_10: + case CFG_METHOD_11: + rtl8125_enable_aspm_clkreq_lock(tp, aspm ? 1 : 0); break; } @@ -14884,6 +17284,8 @@ rtl8125_change_mtu(struct net_device *dev, dev->mtu = new_mtu; + tp->eee.tx_lpi_timer = dev->mtu + ETH_HLEN + 0x20; + if (!netif_running(dev)) goto out; @@ -14900,12 +17302,10 @@ rtl8125_change_mtu(struct net_device *dev, rtl8125_enable_napi(tp); #endif//CONFIG_R8125_NAPI - //netif_carrier_off(dev); - //netif_tx_disable(dev); - rtl8125_hw_config(dev); - rtl8125_enable_hw_linkchg_interrupt(tp); - - rtl8125_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); + if (tp->link_ok(dev)) + rtl8125_link_on_patch(dev); + else + rtl8125_link_down_patch(dev); //mod_timer(&tp->esd_timer, jiffies + RTL8125_ESD_TIMEOUT); //mod_timer(&tp->link_timer, jiffies + RTL8125_LINK_TIMEOUT); @@ -14918,6 +17318,33 @@ rtl8125_change_mtu(struct net_device *dev, return ret; } +static inline void +rtl8125_set_desc_dma_addr(struct rtl8125_private *tp, + struct RxDesc *desc, + dma_addr_t mapping) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + ((struct RxDescV3 *)desc)->addr = cpu_to_le64(mapping); + break; + case RX_DESC_RING_TYPE_4: + ((struct RxDescV4 *)desc)->addr = cpu_to_le64(mapping); + break; + default: + desc->addr = cpu_to_le64(mapping); + break; + } +} + +static inline void +rtl8125_mark_to_asic_v1(struct RxDesc *desc, + u32 rx_buf_sz) +{ + u32 eor = le32_to_cpu(desc->opts1) & RingEnd; + + WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); +} + static inline void rtl8125_mark_to_asic_v3(struct RxDescV3 *descv3, u32 rx_buf_sz) @@ -14927,17 +17354,30 @@ rtl8125_mark_to_asic_v3(struct RxDescV3 *descv3, WRITE_ONCE(descv3->RxDescNormalDDWord4.opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); } +static inline void +rtl8125_mark_to_asic_v4(struct RxDescV4 *descv4, + u32 rx_buf_sz) +{ + u32 eor = le32_to_cpu(descv4->RxDescNormalDDWord2.opts1) & RingEnd; + + WRITE_ONCE(descv4->RxDescNormalDDWord2.opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); +} + void rtl8125_mark_to_asic(struct rtl8125_private *tp, struct RxDesc *desc, u32 rx_buf_sz) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: rtl8125_mark_to_asic_v3((struct RxDescV3 *)desc, rx_buf_sz); - else { - u32 eor = le32_to_cpu(desc->opts1) & RingEnd; - - WRITE_ONCE(desc->opts1, cpu_to_le32(DescOwn | eor | rx_buf_sz)); + break; + case RX_DESC_RING_TYPE_4: + rtl8125_mark_to_asic_v4((struct RxDescV4 *)desc, rx_buf_sz); + break; + default: + rtl8125_mark_to_asic_v1(desc, rx_buf_sz); + break; } } @@ -14950,10 +17390,7 @@ rtl8125_map_to_asic(struct rtl8125_private *tp, const u32 cur_rx) { ring->RxDescPhyAddr[cur_rx] = mapping; - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) - ((struct RxDescV3 *)desc)->addr = cpu_to_le64(mapping); - else - desc->addr = cpu_to_le64(mapping); + rtl8125_set_desc_dma_addr(tp, desc, mapping); wmb(); rtl8125_mark_to_asic(tp, desc, rx_buf_sz); } @@ -15052,7 +17489,8 @@ rtl8125_rx_fill(struct rtl8125_private *tp, tp->rx_buf_sz, DMA_FROM_DEVICE); - rtl8125_map_to_asic(tp, ring, ring->RxDescArray + i, + rtl8125_map_to_asic(tp, ring, + rtl8125_get_rxdesc(tp, ring->RxDescArray, i), rxb->dma + rxb->page_offset, tp->rx_buf_sz, i); } @@ -15098,7 +17536,8 @@ rtl8125_alloc_rx_skb(struct rtl8125_private *tp, if (unlikely(!skb)) goto err_out; - skb_reserve(skb, R8125_RX_ALIGN); + if (!in_intr || !R8125_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8125_RX_ALIGN); mapping = dma_map_single(tp_to_dev(tp), skb->data, rx_buf_sz, DMA_FROM_DEVICE); @@ -15160,8 +17599,7 @@ rtl8125_rx_fill(struct rtl8125_private *tp, rtl8125_get_rxdesc(tp, ring->RxDescArray, i), tp->rx_buf_sz, i, - in_intr - ); + in_intr); if (ret < 0) break; } @@ -15182,20 +17620,39 @@ rtl8125_rx_clear(struct rtl8125_private *tp) } } -static inline void -rtl8125_mark_as_last_descriptor_8125(struct RxDescV3 *descv3) +static void +rtl8125_mark_as_last_descriptor_v1(struct RxDesc *desc) +{ + desc->opts1 |= cpu_to_le32(RingEnd); +} + +static void +rtl8125_mark_as_last_descriptor_v3(struct RxDescV3 *descv3) { descv3->RxDescNormalDDWord4.opts1 |= cpu_to_le32(RingEnd); } -static inline void +static void +rtl8125_mark_as_last_descriptor_v4(struct RxDescV4 *descv4) +{ + descv4->RxDescNormalDDWord2.opts1 |= cpu_to_le32(RingEnd); +} + +void rtl8125_mark_as_last_descriptor(struct rtl8125_private *tp, struct RxDesc *desc) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) - rtl8125_mark_as_last_descriptor_8125((struct RxDescV3 *)desc); - else - desc->opts1 |= cpu_to_le32(RingEnd); + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + rtl8125_mark_as_last_descriptor_v3((struct RxDescV3 *)desc); + break; + case RX_DESC_RING_TYPE_4: + rtl8125_mark_as_last_descriptor_v4((struct RxDescV4 *)desc); + break; + default: + rtl8125_mark_as_last_descriptor_v1(desc); + break; + } } static void @@ -15373,7 +17830,8 @@ static void rtl8125_cancel_schedule_reset_work(struct rtl8125_private *tp) { struct work_struct *work = &tp->reset_task.work; - if (!work->func) return; + if (!work->func) + return; cancel_delayed_work_sync(&tp->reset_task); } @@ -15388,7 +17846,8 @@ static void rtl8125_cancel_schedule_esd_work(struct rtl8125_private *tp) { struct work_struct *work = &tp->esd_task.work; - if (!work->func) return; + if (!work->func) + return; cancel_delayed_work_sync(&tp->esd_task); } @@ -15403,7 +17862,8 @@ static void rtl8125_cancel_schedule_linkchg_work(struct rtl8125_private *tp) { struct work_struct *work = &tp->linkchg_task.work; - if (!work->func) return; + if (!work->func) + return; cancel_delayed_work_sync(&tp->linkchg_task); } @@ -15476,14 +17936,6 @@ rtl8125_wait_for_quiescence(struct net_device *dev) #endif//CONFIG_R8125_NAPI } -static int rtl8125_rx_nostuck(struct rtl8125_private *tp) -{ - int i, ret = 1; - for (i = 0; i < tp->num_rx_rings; i++) - ret &= (tp->rx_ring[i].dirty_rx == tp->rx_ring[i].cur_rx); - return ret; -} - #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20) static void rtl8125_reset_task(void *_data) { @@ -15496,7 +17948,6 @@ static void rtl8125_reset_task(struct work_struct *work) container_of(work, struct rtl8125_private, reset_task.work); struct net_device *dev = tp->dev; #endif - u32 budget = ~(u32)0; int i; rtnl_lock(); @@ -15506,47 +17957,47 @@ static void rtl8125_reset_task(struct work_struct *work) !test_and_clear_bit(R8125_FLAG_TASK_RESET_PENDING, tp->task_flags)) goto out_unlock; - rtl8125_wait_for_quiescence(dev); - - for (i = 0; i < tp->num_rx_rings; i++) { -#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) - rtl8125_rx_interrupt(dev, tp, &tp->rx_ring[i], &budget); -#else - rtl8125_rx_interrupt(dev, tp, &tp->rx_ring[i], budget); -#endif //LINUX_VERSION_CODE < KERNEL_VERSION(2,6,24) - } - + netdev_err(dev, "Device reseting!\n"); + netif_carrier_off(dev); netif_tx_disable(dev); + _rtl8125_wait_for_quiescence(dev); rtl8125_hw_reset(dev); rtl8125_tx_clear(tp); - if (rtl8125_rx_nostuck(tp)) { - rtl8125_rx_clear(tp); - rtl8125_init_ring(dev); + rtl8125_init_ring_indexes(tp); + + rtl8125_tx_desc_init(tp); + for (i = 0; i < tp->num_rx_rings; i++) { + struct rtl8125_rx_ring *ring; + u32 entry; + + ring = &tp->rx_ring[i]; + for (entry = 0; entry < ring->num_rx_desc; entry++) { + struct RxDesc *desc; + + desc = rtl8125_get_rxdesc(tp, ring->RxDescArray, entry); + rtl8125_mark_to_asic(tp, desc, tp->rx_buf_sz); + } + } + #ifdef ENABLE_PTP_SUPPORT - rtl8125_ptp_reset(tp); + rtl8125_ptp_reset(tp); #endif - if (tp->resume_not_chg_speed) { - _rtl8125_check_link_status(dev); - tp->resume_not_chg_speed = 0; - } else { - rtl8125_enable_hw_linkchg_interrupt(tp); +#ifdef CONFIG_R8125_NAPI + rtl8125_enable_napi(tp); +#endif //CONFIG_R8125_NAPI - rtl8125_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); - } + if (tp->resume_not_chg_speed) { + _rtl8125_check_link_status(dev); + + tp->resume_not_chg_speed = 0; } else { - if (unlikely(net_ratelimit())) { - struct rtl8125_private *tp = netdev_priv(dev); + rtl8125_enable_hw_linkchg_interrupt(tp); - if (netif_msg_intr(tp)) { - printk(PFX KERN_EMERG - "%s: Rx buffers shortage\n", dev->name); - } - } - rtl8125_schedule_reset_work(tp); + rtl8125_set_speed(dev, tp->autoneg, tp->speed, tp->duplex, tp->advertising); } out_unlock: @@ -15615,6 +18066,8 @@ rtl8125_tx_timeout(struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); + netdev_err(dev, "Transmit timeout reset Device!\n"); + /* Let's wait a bit while any (async) irq lands on */ rtl8125_schedule_reset_work(tp); } @@ -15710,10 +18163,8 @@ rtl8125_xmit_frags(struct rtl8125_private *tp, /* anti gcc 2.95.3 bugware (sic) */ status = rtl8125_get_txd_opts1(ring, opts[0], len, entry); - if (cur_frag == (nr_frags - 1) || LsoPatchEnabled == TRUE) { - //ring->tx_skb[entry].skb = skb; + if (cur_frag == (nr_frags - 1) || LsoPatchEnabled == TRUE) status |= LastFrag; - } txd->addr = cpu_to_le64(mapping); @@ -15816,9 +18267,20 @@ static int msdn_giant_send_check(struct sk_buff *skb) } #endif +static bool rtl8125_require_pad_ptp_pkt(struct rtl8125_private *tp) +{ + switch (tp->mcfg) { + case CFG_METHOD_2 ... CFG_METHOD_7: + return true; + default: + return false; + } +} + #define MIN_PATCH_LEN (47) static u32 -rtl8125_get_patch_pad_len(struct sk_buff *skb) +rtl8125_get_patch_pad_len(struct rtl8125_private *tp, + struct sk_buff *skb) { u32 pad_len = 0; int trans_data_len; @@ -15827,6 +18289,9 @@ rtl8125_get_patch_pad_len(struct sk_buff *skb) u8 ip_protocol; bool has_trans = skb_transport_header_was_set(skb); + if (!rtl8125_require_pad_ptp_pkt(tp)) + goto no_padding; + if (!(has_trans && (pkt_len < 175))) //128 + MIN_PATCH_LEN goto no_padding; @@ -15874,7 +18339,9 @@ rtl8125_get_patch_pad_len(struct sk_buff *skb) static bool rtl8125_tso_csum(struct sk_buff *skb, struct net_device *dev, - u32 *opts) + u32 *opts, + unsigned int *bytecount, + unsigned short *gso_segs) { struct rtl8125_private *tp = netdev_priv(dev); unsigned long large_send = 0; @@ -15892,12 +18359,28 @@ rtl8125_tso_csum(struct sk_buff *skb, /* TCP Segmentation Offload (or TCP Large Send) */ if (mss) { - assert((skb_transport_offset(skb)%2) == 0); + union { + struct iphdr *v4; + struct ipv6hdr *v6; + unsigned char *hdr; + } ip; + union { + struct tcphdr *tcp; + struct udphdr *udp; + unsigned char *hdr; + } l4; + u32 l4_offset, hdr_len; + + ip.hdr = skb_network_header(skb); + l4.hdr = skb_checksum_start(skb); + + l4_offset = skb_transport_offset(skb); + assert((l4_offset%2) == 0); switch (get_protocol(skb)) { case __constant_htons(ETH_P_IP): - if (skb_transport_offset(skb) <= GTTCPHO_MAX) { + if (l4_offset <= GTTCPHO_MAX) { opts[0] |= GiantSendv4; - opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; + opts[0] |= l4_offset << GTTCPHO_SHIFT; opts[1] |= min(mss, MSS_MAX) << 18; large_send = 1; } @@ -15907,9 +18390,9 @@ rtl8125_tso_csum(struct sk_buff *skb, if (msdn_giant_send_check(skb)) return false; #endif - if (skb_transport_offset(skb) <= GTTCPHO_MAX) { + if (l4_offset <= GTTCPHO_MAX) { opts[0] |= GiantSendv6; - opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; + opts[0] |= l4_offset << GTTCPHO_SHIFT; opts[1] |= min(mss, MSS_MAX) << 18; large_send = 1; } @@ -15923,6 +18406,13 @@ rtl8125_tso_csum(struct sk_buff *skb, if (large_send == 0) return false; + + /* compute length of segmentation header */ + hdr_len = (l4.tcp->doff * 4) + l4_offset; + /* update gso size and bytecount with header size */ + *gso_segs = skb_shinfo(skb)->gso_segs; + *bytecount += (*gso_segs - 1) * hdr_len; + return true; } } @@ -15982,7 +18472,7 @@ rtl8125_tso_csum(struct sk_buff *skb, } if (check_patch_required) { - u32 pad_len = rtl8125_get_patch_pad_len(skb); + u32 pad_len = rtl8125_get_patch_pad_len(tp, skb); if (pad_len > 0) { if (!rtl8125_skb_pad_with_len(skb, skb->len + pad_len)) @@ -16034,11 +18524,27 @@ rtl8125_fast_mod_mask(const u32 input, const u32 mask) return input > mask ? input & mask : input; } +static void rtl8125_doorbell(struct rtl8125_private *tp, + struct rtl8125_tx_ring *ring) +{ + if (tp->EnableTxNoClose) { + if (tp->HwSuppTxNoCloseVer > 3) + RTL_W32(tp, ring->sw_tail_ptr_reg, ring->cur_tx); + else + RTL_W16(tp, ring->sw_tail_ptr_reg, ring->cur_tx); + } else + RTL_W16(tp, TPPOLL_8125, BIT(ring->index)); /* set polling bit */ +} + static netdev_tx_t rtl8125_start_xmit(struct sk_buff *skb, struct net_device *dev) { struct rtl8125_private *tp = netdev_priv(dev); + unsigned int bytecount; + unsigned short gso_segs; + struct ring_info *last; + unsigned int last_entry; unsigned int entry; struct TxDesc *txd; dma_addr_t mapping; @@ -16079,10 +18585,13 @@ rtl8125_start_xmit(struct sk_buff *skb, } } + bytecount = skb->len; + gso_segs = 1; + opts[0] = DescOwn; opts[1] = rtl8125_tx_vlan_tag(tp, skb); - if (unlikely(!rtl8125_tso_csum(skb, dev, opts))) + if (unlikely(!rtl8125_tso_csum(skb, dev, opts, &bytecount, &gso_segs))) goto err_dma_0; frags = rtl8125_xmit_frags(tp, ring, skb, opts); @@ -16093,9 +18602,6 @@ rtl8125_start_xmit(struct sk_buff *skb, opts[0] |= FirstFrag; } else { len = skb->len; - - //ring->tx_skb[entry].skb = skb; - opts[0] |= FirstFrag | LastFrag; } @@ -16106,27 +18612,39 @@ rtl8125_start_xmit(struct sk_buff *skb, netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); goto err_dma_1; } - ring->tx_skb[entry].len = len; + #ifdef ENABLE_PTP_SUPPORT if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { - if (tp->hwtstamp_config.tx_type == HWTSTAMP_TX_ON && - !tp->ptp_tx_skb) { - skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; - - tp->ptp_tx_skb = skb_get(skb); - tp->ptp_tx_start = jiffies; - schedule_work(&tp->ptp_tx_work); - } else { - tp->tx_hwtstamp_skipped++; + if (!test_and_set_bit_lock(__RTL8125_PTP_TX_IN_PROGRESS, &tp->state)) { + if (tp->hwtstamp_config.tx_type == HWTSTAMP_TX_ON && + !tp->ptp_tx_skb) { + skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; + + tp->ptp_tx_skb = skb_get(skb); + tp->ptp_tx_start = jiffies; + schedule_work(&tp->ptp_tx_work); + } else + tp->tx_hwtstamp_skipped++; } } #endif - ring->tx_skb[entry].skb = skb; + /* set first fragment's length */ + ring->tx_skb[entry].len = len; + + /* set skb to last fragment */ + last_entry = (entry + frags) % ring->num_tx_desc; + last = &ring->tx_skb[last_entry]; + last->skb = skb; + last->gso_segs = gso_segs; + last->bytecount = bytecount; + txd->addr = cpu_to_le64(mapping); txd->opts2 = cpu_to_le32(opts[1]); wmb(); txd->opts1 = cpu_to_le32(opts[0]); + netdev_tx_sent_queue(txring_txq(ring), bytecount); + #if LINUX_VERSION_CODE < KERNEL_VERSION(3,5,0) dev->trans_start = jiffies; #else @@ -16147,13 +18665,8 @@ rtl8125_start_xmit(struct sk_buff *skb, netif_stop_subqueue(dev, queue_mapping); } - if (EnableTxNoClose) { - if (tp->HwSuppTxNoCloseVer == 4) - RTL_W32(tp, ring->sw_tail_ptr_reg, ring->cur_tx); - else - RTL_W16(tp, ring->sw_tail_ptr_reg, ring->cur_tx); - } else - RTL_W16(tp, TPPOLL_8125, BIT(ring->index)); /* set polling bit */ + if (netif_xmit_stopped(txring_txq(ring)) || !netdev_xmit_more()) + rtl8125_doorbell(tp, ring); if (unlikely(stop_queue)) { /* Sync with rtl_tx: @@ -16170,7 +18683,6 @@ rtl8125_start_xmit(struct sk_buff *skb, out: return ret; err_dma_1: - ring->tx_skb[entry].skb = NULL; rtl8125_tx_clear_range(tp, ring, ring->cur_tx + 1, frags); err_dma_0: RTLDEV->stats.tx_dropped++; @@ -16184,62 +18696,95 @@ rtl8125_start_xmit(struct sk_buff *skb, goto out; } -static u32 -rtl8125_get_hw_clo_ptr(struct rtl8125_tx_ring *ring) +/* recycle tx no close desc*/ +static int +rtl8125_tx_interrupt_noclose(struct rtl8125_tx_ring *ring, int budget) { + unsigned int total_bytes = 0, total_packets = 0; struct rtl8125_private *tp = ring->priv; + struct net_device *dev = tp->dev; + unsigned int dirty_tx, tx_left; + unsigned int tx_desc_closed; + unsigned int count = 0; - switch (tp->HwSuppTxNoCloseVer) { - case 3: - return RTL_R16(tp, ring->hw_clo_ptr_reg); - case 4: - return RTL_R32(tp, ring->hw_clo_ptr_reg); - default: -#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,0) - WARN_ON(1); -#endif - return 0; + dirty_tx = ring->dirty_tx; + ring->NextHwDesCloPtr = rtl8125_get_hw_clo_ptr(ring); + tx_desc_closed = rtl8125_fast_mod_mask(ring->NextHwDesCloPtr - + ring->BeginHwDesCloPtr, + tp->MaxTxDescPtrMask); + tx_left = min((READ_ONCE(ring->cur_tx) - dirty_tx), tx_desc_closed); + ring->BeginHwDesCloPtr += tx_left; + + while (tx_left > 0) { + unsigned int entry = dirty_tx % ring->num_tx_desc; + struct ring_info *tx_skb = ring->tx_skb + entry; + + rtl8125_unmap_tx_skb(tp->pci_dev, + tx_skb, + ring->TxDescArray + entry); + + if (tx_skb->skb != NULL) { + /* update the statistics for this packet */ + total_bytes += tx_skb->bytecount; + total_packets += tx_skb->gso_segs; + + RTL_NAPI_CONSUME_SKB_ANY(tx_skb->skb, budget); + tx_skb->skb = NULL; + } + dirty_tx++; + tx_left--; } + + if (total_packets) { + netdev_tx_completed_queue(txring_txq(ring), + total_packets, total_bytes); + + RTLDEV->stats.tx_bytes += total_bytes; + RTLDEV->stats.tx_packets+= total_packets; + } + + if (ring->dirty_tx != dirty_tx) { + count = dirty_tx - ring->dirty_tx; + WRITE_ONCE(ring->dirty_tx, dirty_tx); + smp_wmb(); + if (__netif_subqueue_stopped(dev, ring->index) && + (rtl8125_tx_slots_avail(tp, ring))) { + netif_start_subqueue(dev, ring->index); + } + } + + return count; } +/* recycle tx close desc*/ static int -rtl8125_tx_interrupt(struct rtl8125_tx_ring *ring, int budget) +rtl8125_tx_interrupt_close(struct rtl8125_tx_ring *ring, int budget) { + unsigned int total_bytes = 0, total_packets = 0; struct rtl8125_private *tp = ring->priv; struct net_device *dev = tp->dev; unsigned int dirty_tx, tx_left; unsigned int count = 0; - u8 EnableTxNoClose = tp->EnableTxNoClose; dirty_tx = ring->dirty_tx; - smp_rmb(); tx_left = READ_ONCE(ring->cur_tx) - dirty_tx; - if (EnableTxNoClose) { - unsigned int tx_desc_closed; - u32 NextHwDesCloPtr = rtl8125_get_hw_clo_ptr(ring); - ring->NextHwDesCloPtr = NextHwDesCloPtr; - smp_rmb(); - tx_desc_closed = rtl8125_fast_mod_mask(NextHwDesCloPtr - ring->BeginHwDesCloPtr, tp->MaxTxDescPtrMask); - if(tx_left > tx_desc_closed) tx_left = tx_desc_closed; - ring->BeginHwDesCloPtr = NextHwDesCloPtr; - } while (tx_left > 0) { unsigned int entry = dirty_tx % ring->num_tx_desc; struct ring_info *tx_skb = ring->tx_skb + entry; - if (!EnableTxNoClose && - (le32_to_cpu(ring->TxDescArray[entry].opts1) & DescOwn)) + if (le32_to_cpu(ring->TxDescArray[entry].opts1) & DescOwn) break; - RTLDEV->stats.tx_bytes += tx_skb->len; - RTLDEV->stats.tx_packets++; - rtl8125_unmap_tx_skb(tp->pci_dev, tx_skb, ring->TxDescArray + entry); if (tx_skb->skb != NULL) { + /* update the statistics for this packet */ + total_bytes += tx_skb->bytecount; + total_packets += tx_skb->gso_segs; + RTL_NAPI_CONSUME_SKB_ANY(tx_skb->skb, budget); tx_skb->skb = NULL; } @@ -16247,6 +18792,14 @@ rtl8125_tx_interrupt(struct rtl8125_tx_ring *ring, int budget) tx_left--; } + if (total_packets) { + netdev_tx_completed_queue(txring_txq(ring), + total_packets, total_bytes); + + RTLDEV->stats.tx_bytes += total_bytes; + RTLDEV->stats.tx_packets+= total_packets; + } + if (ring->dirty_tx != dirty_tx) { count = dirty_tx - ring->dirty_tx; WRITE_ONCE(ring->dirty_tx, dirty_tx); @@ -16255,15 +18808,25 @@ rtl8125_tx_interrupt(struct rtl8125_tx_ring *ring, int budget) (rtl8125_tx_slots_avail(tp, ring))) { netif_start_subqueue(dev, ring->index); } - smp_rmb(); - if (!EnableTxNoClose && (ring->cur_tx != dirty_tx)) { - RTL_W16(tp, TPPOLL_8125, BIT(ring->index)); - } + + if (ring->cur_tx != dirty_tx) + rtl8125_doorbell(tp, ring); } return count; } +static int +rtl8125_tx_interrupt(struct rtl8125_tx_ring *ring, int budget) +{ + struct rtl8125_private *tp = ring->priv; + + if (tp->EnableTxNoClose) + return rtl8125_tx_interrupt_noclose(ring, budget); + else + return rtl8125_tx_interrupt_close(ring, budget); +} + static int rtl8125_tx_interrupt_with_vector(struct rtl8125_private *tp, const int message_id, @@ -16271,12 +18834,29 @@ rtl8125_tx_interrupt_with_vector(struct rtl8125_private *tp, { int count = 0; - if (message_id == 16) - count += rtl8125_tx_interrupt(&tp->tx_ring[0], budget); + switch (tp->HwCurrIsrVer) { + case 3: + case 4: + if (message_id < tp->num_tx_rings) + count += rtl8125_tx_interrupt(&tp->tx_ring[message_id], budget); + break; + case 5: + if (message_id == 16) + count += rtl8125_tx_interrupt(&tp->tx_ring[0], budget); +#ifdef ENABLE_MULTIPLE_TX_QUEUE + else if (message_id == 17) + count += rtl8125_tx_interrupt(&tp->tx_ring[1], budget); +#endif + break; + default: + if (message_id == 16) + count += rtl8125_tx_interrupt(&tp->tx_ring[0], budget); #ifdef ENABLE_MULTIPLE_TX_QUEUE - else if (message_id == 18) - count += rtl8125_tx_interrupt(&tp->tx_ring[1], budget); + else if (message_id == 18) + count += rtl8125_tx_interrupt(&tp->tx_ring[1], budget); #endif + break; + } return count; } @@ -16284,19 +18864,27 @@ rtl8125_tx_interrupt_with_vector(struct rtl8125_private *tp, static inline int rtl8125_fragmented_frame(struct rtl8125_private *tp, u32 status) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: return (status & (FirstFrag_V3 | LastFrag_V3)) != (FirstFrag_V3 | LastFrag_V3); - else + case RX_DESC_RING_TYPE_4: + return (status & (FirstFrag_V4 | LastFrag_V4)) != (FirstFrag_V4 | LastFrag_V4); + default: return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); + } } static inline int rtl8125_is_non_eop(struct rtl8125_private *tp, u32 status) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: return !(status & LastFrag_V3); - else + case RX_DESC_RING_TYPE_4: + return !(status & LastFrag_V4); + default: return !(status & LastFrag); + } } static inline int @@ -16305,6 +18893,20 @@ rtl8125_rx_desc_type(u32 status) return ((status >> 26) & 0x0F); } +static inline void +rtl8125_rx_v1_csum(struct rtl8125_private *tp, + struct sk_buff *skb, + struct RxDesc *desc) +{ + u32 opts1 = le32_to_cpu(desc->opts1); + + if (((opts1 & RxTCPT) && !(opts1 & RxTCPF)) || + ((opts1 & RxUDPT) && !(opts1 & RxUDPF))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + skb_checksum_none_assert(skb); +} + static inline void rtl8125_rx_v3_csum(struct rtl8125_private *tp, struct sk_buff *skb, @@ -16320,21 +18922,36 @@ rtl8125_rx_v3_csum(struct rtl8125_private *tp, skb_checksum_none_assert(skb); } +static inline void +rtl8125_rx_v4_csum(struct rtl8125_private *tp, + struct sk_buff *skb, + struct RxDescV4 *descv4) +{ + u32 opts1 = le32_to_cpu(descv4->RxDescNormalDDWord2.opts1); + + /* rx csum offload for RTL8125 */ + if (((opts1 & RxTCPT_v4) && !(opts1 & RxTCPF_v4)) || + ((opts1 & RxUDPT_v4) && !(opts1 & RxUDPF_v4))) + skb->ip_summed = CHECKSUM_UNNECESSARY; + else + skb_checksum_none_assert(skb); +} + static inline void rtl8125_rx_csum(struct rtl8125_private *tp, struct sk_buff *skb, - struct RxDesc *desc, - u32 opts1) + struct RxDesc *desc) { - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: rtl8125_rx_v3_csum(tp, skb, (struct RxDescV3 *)desc); - else { - /* rx csum offload for RTL8125 */ - if (((opts1 & RxTCPT) && !(opts1 & RxTCPF)) || - ((opts1 & RxUDPT) && !(opts1 & RxUDPF))) - skb->ip_summed = CHECKSUM_UNNECESSARY; - else - skb_checksum_none_assert(skb); + break; + case RX_DESC_RING_TYPE_4: + rtl8125_rx_v4_csum(tp, skb, (struct RxDescV4 *)desc); + break; + default: + rtl8125_rx_v1_csum(tp, skb, desc); + break; } } @@ -16356,7 +18973,8 @@ rtl8125_try_rx_copy(struct rtl8125_private *tp, u8 *data; data = sk_buff[0]->data; - skb_reserve(skb, R8125_RX_ALIGN); + if (!R8125_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8125_RX_ALIGN); #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,37) prefetch(data - R8125_RX_ALIGN); #endif @@ -16393,7 +19011,8 @@ rtl8125_check_rx_desc_error(struct net_device *dev, { int ret = 0; - if (tp->InitRxDescType == RX_DESC_RING_TYPE_3) { + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: if (unlikely(status & RxRES_V3)) { if (status & (RxRWT_V3 | RxRUNT_V3)) RTLDEV->stats.rx_length_errors++; @@ -16402,7 +19021,18 @@ rtl8125_check_rx_desc_error(struct net_device *dev, ret = -1; } - } else { + break; + case RX_DESC_RING_TYPE_4: + if (unlikely(status & RxRES_V4)) { + if (status & RxRUNT_V4) + RTLDEV->stats.rx_length_errors++; + if (status & RxCRC_V4) + RTLDEV->stats.rx_crc_errors++; + + ret = -1; + } + break; + default: if (unlikely(status & RxRES)) { if (status & (RxRWT | RxRUNT)) RTLDEV->stats.rx_length_errors++; @@ -16411,6 +19041,7 @@ rtl8125_check_rx_desc_error(struct net_device *dev, ret = -1; } + break; } return ret; @@ -16496,7 +19127,8 @@ static void rtl8125_put_rx_buffer(struct rtl8125_private *tp, tp->rx_buf_sz, DMA_FROM_DEVICE); - rtl8125_map_to_asic(tp, ring, ring->RxDescArray + entry, + rtl8125_map_to_asic(tp, ring, + rtl8125_get_rxdesc(tp, ring->RxDescArray, entry), nrxb->dma + nrxb->page_offset, tp->rx_buf_sz, entry); @@ -16539,10 +19171,14 @@ rtl8125_rx_interrupt(struct net_device *dev, rx_left = rtl8125_rx_quota(rx_left, (u32)rx_quota); for (; rx_left > 0; rx_left--, cur_rx++) { - int pkt_size; +#ifdef ENABLE_PTP_SUPPORT + u8 desc_type = RXDESC_TYPE_NORMAL; + struct RxDescV3 ptp_desc; +#endif //ENABLE_PTP_SUPPORT #ifndef ENABLE_PAGE_REUSE const void *rx_buf; #endif //!ENABLE_PAGE_REUSE + u32 pkt_size; entry = cur_rx % ring->num_rx_desc; desc = rtl8125_get_rxdesc(tp, ring->RxDescArray, entry); @@ -16566,9 +19202,36 @@ rtl8125_rx_interrupt(struct net_device *dev, goto release_descriptor; } pkt_size = status & 0x00003fff; - if (likely(!(dev->features & NETIF_F_RXFCS)) && - !rtl8125_is_non_eop(tp, status)) - pkt_size -= ETH_FCS_LEN; + if (likely(!(dev->features & NETIF_F_RXFCS))) { +#ifdef ENABLE_RX_PACKET_FRAGMENT + if (rtl8125_is_non_eop(tp, status) && + pkt_size == tp->rx_buf_sz) { + struct RxDesc *desc_next; + unsigned int entry_next; + int pkt_size_next; + u32 status_next; + + entry_next = (cur_rx + 1) % ring->num_rx_desc; + desc_next = rtl8125_get_rxdesc(tp, ring->RxDescArray, entry_next); + status_next = le32_to_cpu(rtl8125_rx_desc_opts1(tp, desc_next)); + if (!(status_next & DescOwn)) { + pkt_size_next = status_next & 0x00003fff; + if (pkt_size_next < ETH_FCS_LEN) + pkt_size -= (ETH_FCS_LEN - pkt_size_next); + } + } +#endif //ENABLE_RX_PACKET_FRAGMENT + if (!rtl8125_is_non_eop(tp, status)) { + if (pkt_size < ETH_FCS_LEN) { +#ifdef ENABLE_RX_PACKET_FRAGMENT + pkt_size = 0; +#else + goto drop_packet; +#endif //ENABLE_RX_PACKET_FRAGMENT + } else + pkt_size -= ETH_FCS_LEN; + } + } if (unlikely(pkt_size > tp->rx_buf_sz)) goto drop_packet; @@ -16585,22 +19248,19 @@ rtl8125_rx_interrupt(struct net_device *dev, #ifdef ENABLE_PTP_SUPPORT if (tp->EnablePtp) { - u8 desc_type; - desc_type = rtl8125_rx_desc_type(status); if (desc_type == RXDESC_TYPE_NEXT && rx_left > 0) { u32 status_next; struct RxDescV3 *desc_next; unsigned int entry_next; - struct sk_buff *skb_next; - entry_next = (cur_rx + 1) % ring->num_rx_desc; + cur_rx++; + rx_left--; + entry_next = cur_rx % ring->num_rx_desc; desc_next = (struct RxDescV3 *)rtl8125_get_rxdesc(tp, ring->RxDescArray, entry_next); - rmb(); status_next = le32_to_cpu(desc_next->RxDescNormalDDWord4.opts1); if (unlikely(status_next & DescOwn)) { udelay(1); - rmb(); status_next = le32_to_cpu(desc_next->RxDescNormalDDWord4.opts1); if (unlikely(status_next & DescOwn)) { if (netif_msg_rx_err(tp)) { @@ -16608,24 +19268,32 @@ rtl8125_rx_interrupt(struct net_device *dev, "%s: Rx Next Desc ERROR. status = %08x\n", dev->name, status_next); } - break; + rtl8125_set_desc_dma_addr(tp, (struct RxDesc *)desc_next, + ring->RxDescPhyAddr[entry_next]); + wmb(); + rtl8125_mark_to_asic(tp, (struct RxDesc *)desc_next, tp->rx_buf_sz); + goto drop_packet; } } - cur_rx++; - rx_left--; + rmb(); + desc_type = rtl8125_rx_desc_type(status_next); - if (desc_type == RXDESC_TYPE_PTP) - rtl8125_rx_ptp_pktstamp(tp, skb, desc_next); - else + if (desc_type == RXDESC_TYPE_PTP) { + ptp_desc = *desc_next; + rmb(); + rtl8125_set_desc_dma_addr(tp, (struct RxDesc *)desc_next, + ring->RxDescPhyAddr[entry_next]); + wmb(); + rtl8125_mark_to_asic(tp, (struct RxDesc *)desc_next, tp->rx_buf_sz); + } else { WARN_ON(1); - - rx_buf_phy_addr = ring->RxDescPhyAddr[entry_next]; - dma_unmap_single(tp_to_dev(tp), rx_buf_phy_addr, - tp->rx_buf_sz, DMA_FROM_DEVICE); - skb_next = ring->Rx_skbuff[entry_next]; - dev_kfree_skb_any(skb_next); - ring->Rx_skbuff[entry_next] = NULL; + rtl8125_set_desc_dma_addr(tp, (struct RxDesc *)desc_next, + ring->RxDescPhyAddr[entry_next]); + wmb(); + rtl8125_mark_to_asic(tp, (struct RxDesc *)desc_next, tp->rx_buf_sz); + goto drop_packet; + } } else WARN_ON(desc_type != RXDESC_TYPE_NORMAL); } @@ -16642,12 +19310,16 @@ rtl8125_rx_interrupt(struct net_device *dev, } skb->dev = dev; - skb_reserve(skb, R8125_RX_ALIGN); + if (!R8125_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8125_RX_ALIGN); skb_put(skb, pkt_size); } else skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rxb->page, rxb->page_offset, pkt_size, tp->rx_buf_page_size / 2); - +#ifdef ENABLE_PTP_SUPPORT + if (desc_type == RXDESC_TYPE_PTP) + rtl8125_rx_ptp_pktstamp(tp, skb, &ptp_desc); +#endif //ENABLE_PTP_SUPPORT //recycle desc rtl8125_put_rx_buffer(tp, ring, cur_rx, rxb); @@ -16664,9 +19336,13 @@ rtl8125_rx_interrupt(struct net_device *dev, } skb->dev = dev; - skb_reserve(skb, R8125_RX_ALIGN); + if (!R8125_USE_NAPI_ALLOC_SKB) + skb_reserve(skb, R8125_RX_ALIGN); skb_put(skb, pkt_size); - +#ifdef ENABLE_PTP_SUPPORT + if (desc_type == RXDESC_TYPE_PTP) + rtl8125_rx_ptp_pktstamp(tp, skb, &ptp_desc); +#endif //ENABLE_PTP_SUPPORT rx_buf_phy_addr = ring->RxDescPhyAddr[entry]; dma_sync_single_for_cpu(tp_to_dev(tp), rx_buf_phy_addr, tp->rx_buf_sz, @@ -16692,12 +19368,14 @@ rtl8125_rx_interrupt(struct net_device *dev, #endif //ENABLE_RX_PACKET_FRAGMENT #ifdef ENABLE_RSS_SUPPORT - rtl8125_rx_hash(tp, (struct RxDescV3 *)desc, skb); + rtl8125_rx_hash(tp, desc, skb); #endif - rtl8125_rx_csum(tp, skb, desc, status); + rtl8125_rx_csum(tp, skb, desc); skb->protocol = eth_type_trans(skb, dev); + total_rx_bytes += skb->len; + if (skb->pkt_type == PACKET_MULTICAST) total_rx_multicast_packets++; @@ -16707,7 +19385,6 @@ rtl8125_rx_interrupt(struct net_device *dev, #if LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0) dev->last_rx = jiffies; #endif //LINUX_VERSION_CODE < KERNEL_VERSION(4,11,0) - total_rx_bytes += skb->len; total_rx_packets++; #ifdef ENABLE_PAGE_REUSE @@ -16716,6 +19393,14 @@ rtl8125_rx_interrupt(struct net_device *dev, #endif release_descriptor: + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + case RX_DESC_RING_TYPE_4: + rtl8125_set_desc_dma_addr(tp, desc, + ring->RxDescPhyAddr[entry]); + wmb(); + break; + } rtl8125_mark_to_asic(tp, desc, tp->rx_buf_sz); continue; drop_packet: @@ -16753,10 +19438,30 @@ rtl8125_rx_interrupt(struct net_device *dev, static bool rtl8125_linkchg_interrupt(struct rtl8125_private *tp, u32 status) { - if (tp->HwCurrIsrVer == 2) + switch (tp->HwCurrIsrVer) { + case 2: + case 3: return status & ISRIMR_V2_LINKCHG; + case 4: + return status & ISRIMR_V4_LINKCHG; + case 5: + return status & ISRIMR_V5_LINKCHG; + default: + return status & LinkChg; + } +} - return status & LinkChg; +static u32 +rtl8125_get_linkchg_message_id(struct rtl8125_private *tp) +{ + switch (tp->HwCurrIsrVer) { + case 4: + return 29; + case 5: + return 18; + default: + return 21; + } } /* @@ -16812,15 +19517,12 @@ static irqreturn_t rtl8125_interrupt(int irq, void *dev_instance) tp->CmacResetIntr = TRUE; DashIntType2Status = RTL_CMAC_R8(tp, CMAC_IBISR0); - if (DashIntType2Status & ISRIMR_DASH_TYPE2_ROK) { + if (DashIntType2Status & ISRIMR_DASH_TYPE2_ROK) tp->RcvFwDashOkEvt = TRUE; - } - if (DashIntType2Status & ISRIMR_DASH_TYPE2_TOK) { + if (DashIntType2Status & ISRIMR_DASH_TYPE2_TOK) tp->SendFwHostOkEvt = TRUE; - } - if (DashIntType2Status & ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE) { + if (DashIntType2Status & ISRIMR_DASH_TYPE2_RX_DISABLE_IDLE) tp->DashFwDisableRx = TRUE; - } RTL_CMAC_W8(tp, CMAC_IBISR0, DashIntType2Status); } @@ -16896,23 +19598,27 @@ static irqreturn_t rtl8125_interrupt_msix(int irq, void *dev_instance) if (!tp->irq_tbl[message_id].requested) break; #endif - rtl8125_disable_hw_interrupt_v2(tp, message_id); - - rtl8125_clear_hw_isr_v2(tp, message_id); - //link change - if (message_id == 21) { + if (message_id == rtl8125_get_linkchg_message_id(tp)) { + rtl8125_disable_hw_interrupt_v2(tp, message_id); + rtl8125_clear_hw_isr_v2(tp, message_id); rtl8125_schedule_linkchg_work(tp); break; } #ifdef CONFIG_R8125_NAPI - if (likely(RTL_NETIF_RX_SCHEDULE_PREP(dev, &r8125napi->napi))) + if (likely(RTL_NETIF_RX_SCHEDULE_PREP(dev, &r8125napi->napi))) { + rtl8125_disable_hw_interrupt_v2(tp, message_id); __RTL_NETIF_RX_SCHEDULE(dev, &r8125napi->napi); - else if (netif_msg_intr(tp)) + } else if (netif_msg_intr(tp)) printk(KERN_INFO "%s: interrupt message id %d in poll_msix\n", dev->name, message_id); + rtl8125_clear_hw_isr_v2(tp, message_id); #else + rtl8125_disable_hw_interrupt_v2(tp, message_id); + + rtl8125_clear_hw_isr_v2(tp, message_id); + rtl8125_tx_interrupt_with_vector(tp, message_id, ~(u32)0); if (message_id < tp->num_rx_rings) { @@ -16957,10 +19663,12 @@ static int rtl8125_resource_freed(struct rtl8125_private *tp) int i; for (i = 0; i < tp->num_tx_rings; i++) - if (tp->tx_ring[i].TxDescArray) return 0; + if (tp->tx_ring[i].TxDescArray) + return 0; for (i = 0; i < tp->num_rx_rings; i++) - if (tp->rx_ring[i].RxDescArray) return 0; + if (tp->rx_ring[i].RxDescArray) + return 0; return 1; } @@ -17006,7 +19714,6 @@ static void rtl8125_shutdown(struct pci_dev *pdev) if (HW_DASH_SUPPORT_DASH(tp)) rtl8125_driver_stop(tp); - rtl8125_set_bios_setting(dev); if (s5_keep_curr_mac == 0 && tp->random_mac == 0) rtl8125_rar_set(tp, tp->org_mac_addr); @@ -17159,6 +19866,8 @@ rtl8125_resume(struct device *device) /* restore last modified mac address */ rtl8125_rar_set(tp, dev->dev_addr); + rtl8125_check_hw_phy_mcu_code_ver(dev); + tp->resume_not_chg_speed = 0; if (tp->check_keep_link_speed && //tp->link_ok(dev) && diff --git a/src/r8125_ptp.c b/src/r8125_ptp.c old mode 100755 new mode 100644 index 6010a18..02c1ab0 --- a/src/r8125_ptp.c +++ b/src/r8125_ptp.c @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -40,6 +40,7 @@ #include #include #include +#include #include "r8125.h" #include "r8125_ptp.h" @@ -63,8 +64,7 @@ static int _rtl8125_phc_gettime(struct rtl8125_private *tp, struct timespec64 *t /* nanoseconds */ //0x6808[29:0] - ts64->tv_nsec = (RTL_R32(tp, PTP_SOFT_CONFIG_Time_NS_8125) & 0x3fffffff) + - tp->ptp_adjust; + ts64->tv_nsec = (RTL_R32(tp, PTP_SOFT_CONFIG_Time_NS_8125) & 0x3fffffff); /* seconds */ //0x680C[47:0] @@ -92,18 +92,38 @@ static int _rtl8125_phc_settime(struct rtl8125_private *tp, const struct timespe return 0; } -#if 0 static int _rtl8125_phc_adjtime(struct rtl8125_private *tp, s64 delta) { - struct timespec64 now, then = ns_to_timespec64(delta); + struct timespec64 d; + bool negative = false; + u64 tohw; u32 nsec; u64 sec; - _rtl8125_phc_gettime(tp, &now); - now = timespec64_add(now, then); + if (delta < 0) { + negative = true; + tohw = -delta; + } else { + tohw = delta; + } + + d = ns_to_timespec64(tohw); - nsec = now.tv_nsec & 0x3fffffff; - sec = now.tv_sec & 0x0000ffffffffffff; + nsec = d.tv_nsec; + sec = d.tv_sec; + + if (negative) { + nsec = -nsec; + sec = -sec; + } + + nsec &= 0x3fffffff; + sec &= 0x0000ffffffffffff; + + if (negative) { + nsec |= PTP_SOFT_CONFIG_TIME_NS_NEGATIVE; + sec |= PTP_SOFT_CONFIG_TIME_S_NEGATIVE; + } /* nanoseconds */ //0x6808[29:0] @@ -120,24 +140,22 @@ static int _rtl8125_phc_adjtime(struct rtl8125_private *tp, s64 delta) return 0; } -#endif static int rtl8125_phc_adjtime(struct ptp_clock_info *ptp, s64 delta) { struct rtl8125_private *tp = container_of(ptp, struct rtl8125_private, ptp_clock_info); - unsigned long flags; - //int ret = 0; + int ret; //netif_info(tp, drv, tp->dev, "phc adjust time\n"); - spin_lock_irqsave(&tp->lock, flags); - //ret = _rtl8125_phc_adjtime(tp, delta); - tp->ptp_adjust += delta; - spin_unlock_irqrestore(&tp->lock, flags); + rtnl_lock(); + ret = _rtl8125_phc_adjtime(tp, delta); + rtnl_unlock(); - return 0; + return ret; } +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) /* 1ppm means every 125MHz plus 125Hz. It also means every 8ns minus 8ns*10^(-6) @@ -194,18 +212,18 @@ static int rtl8125_phc_adjfreq(struct ptp_clock_info *ptp, s32 delta) return 0; } +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) static int rtl8125_phc_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts64) { struct rtl8125_private *tp = container_of(ptp, struct rtl8125_private, ptp_clock_info); - unsigned long flags; int ret; //netif_info(tp, drv, tp->dev, "phc get ts\n"); - spin_lock_irqsave(&tp->lock, flags); + rtnl_lock(); ret = _rtl8125_phc_gettime(tp, ts64); - spin_unlock_irqrestore(&tp->lock, flags); + rtnl_unlock(); return ret; } @@ -214,15 +232,13 @@ static int rtl8125_phc_settime(struct ptp_clock_info *ptp, const struct timespec64 *ts64) { struct rtl8125_private *tp = container_of(ptp, struct rtl8125_private, ptp_clock_info); - unsigned long flags; int ret; //netif_info(tp, drv, tp->dev, "phc set ts\n"); - spin_lock_irqsave(&tp->lock, flags); + rtnl_lock(); ret = _rtl8125_phc_settime(tp, ts64); - tp->ptp_adjust = 0; - spin_unlock_irqrestore(&tp->lock, flags); + rtnl_unlock(); return ret; } @@ -231,14 +247,13 @@ static int rtl8125_phc_enable(struct ptp_clock_info *ptp, struct ptp_clock_request *rq, int on) { struct rtl8125_private *tp = container_of(ptp, struct rtl8125_private, ptp_clock_info); - unsigned long flags; u16 ptp_ctrl; //netif_info(tp, drv, tp->dev, "phc enable type %x on %d\n", rq->type, on); switch (rq->type) { case PTP_CLK_REQ_PPS: - spin_lock_irqsave(&tp->lock, flags); + rtnl_lock(); ptp_ctrl = RTL_R16(tp, PTP_CTRL_8125); ptp_ctrl &= ~BIT_15; if (on) @@ -246,7 +261,7 @@ static int rtl8125_phc_enable(struct ptp_clock_info *ptp, else ptp_ctrl &= ~BIT_14; RTL_W16(tp, PTP_CTRL_8125, ptp_ctrl); - spin_unlock_irqrestore(&tp->lock, flags); + rtnl_unlock(); return 0; default: return -EOPNOTSUPP; @@ -296,16 +311,34 @@ static const struct ptp_clock_info rtl_ptp_clock_info = { .n_per_out = 0, .n_pins = 0, .pps = 1, +#if LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) .adjfreq = rtl8125_phc_adjfreq, +#endif //LINUX_VERSION_CODE < KERNEL_VERSION(6,2,0) .adjtime = rtl8125_phc_adjtime, .gettime64 = rtl8125_phc_gettime, .settime64 = rtl8125_phc_settime, .enable = rtl8125_phc_enable, }; -static int rtl8125_get_tx_ptp_pkt_tstamp(struct rtl8125_private *tp, struct timespec64 *ts64) +static int rtl8125_ptp_egresstime(struct rtl8125_private *tp, struct timespec64 *ts64, u32 regnum) { - return _rtl8125_phc_gettime(tp, ts64); + /* nanoseconds */ + //[29:0] + ts64->tv_nsec = rtl8125_mac_ocp_read(tp, PTP_EGRESS_TIME_BASE_NS_8125 + regnum * 16 + 2); + ts64->tv_nsec <<= 16; + ts64->tv_nsec |= rtl8125_mac_ocp_read(tp, PTP_EGRESS_TIME_BASE_NS_8125 + regnum * 16); + ts64->tv_nsec &= 0x3fffffff; + + /* seconds */ + //[47:0] + ts64->tv_sec = rtl8125_mac_ocp_read(tp, PTP_EGRESS_TIME_BASE_S_8125 + regnum * 16 + 4); + ts64->tv_sec <<= 16; + ts64->tv_sec |= rtl8125_mac_ocp_read(tp, PTP_EGRESS_TIME_BASE_S_8125 + regnum * 16 + 2); + ts64->tv_sec <<= 16; + ts64->tv_sec |= rtl8125_mac_ocp_read(tp, PTP_EGRESS_TIME_BASE_S_8125 + regnum * 16); + ts64->tv_sec &= 0x0000ffffffffffff; + + return 0; } static void rtl8125_ptp_tx_hwtstamp(struct rtl8125_private *tp) @@ -313,10 +346,18 @@ static void rtl8125_ptp_tx_hwtstamp(struct rtl8125_private *tp) struct sk_buff *skb = tp->ptp_tx_skb; struct skb_shared_hwtstamps shhwtstamps = {0}; struct timespec64 ts64; + u32 regnum; RTL_W8(tp, PTP_ISR_8125, PTP_ISR_TOK | PTP_ISR_TER); - rtl8125_get_tx_ptp_pkt_tstamp(tp, &ts64); + //IO 0x2302 bit 10~11 WR_PTR + regnum = RTL_R16(tp, 0x2032) & 0x0C00; + regnum >>= 10; + regnum = (regnum + 3) % 4; + + rtnl_lock(); + rtl8125_ptp_egresstime(tp, &ts64, regnum); + rtnl_unlock(); /* Upper 32 bits contain s, lower 32 bits contain ns. */ shhwtstamps.hwtstamp = ktime_set(ts64.tv_sec, @@ -328,6 +369,7 @@ static void rtl8125_ptp_tx_hwtstamp(struct rtl8125_private *tp) * while we're notifying the stack. */ tp->ptp_tx_skb = NULL; + clear_bit_unlock(__RTL8125_PTP_TX_IN_PROGRESS, &tp->state); /* Notify the stack and free the skb after we've unlocked */ skb_tstamp_tx(skb, &shhwtstamps); @@ -339,23 +381,21 @@ static void rtl8125_ptp_tx_work(struct work_struct *work) { struct rtl8125_private *tp = container_of(work, struct rtl8125_private, ptp_tx_work); - unsigned long flags; - - spin_lock_irqsave(&tp->lock, flags); if (!tp->ptp_tx_skb) - goto Exit; + return; if (time_is_before_jiffies(tp->ptp_tx_start + RTL8125_PTP_TX_TIMEOUT)) { dev_kfree_skb_any(tp->ptp_tx_skb); tp->ptp_tx_skb = NULL; + clear_bit_unlock(__RTL8125_PTP_TX_IN_PROGRESS, &tp->state); tp->tx_hwtstamp_timeouts++; /* Clear the tx valid bit in TSYNCTXCTL register to enable * interrupt */ RTL_W8(tp, PTP_ISR_8125, PTP_ISR_TOK | PTP_ISR_TER); - goto Exit; + return; } if (RTL_R8(tp, PTP_ISR_8125) & (PTP_ISR_TOK)) @@ -364,8 +404,6 @@ static void rtl8125_ptp_tx_work(struct work_struct *work) /* reschedule to check later */ schedule_work(&tp->ptp_tx_work); -Exit: - spin_unlock_irqrestore(&tp->lock, flags); } static int rtl8125_hwtstamp_enable(struct rtl8125_private *tp, bool enable) @@ -380,11 +418,9 @@ static int rtl8125_hwtstamp_enable(struct rtl8125_private *tp, bool enable) //ptp source 0:gphy 1:mac rtl8125_mac_ocp_write(tp, 0xDC00, rtl8125_mac_ocp_read(tp, 0xDC00) | BIT_6); //enable ptp - ptp_ctrl = (BIT_0 | BIT_3 | BIT_4 | BIT_6 | BIT_10 | BIT_12 | BIT_13); - if (tp->ptp_master_mode) { - ptp_ctrl &= ~BIT_13; + ptp_ctrl = (BIT_0 | BIT_3 | BIT_4 | BIT_6 | BIT_10 | BIT_12); + if (tp->ptp_master_mode) ptp_ctrl |= BIT_1; - } RTL_W16(tp, PTP_CTRL_8125, ptp_ctrl); //set system time @@ -393,9 +429,7 @@ static int rtl8125_hwtstamp_enable(struct rtl8125_private *tp, bool enable) _rtl8125_phc_settime(tp, timespec64_to_timespec(ts64)); */ ktime_get_real_ts64(&ts64); - ts64.tv_nsec += tp->ptp_adjust; _rtl8125_phc_settime(tp, &ts64); - tp->ptp_adjust = 0; } return 0; @@ -449,8 +483,6 @@ void rtl8125_ptp_init(struct rtl8125_private *tp) /* we have a clock so we can initialize work now */ INIT_WORK(&tp->ptp_tx_work, rtl8125_ptp_tx_work); - tp->ptp_adjust = 0; - /* reset the PTP related hardware bits */ rtl8125_ptp_reset(tp); @@ -552,24 +584,17 @@ static int rtl8125_get_tstamp(struct net_device *netdev, struct ifreq *ifr) int rtl8125_ptp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) { - struct rtl8125_private *tp = netdev_priv(netdev); int ret; - unsigned long flags; //netif_info(tp, drv, tp->dev, "ptp ioctl\n"); - ret = 0; switch (cmd) { #ifdef ENABLE_PTP_SUPPORT case SIOCSHWTSTAMP: - spin_lock_irqsave(&tp->lock, flags); ret = rtl8125_set_tstamp(netdev, ifr); - spin_unlock_irqrestore(&tp->lock, flags); break; case SIOCGHWTSTAMP: - spin_lock_irqsave(&tp->lock, flags); ret = rtl8125_get_tstamp(netdev, ifr); - spin_unlock_irqrestore(&tp->lock, flags); break; #endif default: @@ -588,7 +613,7 @@ void rtl8125_rx_ptp_pktstamp(struct rtl8125_private *tp, struct sk_buff *skb, tv_sec = le32_to_cpu(descv3->RxDescTimeStamp.TimeStampHigh) + ((u64)le32_to_cpu(descv3->RxDescPTPDDWord4.TimeStampHHigh) << 32); - tv_nsec = le32_to_cpu(descv3->RxDescTimeStamp.TimeStampLow) + tp->ptp_adjust; + tv_nsec = le32_to_cpu(descv3->RxDescTimeStamp.TimeStampLow); skb_hwtstamps(skb)->hwtstamp = ktime_set(tv_sec, tv_nsec); } diff --git a/src/r8125_ptp.h b/src/r8125_ptp.h old mode 100755 new mode 100644 index 7a1fe83..b24136a --- a/src/r8125_ptp.h +++ b/src/r8125_ptp.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/r8125_realwow.h b/src/r8125_realwow.h old mode 100755 new mode 100644 index e5e9b46..603b877 --- a/src/r8125_realwow.h +++ b/src/r8125_realwow.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/r8125_rss.c b/src/r8125_rss.c old mode 100755 new mode 100644 index 1f55c44..691cd8d --- a/src/r8125_rss.c +++ b/src/r8125_rss.c @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8168 is the Linux device driver released for Realtek Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -41,9 +41,12 @@ enum rtl8125_rss_register_content { RSS_CTRL_IPV4_SUPP = (1 << 1), RSS_CTRL_TCP_IPV6_SUPP = (1 << 2), RSS_CTRL_IPV6_SUPP = (1 << 3), + RSS_CTRL_IPV6_EXT_SUPP = (1 << 4), + RSS_CTRL_TCP_IPV6_EXT_SUPP = (1 << 5), RSS_HALF_SUPP = (1 << 7), RSS_CTRL_UDP_IPV4_SUPP = (1 << 11), RSS_CTRL_UDP_IPV6_SUPP = (1 << 12), + RSS_CTRL_UDP_IPV6_EXT_SUPP = (1 << 13), RSS_QUAD_CPU_EN = (1 << 16), RSS_HQ_Q_SUP_R = (1 << 31), }; @@ -57,21 +60,21 @@ static int rtl8125_get_rss_hash_opts(struct rtl8125_private *tp, switch (cmd->flow_type) { case TCP_V4_FLOW: cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; - /* fallthrough */ + fallthrough; case UDP_V4_FLOW: if (tp->rss_flags & RTL_8125_RSS_FLAG_HASH_UDP_IPV4) cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; - /* fallthrough */ + fallthrough; case IPV4_FLOW: cmd->data |= RXH_IP_SRC | RXH_IP_DST; break; case TCP_V6_FLOW: cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; - /* fallthrough */ + fallthrough; case UDP_V6_FLOW: if (tp->rss_flags & RTL_8125_RSS_FLAG_HASH_UDP_IPV6) cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; - /* fallthrough */ + fallthrough; case IPV6_FLOW: cmd->data |= RXH_IP_SRC | RXH_IP_DST; break; @@ -131,13 +134,16 @@ static int _rtl8125_set_rss_hash_opt(struct rtl8125_private *tp) rss_ctrl |= RSS_CTRL_TCP_IPV4_SUPP | RSS_CTRL_IPV4_SUPP | RSS_CTRL_IPV6_SUPP - | RSS_CTRL_TCP_IPV6_SUPP; + | RSS_CTRL_IPV6_EXT_SUPP + | RSS_CTRL_TCP_IPV6_SUPP + | RSS_CTRL_TCP_IPV6_EXT_SUPP; if (rss_flags & RTL_8125_RSS_FLAG_HASH_UDP_IPV4) rss_ctrl |= RSS_CTRL_UDP_IPV4_SUPP; if (rss_flags & RTL_8125_RSS_FLAG_HASH_UDP_IPV6) - rss_ctrl |= RSS_CTRL_UDP_IPV6_SUPP; + rss_ctrl |= RSS_CTRL_UDP_IPV6_SUPP | + RSS_CTRL_UDP_IPV6_EXT_SUPP; hash_mask_len = ilog2(rtl8125_rss_indir_tbl_entries(tp)); hash_mask_len &= (BIT_0 | BIT_1 | BIT_2); @@ -239,16 +245,20 @@ static int rtl8125_set_rss_hash_opt(struct rtl8125_private *tp, rss_ctrl |= RSS_CTRL_TCP_IPV4_SUPP | RSS_CTRL_IPV4_SUPP | RSS_CTRL_IPV6_SUPP - | RSS_CTRL_TCP_IPV6_SUPP; + | RSS_CTRL_IPV6_EXT_SUPP + | RSS_CTRL_TCP_IPV6_SUPP + | RSS_CTRL_TCP_IPV6_EXT_SUPP; rss_ctrl &= ~(RSS_CTRL_UDP_IPV4_SUPP | - RSS_CTRL_UDP_IPV6_SUPP); + RSS_CTRL_UDP_IPV6_SUPP | + RSS_CTRL_UDP_IPV6_EXT_SUPP); if (rss_flags & RTL_8125_RSS_FLAG_HASH_UDP_IPV4) rss_ctrl |= RSS_CTRL_UDP_IPV4_SUPP; if (rss_flags & RTL_8125_RSS_FLAG_HASH_UDP_IPV6) - rss_ctrl |= RSS_CTRL_UDP_IPV6_SUPP; + rss_ctrl |= RSS_CTRL_UDP_IPV6_SUPP | + RSS_CTRL_UDP_IPV6_EXT_SUPP; RTL_W32(tp, RSS_CTRL_8125, rss_ctrl); } @@ -314,28 +324,6 @@ static void rtl8125_get_reta(struct rtl8125_private *tp, u32 *indir) indir[i] = tp->rss_indir_tbl[i]; } -int rtl8125_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, - u8 *hfunc) -{ - struct rtl8125_private *tp = netdev_priv(dev); - - netif_info(tp, drv, tp->dev, "rss get rxfh\n"); - - if (!(dev->features & NETIF_F_RXHASH)) - return -EOPNOTSUPP; - - if (hfunc) - *hfunc = ETH_RSS_HASH_TOP; - - if (indir) - rtl8125_get_reta(tp, indir); - - if (key) - memcpy(key, tp->rss_key, rtl8125_get_rxfh_key_size(dev)); - - return 0; -} - static u32 rtl8125_rss_key_reg(struct rtl8125_private *tp) { return RSS_KEY_8125; @@ -376,6 +364,88 @@ static void rtl8125_store_rss_key(struct rtl8125_private *tp) RTL_W32(tp, rss_key_reg + i, *rss_key++); } +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,8,0) +int rtl8125_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + netif_info(tp, drv, tp->dev, "rss get rxfh\n"); + + if (!(dev->features & NETIF_F_RXHASH)) + return -EOPNOTSUPP; + + rxfh->hfunc = ETH_RSS_HASH_TOP; + + if (rxfh->indir) + rtl8125_get_reta(tp, rxfh->indir); + + if (rxfh->key) + memcpy(rxfh->key, tp->rss_key, RTL8125_RSS_KEY_SIZE); + + return 0; +} + +int rtl8125_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh, + struct netlink_ext_ack *extack) +{ + struct rtl8125_private *tp = netdev_priv(dev); + int i; + u32 reta_entries = rtl8125_rss_indir_tbl_entries(tp); + + netif_info(tp, drv, tp->dev, "rss set rxfh\n"); + + /* We require at least one supported parameter to be changed and no + * change in any of the unsupported parameters + */ + if (rxfh->hfunc != ETH_RSS_HASH_NO_CHANGE && rxfh->hfunc != ETH_RSS_HASH_TOP) + return -EOPNOTSUPP; + + /* Fill out the redirection table */ + if (rxfh->indir) { + int max_queues = tp->num_rx_rings; + + /* Verify user input. */ + for (i = 0; i < reta_entries; i++) + if (rxfh->indir[i] >= max_queues) + return -EINVAL; + + for (i = 0; i < reta_entries; i++) + tp->rss_indir_tbl[i] = rxfh->indir[i]; + } + + /* Fill out the rss hash key */ + if (rxfh->key) + memcpy(tp->rss_key, rxfh->key, RTL8125_RSS_KEY_SIZE); + + rtl8125_store_reta(tp); + + rtl8125_store_rss_key(tp); + + return 0; +} +#else +int rtl8125_get_rxfh(struct net_device *dev, u32 *indir, u8 *key, + u8 *hfunc) +{ + struct rtl8125_private *tp = netdev_priv(dev); + + netif_info(tp, drv, tp->dev, "rss get rxfh\n"); + + if (!(dev->features & NETIF_F_RXHASH)) + return -EOPNOTSUPP; + + if (hfunc) + *hfunc = ETH_RSS_HASH_TOP; + + if (indir) + rtl8125_get_reta(tp, indir); + + if (key) + memcpy(key, tp->rss_key, RTL8125_RSS_KEY_SIZE); + + return 0; +} + int rtl8125_set_rxfh(struct net_device *dev, const u32 *indir, const u8 *key, const u8 hfunc) { @@ -406,7 +476,7 @@ int rtl8125_set_rxfh(struct net_device *dev, const u32 *indir, /* Fill out the rss hash key */ if (key) - memcpy(tp->rss_key, key, rtl8125_get_rxfh_key_size(dev)); + memcpy(tp->rss_key, key, RTL8125_RSS_KEY_SIZE); rtl8125_store_reta(tp); @@ -414,11 +484,19 @@ int rtl8125_set_rxfh(struct net_device *dev, const u32 *indir, return 0; } +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(6,8,0) */ static u32 rtl8125_get_rx_desc_hash(struct rtl8125_private *tp, - struct RxDescV3 *descv3) + struct RxDesc *desc) { - return le32_to_cpu(descv3->RxDescNormalDDWord2.RSSResult); + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + return le32_to_cpu(((struct RxDescV3 *)desc)->RxDescNormalDDWord2.RSSResult); + case RX_DESC_RING_TYPE_4: + return le32_to_cpu(((struct RxDescV4 *)desc)->RxDescNormalDDWord1.RSSResult); + default: + return 0; + } } #define RXS_8125B_RSS_UDP BIT(9) @@ -427,9 +505,16 @@ static u32 rtl8125_get_rx_desc_hash(struct rtl8125_private *tp, #define RXS_8125_RSS_TCP BIT(13) #define RTL8125_RXS_RSS_L3_TYPE_MASK (RXS_8125_RSS_IPV4 | RXS_8125_RSS_IPV6) #define RTL8125_RXS_RSS_L4_TYPE_MASK (RXS_8125_RSS_TCP | RXS_8125B_RSS_UDP) -void rtl8125_rx_hash(struct rtl8125_private *tp, - struct RxDescV3 *descv3, - struct sk_buff *skb) + +#define RXS_8125B_RSS_UDP_V4 BIT(11) +#define RXS_8125_RSS_IPV4_V4 BIT(12) +#define RXS_8125_RSS_IPV6_V4 BIT(13) +#define RXS_8125_RSS_TCP_V4 BIT(14) +#define RTL8125_RXS_RSS_L3_TYPE_MASK_V4 (RXS_8125_RSS_IPV4_V4 | RXS_8125_RSS_IPV6_V4) +#define RTL8125_RXS_RSS_L4_TYPE_MASK_V4 (RXS_8125_RSS_TCP_V4 | RXS_8125B_RSS_UDP_V4) +static void rtl8125_rx_hash_v3(struct rtl8125_private *tp, + struct RxDescV3 *descv3, + struct sk_buff *skb) { u16 rss_header_info; @@ -441,11 +526,46 @@ void rtl8125_rx_hash(struct rtl8125_private *tp, if (!(rss_header_info & RTL8125_RXS_RSS_L3_TYPE_MASK)) return; - skb_set_hash(skb, rtl8125_get_rx_desc_hash(tp, descv3), + skb_set_hash(skb, rtl8125_get_rx_desc_hash(tp, (struct RxDesc *)descv3), (RTL8125_RXS_RSS_L4_TYPE_MASK & rss_header_info) ? PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); } +static void rtl8125_rx_hash_v4(struct rtl8125_private *tp, + struct RxDescV4 *descv4, + struct sk_buff *skb) +{ + u16 rss_header_info; + + if (!(tp->dev->features & NETIF_F_RXHASH)) + return; + + rss_header_info = le16_to_cpu(descv4->RxDescNormalDDWord1.RSSInfo); + + if (!(rss_header_info & RTL8125_RXS_RSS_L3_TYPE_MASK_V4)) + return; + + skb_set_hash(skb, rtl8125_get_rx_desc_hash(tp, (struct RxDesc *)descv4), + (RTL8125_RXS_RSS_L4_TYPE_MASK_V4 & rss_header_info) ? + PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3); +} + +void rtl8125_rx_hash(struct rtl8125_private *tp, + struct RxDesc *desc, + struct sk_buff *skb) +{ + switch (tp->InitRxDescType) { + case RX_DESC_RING_TYPE_3: + rtl8125_rx_hash_v3(tp, (struct RxDescV3 *)desc, skb); + break; + case RX_DESC_RING_TYPE_4: + rtl8125_rx_hash_v4(tp, (struct RxDescV4 *)desc, skb); + break; + default: + return; + } +} + void rtl8125_disable_rss(struct rtl8125_private *tp) { RTL_W32(tp, RSS_CTRL_8125, 0x00); diff --git a/src/r8125_rss.h b/src/r8125_rss.h old mode 100755 new mode 100644 index 8864139..5aaaf82 --- a/src/r8125_rss.h +++ b/src/r8125_rss.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -47,18 +47,25 @@ enum rtl8125_rss_flag { }; struct rtl8125_private; +struct RxDesc; int rtl8125_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, u32 *rule_locs); int rtl8125_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd); u32 rtl8125_get_rxfh_key_size(struct net_device *netdev); u32 rtl8125_rss_indir_size(struct net_device *netdev); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6,8,0) +int rtl8125_get_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh); +int rtl8125_set_rxfh(struct net_device *dev, struct ethtool_rxfh_param *rxfh, + struct netlink_ext_ack *extack); +#else int rtl8125_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key, u8 *hfunc); int rtl8125_set_rxfh(struct net_device *netdev, const u32 *indir, const u8 *key, const u8 hfunc); +#endif /* LINUX_VERSION_CODE >= KERNEL_VERSION(6,8,0) */ void rtl8125_rx_hash(struct rtl8125_private *tp, - struct RxDescV3 *descv3, + struct RxDesc *desc, struct sk_buff *skb); void _rtl8125_config_rss(struct rtl8125_private *tp); void rtl8125_config_rss(struct rtl8125_private *tp); diff --git a/src/rtl_eeprom.c b/src/rtl_eeprom.c old mode 100755 new mode 100644 index 03660dd..21b6922 --- a/src/rtl_eeprom.c +++ b/src/rtl_eeprom.c @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free @@ -93,7 +93,7 @@ void rtl8125_eeprom_cleanup(struct rtl8125_private *tp) rtl8125_lower_clock(tp, &x); } -int rtl8125_eeprom_cmd_done(struct rtl8125_private *tp) +static int rtl8125_eeprom_cmd_done(struct rtl8125_private *tp) { u8 x; int i; @@ -123,9 +123,8 @@ u16 rtl8125_eeprom_read_sc(struct rtl8125_private *tp, u16 reg) u8 x; u16 data; - if(tp->eeprom_type == EEPROM_TYPE_NONE) { + if(tp->eeprom_type == EEPROM_TYPE_NONE) return -1; - } if (tp->eeprom_type==EEPROM_TYPE_93C46) addr_sz = 6; @@ -157,9 +156,8 @@ void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data) int addr_sz = 6; int w_dummy_addr = 4; - if(tp->eeprom_type == EEPROM_TYPE_NONE) { - return ; - } + if(tp->eeprom_type == EEPROM_TYPE_NONE) + return; if (tp->eeprom_type==EEPROM_TYPE_93C46) { addr_sz = 6; @@ -178,17 +176,15 @@ void rtl8125_eeprom_write_sc(struct rtl8125_private *tp, u16 reg, u16 data) rtl8125_shift_out_bits(tp, RTL_EEPROM_ERASE_OPCODE, 3); rtl8125_shift_out_bits(tp, reg, addr_sz); - if (rtl8125_eeprom_cmd_done(tp) < 0) { + if (rtl8125_eeprom_cmd_done(tp) < 0) return; - } rtl8125_stand_by(tp); rtl8125_shift_out_bits(tp, RTL_EEPROM_WRITE_OPCODE, 3); rtl8125_shift_out_bits(tp, reg, addr_sz); rtl8125_shift_out_bits(tp, data, 16); - if (rtl8125_eeprom_cmd_done(tp) < 0) { + if (rtl8125_eeprom_cmd_done(tp) < 0) return; - } rtl8125_stand_by(tp); rtl8125_shift_out_bits(tp, RTL_EEPROM_EWDS_OPCODE, 5); @@ -207,7 +203,6 @@ void rtl8125_raise_clock(struct rtl8125_private *tp, u8 *x) void rtl8125_lower_clock(struct rtl8125_private *tp, u8 *x) { - *x = *x & ~Cfg9346_EESK; RTL_W8(tp, Cfg9346, *x); udelay(RTL_CLOCK_RATE); diff --git a/src/rtl_eeprom.h b/src/rtl_eeprom.h old mode 100755 new mode 100644 index 8faed17..9751bf7 --- a/src/rtl_eeprom.h +++ b/src/rtl_eeprom.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/rtltool.c b/src/rtltool.c old mode 100755 new mode 100644 index f40df6f..f2f2ed3 --- a/src/rtltool.c +++ b/src/rtltool.c @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free diff --git a/src/rtltool.h b/src/rtltool.h old mode 100755 new mode 100644 index a54f8e6..6d4ba69 --- a/src/rtltool.h +++ b/src/rtltool.h @@ -2,10 +2,10 @@ /* ################################################################################ # -# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet +# r8125 is the Linux device driver released for Realtek 2.5 Gigabit Ethernet # controllers with PCI-Express interface. # -# Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved. +# Copyright(c) 2024 Realtek Semiconductor Corp. All rights reserved. # # This program is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by the Free