PicoRV_Tang9K.gprj

<?xml version="1" encoding="UTF-8"?>
<!DOCTYPE gowin-fpga-project>
<Project>
    <Template>FPGA</Template>
    <Version>5</Version>
    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
    <FileList>
        <File path="src/btRAM.v" type="file.verilog" enable="1"/>
        <File path="src/dBounce.v" type="file.verilog" enable="1"/>
        <File path="src/delay.v" type="file.verilog" enable="1"/>
        <File path="src/mypll.v" type="file.verilog" enable="1"/>
        <File path="src/picorv32-master/picorv32.v" type="file.verilog" enable="1"/>
        <File path="src/picorv32.v" type="file.verilog" enable="0"/>
        <File path="src/rom.v" type="file.verilog" enable="1"/>
        <File path="src/simpleuart.v" type="file.verilog" enable="1"/>
        <File path="src/top.v" type="file.verilog" enable="1"/>
        <File path="src/pins.cst" type="file.cst" enable="1"/>
        <File path="src/Tang9kPicoRV.sdc" type="file.sdc" enable="1"/>
    </FileList>
</Project>