From b4c2cc0def6d8cae846c746b4c09f8712ef06868 Mon Sep 17 00:00:00 2001 From: ghostway Date: Mon, 9 Sep 2024 18:48:53 +0300 Subject: [PATCH] wip --- cranelift/codegen/src/isa/s390x/inst.isle | 1 + cranelift/codegen/src/isa/s390x/lower.isle | 51 ++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/cranelift/codegen/src/isa/s390x/inst.isle b/cranelift/codegen/src/isa/s390x/inst.isle index 36af4ba75cc5..25ec4b19620e 100644 --- a/cranelift/codegen/src/isa/s390x/inst.isle +++ b/cranelift/codegen/src/isa/s390x/inst.isle @@ -3371,6 +3371,7 @@ (bool producer (invert_cond cond))) ;; Use a boolean condition to select between two registers. +; important (decl select_bool_reg (Type ProducesBool Reg Reg) Reg) (rule (select_bool_reg ty (ProducesBool.ProducesBool producer cond) reg_true reg_false) (with_flags_reg producer (cmov_reg_reg ty cond reg_true reg_false))) diff --git a/cranelift/codegen/src/isa/s390x/lower.isle b/cranelift/codegen/src/isa/s390x/lower.isle index 330cb3910cfc..030b16489d32 100644 --- a/cranelift/codegen/src/isa/s390x/lower.isle +++ b/cranelift/codegen/src/isa/s390x/lower.isle @@ -3844,6 +3844,57 @@ (add_logical_mem_zext32_with_flags_paired ty y (sink_uload32 x)) (trap_if_impl (mask_as_cond 3) tc))) +;;;; Rules for `uadd_overflow` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; options: +; 1. add BO (branch on overflow) to the backend +; 2. find how I can get and use the flags from a ProducesFlags instruction + +(rule 0 (lower (has_type (fits_in_64 ty) (uadd_overflow x y))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_reg_with_flags_paired ty x y) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 4 (lower (has_type (fits_in_64 ty) (uadd_overflow x (zext32_value y)))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_reg_zext32_with_flags_paired ty x y) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 8 (lower (has_type (fits_in_64 ty) (uadd_overflow (zext32_value x) y))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_reg_zext32_with_flags_paired ty y x) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 3 (lower (has_type (fits_in_64 ty) (uadd_overflow x (u32_from_value y)))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_zimm32_with_flags_paired ty x y) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 7 (lower (has_type (fits_in_64 ty) (uadd_overflow (u32_from_value x) y))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_zimm32_with_flags_paired ty y x) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 2 (lower (has_type (fits_in_64 ty) (uadd_overflow x (sinkable_load_32_64 y)))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_mem_with_flags_paired ty x (sink_load y)) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 6 (lower (has_type (fits_in_64 ty) (uadd_overflow (sinkable_load_32_64 x) y))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_mem_with_flags_paired ty y (sink_load x)) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 1 (lower (has_type (fits_in_64 ty) (uadd_overflow x (sinkable_uload32 y)))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_mem_zext32_with_flags_paired ty x (sink_uload32 y)) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + +(rule 5 (lower (has_type (fits_in_64 ty) (uadd_overflow (sinkable_uload32 x) y))) + (let ((one Reg (imm $I8 1)) + (overflow Reg (select_bool_reg ty (bool (add_logical_mem_zext32_with_flags_paired ty y (sink_uload32 x)) (mask_as_cond 3)) one (zero_reg)))) + (value_reg overflow))) + ;;;; Rules for `return` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (rule (lower (return args))