SPISlave getting data without shift on the FIFO queue depth

[chelyuk]

I need to create a program for SPI slave which should send response appropriately depends on receive bytes.

I am using the following approach:

void recvCallback(uint8_t *data, size_t len)
{
    memcpy((uint8_t* )recvBuff, data, len);
    gLen = len;
    sentBack = true;
}

void sentCallback()
{
        if (recvBuff[0] != 0)
        {
            SPISlave1.setData((uint8_t* )recvBuff, gLen);
        }
        else
        {
            SPISlave1.setData(DUMMY, sizeof(DUMMY));
        }
}

But at first master got 8 dummies and only then starting the communication with the 8 bytes shift.
As far as I understand I need to disable the bit TXMIS for SPI: SSPMIS Register (Datasheet p. 521)

Could you advise is it possible with SPISlave library?
Or what is proper way with SPISlave to achieve response with 1 byte delay and not with the whole FIFO queue depth?

[earlephilhower]

SPISlave isn't capable of doing that, no. In general, because SPI has no handshaking and interrupts are unpredictable, it preloads response data into the HW FIFO as you saw. That way there is no/very little CPU limitation on responding properly.

Theoretically you could twiddle the HW directly (maybe set core1 up doing nothing but polling the SPI block?) but even with that, I doubt you'd be able to get a 0-bit turnaround (i.e. 8 bits command in changes bit 9 of the output like in your message). The HW block itself will have a shift register that will probably be loaded w/the next 8-bits at the same time as the last 8-bit is sampled from input.

[chelyuk]

I do not need 0-byte turnaround. I need to implement something like:

 Master                                                              Slave
                 --> Request  1 Byte -->
              <-- response Dummy  1 Byte <--
              
              
                --> request Dummy 1 Byte -->
         <-- response on Prev Request 1 Byte <--    

But for now I could not react on the previous byte. But only on the byte that was put to the FIFO 8 bytes ago. So, I need some way to disable FIFO or to make it's depth 1 instead of 8.

[earlephilhower]

Ah, 2 transactions seems much more doable. That said, the SpiSlave class itself does not load anything into the FIFO that you don't sent into it. See:

arduino-pico/libraries/SPISlave/src/SPISlave.cpp

Lines 175 to 183 in 28b0eda

	// Attempt to send as many ytes to the TX FIFO as we have/are free
	while (spi_is_writable(_spi)) {
	for (; _dataLeft && spi_is_writable(_spi); _dataLeft--) {
	spi_get_hw(_spi)->dr = *(_dataOut++);
	}
	if (!_dataLeft && _sentCB) {
	_sentCB();
	}
	}

So, it's not going to 0-pad data to FIFO size. (Underflow may send 0s, though, but that's just an error condition)

You need to put something into the FIFO before the 1st transfer, though (that dummy byte). The example does this with the small message in setup.

[chelyuk]

So, this is what actually I did. I put in the setup 8 DUMMY bytes to the FIFO.
And when master start the communication the first 8 bytes it got the one I put on the slave side in the setup. And only when master push all this buffer it starts to get the data it send. So, I need to get rid of this first bytes:

AA_REQUEST: AA
M-RECV: 00
DUMMY: DB
M-RECV: 00
AB_REQUEST: AB
M-RECV: 00
DUMMY: DB
M-RECV: 00
AC_REQUEST: AC
M-RECV: 00
DUMMY: DB
M-RECV: 00
AD_REQUEST: AD
M-RECV: 00
DUMMY: DB
M-RECV: 00
AE_REQUEST: AE
M-RECV: EE
DUMMY: DB
M-RECV: DB
AF_REQUEST: AF
M-RECV: AB
DUMMY: DB
M-RECV: DB
AA_REQUEST: AA
M-RECV: AC
DUMMY: DB

In the printout above. You could see the first 8 bytes 0x00 which I put in the setup. Then 0xEE in response to 0xAE, because slave was not able to analyze the first one. And after that the proper communication is going. But again, slave response with the data it should sent back 8 bytes ago. This is the delay caused by the data from setup.

[earlephilhower]

Err, I really don't see what you're doing, sorry. If you're loading 8 bytes of 0 into the SPI FIFO then of course things will be 8 bytes delayed, no? A single dummy byte in the FIFO is all it seems you'd need in your comms case (i.e. since the 1st command in write will simultaneously read out dummy data). SPISlave, and the SPI slave HW block, will not clear the FIFO between transactions.

[chelyuk]

On the master side I am sending the 6 pairs of bytes.
Every pair is a separate transaction (CS line goes down and up). Every byte is a separate transfer inside transaction. So, 2 transfers per transaction. The second byte is always Dummy to push the data from the slave. The first byte is starting from 0xAA to 0xAF and then the loop goes from the beginning.

#include <SPI.h>

SPISettings spisettings(4000000, MSBFIRST, SPI_MODE0);


const uint8_t AA_REQUEST[1] = {0xAA};
const uint8_t AB_REQUEST[1] = {0xAB};
const uint8_t AC_REQUEST[1] = {0xAC};
const uint8_t AD_REQUEST[1] = {0xAD};
const uint8_t AE_REQUEST[1] = {0xAE};
const uint8_t AF_REQUEST[1] = {0xAF};

const uint8_t DUMMY[1] = {0xDB};

uint8_t recvBuff[1] = {0}; // Buffer to store response data

// Core 0 will be SPI master
void setup()
{
    SPI.setRX(0);
    SPI.setCS(1);
    SPI.setSCK(2);
    SPI.setTX(3);
    SPI.begin(true);

    Serial.begin(115200);
    delay(5000);
}

void printAndTransfer(const char* label, const uint8_t* sendBuff, uint8_t* recvBuff, size_t size) 
{
    Serial.print(label);
    for (size_t i = 0; i < size; i++)
    {
        Serial.printf("%02X", sendBuff[i]);
        Serial.print(" ");
    }

    Serial.println();
    SPI.transfer(sendBuff, recvBuff, size);
    
    Serial.print("M-RECV: ");
    for (size_t i = 0; i < size; i++) 
    {
        Serial.printf("%02X", recvBuff[i]);
        Serial.print(" ");
    }

    Serial.println();
}

int transmits = 0;
void loop()
{
    SPI.beginTransaction(spisettings);

    printAndTransfer("AA_REQUEST: ", AA_REQUEST, recvBuff, sizeof(AA_REQUEST));
    printAndTransfer("DUMMY: ", DUMMY, recvBuff, sizeof(DUMMY));

    SPI.endTransaction();
    delay(1000);

    SPI.beginTransaction(spisettings);
    
    printAndTransfer("AB_REQUEST: ", AB_REQUEST, recvBuff, sizeof(AB_REQUEST));
    printAndTransfer("DUMMY: ", DUMMY, recvBuff, sizeof(DUMMY));

    SPI.endTransaction();

    delay(1000);

    SPI.beginTransaction(spisettings);
    
    printAndTransfer("AC_REQUEST: ", AC_REQUEST, recvBuff, sizeof(AC_REQUEST));
    printAndTransfer("DUMMY: ", DUMMY, recvBuff, sizeof(DUMMY));

    SPI.endTransaction();

    delay(1000);

    SPI.beginTransaction(spisettings);

    printAndTransfer("AD_REQUEST: ", AD_REQUEST, recvBuff, sizeof(AD_REQUEST));
    printAndTransfer("DUMMY: ", DUMMY, recvBuff, sizeof(DUMMY));
    
    SPI.endTransaction();

    delay(1000);

    SPI.beginTransaction(spisettings);

    printAndTransfer("AE_REQUEST: ", AE_REQUEST, recvBuff, sizeof(AE_REQUEST));
    printAndTransfer("DUMMY: ", DUMMY, recvBuff, sizeof(DUMMY));
    
    SPI.endTransaction();

    delay(1000);

    SPI.beginTransaction(spisettings);

    printAndTransfer("AF_REQUEST: ", AF_REQUEST, recvBuff, sizeof(AF_REQUEST));
    printAndTransfer("DUMMY: ", DUMMY, recvBuff, sizeof(DUMMY));
    
    SPI.endTransaction();

    transmits++;
    delay(8000);
}

The master supposed to get the first non zero byte and send it back for next the transfer

const uint8_t DUMMY[1] = {0xEE};

volatile uint8_t sendBuff[1] = {0};
volatile uint8_t recvBuff[1] = {0};

volatile bool isSPISlaveEnabled = false;

void recvCallback(uint8_t *data, size_t len)
{
    memcpy((uint8_t* )recvBuff, data, len);
    gLen = len;
    sentBack = true;
}

void sentCallback()
{
        if (recvBuff[0] != 0)
        {
            SPISlave1.setData((uint8_t* )recvBuff, gLen);
        }
        else
        {
            SPISlave1.setData(DUMMY, sizeof(DUMMY));
        }
}

void setup()
{
    Serial.begin(115200);
    startSPISlave();
}

void startSPISlave()
{
    SPISlave1.setRX(_RX_SLAVE);
    SPISlave1.setCS(_CS_SLAVE);
    SPISlave1.setSCK(_SCK_SLAVE);
    SPISlave1.setTX(_TX_SLAVE);
    // Ensure we start with something to send...

    isSPISlaveEnabled = true;
    // Hook our callbacks into the slave
    SPISlave1.onDataRecv(recvCallback);
    SPISlave1.onDataSent(sentCallback);
    SPISlave1.begin(spisettings);
    Serial.println("S-INFO: SPISlave started");
}

void loop()
{
    if (sentBack)
    {
        Serial.printf("Len = %d\n", gLen);

        for (size_t i = 0; i < gLen; i++)
        {
            Serial.printf("%2X ", recvBuff[i]);
        }

        Serial.println();

        sentBack = false;
    }
}    

And the problem I faced with that first 8 bytes slave is not setting the data it should in response. Even though I saw that Slave printout non null bytes it got from the master. Anyway it set the Dummy byte values and not exact data it got from the Master for the first 8 Bytes. And only after the 8 bytes it start to analyze input and set proper data in response. But still it set the data based on what it get 8 bytes before, and not based on the previous byte.

[chelyuk]

In case I does not setData to the FIFO for the first bytes the program is stuck. So, I have to put something in the FIFO.
I suppose it could be related to interruptions in the imsc register. IN case my suggestion is correct, to be able to work with 1 byte transfers. SPI initialization required to turn of interrupts for imsc till the FIFO will be filled and then enable them to start communication

[chelyuk]

Ultimately, my question is related to the minimal SPI transfer size which your library suppose to handle. I achieve the proper communication with SPI transfer size from 8 bytes amd higher. But for less then 8 bytes it does not work properly for me. Is it possible to achieve stable communication with the SPI transfer 1 byte per each transer?

…

________________________________ From: Earle F. Philhower, III ***@***.***> Sent: Sunday, August 4, 2024 11:17:02 PM To: earlephilhower/arduino-pico ***@***.***> Cc: chelyuk ***@***.***>; Author ***@***.***> Subject: Re: [earlephilhower/arduino-pico] SPISlave getting data without shift on the FIFO queue depth (Discussion #2316) Err, I really don't see what you're doing, sorry. If you're loading 8 bytes of 0 into the SPI FIFO then of course things will be 8 bytes delayed, no? A single dummy byte in the FIFO is all it seems you'd need in your comms case (i.e. since the 1st command in write will simultaneously read out dummy data). SPISlave, and the SPI slave HW block, will not clear the FIFO between transactions. — Reply to this email directly, view it on GitHub<#2316 (reply in thread)>, or unsubscribe<https://github.com/notifications/unsubscribe-auth/AG5IHYADMKL6JFYCCGJ2SKLZP2D35AVCNFSM6AAAAABL67S4WWVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTAMRTGY4DGMY>. You are receiving this because you authored the thread.Message ID: ***@***.***>