- Circuit: 12-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and mse parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add12u_19A | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [VerilogPDK45] [C] |
| add12u_2X6 | 0.012 | 0.024 | 75.00 | 0.034 | 1.5 | [Verilog] [VerilogPDK45] [C] |
| add12u_0T9 | 0.037 | 0.098 | 90.62 | 0.10 | 14 | [Verilog] [VerilogPDK45] [C] |
| add12u_0XY | 0.10 | 0.24 | 96.88 | 0.28 | 92 | [Verilog] [C] |
| add12u_013 | 0.21 | 0.82 | 97.84 | 0.58 | 474 | [Verilog] [C] |
| add12u_0HR | 0.50 | 1.67 | 99.28 | 1.39 | 2518 | [Verilog] [C] |
| add12u_2L7 | 1.56 | 3.12 | 99.98 | 4.26 | 20920 | [Verilog] [VerilogPDK45] [C] |
| add12u_04U | 3.20 | 7.71 | 99.91 | 8.54 | 92047 | [Verilog] [C] |
| add12u_1KC | 6.25 | 12.50 | 100.00 | 16.24 | 325756 | [Verilog] [VerilogPDK45] [C] |
| add12u_2MB | 12.50 | 25.00 | 100.00 | 30.62 | 13015.54e2 | [Verilog] [C] |
- V. Mrazek, Z. Vasicek and R. Hrbacek, "Role of circuit representation in evolutionary design of energy-efficient approximate circuits" in IET Computers & Digital Techniques, vol. 12, no. 4, pp. 139-149, 7 2018. doi: 10.1049/iet-cdt.2017.0188