- Circuit: 16-bit unsigned adders
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add16u_1E2 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add16u_1NN | 0.00061 | 0.0031 | 18.75 | 0.0016 | 3.0 | [Verilog] [C] |
| add16u_1HK | 0.0014 | 0.0076 | 29.69 | 0.0037 | 13 | [Verilog] [C] |
| add16u_1DM | 0.00069 | 0.0031 | 37.50 | 0.0019 | 2.2 | [Verilog] [C] |
| add16u_1MB | 0.015 | 0.049 | 49.22 | 0.041 | 876 | [Verilog] [C] |
| add16u_1US | 0.056 | 0.32 | 68.55 | 0.15 | 14574 | [Verilog] [C] |
| add16u_1X9 | 2.01 | 6.46 | 89.45 | 5.41 | 16774.987e3 | [Verilog] [C] |
| add16u_0MH | 9.90 | 34.18 | 100.00 | 22.35 | 25358.103e4 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020