- Circuit: 8-bit signed adders (with overflow)
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| add8s_83C | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| add8s_6FR | 0.39 | 1.56 | 37.30 | 1.48 | 0.7 | [Verilog] [C] |
| add8s_6XL | 1.09 | 3.12 | 77.83 | 7.00 | 2.9 | [Verilog] [C] |
| add8s_704 | 2.19 | 10.16 | 88.98 | 12.68 | 12 | [Verilog] [C] |
| add8s_6UC | 4.45 | 15.62 | 94.39 | 23.64 | 49 | [Verilog] [C] |
| add8s_6PA | 7.66 | 23.44 | 96.91 | 33.04 | 142 | [Verilog] [C] |
| add8s_6T8 | 18.28 | 54.69 | 98.52 | 67.56 | 839 | [Verilog] [C] |
| add8s_6HF | 44.45 | 100.00 | 99.48 | 99.98 | 4551 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020