- Circuit: 8x2-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x2u_106 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x2u_0PJ | 0.049 | 0.20 | 25.00 | 0.76 | 1.0 | [Verilog] [C] |
| mul8x2u_0S7 | 0.067 | 0.29 | 37.50 | 1.45 | 1.5 | [Verilog] [C] |
| mul8x2u_0HB | 0.19 | 0.59 | 62.50 | 3.58 | 7.5 | [Verilog] [C] |
| mul8x2u_0ZF | 0.47 | 2.05 | 70.90 | 8.16 | 49 | [Verilog] [C] |
| mul8x2u_0ZV | 1.66 | 6.15 | 73.24 | 18.64 | 615 | [Verilog] [C] |
| mul8x2u_0XM | 4.90 | 15.53 | 74.22 | 43.01 | 5217 | [Verilog] [C] |
| mul8x2u_0NG | 18.68 | 74.71 | 74.71 | 100.00 | 76011 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020