- Circuit: 8x3-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mae parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x3u_0KE | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x3u_1JC | 0.0061 | 0.098 | 6.25 | 0.07 | 0.25 | [Verilog] [C] |
| mul8x3u_1R5 | 0.012 | 0.049 | 25.00 | 0.32 | 0.25 | [Verilog] [C] |
| mul8x3u_0MU | 0.085 | 0.29 | 62.50 | 1.86 | 6.2 | [Verilog] [C] |
| mul8x3u_15X | 0.21 | 0.68 | 73.05 | 4.15 | 36 | [Verilog] [C] |
| mul8x3u_0BH | 0.57 | 2.05 | 84.72 | 9.25 | 235 | [Verilog] [C] |
| mul8x3u_0SF | 1.34 | 5.22 | 85.69 | 18.70 | 1309 | [Verilog] [C] |
| mul8x3u_00D | 3.46 | 14.50 | 86.62 | 37.23 | 8553 | [Verilog] [C] |
| mul8x3u_0Q5 | 8.40 | 31.01 | 87.06 | 65.71 | 51275 | [Verilog] [C] |
| mul8x3u_0QB | 21.79 | 87.16 | 87.16 | 100.00 | 380056 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020