- Circuit: 8x4-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and mre parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x4u_2UU | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x4u_35S | 0.0031 | 0.049 | 6.25 | 0.043 | 0.25 | [Verilog] [C] |
| mul8x4u_2AN | 0.0061 | 0.024 | 25.00 | 0.18 | 0.25 | [Verilog] [C] |
| mul8x4u_3AA | 0.018 | 0.049 | 37.50 | 0.50 | 1.5 | [Verilog] [C] |
| mul8x4u_30G | 0.047 | 0.17 | 60.16 | 1.18 | 8.0 | [Verilog] [C] |
| mul8x4u_3JN | 0.13 | 0.42 | 84.38 | 2.76 | 50 | [Verilog] [C] |
| mul8x4u_0S7 | 0.40 | 1.59 | 90.77 | 7.28 | 427 | [Verilog] [C] |
| mul8x4u_366 | 1.39 | 5.37 | 91.77 | 17.71 | 5418 | [Verilog] [C] |
| mul8x4u_4Z7 | 3.97 | 18.63 | 93.09 | 39.63 | 43327 | [Verilog] [C] |
| mul8x4u_555 | 23.35 | 93.38 | 93.38 | 100.00 | 16831.062e2 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020