- Circuit: 8x7-bit unsigned multiplier
- Selection criteria: pareto optimal sub-set wrt. pwr and ep parameters
| Circuit name | MAE% | WCE% | EP% | MRE% | MSE | Download |
|---|---|---|---|---|---|---|
| mul8x7u_0V5 | 0.00 | 0.00 | 0.00 | 0.00 | 0 | [Verilog] [C] |
| mul8x7u_4L6 | 0.022 | 0.20 | 11.13 | 0.26 | 456 | [Verilog] [C] |
| mul8x7u_4MD | 0.0053 | 0.012 | 43.75 | 0.20 | 7.0 | [Verilog] [C] |
| mul8x7u_3UT | 0.0033 | 0.012 | 53.12 | 0.13 | 2.8 | [Verilog] [C] |
| mul8x7u_1FZ | 0.25 | 0.78 | 56.99 | 5.77 | 12964 | [Verilog] [C] |
| mul8x7u_3LF | 0.01 | 0.04 | 76.38 | 0.36 | 19 | [Verilog] [C] |
| mul8x7u_6TV | 0.046 | 0.17 | 87.27 | 1.30 | 393 | [Verilog] [C] |
| mul8x7u_4MC | 24.71 | 98.83 | 98.83 | 100.00 | 11722.021e4 | [Verilog] [C] |
- V. Mrazek, L. Sekanina, Z. Vasicek "Libraries of Approximate Circuits: Automated Design and Application in CNN Accelerators" IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol 10, No 4, 2020