Replies: 8 comments 28 replies
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I don't know if any of this helps or not, but I see that the first Stacked Nots (below the BootROM) have gone to the poly and there is no M1 anymore :( But it seems to me they have nowhere to go but to join together one after another in a train. 😃 |
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Oh thank you! This helps a lot. Now the connection from the huge input pads can be clearly seen, how it is winding up and down under the metal. For the standard cells, the active areas and n-wells have never been so perfectly visible before. Also the connections between M1 and M2 can be seen as rectangles. The other die shots we had were so blurry that those connections looked circular. Oh, and 0018 is a perfect shot of those big DFFSR flip flops. This will save me a huge amount of time, seeing poly and active so clearly. And those long strips of small vias under the supply rails are really nothing more than well connections like I guessed. I'm still not getting what those spare cells are supposed to be (0017). But I think I will be able to figure out their layout now. |
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Have you seen a ripped off M2 on a silicon-pron? There's a DMG CPU-B and M1 for the parts you asked for there you can clearly see. In particular I see that for Stacked Nots1 (under BootROM) the outputs do not go anywhere (floating). https://siliconpr0n.org/map/nintendo/dmg-cpu-b/s1-1_mit20x/#x=13088&y=6496&z=8 |
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Yes, I've seen that. That's where I got my pron from. :) |
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Hi, just wanted to let you know, I have finally drawn the layout for the RST pad from your picture: http://iceboy.a-singer.de/doc/dmg_cells.html#ibuf_a |
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I'm happy you like the diodes! :) Régis and I, we would very much like to add the analog sound stuff to the schematic. It would be great to have better pictures of those. I marked some areas, but of course those analog things exist two or four times, so there are other options. While making the layout of the ~RST pad, I heavily relied on your picture for those diodes and the n-wells. Learning from this, I think it would be very helpful to have pictures of the other IO pads as well. The more metal you get off the better. But I understand it may be risky taking off to much. What I would also find interesting are those things in each of the four corners, could be diodes or capacitors: There are some big pads with hundreds of holes. Maybe substrate connections to ground? I don't understand why they are only in this area: The different types of flip flops are very densely packet cells. You already took perfect shots of the one with DFF with set&reset inputs. It would be good to have pictures of the other flip flops as well. It's already getting late, I will try to look for some specimen that can be easily located close to the border or near big structures, so that it's easier to find under the microscope. Yeah, I don't know how much work this is. Don't feel pressured, just do what you can when you are in the mood for it. There is no hurry, I still have a lot of other cells to draw anyway. :) |
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Isn't that a typo? The DMG SoC uses p-wells everywhere as far as I can see. |
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No, I double checked. I'm confusing n- and p-well all the time, but then the rules checker of Electric VLSI always sets me straight again. I guess you are the same as me there. :) You mean PMOS transistors need a well, right? Yeah, that's the n-well. It needs opposite doping than the transistors that sit in it. |
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Right. That's right. So I need to relabel this stuff everywhere in the chips :) |
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Oh no 😟 |
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Analog stuff: https://drive.google.com/drive/u/2/folders/1bMiEECDJHcIFA21s0CERc2Yqiyr9NCi- Previews: |
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Thank you. That was so fast. I stared at the analog IOs for a while. I think I have an idea now how they are implemented. If I see it correctly, they are bidirectional. I think they are just a big transmission gate, meaning, one big NMOS and one big PMOS, both being permanently enabled, having their gate connected to VDD and GND respectively. They are a bit different at the top though, I don't know why yet. |
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Nah, only the analog input is a transmission gate. The outputs are different. |
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Okay, I created a secret new floorplan for the map. It can only be enabled by this link:
I haven't colored the DFFSR flip flop, because you already took perfect pictures of it with the spare cells. I will remove this floorplan if you're done. |
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This is the area I mean: |
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I can't say for sure right now where the "skin" peeled off is better and where it's worse. Thanks for the map, as soon as I get to the microscope I will collect you samples of cells, where you can see better poly. |
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https://drive.google.com/drive/u/2/folders/1-VlFxGOgzJBf4ymO2J9WbGne3Zc96t0w S Pad: P14+P15+Bottom right cross: /NMI Pad (gone): pad comb (somewhere from the top pads): Cross-sections: Mass viases section: |
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Single slides should be rotated +0.20 deg. Stitched images are aligned. |
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Interesting things. 🤔 The XCrosses look the same as the thing that is right next to the SCK and SIN pads for example. I think it's a polarity protection, implemented by a lot of NMOSes, which have their gates wired to GND and their source/drain terminals wired to GND and VDD. When the polarity is correct, then they are not conductive, because the gate is grounded. If the polarity is reversed, then the gate is VDD and they are conductive. But there is more. It is possible that they also implement capacitors. Could be diodes as well, but for diodes I can't see a reason for the comb shapes. (By comb shapes I mean the small ones on the N/P active layer, not the big metal combs.) It's just a wild guess, but I think the comb shape could improve the capacity by not allowing the charges to push themselves too far away from each other, making better use of the area. Similar like braid wire counters the skin effect, allowing more current per area. Does this make sense, or do you have another idea? Could also just be my confirmation bias, because I was suspecting capacitors before. |
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I don't know much about analog components of integrated circuits, because I do most of my analysis of logic, and there is enough knowledge that a transistor is a "switch with a short gate memory" 😄 |
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Although it may be some simple protection against a change of polarity. After all, we have a handheld where the user can easily insert the batteries backwards 🤣 |
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Cells: https://drive.google.com/drive/u/2/folders/108xxdoMb1MvxBl9psPZuUqRCLP_3O43- I hope I got the colors right 😃 I don't really figure out where the Green/DarkGreen and Gray/DarkGray are. If anything, I'll do a follow-up. |
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It would be nice if instead of Furrtek cryptic designations, you could write on the cell its type and just its ordinal number (g0, g1, g2 etc.). |
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Sorry about the green and gray colors, I didn't notice that. You got everything. You just mixed up the gray and dark-gray (MUXI and DR_LATCH). Maybe the gray looks darker than the dark-gray because of the way Leaflet mixes the transparent layers. The quality of your pictures is really so much better than the others. I will fix the shapes of the poly and active areas of the latches and muxes. It will safe me a lot of time and guess work when I'm layouting the flip-flops. Thank you very much! 😘 |
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I was thinking about adding the cell type to the label layer of the map, but I haven't done it yet, because I need to implement it in a generic way. I don't want to place the text for each cell type manually. My converter tool must find a good non-overlapping placement on its own. For bigger cells, this isn't a problem, but the small inverters are tricky. When I reduce the font size, then it looks like shit, because the resolution of the pictures is much lower than the maximum zoom level of the map. I can't increase this resolution, because the pictures generated by my tool are already 16Kx16K and this takes multiple gigabytes of RAM on my PC when running it on the Mono Framework. The C# object that I use for drawing needs more memory than just the raw pixel data, because all drawing changes are put in a fifo and get applied delayed somehow to speed things up for smaller images, I don't really know. I call Flush functions very often in a desperate attempt to counter that. If I don't flush, then my kernel runs out of memory and starts killing shit. But yes, having the cell type on the map is also something I really want to have. Régis and I, we wanted to stay compatible to Furrtek, so we chose to keep the cryptic naming scheme. We already had documents and also discussions in which we are referring to the cells in Furrtek's names. Would you prefer it if the cells were simply numbered, or did you propose that for making more space for the cell type? |
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I don't mind leaving the Furrtek names, if that's more convenient for you :) |
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I have to think about how to add the types there. For now I have added more information to the popup that opens when you click on a cell. |
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There is one part of the boot ROM that I don't understand. It is at the left hand side of the boot ROM, where the row selector active area is connected to VDD. My problem is, there is a visible edge around the VDD vias. This makes it look like all of those vias are connected to the same area below. But this can't be true, because this would mean that there are no well connections. In my layout, I made the six vias in the middle the well connection, but I'm not sure if this is correct. Do you have better visuals of that area? Could also be the VDD metal that gets wider around the vias, but it's not really clear. |
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was on vacation, when I get to the microscope will take pictures 😃 |
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OMG, there is no well connection at all. Electric's rules checker will kill me. 😱 |
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I've been tidying up my chip collection and decided to save what's left over from my DMG-CPU B polishing sessions. I'll put it here: https://drive.google.com/drive/u/3/folders/11EcTeWtmXpVKZfzkdOcWubE6-Ka3VMSu ClkGen and PPU are already there now. |
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Great! Maybe I can stitch them together for a third map option. The detail of those pictures would be worth it, even if it doesn't cover the whole chip surface. And it's always good to have more pictures of those cells. |
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Updated Cells1: ClkGen Cells are made on a 20x objective, MegaCells are made on a 40x objective. |
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Hi,
@msinger, moved the topic into a separate discussion (from #13).
😃
RST Pad
XI Pad
SIN Pad
SCK Pad
Stacked Nots
Spare
Source pics (slides)
Slides_1.zip
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