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multiplier m should represent the number of devices connected in parallel, hence changing the effective total width of transistors
Actual Behavior
but changing multiplier m has completely no effect on the circuit behavior
Current Solution
To simulate a device with large width (ex: a power transistor with wdith > 10mm), we currently have two solutions:
manually connect more than 100 MOS in the schematic to achieve the same effect as using the multiplier, since the maximum width of a single MOS is 100um
use the provided ideal device nmos4 .sym from Xschem standard library, but still unsure whether the simulation result would be largely different from using nfet_03v3 from the GF180 pdk
FYR if anyone is facing the same problem
The text was updated successfully, but these errors were encountered:
Expected Behavior
multiplier m should represent the number of devices connected in parallel, hence changing the effective total width of transistors
Actual Behavior
but changing multiplier m has completely no effect on the circuit behavior
Current Solution
To simulate a device with large width (ex: a power transistor with wdith > 10mm), we currently have two solutions:
FYR if anyone is facing the same problem
The text was updated successfully, but these errors were encountered: