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Copy pathksim.kt
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ksim.kt
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/*
KUE-CHIP2 Simulator
Copyright (C) 2018 Hideyuki Kawabata
*/
import java.io.File
import java.io.InputStream
class Byte(n: Int) {
var bit = Array(8, {_->0})
var cf = 0
var vf = 0
var nf = 0
var zf = 0
init {
num2byte(n)
}
fun getBit(i: Int): Int {return bit[i]}
fun getCF(): Int {return cf}
fun getVF(): Int {return vf}
fun getNF(): Int {return nf}
fun getZF(): Int {return zf}
fun num2byte(n: Int) {
tailrec fun f(n: Int, i: Int) {
if (i > 7) return
bit[i] = n.rem(2)
f(n.div(2), i+1)
}
tailrec fun make_positive(n: Int): Int {
if (n < 0) {
return make_positive(256 + n)
} else {
return n
}
}
f(make_positive(n), 0)
}
fun byte2num(): Int {
tailrec fun f(n: Int, i: Int): Int {
if (i > 7) return n
return f(n*2 + bit[7-i], i+1)
}
return f(0, 0)
}
fun toStr(): String {
var s: String = "["
for (i: Int in 0..3) {
s = s.plus("%1d".format(bit[7-i]))
}
// s = s.plus(" ")
for (i: Int in 4..7) {
s = s.plus("%1d".format(bit[7-i]))
}
s = s.plus("]")
return s
}
fun print() {
for (i: Int in 0..3) {
print("%1d".format(bit[7-i]))
}
// print(" ")
for (i: Int in 4..7) {
print("%1d".format(bit[7-i]))
}
println()
}
fun copy(b: Byte): Byte {
val bbit = b.getBits()
for (i: Int in 0..7) {
bit[i] = bbit[i]
}
return this
}
fun getBits(): Array<Int> {
return bit
}
fun and(b: Byte): Byte {
tailrec fun f(i: Int) {
if (i > 7) return
if (b.getBits()[i] == 0) bit[i] = 0
f(i+1)
}
f(0)
return this
}
fun or(b: Byte): Byte {
tailrec fun f(i: Int) {
if (i > 7) return
if (b.getBits()[i] > 0) bit[i] = 1
f(i+1)
}
f(0)
return this
}
fun eor(b: Byte): Byte {
tailrec fun f(i: Int) {
if (i > 7) return
if (b.getBits()[i] == bit[i]) {
bit[i] = 0
} else {
bit[i] = 1
}
f(i+1)
}
f(0)
return this
}
fun add(b: Byte): Byte {
var carry = 0
var carry_prev = 0
for (i: Int in 0..7) {
carry_prev = carry
if (bit[i] == 0 && b.bit[i] == 0) { // 0, 0
if (carry > 0) {
bit[i] = 1; carry = 0
} else {
bit[i] = 0; carry = 0
}
} else if (bit[i] == 0 && b.bit[i] == 1) { // 0, 1
if (carry > 0) {
bit[i] = 0; carry = 1
} else {
bit[i] = 1; carry = 0
}
} else if (bit[i] == 1 && b.bit[i] == 0) { // 1, 0
if (carry > 0) {
bit[i] = 0; carry = 1
} else {
bit[i] = 1; carry = 0
}
} else { // 1, 1
if (carry > 0) {
bit[i] = 1; carry = 1
} else {
bit[i] = 0; carry = 1
}
}
}
if (carry == carry_prev) {
vf = 0
} else {
vf = 1
}
cf = carry
return this
}
fun sub(b: Byte): Byte {
var borrow = 0
var borrow_prev = 0
for (i: Int in 0..7) {
borrow_prev = borrow
if (bit[i] == 0 && b.bit[i] == 0) { // 0, 0
if (borrow > 0) {
bit[i] = 1; borrow = 1
} else {
bit[i] = 0; borrow = 0
}
} else if (bit[i] == 0 && b.bit[i] == 1) { // 0, 1
if (borrow > 0) {
bit[i] = 0; borrow = 1
} else {
bit[i] = 1; borrow = 1
}
} else if (bit[i] == 1 && b.bit[i] == 0) { // 1, 0
if (borrow > 0) {
bit[i] = 0; borrow = 0
} else {
bit[i] = 1; borrow = 0
}
} else { // 1, 1
if (borrow > 0) {
bit[i] = 1; borrow = 1
} else {
bit[i] = 0; borrow = 0
}
}
}
if (borrow == borrow_prev) {
vf = 0
} else {
vf = 1
}
cf = borrow
return this
}
fun cmp(b: Byte): Int {
val tn = this.byte2num()
val bn = b.byte2num()
return (tn - bn)
}
fun sra(): Byte {
cf = bit[0]
for (i: Int in 0..6) {
bit[i] = bit[i+1]
}
vf = 0
return this
}
fun sla(): Byte {
cf = bit[7]
for (i: Int in 0..6) {
bit[7-i] = bit[7-i-1]
}
bit[0] = 0
vf = if (cf != bit[7]) {1} else {0}
return this
}
fun srl(): Byte {
cf = bit[0]
for (i: Int in 0..6) {
bit[i] = bit[i+1]
}
bit[7] = 0
vf = 0
return this
}
fun sll(): Byte {
cf = bit[7]
for (i: Int in 0..6) {
bit[7-i] = bit[7-i-1]
}
bit[0] = 0
vf = 0
return this
}
fun rra(cf_: Int): Byte {
val t = bit[0]
for (i: Int in 0..6) {
bit[i] = bit[i+1]
}
bit[7] = cf_
cf = t
vf = 0
return this
}
fun rla(cf_: Int): Byte {
var t = bit[7]
for (i: Int in 0..6) {
bit[7-i] = bit[7-i-1]
}
bit[0] = cf_
cf = t
vf = if (cf == bit[7]) {0} else {1}
return this
}
fun rrl(): Byte {
cf = bit[0]
for (i: Int in 0..6) {
bit[i] = bit[i+1]
}
bit[7] = cf
vf = 0
return this
}
fun rll(): Byte {
cf = bit[7]
for (i: Int in 0..6) {
bit[7-i] = bit[7-i-1]
}
bit[0] = cf
vf = 0
return this
}
fun inc(): Byte {
var num = this.byte2num()
this.num2byte(num + 1)
return this
}
}
class KueChip2Board() {
var opflag = 0
var acc = Byte(0)
var ix = Byte(0)
var pc = Byte(0)
var mar = Byte(0)
var ir = Byte(0)
var dr = Byte(0)
var zerof = 0
var negf = 0
var vf = 0
var cf = 0
var mem = Array(256, {_->Byte(0)})
var dmem = Array(256, {_->Byte(0)})
// var pmode = "decimal"
var pmode = "hex"
// the same as the function in kas.kt
fun parseNumber0(s: String): Int {
//println("(parseNumber0) s=" + s)
if (s == "") throw SymError("(in parseNumber0) " + s + ": not a number")
val ca = s.toCharArray()
if (!s[0].isDigit()) {
throw SymError("(in parseNumber0) " + s + ": not a number")
} else if (s[ca.size-1] == 'h') {
var s2 = s.trim({ch -> ch == 'h'})
try {
return (s2.toLong(radix = 16).toInt()) // 0AH
} catch (e: NumberFormatException) {
throw SymError("(in parseNumber0) " + s + ": not a number")
}
} else {
try {
return s.toInt() // 3
} catch (e: NumberFormatException) {
throw SymError("(in parseNumber0) " + s + ": not a number")
}
}
}
fun togglePrintMode() {
if (pmode == "hex") pmode = "decimal" else pmode = "hex"
}
fun printAll() {
printRegs()
printMem()
printDMem()
}
fun printRegs() {
val v_acc = acc.byte2num()
val s_acc = if (v_acc < 128) {
"(" + v_acc.toString() + ")"
} else {
"(" + (v_acc-256).toString() + "/" + v_acc.toString() + ")"
}
if (pmode == "hex") {
print("ACC=" + "%02X".format(acc.byte2num()) + s_acc + ", ")
} else {
print("ACC" + acc.toStr() + "=" + s_acc + ", ")
}
val v_ix = ix.byte2num()
val s_ix = if (v_ix < 128) {
"(" + v_ix.toString() + ")"
} else {
"(" + (v_ix-256).toString() + "/" + v_ix.toString() + ")"
}
if (pmode == "hex") {
print("IX=" + "%02X".format(ix.byte2num()) + s_ix + ", ")
} else {
print("IX" + ix.toStr() + "=" + s_ix + ", ")
}
print("CF=%d, VF=%d, NF=%d, ZF=%d".format(cf,vf,negf,zerof))
println()
val v_pc = pc.byte2num()
val s_pc = if (v_pc < 128) {
"(" + v_pc.toString() + ")"
} else {
"(" + (v_pc-256).toString() + "/" + v_pc.toString() + ")"
}
if (pmode == "hex") {
print("PC=" + "%02X".format(pc.byte2num()) + s_pc + ", ")
} else {
print("PC" + pc.toStr() + "=" + s_pc + ", ")
}
val v_mar = mar.byte2num()
val s_mar = if (v_mar < 128) {
"(" + v_mar.toString() + ")"
} else {
"(" + (v_mar-256).toString() + "/" + v_mar.toString() + ")"
}
if (pmode == "hex") {
print("MAR=" + "%02X".format(mar.byte2num()) + s_mar + ", ")
} else {
print("MAR" + mar.toStr() + "=" + s_mar + ", ")
}
val v_ir = ir.byte2num()
val s_ir = if (v_ir < 128) {
"(" + v_ir.toString() + ")"
} else {
"(" + (v_ir-256).toString() + "/" + v_ir.toString() + ")"
}
if (pmode == "hex") {
print("IR=" + "%02X".format(ir.byte2num()) + s_ir + ", ")
} else {
print("IR" + ir.toStr() + "=" + s_ir + ", ")
}
val v_dr = dr.byte2num()
val s_dr = if (v_dr < 128) {
"(" + v_dr.toString() + ")"
} else {
"(" + (v_dr-256).toString() + "/" + v_dr.toString() + ")"
}
if (pmode == "hex") {
print("DR=" + "%02X".format(dr.byte2num()) + s_dr)
} else {
print("DR" + dr.toStr() + "=" + s_dr)
}
// print(", OP=" + opflag)
println()
}
fun printMem() {
var fmt_entity: String
var fmt_addr: String
if (pmode == "hex") {
fmt_entity = " %02X"
fmt_addr = " %02X"
} else {
fmt_entity = "%4d"
fmt_addr = "%3d"
}
for (addr: Int in 0..255) {
if (addr.rem(16) == 0) {
if (addr != 0) println()
print(fmt_addr.format(addr) + " : ")
}
print(fmt_entity.format(mem[addr].byte2num()))
}
println()
}
fun printDMem() {
var fmt_entity: String
var fmt_addr: String
if (pmode == "hex") {
fmt_entity = " %02X"
fmt_addr = "1%02X"
} else {
fmt_entity = "%4d"
fmt_addr = "%3d"
}
for (addr: Int in 0..255) {
if (addr.rem(16) == 0) {
if (addr != 0) println()
print(fmt_addr.format(addr) + " : ")
}
print(fmt_entity.format(dmem[addr].byte2num()))
}
println()
}
fun setMem(v: String, a: String) {
val value = parseNumber0(v)
val addr = parseNumber0(a)
mem[addr].num2byte(value)
}
fun setDMem(v: String, a: String) {
val value = parseNumber0(v)
val addr = parseNumber0(a)
dmem[addr].num2byte(value)
}
// "acc" -> acc
fun name2reg(s: String): Byte {
when (s) {
"acc" -> return acc
"ix" -> return ix
// else -> return Byte(s.toInt()) // immediate value
else -> return Byte(parseNumber0(s)) // immediate value
}
}
// FLAG
fun setFlag(b: Byte) {
negf = b.getBit(7)
when (b.byte2num()) {
0 -> zerof = 1
else -> zerof = 0
}
}
// LD
fun ld(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
// val n2 = parseNumber0(opr2)
val n2 = r2.byte2num()
//println("(LD) opr1=" + opr1 + " opr2=" + opr2 + " n2=" + n2)
when (ty) {
instT.OP_RR -> r1.copy(r2) // LD ACC, IX
instT.OP_RImm -> r1.copy(r2) // LD ACC, 3
instT.OP_RDir -> r1.copy(mem[n2]) // LD ACC, [3]
instT.OP_RDis -> r1.copy(mem[(ix.byte2num() + n2).rem(256)]) // LD ACC, [IX+3]
instT.OP_RDir2 -> r1.copy(dmem[n2]) // LD ACC, (3)
instT.OP_RDis2 -> r1.copy(dmem[(ix.byte2num() + n2).rem(256)]) // LD ACC, (IX+3)
else -> throw SymError("(in ld)" + ty + ": illegal addressing")
}
}
// ST
fun st(ty: instT, opr1: String, opr2: String) {
//println("(ST) opr1=" + opr1 + " opr2=" + opr2)
val r1 = name2reg(opr1)
val n2 = parseNumber0(opr2)
when (ty) {
instT.OP_RR -> {}
instT.OP_RImm -> {}
instT.OP_RDir -> mem[n2].copy(r1) // ST ACC, [5]
instT.OP_RDis -> mem[(ix.byte2num() + n2).rem(256)].copy(r1) // ST ACC, [IX+3]
instT.OP_RDir2 -> dmem[n2].copy(r1) // ST ACC, (5)
instT.OP_RDis2 -> dmem[(ix.byte2num() + n2).rem(256)].copy(r1) // ST ACC, (IX+3)
else -> throw SymError("(in ld)" + ty + ": illegal addressing")
}
}
// ADD
fun add(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
var n2 = r2.byte2num()
when (ty) {
instT.OP_RR -> r1.add(r2) // ADD ACC, IX
instT.OP_RImm -> r1.add(r2) // ADD ACC, 3
instT.OP_RDir -> r1.add(mem[n2]) // ADD ACC, [5]
instT.OP_RDis -> r1.add(mem[(ix.byte2num() + n2).rem(256)]) // ADD ACC, [IX+2]
instT.OP_RDir2 -> r1.add(dmem[n2]) // ADD ACC, (5)
instT.OP_RDis2 -> r1.add(dmem[(ix.byte2num() + n2).rem(256)]) // ADD ACC, (IX+2)
else -> throw SymError("(in add)" + ty + ": illegal addressing")
}
// cf = r1.getCF()
vf = r1.getVF()
setFlag(r1)
}
// SUB
fun sub(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
// val n2 = parseNumber0(opr2)
val n2 = r2.byte2num()
when (ty) {
instT.OP_RR -> r1.sub(r2) // SUB ACC, IX
instT.OP_RImm -> r1.sub(r2) // SUB ACC, 3
instT.OP_RDir -> r1.sub(mem[n2]) // SUB ACC, [5]
instT.OP_RDis -> r1.sub(mem[(ix.byte2num() + n2).rem(256)]) // SUB ACC, [IX+2]
instT.OP_RDir2 -> r1.sub(dmem[n2]) // SUB ACC, (5)
instT.OP_RDis2 -> r1.sub(dmem[(ix.byte2num() + n2).rem(256)]) // SUB ACC, (IX+2)
else -> throw SymError("(in sub)" + ty + ": illegal addressing")
}
// cf = r1.getCF()
vf = r1.getVF()
setFlag(r1)
}
// ADC
fun adc(ty: instT, opr1: String, opr2: String) {
add(ty, opr1, opr2)
val r1 = name2reg(opr1)
val cf_1 = r1.getCF()
r1.add(Byte(cf))
val cf_2 = r1.getCF()
cf = if (cf_1 > cf_2) cf_1 else cf_2
}
// SBC
fun sbc(ty: instT, opr1: String, opr2: String) {
sub(ty, opr1, opr2)
val r1 = name2reg(opr1)
// cf = r1.getCF()
// r1.sub(Byte(cf))
val cf_1 = r1.getCF()
r1.sub(Byte(cf))
val cf_2 = r1.getCF()
cf = if (cf_1 > cf_2) cf_1 else cf_2
}
// AND
fun and(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
// val n2 = parseNumber0(opr2)
val n2 = r2.byte2num()
when (ty) {
instT.OP_RR -> r1.and(r2) // AND ACC, IX
instT.OP_RImm -> r1.and(r2) // AND ACC, 3
instT.OP_RDir -> r1.and(mem[n2]) // AND ACC, [5]
instT.OP_RDis -> r1.and(mem[(ix.byte2num() + n2).rem(256)]) // AND ACC, [IX+2]
instT.OP_RDir2 -> r1.and(dmem[n2]) // AND ACC, (5)
instT.OP_RDis2 -> r1.and(dmem[(ix.byte2num() + n2).rem(256)]) // AND ACC, (IX+2)
else -> throw SymError("(in and)" + ty + ": illegal addressing")
}
setFlag(r1)
vf = 0
}
// OR
fun or(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
// val n2 = parseNumber0(opr2)
val n2 = r2.byte2num()
when (ty) {
instT.OP_RR -> r1.or(r2) // OR ACC, IX
instT.OP_RImm -> r1.or(r2) // OR ACC, 3
instT.OP_RDir -> r1.or(mem[n2]) // OR ACC, [5]
instT.OP_RDis -> r1.or(mem[(ix.byte2num() + n2).rem(256)]) // OR ACC, [IX+2]
instT.OP_RDir2 -> r1.or(dmem[n2]) // OR ACC, (5)
instT.OP_RDis2 -> r1.or(dmem[(ix.byte2num() + n2).rem(256)]) // OR ACC, (IX+2)
else -> throw SymError("(in or)" + ty + ": illegal addressing")
}
setFlag(r1)
vf = 0
}
// EOR
fun eor(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
// val n2 = parseNumber0(opr2)
val n2 = r2.byte2num()
when (ty) {
instT.OP_RR -> r1.eor(r2) // EOR ACC, IX
instT.OP_RImm -> r1.eor(r2) // EOR ACC, 3
instT.OP_RDir -> r1.eor(mem[n2]) // EOR ACC, [5]
instT.OP_RDis -> r1.eor(mem[(ix.byte2num() + n2).rem(256)]) // EOR ACC, [IX+2]
instT.OP_RDir2 -> r1.eor(dmem[n2]) // EOR ACC, (5)
instT.OP_RDis2 -> r1.eor(dmem[(ix.byte2num() + n2).rem(256)]) // EOR ACC, (IX+2)
else -> throw SymError("(in eor)" + ty + ": illegal addressing")
}
setFlag(r1)
vf = 0
}
// CMP
fun cmp(ty: instT, opr1: String, opr2: String) {
val r1 = name2reg(opr1)
val r2 = name2reg(opr2)
val t = Byte(0)
// val n2 = parseNumber0(opr2)
val n2 = r2.byte2num()
when (ty) {
instT.OP_RR -> t.copy(r1).sub(r2) // CMP ACC, IX
instT.OP_RImm -> t.copy(r1).sub(r2) // CMP ACC, 3
instT.OP_RDir -> t.copy(r1).sub(mem[n2]) // CMP ACC, [5]
instT.OP_RDis -> t.copy(r1).sub(mem[(ix.byte2num() + n2).rem(256)]) // CMP ACC, [IX+2]
instT.OP_RDir2 -> t.copy(r1).sub(dmem[n2]) // CMP ACC, (5)
instT.OP_RDis2 -> t.copy(r1).sub(dmem[(ix.byte2num() + n2).rem(256)]) // CMP ACC, (IX+2)
else -> throw SymError("(in cmp)" + ty + ": illegal addressing")
}
vf = t.getVF()
setFlag(t)
}
fun sra(opr1: String) {
val b = name2reg(opr1).sra()
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun sla(opr1: String) {
val b = name2reg(opr1).sla()
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun srl(opr1: String) {
val b = name2reg(opr1).srl()
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun sll(opr1: String) {
val b = name2reg(opr1).sll()
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun rra(opr1: String) {
val b = name2reg(opr1).rra(cf)
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun rla(opr1: String) {
val b = name2reg(opr1).rla(cf)
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun rrl(opr1: String) {
val b = name2reg(opr1).rrl()
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun rll(opr1: String) {
val b = name2reg(opr1).rll()
cf = b.getCF()
vf = b.getVF()
setFlag(b)
}
fun ba(opr1: String) {
pc.num2byte(parseNumber0(opr1))
}
fun bvf(opr1: String) {
if (vf == 1) pc.num2byte(parseNumber0(opr1))
}
fun bnz(opr1: String) {
if (zerof == 0) pc.num2byte(parseNumber0(opr1))
}
fun bz(opr1: String) {
if (zerof == 1) pc.num2byte(parseNumber0(opr1))
}
fun bzp(opr1: String) {
if (negf == 0) pc.num2byte(parseNumber0(opr1))
}
fun bn(opr1: String) {
if (negf == 1) pc.num2byte(parseNumber0(opr1))
}
fun bp(opr1: String) {
if ((negf == 0) && (zerof == 0)) pc.num2byte(parseNumber0(opr1))
}
fun bzn(opr1: String) {
if ((negf == 1) || (zerof == 1)) pc.num2byte(parseNumber0(opr1))
}
fun bni(opr1: String) {
println("bni: not implemented yet")
if (false) pc.num2byte(parseNumber0(opr1))
}
fun bno(opr1: String) {
println("bno: not implemented yet")
if (false) pc.num2byte(parseNumber0(opr1))
}
fun bnc(opr1: String) {
if (cf == 0) pc.num2byte(parseNumber0(opr1))
}
fun bc(opr1: String) {
if (cf == 1) pc.num2byte(parseNumber0(opr1))
}
fun bge(opr1: String) {
if ((vf == 0) && (negf == 0) || (vf == 1) && (negf == 1))
pc.num2byte(parseNumber0(opr1))
}
fun blt(opr1: String) {
if ((vf == 1) && (negf == 0) || (vf == 0) && (negf == 1))
pc.num2byte(parseNumber0(opr1))
}
fun bgt(opr1: String) {
if (((vf == 0) && (negf == 0) || (vf == 1) && (negf == 1)) && zerof == 0)
pc.num2byte(parseNumber0(opr1))
}
fun ble(opr1: String) {
if (((vf == 1) && (negf == 0) || (vf == 0) && (negf == 1)) || zerof == 1)
pc.num2byte(parseNumber0(opr1))
}
fun nop() {}
fun hlt() {opflag = 0}
fun outop() {}
fun inop() {}
fun rcf() {cf = 0}
fun scf() {cf = 1}
fun reset() {
pc.num2byte(0)
ir.num2byte(0)
dr.num2byte(0)
acc.num2byte(0)
ix.num2byte(0)
mar.num2byte(0)
zerof = 0
negf = 0
cf = 0
vf = 0
}
fun loadfile(fname: String) {
try {
val inputStream: InputStream = File(fname).inputStream()
val hex = mutableListOf<String>()
inputStream.bufferedReader().useLines {
lines -> lines.forEach {hex.add(it)}
}
var addr = 0
val pat1 = " *([0-9a-fA-F][0-9a-fA-F]*) *: *([0-9a-fA-F][0-9a-fA-F]).*".toRegex()
val pat2 = " *([0-9a-fA-F][0-9a-fA-F]).*".toRegex()
hex.forEach {
if (pat1.matches(it)) {
val (ca, va) = pat1.find(it)!!.destructured
addr = ca.toLong(radix = 16).toInt()
if (addr <= 0xff) {
mem[addr].num2byte(va.toLong(radix = 16).toInt())
} else {
dmem[addr-0x100].num2byte(va.toLong(radix = 16).toInt())
}
} else if (pat2.matches(it)) {
val (va) = pat2.find(it)!!.destructured
mem[addr].num2byte(va.toLong(radix = 16).toInt())
} else if (" *".toRegex().matches(it)) {
// do nothing
} else {
throw SymError("(loadfile) " + fname + ":" + it + ": illegal format")
}
addr++
}
println("OK.")
} catch (e: java.io.FileNotFoundException) {
println(fname + ": no such file")
} catch (e: SymError) {
println(e)
}
}
fun single(): Int {
// Read one byte from [PC] to ir and inc PC.
ir.copy(mem[pc.byte2num()])
pc.inc()
// Decode.
// If the instruction is a two-byte long,
// read next byte form [PC] to dr and inc PC.
val p = decode()
val ty = p.first.first
val op = p.first.second
var opr1 = p.first.third
var opr2 = p.second
if (ty == instT.OP_RImm ||
ty == instT.OP_RDir ||
ty == instT.OP_RDis ||
ty == instT.OP_RDir2 ||
ty == instT.OP_RDis2 ||
ty == instT.BR) {
dr.copy(mem[pc.byte2num()])
opr2 = dr.byte2num().toString()
pc.inc()
}
if (opr1 == "") {
opr1 = opr2
opr2 = ""
}
// println("inst: " + op + " " + opr1 + " " + opr2)
// Organize the instruction and execute it.
dispatch(this, op, ty, opr1, opr2)
return opflag
}
tailrec fun run(): Int {
opflag = 1
val f = single()
if (f > 0) {
print(".")
return run()
} else {
print(".\n")
return f
}
}
fun decode(): Pair<Triple<instT, String, String>, String> {
when (ir.byte2num()) {
0x00 -> return Pair(Triple(instT.OP_R, "nop", ""), "")
0x0f -> return Pair(Triple(instT.OP_R, "hlt", ""), "")
0x10 -> return Pair(Triple(instT.OP_R, "out", ""), "")
0x1f -> return Pair(Triple(instT.OP_R, "in", ""), "")
0x20 -> return Pair(Triple(instT.OP_R, "rcf", ""), "")
0x2f -> return Pair(Triple(instT.OP_R, "scf", ""), "")
0x30 -> return Pair(Triple(instT.BR, "ba", ""), "")
0x38 -> return Pair(Triple(instT.BR, "bvf", ""), "")
0x31 -> return Pair(Triple(instT.BR, "bnz", ""), "")
0x39 -> return Pair(Triple(instT.BR, "bz", ""), "")
0x32 -> return Pair(Triple(instT.BR, "bzp", ""), "")
0x3a -> return Pair(Triple(instT.BR, "bn", ""), "")
0x33 -> return Pair(Triple(instT.BR, "bp", ""), "")
0x3b -> return Pair(Triple(instT.BR, "bzn", ""), "")
0x34 -> return Pair(Triple(instT.BR, "bni", ""), "")
0x3c -> return Pair(Triple(instT.BR, "bno", ""), "")
0x35 -> return Pair(Triple(instT.BR, "bnc", ""), "")
0x3d -> return Pair(Triple(instT.BR, "bc", ""), "")
0x36 -> return Pair(Triple(instT.BR, "bge", ""), "")
0x3e -> return Pair(Triple(instT.BR, "blt", ""), "")
0x37 -> return Pair(Triple(instT.BR, "bgt", ""), "")
0x3f -> return Pair(Triple(instT.BR, "ble", ""), "")
0x40 -> return Pair(Triple(instT.OP_R, "sra", "acc"), "")
0x41 -> return Pair(Triple(instT.OP_R, "sla", "acc"), "")
0x42 -> return Pair(Triple(instT.OP_R, "srl", "acc"), "")
0x43 -> return Pair(Triple(instT.OP_R, "sll", "acc"), "")
0x44 -> return Pair(Triple(instT.OP_R, "rra", "acc"), "")
0x45 -> return Pair(Triple(instT.OP_R, "rla", "acc"), "")
0x46 -> return Pair(Triple(instT.OP_R, "rrl", "acc"), "")
0x47 -> return Pair(Triple(instT.OP_R, "rll", "acc"), "")
0x48 -> return Pair(Triple(instT.OP_R, "sra", "ix"), "")
0x49 -> return Pair(Triple(instT.OP_R, "sla", "ix"), "")
0x4a -> return Pair(Triple(instT.OP_R, "srl", "ix"), "")
0x4b -> return Pair(Triple(instT.OP_R, "sll", "ix"), "")
0x4c -> return Pair(Triple(instT.OP_R, "rra", "ix"), "")
0x4d -> return Pair(Triple(instT.OP_R, "rla", "ix"), "")
0x4e -> return Pair(Triple(instT.OP_R, "rrl", "ix"), "")
0x4f -> return Pair(Triple(instT.OP_R, "rll", "ix"), "")
0x60 -> return Pair(Triple(instT.OP_RR, "ld", "acc"), "acc")
0x61 -> return Pair(Triple(instT.OP_RR, "ld", "acc"), "ix")
0x62 -> return Pair(Triple(instT.OP_RImm, "ld", "acc"), "")
0x64 -> return Pair(Triple(instT.OP_RDir, "ld", "acc"), "")
0x65 -> return Pair(Triple(instT.OP_RDir2, "ld", "acc"), "")
0x66 -> return Pair(Triple(instT.OP_RDis, "ld", "acc"), "")
0x67 -> return Pair(Triple(instT.OP_RDis2, "ld", "acc"), "")
0x68 -> return Pair(Triple(instT.OP_RR, "ld", "ix"), "acc")
0x69 -> return Pair(Triple(instT.OP_RR, "ld", "ix"), "ix")
0x6a -> return Pair(Triple(instT.OP_RImm, "ld", "ix"), "")
0x6c -> return Pair(Triple(instT.OP_RDir, "ld", "ix"), "")
0x6d -> return Pair(Triple(instT.OP_RDir2, "ld", "ix"), "")
0x6e -> return Pair(Triple(instT.OP_RDis, "ld", "ix"), "")
0x6f -> return Pair(Triple(instT.OP_RDis2, "ld", "ix"), "")
0x74 -> return Pair(Triple(instT.OP_RDir, "st", "acc"), "")
0x75 -> return Pair(Triple(instT.OP_RDir2, "st", "acc"), "")
0x76 -> return Pair(Triple(instT.OP_RDis, "st", "acc"), "")
0x77 -> return Pair(Triple(instT.OP_RDis2, "st", "acc"), "")
0x7c -> return Pair(Triple(instT.OP_RDir, "st", "ix"), "")
0x7d -> return Pair(Triple(instT.OP_RDir2, "st", "ix"), "")
0x7e -> return Pair(Triple(instT.OP_RDis, "st", "ix"), "")
0x7f -> return Pair(Triple(instT.OP_RDis2, "st", "ix"), "")
0x80 -> return Pair(Triple(instT.OP_RR, "sbc", "acc"), "acc")
0x81 -> return Pair(Triple(instT.OP_RR, "sbc", "acc"), "ix")
0x82 -> return Pair(Triple(instT.OP_RImm, "sbc", "acc"), "")
0x84 -> return Pair(Triple(instT.OP_RDir, "sbc", "acc"), "")
0x85 -> return Pair(Triple(instT.OP_RDir2, "sbc", "acc"), "")
0x86 -> return Pair(Triple(instT.OP_RDis, "sbc", "acc"), "")
0x87 -> return Pair(Triple(instT.OP_RDis2, "sbc", "acc"), "")
0x88 -> return Pair(Triple(instT.OP_RR, "sbc", "ix"), "acc")
0x89 -> return Pair(Triple(instT.OP_RR, "sbc", "ix"), "ix")
0x8a -> return Pair(Triple(instT.OP_RImm, "sbc", "ix"), "")
0x8c -> return Pair(Triple(instT.OP_RDir, "sbc", "ix"), "")
0x8d -> return Pair(Triple(instT.OP_RDir2, "sbc", "ix"), "")
0x8e -> return Pair(Triple(instT.OP_RDis, "sbc", "ix"), "")
0x8f -> return Pair(Triple(instT.OP_RDis2, "sbc", "ix"), "")
0x90 -> return Pair(Triple(instT.OP_RR, "adc", "acc"), "acc")
0x91 -> return Pair(Triple(instT.OP_RR, "adc", "acc"), "ix")
0x92 -> return Pair(Triple(instT.OP_RImm, "adc", "acc"), "")
0x94 -> return Pair(Triple(instT.OP_RDir, "adc", "acc"), "")
0x95 -> return Pair(Triple(instT.OP_RDir2, "adc", "acc"), "")
0x96 -> return Pair(Triple(instT.OP_RDis, "adc", "acc"), "")
0x97 -> return Pair(Triple(instT.OP_RDis2, "adc", "acc"), "")
0x98 -> return Pair(Triple(instT.OP_RR, "adc", "ix"), "acc")
0x99 -> return Pair(Triple(instT.OP_RR, "adc", "ix"), "ix")
0x9a -> return Pair(Triple(instT.OP_RImm, "adc", "ix"), "")
0x9c -> return Pair(Triple(instT.OP_RDir, "adc", "ix"), "")
0x9d -> return Pair(Triple(instT.OP_RDir2, "adc", "ix"), "")
0x9e -> return Pair(Triple(instT.OP_RDis, "adc", "ix"), "")
0x9f -> return Pair(Triple(instT.OP_RDis2, "adc", "ix"), "")
0xa0 -> return Pair(Triple(instT.OP_RR, "sub", "acc"), "acc")
0xa1 -> return Pair(Triple(instT.OP_RR, "sub", "acc"), "ix")
0xa2 -> return Pair(Triple(instT.OP_RImm, "sub", "acc"), "")
0xa4 -> return Pair(Triple(instT.OP_RDir, "sub", "acc"), "")
0xa5 -> return Pair(Triple(instT.OP_RDir2, "sub", "acc"), "")
0xa6 -> return Pair(Triple(instT.OP_RDis, "sub", "acc"), "")
0xa7 -> return Pair(Triple(instT.OP_RDis2, "sub", "acc"), "")
0xa8 -> return Pair(Triple(instT.OP_RR, "sub", "ix"), "acc")
0xa9 -> return Pair(Triple(instT.OP_RR, "sub", "ix"), "ix")
0xaa -> return Pair(Triple(instT.OP_RImm, "sub", "ix"), "")
0xac -> return Pair(Triple(instT.OP_RDir, "sub", "ix"), "")
0xad -> return Pair(Triple(instT.OP_RDir2, "sub", "ix"), "")
0xae -> return Pair(Triple(instT.OP_RDis, "sub", "ix"), "")
0xaf -> return Pair(Triple(instT.OP_RDis2, "sub", "ix"), "")
0xb0 -> return Pair(Triple(instT.OP_RR, "add", "acc"), "acc")
0xb1 -> return Pair(Triple(instT.OP_RR, "add", "acc"), "ix")
0xb2 -> return Pair(Triple(instT.OP_RImm, "add", "acc"), "")
0xb4 -> return Pair(Triple(instT.OP_RDir, "add", "acc"), "")
0xb5 -> return Pair(Triple(instT.OP_RDir2, "add", "acc"), "")
0xb6 -> return Pair(Triple(instT.OP_RDis, "add", "acc"), "")
0xb7 -> return Pair(Triple(instT.OP_RDis2, "add", "acc"), "")
0xb8 -> return Pair(Triple(instT.OP_RR, "add", "ix"), "acc")
0xb9 -> return Pair(Triple(instT.OP_RR, "add", "ix"), "ix")
0xba -> return Pair(Triple(instT.OP_RImm, "add", "ix"), "")
0xbc -> return Pair(Triple(instT.OP_RDir, "add", "ix"), "")
0xbd -> return Pair(Triple(instT.OP_RDir2, "add", "ix"), "")
0xbe -> return Pair(Triple(instT.OP_RDis, "add", "ix"), "")
0xbf -> return Pair(Triple(instT.OP_RDis2, "add", "ix"), "")
0xc0 -> return Pair(Triple(instT.OP_RR, "eor", "acc"), "acc")
0xc1 -> return Pair(Triple(instT.OP_RR, "eor", "acc"), "ix")
0xc2 -> return Pair(Triple(instT.OP_RImm, "eor", "acc"), "")
0xc4 -> return Pair(Triple(instT.OP_RDir, "eor", "acc"), "")
0xc5 -> return Pair(Triple(instT.OP_RDir2, "eor", "acc"), "")
0xc6 -> return Pair(Triple(instT.OP_RDis, "eor", "acc"), "")
0xc7 -> return Pair(Triple(instT.OP_RDis2, "eor", "acc"), "")
0xc8 -> return Pair(Triple(instT.OP_RR, "eor", "ix"), "acc")
0xc9 -> return Pair(Triple(instT.OP_RR, "eor", "ix"), "ix")
0xca -> return Pair(Triple(instT.OP_RImm, "eor", "ix"), "")
0xcc -> return Pair(Triple(instT.OP_RDir, "eor", "ix"), "")
0xcd -> return Pair(Triple(instT.OP_RDir2, "eor", "ix"), "")
0xce -> return Pair(Triple(instT.OP_RDis, "eor", "ix"), "")
0xcf -> return Pair(Triple(instT.OP_RDis2, "eor", "ix"), "")
0xd0 -> return Pair(Triple(instT.OP_RR, "or", "acc"), "acc")
0xd1 -> return Pair(Triple(instT.OP_RR, "or", "acc"), "ix")
0xd2 -> return Pair(Triple(instT.OP_RImm, "or", "acc"), "")
0xd4 -> return Pair(Triple(instT.OP_RDir, "or", "acc"), "")
0xd5 -> return Pair(Triple(instT.OP_RDir2, "or", "acc"), "")
0xd6 -> return Pair(Triple(instT.OP_RDis, "or", "acc"), "")
0xd7 -> return Pair(Triple(instT.OP_RDis2, "or", "acc"), "")