From 0c95051b617be8fd242e317c442a1881d5f28034 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 5 Aug 2024 11:59:52 +0800 Subject: [PATCH 1/4] [RISCV] Support `svukte` extension This is the extension for "Address-Independent Latency of User-Mode Faults to Supervisor Addresses". Spec: https://github.com/riscv/riscv-isa-manual/pull/1564 The spec states that the `svukte` depends on `sv39`, but we don't have `sv39` yet, so I didn't add it to the implied list. --- clang/test/Driver/print-supported-extensions-riscv.c | 1 + clang/test/Preprocessor/riscv-target-features.c | 8 ++++++++ llvm/lib/Target/RISCV/RISCVFeatures.td | 4 ++++ llvm/test/CodeGen/RISCV/attributes.ll | 4 ++++ llvm/test/MC/RISCV/attribute-arch.s | 3 +++ llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 + 6 files changed, 21 insertions(+) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 774dc3a4e1e756..151e4701a1da84 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -187,6 +187,7 @@ // CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography) // CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level) // CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level) +// CHECK-NEXT: svukte 0.3 'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses) // CHECK-EMPTY: // CHECK-NEXT: Supported Profiles // CHECK-NEXT: rva20s64 diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 7e8d1fa2448b80..f1ec6d5734f251 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1811,6 +1811,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-SSCTR-EXT %s // CHECK-SSCTR-EXT: __riscv_ssctr 1000000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_svukte0p3 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_svukte0p3 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SVUKTE-EXT %s +// CHECK-SVUKTE-EXT: __riscv_svukte 3000{{$}} + // Misaligned // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \ diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index ad733e1488b5ca..d0d9aa64af4e20 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1056,6 +1056,10 @@ def FeatureStdExtSha FeatureStdExtShvstvala, FeatureStdExtShtvala, FeatureStdExtShvstvecd, FeatureStdExtShvsatpa, FeatureStdExtShgatpa]>; +def FeatureStdExtSvukte + : RISCVExperimentalExtension<"svukte", 0, 3, + "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)">; + // Pointer Masking extensions // A supervisor-level extension that provides pointer masking for the next lower diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 7624071f4f93ec..35c8cc94f40902 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -62,6 +62,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV32SVBARE %s ; RUN: llc -mtriple=riscv32 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV32SVNAPOT %s ; RUN: llc -mtriple=riscv32 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV32SVPBMT %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV32SVUKTE %s ; RUN: llc -mtriple=riscv32 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV32SVVPTC %s ; RUN: llc -mtriple=riscv32 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV32SVINVAL %s ; RUN: llc -mtriple=riscv32 -mattr=+xcvalu %s -o - | FileCheck --check-prefix=RV32XCVALU %s @@ -205,6 +206,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+svbare %s -o - | FileCheck --check-prefixes=CHECK,RV64SVBARE %s ; RUN: llc -mtriple=riscv64 -mattr=+svnapot %s -o - | FileCheck --check-prefixes=CHECK,RV64SVNAPOT %s ; RUN: llc -mtriple=riscv64 -mattr=+svpbmt %s -o - | FileCheck --check-prefixes=CHECK,RV64SVPBMT %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-svukte %s -o - | FileCheck --check-prefixes=CHECK,RV64SVUKTE %s ; RUN: llc -mtriple=riscv64 -mattr=+svvptc %s -o - | FileCheck --check-prefixes=CHECK,RV64SVVPTC %s ; RUN: llc -mtriple=riscv64 -mattr=+svinval %s -o - | FileCheck --check-prefixes=CHECK,RV64SVINVAL %s ; RUN: llc -mtriple=riscv64 -mattr=+xventanacondops %s -o - | FileCheck --check-prefixes=CHECK,RV64XVENTANACONDOPS %s @@ -364,6 +366,7 @@ ; RV32SVBARE: .attribute 5, "rv32i2p1_svbare1p0" ; RV32SVNAPOT: .attribute 5, "rv32i2p1_svnapot1p0" ; RV32SVPBMT: .attribute 5, "rv32i2p1_svpbmt1p0" +; RV32SVUKTE: .attribute 5, "rv32i2p1_svukte0p3" ; RV32SVVPTC: .attribute 5, "rv32i2p1_svvptc1p0" ; RV32SVINVAL: .attribute 5, "rv32i2p1_svinval1p0" ; RV32XCVALU: .attribute 5, "rv32i2p1_xcvalu1p0" @@ -509,6 +512,7 @@ ; RV64SVBARE: .attribute 5, "rv64i2p1_svbare1p0" ; RV64SVNAPOT: .attribute 5, "rv64i2p1_svnapot1p0" ; RV64SVPBMT: .attribute 5, "rv64i2p1_svpbmt1p0" +; RV64SVUKTE: .attribute 5, "rv64i2p1_svukte0p3" ; RV64SVVPTC: .attribute 5, "rv64i2p1_svvptc1p0" ; RV64SVINVAL: .attribute 5, "rv64i2p1_svinval1p0" ; RV64XVENTANACONDOPS: .attribute 5, "rv64i2p1_xventanacondops1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 72a1db865e025d..f5b5a9ad3cab58 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -381,6 +381,9 @@ .attribute arch, "rv32i_svbare1p0" # CHECK: attribute 5, "rv32i2p1_svbare1p0" +.attribute arch, "rv32i_svukte0p3" +# CHECK: attribute 5, "rv32i2p1_svukte0p3" + .attribute arch, "rv32i_svvptc1p0" # CHECK: attribute 5, "rv32i2p1_svvptc1p0" diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 09c0f4159cc7ee..62e094ce296c09 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1094,6 +1094,7 @@ Experimental extensions zvkgs 0.7 smctr 1.0 ssctr 1.0 + svukte 0.3 Supported Profiles rva20s64 From 86ba0796b8bbac94e4bb071fc72c82c2e99b3a1d Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 18 Nov 2024 23:04:48 -0800 Subject: [PATCH 2/4] fixup! [RISCV] Support `svukte` extension --- llvm/docs/RISCVUsage.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 1317221448ea5b..3c9f4d08e9bd5a 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -158,6 +158,7 @@ on support follow. ``Svinval`` Assembly Support ``Svnapot`` Assembly Support ``Svpbmt`` Supported + ``Svukte`` Supported ``Svvptc`` Supported ``V`` Supported ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) From 4d7ab7fb8110313c29d7a34c34acba5f567cf418 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 18 Nov 2024 23:32:05 -0800 Subject: [PATCH 3/4] fixup! [RISCV] Support `svukte` extension --- llvm/docs/RISCVUsage.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 3c9f4d08e9bd5a..80d335ff77ed81 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -158,7 +158,6 @@ on support follow. ``Svinval`` Assembly Support ``Svnapot`` Assembly Support ``Svpbmt`` Supported - ``Svukte`` Supported ``Svvptc`` Supported ``V`` Supported ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) @@ -330,6 +329,9 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smctr``, ``experimental-ssctr`` LLVM implements the `1.0-rc3 specification `__. +``experimental-svukte``, ``experimental-svukte`` + LLVM implements the `0.3 draft specification `__. + To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`. Vendor Extensions From 3cb5bb2fc8013999c95c5400dd042a336a8edc89 Mon Sep 17 00:00:00 2001 From: Brandon Wu Date: Mon, 25 Nov 2024 18:08:30 -0800 Subject: [PATCH 4/4] fixup! [RISCV] Support `svukte` extension --- llvm/docs/RISCVUsage.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index 80d335ff77ed81..bac267591e0152 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -329,7 +329,7 @@ The primary goal of experimental support is to assist in the process of ratifica ``experimental-smctr``, ``experimental-ssctr`` LLVM implements the `1.0-rc3 specification `__. -``experimental-svukte``, ``experimental-svukte`` +``experimental-svukte`` LLVM implements the `0.3 draft specification `__. To use an experimental extension from `clang`, you must add `-menable-experimental-extensions` to the command line, and specify the exact version of the experimental extension you are using. To use an experimental extension with LLVM's internal developer tools (e.g. `llc`, `llvm-objdump`, `llvm-mc`), you must prefix the extension name with `experimental-`. Note that you don't need to specify the version with internal tools, and shouldn't include the `experimental-` prefix with `clang`.