From e86ec029fd844cf2f17a40872c9ca5a0f5335b83 Mon Sep 17 00:00:00 2001 From: Lucas Russo Date: Fri, 7 Aug 2020 13:38:16 -0300 Subject: [PATCH] modules/position_calc: fix abs () interpretation when not using down-conversion This fixes #82 github issue. --- hdl/modules/position_calc/position_calc.vhd | 23 +++++---------------- 1 file changed, 5 insertions(+), 18 deletions(-) diff --git a/hdl/modules/position_calc/position_calc.vhd b/hdl/modules/position_calc/position_calc.vhd index 4a8c77d1..0f65ffb8 100644 --- a/hdl/modules/position_calc/position_calc.vhd +++ b/hdl/modules/position_calc/position_calc.vhd @@ -351,16 +351,13 @@ architecture rtl of position_calc is ----------- type t_input is array(3 downto 0) of std_logic_vector(g_input_width-1 downto 0); signal adc_input : t_input := (others => (others => '0')); - signal adc_input_abs : t_input := (others => (others => '0')); type t_input_valid is array(3 downto 0) of std_logic; signal adc_input_valid : t_input_valid := (others => '0'); - signal adc_input_abs_valid : t_input_valid := (others => '0'); signal iq_valid : t_input_valid := (others => '0'); type t_input_tag is array(3 downto 0) of std_logic_vector(c_adc_tag_width-1 downto 0); signal adc_input_tag : t_input_tag := (others => (others => '0')); - signal adc_input_abs_tag : t_input_tag := (others => (others => '0')); type t_input_tag_en is array(3 downto 0) of std_logic; signal input_tag_en : t_input_tag_en := (others => '0'); @@ -644,16 +641,6 @@ begin gen_without_downconv : if (not g_with_downconv) generate - -- With no down-conversion (no CORDIC for coordinate conversion) - -- we might have negative amplitudes and mis-representation will occur. - -- - -- To fix that, we must take either the absolute value of output of the - -- filters or take the absolute value before the first filter. Here we - -- have opted for the primer. - adc_input_abs(chan) <= std_logic_vector(abs(signed(adc_input(chan)))); - adc_input_abs_valid(chan) <= adc_input_valid(chan); - adc_input_abs_tag(chan) <= adc_input_tag(chan); - cmp_tbt_cic : cic_dyn generic map ( g_input_width => g_input_width, @@ -675,8 +662,8 @@ begin -- rate, so we don't have to -- change them downstream ce_out_i => ce_tbt_cordic(chan), - valid_i => adc_input_abs_valid(chan), - data_i => adc_input_abs(chan), + valid_i => adc_input_valid(chan), + data_i => adc_input(chan), ratio_i => c_tbt_ratio_slv, data_tag_i => tbt_tag_i, data_tag_en_i => tbt_tag_en_i, @@ -711,9 +698,9 @@ begin rst_i => rst_i, ce_i => ce_adc(chan), ce_out_i => ce_fofb_cordic(chan), - valid_i => adc_input_abs_valid(chan), - data_i => adc_input_abs(chan), - data_tag_i => adc_input_abs_tag(chan), + valid_i => adc_input_valid(chan), + data_i => adc_input(chan), + data_tag_i => adc_input_tag(chan), -- Don't use CIC synchronization feature data_tag_en_i => '0', data_mask_num_samples_beg_i => (others => '0'),