Make ADC acquisitions / DAC actuation synchronized with the RF reference clock

[augustofg]

The current implementation of the power-supply current controller loop is not synchronised with anything, it will start a new ADC conversion immediately after the previous finished:

rtm-lamp-gw/hdl/modules/rtmlamp_ohwr/rtmlamp_ohwr.vhd

Lines 499 to 512 in e144d66

	----------------------------------------
	-- ADC start when both are ready
	----------------------------------------
	p_gen_adc_start_valid: process (clk_i)
	begin
	if rising_edge (clk_i) then
	if rst_n_i = '0' then
	adc_start <= '0';
	else
	adc_start <= adc_ready; -- FIXME: ADC conversions should start after
	-- a integer number of clk_ref_i edges
	end if;
	end if;
	end process;

Fixing this will require a major refactoring in rtmlamp_ohwr.vhd. The necessary steps to conclude this refactoring are the following:

• Implement a configurable strobe generator that counts in RF/4 cycles;
• Implement a CNV/LDAC pulse generator in a single core and use the readout (ADC) and writeout (DAC) interfaces directly;
• Implement the state machines for waiting the strobe / generating the CNV/LDAC pulse, wait for the ADC and read the conversion result, write the DAC data;
• Remove all CDC FIFOs and use gc_sync_word_rd / gc_sync_word_wr instead as we don't need to transfer data at consecutive clock cycles;
• Implement current loop stuck detection and automatic disabling of the power amplifiers outputs;
• Expose status flags via wishbone to indicate current loop stuck and strobe pulse lost conditions.