[rstmgr] D2(S) Signoff

[msfschaffner]

Description

Ensure D2(S) signoff criteria are still maintained (this is not a focus area block).

[matutem]

Commits since Earlgrey-ES tapeout

git log Earlgrey-M2.5.2-RC0.. --oneline -- hw/ip/rstmgr/ hw/ip_templates/rstmgr

• 15cd8d3 [ipgen,rstmgr] Remove hw/ip/rstmgr and old autogen files
  • no impact: transition to ipgen
• 0750df2 [ipgen,rstmgr] Fix core files
  • no impact: transition to ipgen
• b16179d [ipgen,rstmgr] Fix BUILD files
  • no impact: transition to ipgen
• f3227f1 [ipgen,rstmgr] Change templates to use plain dictionaries
  • no impact: transition to ipgen
• f9d8ed1 [ipgen,rstmgr] Turn a few more files into templates and fix paths
  • no impact: transition to ipgen
• f58a9a1 [ipgen,rstmgr] Remove files that are generated
  • no impact: transition to ipgen
• f99c77f [ipgen,rstmgr] Move some template files to their intended destination
  • no impact: transition to ipgen
• a23c70b [ipgen,rstmgr] Copy all hw/ip/rstmgr files to ip_templates
  • no impact: transition to ipgen
• 275cf14 [ipgen,rstmgr] Add tpldesc hjson file
  • no impact: transition to ipgen
• 27309c6 [topgen,rstmgr] Remove useless reset_obj generation variable
  • no impact: transition to ipgen
• 61a237e [util/reggen] reverse order of substruct generation
  • no RTL impact, and DV impact is transparent to the code
• ce648ca [ipgen.pwrmgr] Change core files to vlnv naming and label as virtual
  • no impact: core file enhancement to avoid multi-top issues
• de31bdf [reggen] Remove the devmode input
  • no impact: devmode_i was set to constant 1'b1 and changes are transparent
• 0c759b9 [dv,rstmgr] Fix lint warning in constraint
  • no impact: fixes lint waning with a simple rename
• af22161 [sival,chip_testplans] Handle alert_handler enables tests
  • no impact: it corrects a mistake in the testplan
• 3f88a55 [pwrmgr,ipgen] Generate pwrmgr ip_autogen files with topgen
  • no impact: it only changes some links to pwrmgr in documentation
• 1ecc9b9 [rstmgr,pwrmgr] Replace tabs with spaces in plans
  • no impact: trivial formatting change in testplans
• 1f7c806 [sival,rstmgr] Add features in rstmgr.hjson.tpl
  • no impact: adds features in hjson file for sival tracking
• 1b16ca2 [reggen] Add mubi support SWAccess that sets/clears a reg
  • has RTL and DV impact: it needs improved testing
• 59f8142 [doc] Moved badges over to using hosted images
  • no impact: documentation-only change
• 324a77e [doc] rstmgr registers and interfaces now use CMDGEN
  • no impact: documentation-only change
• 0e6148c [dv/rstmgr] Add SVA checking rst_en_o track resets_o
  • positive impact: adds SVA to check resets and rst_en (for alert handler) are in sync, fixing outstanding issue
• 9d1f184 [dv/rstmgr] Fix leaf_rst_cnsty test
  • no impact: fixes a test flakiness due to issuing transactions that violate the alert protocol
• 7688e71 [reggen] Add initial support for version and cip_id hjson fields
  • no impact: adds version and cip_id in hjson metadata
• fbd888e Revert "[reggen] Add CIP_IDs and bump all major versions"
  • no impact: reverts PR below
• 0ba10b3 [reggen] Add CIP_IDs and bump all major versions
  • no impact: this PR was reverted

Issues closed since the Earlgrey-ES tapeout

• [ip,doc] Fix inaccurate references to reset behavior #20700
  • Documentation-only
• [top_darjeeling] watch dog reset should be mapped to bit 0 #20415
  • Darjeeling only
• [chip-test] chip_sw_rv_core_ibex_double_fault #20030
  • Fixes test
• [chip-test] chip_sw_rv_core_ibex_fault_dump #20029
  • Fixes test
• [top_englishbreakfast,util] Fix paths to ip-specific ips in prepare_sw.py #19819
  • Issue was mistakenly filed
• [prim_sync_reqack] Check usage of EnRzHs parameter to make EDN interfaces partial-reset safe #19259
  • Closed since the issue was not relevant
• [top-level,test,cdc] Fix CDC failure for chip_sw_power_idle_load #19256
  • DV failure was fixed
• [rtl] Are design guidlines for use of prim_lc_sync correct? #19044
  • Closed after checking this was not a problem
• [dv/rstmgr] Add SVA expecting rst_en_o to track resets_o #16641
  • There was a fix for this issue
• Flow error that dc is unsupported for job runtime extraction #16562
  • Was not a real issue
• [rtl/rstmgr] Fix consistency checker #16384
  • Needs some feedback to really sort out the issue
• [ibex] Shadow reset for shadow core #8538
  • Closed after analysis

Currently open issues

• [sival,sensor_ctrl] Fix unexpected alert 5 #20798
  • This is an AST issue, and it is expected to be fixed for PROD. It refers to rstmgr since the issue causes a failure in a top-level test associated to rstmgr.
• [test-triage] Fix rstmgr_alert_info_test_fpga_cw310_sival #20589
  • This issue relates to a test failure that has been diagnosed and it relates to a test environment problem, not an actual device defect.
• [sival] prod_all_tests #20194
  • This is a tracking issue for multiple blocks, and shows no open issues for rstmgr.
• [rstmgr] D2(S) Signoff #20991 (comment)
  • Another tracking issue that shows no open items for rstmgr.
• [rstmgr] Make rstmgr DV top-level agnostic #19538
  • This is a multi-top issue that is not required for PROD.
• [dv/csr_utils] Fix handling of reset for rstmgr alert_info_ctrl #18258
  • This is a dv infrastructure issue, and does not suggest a functional problem. I think the issue is obsolete anyway.
• [usbdev] FIFO state inaccessible to software #17300
  • This issue is open, but the use-case is unclear, and may not require hardware changes. It is mostly a USB issue, and refers to rstmgr only as a way to reset the USB block.
• [lint,top_earlgrey] Unused variable Verilator lint error in aon_osc.sv #16846
  • This is an AST issue related to lint checkers, and most likely should be closed.
• [clkmgr] Template exclusions  #16640
  • This is a clkmgr issue, and it only relates to improving the coverage flow.
• [dv/rstmgr] Apply different reset kinds where applicable #16148
  • This is an enhancement request for block level, but the full-chip tests exercise the functionality and show no defects.
• [rtl,reset] Improve handling of main domain power glitches #15986
  • I doubt we should fix this for PROD, so I think it is not a relevant issue.
• [chip, dv, cov] Address low coverage of alert_dump and crashdump signals #15427
  • This issue needs to be discussed and we need to agree if anything is needed.
• [rv_dm,rtl] Fix acknowledgment of reset in dmstatus.allhavereset/dmstatus.anyhavereset #15123
  • This seems to be a low priority issue, but needs resolution.
• [dv,rstmgr] Generate list of rstmgr_leaf_rst instances #13640
  • This is a non-indispensable enhancement.
• [top/doc] Autogenerated tables for top-specific IP #12848
  • This issue needs a better description, and it is documentation-only.
• [dv/exclusions] Change handling of full-chip exclusions #11520
  • This is a non-indispensable enhancement.
• [rtl/rstmgr] Make cpu and alert info layout known to sw #8945
  • This is a non-indispensable enhancement.
• [tracking] Use ipgen to produce templated IPs #8440
  • The rstmgr work in this issue was already completed.
• [reggen] Add support for compact regwen_multi type #8185
  • This is not required for PROD, and perhaps we can just close the issue?
• [ast] Make ast a comportable module or at least a comportable front-end #7978
  • This won't be addressed for PROD, and perhaps the issue can be closed.
• [rstmgr] module reset detection improvements #7780.
  • This should not be done for PROD, and may be addressed for multi-top, though IMO it is low priority
• [sw] polling in ROM #6220
  • This issue is open, and needs software feedback. Not necessarily a rstmgr issue though.
• [fpga] Invalid input clock frequency for BUFGMUX #3637
  • This is an fpga issue.
• [topgen] Remove duplicated license headers from autogen files #2929
  • This is not an issue for rstmgr since it is generated by ipgen. The issue for clkmgr and flash_ctrl will also be gone once ipgen is completed for them.

Summary

• The RTL change in eb412d1 (1b16ca2) is important and fixes an issue relevant to D2S, but it needs some DV enhancement to the CIP CSR tests.
• The issue [rtl/rstmgr] Fix consistency checker #16384 needs a more complete analysis.

For D2S, only the latter issue needs to be sorted out.

[msfschaffner]

Thanks for putting this together, @matutem.

Agreed that the RTL change for MUBI CSRs could use a dedicated CIP CSR test.
The RTL side of it should be done however.

Given the priorities and recommendation for #16384, I do not think that we will be able to enhance this for Earlgrey PROD.
My suggestion would therefore be to leave the design as it is today and sign it off for D2S.