From f96e9c2fd6c96270cf3cffaffd599e9a956f980b Mon Sep 17 00:00:00 2001 From: Matt Keeter Date: Sun, 19 May 2024 15:17:55 -0400 Subject: [PATCH] Add input register shuffling to test calling convention --- fidget/src/jit/aarch64/float_slice.rs | 4 ++++ fidget/src/jit/aarch64/grad_slice.rs | 4 ++++ fidget/src/jit/aarch64/interval.rs | 4 ++++ fidget/src/jit/aarch64/point.rs | 4 ++++ fidget/src/jit/mod.rs | 21 +++++++++++++++++++++ fidget/src/jit/x86_64/float_slice.rs | 4 ++++ fidget/src/jit/x86_64/grad_slice.rs | 4 ++++ fidget/src/jit/x86_64/interval.rs | 4 ++++ fidget/src/jit/x86_64/point.rs | 4 ++++ 9 files changed, 53 insertions(+) diff --git a/fidget/src/jit/aarch64/float_slice.rs b/fidget/src/jit/aarch64/float_slice.rs index c7bb3121..d7918589 100644 --- a/fidget/src/jit/aarch64/float_slice.rs +++ b/fidget/src/jit/aarch64/float_slice.rs @@ -88,6 +88,10 @@ impl Assembler for FloatSliceAssembler { fn init(mmap: Mmap, slot_count: usize) -> Self { let mut out = AssemblerData::new(mmap); out.prepare_stack(slot_count, STACK_SIZE as usize); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops // Preserve frame and link register, and set up the frame pointer ; stp x29, x30, [sp, 0x0] diff --git a/fidget/src/jit/aarch64/grad_slice.rs b/fidget/src/jit/aarch64/grad_slice.rs index 2a53db33..286dc85f 100644 --- a/fidget/src/jit/aarch64/grad_slice.rs +++ b/fidget/src/jit/aarch64/grad_slice.rs @@ -92,6 +92,10 @@ impl Assembler for GradSliceAssembler { fn init(mmap: Mmap, slot_count: usize) -> Self { let mut out = AssemblerData::new(mmap); out.prepare_stack(slot_count, STACK_SIZE as usize); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops // Preserve frame and link register, and set up the frame pointer ; stp x29, x30, [sp, 0x0] diff --git a/fidget/src/jit/aarch64/interval.rs b/fidget/src/jit/aarch64/interval.rs index a19179c0..90d5e116 100644 --- a/fidget/src/jit/aarch64/interval.rs +++ b/fidget/src/jit/aarch64/interval.rs @@ -87,6 +87,10 @@ impl Assembler for IntervalAssembler { fn init(mmap: Mmap, slot_count: usize) -> Self { let mut out = AssemblerData::new(mmap); out.prepare_stack(slot_count, STACK_SIZE as usize); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops // Preserve frame and link register, and set up the frame pointer ; stp x29, x30, [sp, 0x0] diff --git a/fidget/src/jit/aarch64/point.rs b/fidget/src/jit/aarch64/point.rs index dc6942a4..764a6f46 100644 --- a/fidget/src/jit/aarch64/point.rs +++ b/fidget/src/jit/aarch64/point.rs @@ -81,6 +81,10 @@ impl Assembler for PointAssembler { fn init(mmap: Mmap, slot_count: usize) -> Self { let mut out = AssemblerData::new(mmap); out.prepare_stack(slot_count, STACK_SIZE as usize); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops // Preserve frame and link register, and set up the frame pointer ; stp x29, x30, [sp, 0x0] diff --git a/fidget/src/jit/mod.rs b/fidget/src/jit/mod.rs index c183b730..e14e8440 100644 --- a/fidget/src/jit/mod.rs +++ b/fidget/src/jit/mod.rs @@ -322,6 +322,27 @@ impl AssemblerData { self.push_stack(); } + #[cfg(all(target_arch = "aarch64", test))] + fn input_register_shenanigans(&mut self) { + dynasm!(self.ops + ; mov x3, 0xABCD + ; lsl x4, x3, 16 + ; orr x3, x3, x4 + ); + } + + #[cfg(all(target_arch = "x86_64", test))] + fn input_register_shenanigans(&mut self) { + dynasm!(self.ops + ; mov rcx, 0xABCDABCDu32 as i32 + ; mov r8, 0xABCDABCDu32 as i32 + ; mov r9, 0xABCDABCDu32 as i32 + ); + for i in 4..=7 { + dynasm!(self.ops ; mov X(i), x3); + } + } + #[cfg(target_arch = "aarch64")] fn push_stack(&mut self) { assert!(self.mem_offset < 4096); diff --git a/fidget/src/jit/x86_64/float_slice.rs b/fidget/src/jit/x86_64/float_slice.rs index db7c59e8..95d99b35 100644 --- a/fidget/src/jit/x86_64/float_slice.rs +++ b/fidget/src/jit/x86_64/float_slice.rs @@ -66,6 +66,10 @@ impl Assembler for FloatSliceAssembler { ; mov rbp, rsp ); out.prepare_stack(slot_count, STACK_SIZE_UPPER + STACK_SIZE_LOWER); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops // TODO should there be a `vzeroupper` in here? diff --git a/fidget/src/jit/x86_64/grad_slice.rs b/fidget/src/jit/x86_64/grad_slice.rs index a33b09c8..6bae6b0b 100644 --- a/fidget/src/jit/x86_64/grad_slice.rs +++ b/fidget/src/jit/x86_64/grad_slice.rs @@ -60,6 +60,10 @@ impl Assembler for GradSliceAssembler { ; mov rbp, rsp ); out.prepare_stack(slot_count, STACK_SIZE_UPPER + STACK_SIZE_LOWER); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops ; xor rcx, rcx // set the array offset (rcx) to 0 diff --git a/fidget/src/jit/x86_64/interval.rs b/fidget/src/jit/x86_64/interval.rs index 2a242f23..82f6a881 100644 --- a/fidget/src/jit/x86_64/interval.rs +++ b/fidget/src/jit/x86_64/interval.rs @@ -58,6 +58,10 @@ impl Assembler for IntervalAssembler { ; mov rbp, rsp ); out.prepare_stack(slot_count, STACK_SIZE_UPPER + STACK_SIZE_LOWER); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops ; vzeroupper ); diff --git a/fidget/src/jit/x86_64/point.rs b/fidget/src/jit/x86_64/point.rs index 21140cf8..8adf1de7 100644 --- a/fidget/src/jit/x86_64/point.rs +++ b/fidget/src/jit/x86_64/point.rs @@ -57,6 +57,10 @@ impl Assembler for PointAssembler { ; mov rbp, rsp ); out.prepare_stack(slot_count, STACK_SIZE_UPPER + STACK_SIZE_LOWER); + + #[cfg(test)] + out.input_register_shenanigans(); + dynasm!(out.ops ; vzeroupper );