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models.smv
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MODULE UART (proc, proc2UARTvalue, proc2UARTAddress, uart2CPU, uart2mem, uart2memValue)
VAR
Rx : unsigned word [ 8 ]; -- receive from outside
Tx : array 0 .. 7 of unsigned word [ 8 ]; --array of bytes
ASSIGN
next (Tx[0]) :=
case
proc = write2UART & proc2UARTAddress = 0 : proc2UARTvalue;
TRUE : (Tx[0]);
esac;
next (Tx[1]) :=
case
proc = write2UART & proc2UARTAddress = 1 : proc2UARTvalue;
TRUE : (Tx[1]);
esac;
next (Tx[2]) :=
case proc = write2UART & proc2UARTAddress = 2 : proc2UARTvalue;
TRUE : (Tx[2]);
esac;
next (Tx[3]) :=
case
proc = write2UART & proc2UARTAddress = 3 : proc2UARTvalue;
TRUE : (Tx[3]);
esac;
next (Tx[4]) :=
case
proc = write2UART & proc2UARTAddress = 4 : proc2UARTvalue;
TRUE : (Tx[4]);
esac;
next (Tx[5]) :=
case
proc = write2UART & proc2UARTAddress = 5 : proc2UARTvalue;
TRUE : (Tx[5]);
esac;
next (Tx[6]) :=
case
proc = write2UART & proc2UARTAddress = 6 : proc2UARTvalue;
TRUE : (Tx[6]);
esac;
next (Tx[7]) :=
case
proc = write2UART & proc2UARTAddress = 7 : proc2UARTvalue;
TRUE : (Tx[7]);
esac;
next (uart2CPU) :=
case
proc = read2UART : Rx;
TRUE : Rx;
esac;
MODULE MEM (proc, proc2memValue, proc2memAddress, mem2proc, uart2memValue, DMAadress)
VAR
data : array 0 .. 7 of unsigned word [ 8 ];
ASSIGN
next (mem2proc) :=
case
proc = read & proc2memAddress = 0 : data[0];
proc = read & proc2memAddress = 1 : data[1];
proc = read & proc2memAddress = 2 : data[2];
proc = read & proc2memAddress = 3 : data[3];
proc = read & proc2memAddress = 4 : data[4];
proc = read & proc2memAddress = 5 : data[5];
proc = read & proc2memAddress = 6 : data[6];
proc = read & proc2memAddress = 7 : data[7];
TRUE : mem2proc;
esac;
next (data[0]) :=
case
proc = write & proc2memAddress = 0 : proc2memValue;
DMAadress = 0 : uart2memValue;
TRUE : data[0];
esac;
next (data[1]) :=
case
proc = write & proc2memAddress = 1 : proc2memValue;
DMAadress = 1 : uart2memValue;
TRUE : data[1];
esac;
next (data[2]) :=
case
proc = write & proc2memAddress = 2 : proc2memValue;
TRUE : data[2];
esac;
next (data[3]) :=
case
proc = write & proc2memAddress = 3 : proc2memValue;
TRUE : data[3];
esac;
next (data[4]) :=
case
proc = write & proc2memAddress = 4 : proc2memValue;
TRUE : data[4];
esac;
next (data[5]) :=
case
proc = write & proc2memAddress = 4 : proc2memValue;
TRUE : data[5];
esac;
next (data[6]) :=
case
proc = write & proc2memAddress = 4 : proc2memValue;
TRUE : data[6];
esac;
next (data[7]) :=
case
proc = write & proc2memAddress = 4 : proc2memValue;
TRUE : data[7];
esac;
MODULE DMA (proc, DMAmemAddress)
VAR
address : 0..7;
control : unsigned word [ 8 ];
ASSIGN
init(control) := 0ud8_31;
next (address) :=
case
proc = setDMAaddress : DMAmemAddress;
TRUE : address;
esac;
MODULE main
VAR
proc : {idle, read, write, read2UART, write2UART, setDMAaddress};
mem2proc : unsigned word [ 8 ];
proc2memValue : unsigned word [ 8 ];
proc2memAddress : 0 .. 7;
DMAmemAddress : 0 .. 7;
uart2CPU : unsigned word [ 8 ];
uart2mem : unsigned word [ 8 ];
proc2UARTvalue : unsigned word [ 8 ];
proc2UARTAddress : 0 .. 7;
uart2memValue : unsigned word [ 8 ]; -- external
memory : MEM (proc, proc2memValue, proc2memAddress, mem2proc, uart2mem, DMAmemAddress);
uart0 : UART (proc, proc2UARTvalue, proc2UARTAddress, uart2CPU, uart2mem, uart2memValue);
dma : DMA (proc, DMAmemAddress);
ASSIGN
LTLSPEC G (proc = write2UART & proc2UARTAddress = 0) -> F ( next(uart0.Tx[0]) = proc2UARTvalue )
LTLSPEC G (proc != write & proc2memAddress != 1 & DMAmemAddress != 1) -> G (memory.data[1] = next(memory.data[1]))
LTLSPEC G (proc = setDMAaddress & DMAmemAddress != 1 & proc2memAddress = 1) -> G (memory.data[1] = next
(memory.data[1]))