From 5bac92f2c7b2b9d14429141b8a6a2cec513131d0 Mon Sep 17 00:00:00 2001
From: Andreas Kurth <adk@lowrisc.org>
Date: Wed, 28 Sep 2022 08:48:05 +0000
Subject: [PATCH] dm_mem: Clear state of hart upon ndmreset

As described in #118, the debug module currently considers a hart that
is being reset with `ndmreset` to be halted.  However, after a reset,
the hart is no longer halted.

This commit feeds `ndmreset` into `dm_mem`, where it clears the state of
the hart and sets it to neither halted nor resuming.

Signed-off-by: Andreas Kurth <adk@lowrisc.org>
---
 src/dm_mem.sv | 14 ++++++++++++++
 src/dm_top.sv |  5 ++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/dm_mem.sv b/src/dm_mem.sv
index 22ceabe..c1cc0e8 100755
--- a/src/dm_mem.sv
+++ b/src/dm_mem.sv
@@ -26,6 +26,7 @@ module dm_mem #(
   input  logic                             rst_ni,      // debug module reset
 
   output logic [NrHarts-1:0]               debug_req_o,
+  input  logic                             ndmreset_i,
   input  logic [19:0]                      hartsel_i,
   // from Ctrl and Status register
   input  logic [NrHarts-1:0]               haltreq_i,
@@ -201,6 +202,13 @@ module dm_mem #(
       cmderror_valid_o = 1'b1;
       cmderror_o = dm::CmdErrorException;
     end
+
+    if (ndmreset_i) begin
+      // Clear state of hart and its control signals when it is being reset.
+      state_d = Idle;
+      go      = 1'b0;
+      resume  = 1'b0;
+    end
   end
 
   // word mux for 32bit and 64bit buses
@@ -332,6 +340,12 @@ module dm_mem #(
       end
     end
 
+    if (ndmreset_i) begin
+      // When harts are reset, they are neither halted nor resuming.
+      halted_d_aligned   = '0;
+      resuming_d_aligned = '0;
+    end
+
     data_o = data_bits;
   end
 
diff --git a/src/dm_top.sv b/src/dm_top.sv
index 3c9c445..c21e58d 100644
--- a/src/dm_top.sv
+++ b/src/dm_top.sv
@@ -86,6 +86,7 @@ module dm_top #(
   logic [dm::DataCount-1:0][31:0]   data_csrs_mem;
   logic [dm::DataCount-1:0][31:0]   data_mem_csrs;
   logic                             data_valid;
+  logic                             ndmreset;
   logic [19:0]                      hartsel;
   // System Bus Access Module
   logic [BusWidth-1:0]              sbaddress_csrs_sba;
@@ -104,6 +105,7 @@ module dm_top #(
   logic                             sberror_valid;
   logic [2:0]                       sberror;
 
+  assign ndmreset_o = ndmreset;
 
   dm_csrs #(
     .NrHarts(NrHarts),
@@ -120,7 +122,7 @@ module dm_top #(
     .dmi_resp_valid_o,
     .dmi_resp_ready_i,
     .dmi_resp_o,
-    .ndmreset_o,
+    .ndmreset_o              ( ndmreset              ),
     .dmactive_o,
     .hartsel_o               ( hartsel               ),
     .hartinfo_i,
@@ -201,6 +203,7 @@ module dm_top #(
     .clk_i,
     .rst_ni,
     .debug_req_o,
+    .ndmreset_i              ( ndmreset              ),
     .hartsel_i               ( hartsel               ),
     .haltreq_i               ( haltreq               ),
     .resumereq_i             ( resumereq             ),