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I am changing my LFO implementation to fit the original architecture following your C translation of the chip. I have found a difference between my Verilog implementation (of your code) and your C code.
The top plot is the Verilog output, and the bottom is the C code. Note how the PM sign bit is lost for the first couple of pulses. Note too that there is a glitch in the sign. For the Verilog counterpart, the PM sign tracks the signal as expected. The amplitude part of the modulation seems equal. Only the sign is different.
I am trying to translate your C code to schematics first and then convert it in a more or less 1:1 translation to modern RTL code. So I try to understand the circuit while I translate it. Thus, I may have fixed something inadvertently in the translation.
I still haven't finished debugging other differences, but this one may be a genuine problem in the C code.
The text was updated successfully, but these errors were encountered:
I am changing my LFO implementation to fit the original architecture following your C translation of the chip. I have found a difference between my Verilog implementation (of your code) and your C code.
The top plot is the Verilog output, and the bottom is the C code. Note how the PM sign bit is lost for the first couple of pulses. Note too that there is a glitch in the sign. For the Verilog counterpart, the PM sign tracks the signal as expected. The amplitude part of the modulation seems equal. Only the sign is different.
I am trying to translate your C code to schematics first and then convert it in a more or less 1:1 translation to modern RTL code. So I try to understand the circuit while I translate it. Thus, I may have fixed something inadvertently in the translation.
I still haven't finished debugging other differences, but this one may be a genuine problem in the C code.
The text was updated successfully, but these errors were encountered: