diff --git a/hal/armv7m/imxrt/117x/imxrt.c b/hal/armv7m/imxrt/117x/imxrt.c index b645717f..2e7080d1 100644 --- a/hal/armv7m/imxrt/117x/imxrt.c +++ b/hal/armv7m/imxrt/117x/imxrt.c @@ -41,6 +41,29 @@ enum { wdog_wcr = 0, wdog_wsr, wdog_wrsr, wdog_wicr, wdog_wmcr }; enum { rtwdog_cs = 0, rtwdog_cnt, rtwdog_total, rtwdog_win }; +/* ANADIG & ANATOP complex */ +enum { + /* OSC */ + osc_48m_ctrl = 0x04, osc_24m_ctrl = 0x08, osc_400m_ctrl0 = 0x10, osc_400m_ctrl1 = 0x14, osc_400m_ctrl2 = 0x18, + osc_16m_ctrl = 0x30, + /* PLL */ + arm_pll_ctrl = 0x80, sys_pll3_ctrl = 0x84, sys_pll3_update= 0x88, sys_pll3_pfd = 0x8c, + sys_pll2_ctrl = 0x90, sys_pll2_update = 0x94, sys_pll2_ss = 0x98, sys_pll2_pfd = 0x9c, + sys_pll2_mfd = 0xa8, sys_pll1_ss = 0xac, sys_pll1_ctrl = 0xb0, sys_pll1_denominator = 0xb4, + sys_pll1_numerator = 0xb8, sys_pll1_div_select = 0xbc, pll_audio_ctrl = 0xc0, pll_audio_ss = 0xc4, + pll_audio_denominator = 0xc8, pll_audio_numerator = 0xcc, pll_audio_div_select = 0xd0, pll_video_ctrl = 0xd4, + pll_video_ss = 0xd8, pll_video_denominator = 0xdc, pll_video_numerator = 0xe0, pll_video_div_select = 0xe4, + + /* PMU */ + pmu_ldo_pll = 0x140, pmu_ldo_lpsr_ana = 0x144, pmu_ldo_lpsr_dig2 = 0x148, pmu_ldo_lpsr_dig = 0x14c, + pmu_ref_ctrl = 0x15c, + + + /* ANATOP AI */ + vddsoc_ai_ctrl = 0x208, vddsoc_ai_wdata = 0x20c, vddsoc_ai_rdata = 0x210 +}; + + struct { volatile u32 *aips[4]; volatile u32 *stk; @@ -55,6 +78,7 @@ struct { volatile u32 *iomuxc; volatile u32 *gpio[13]; volatile u32 *ccm; + volatile u32 *anadig_pll; u32 cpuclk; u32 cm4state; @@ -317,8 +341,9 @@ __attribute__((section(".noxip"))) int _imxrt_getDevClock(int clock, int *div, i unsigned int t; volatile u32 *reg = imxrt_common.ccm + (clock * 0x20); - if (clock < pctl_clk_cm7 || clock > pctl_clk_ccm_clko2) + if ((clock < pctl_clk_m7) || (clock > pctl_clk_clko2)) { return -1; + } t = *reg; @@ -336,8 +361,9 @@ __attribute__((section(".noxip"))) int _imxrt_setDevClock(int clock, int div, in unsigned int t; volatile u32 *reg = imxrt_common.ccm + (clock * 0x20); - if (clock < pctl_clk_cm7 || clock > pctl_clk_ccm_clko2) + if ((clock < pctl_clk_m7) || (clock > pctl_clk_clko2)) { return -1; + } t = *reg & ~0x01ff07ffu; *reg = t | (!state << 24) | ((mfn & 0xf) << 20) | ((mfd & 0xf) << 16) | ((mux & 0x7) << 8) | (div & 0xff); @@ -389,6 +415,511 @@ __attribute__((section(".noxip"))) int _imxrt_setLevelLPCG(int clock, int level) } +static void _imxrt_delay(u32 ticks) +{ + /* TODO: use better method e.g. count cycles, must not use IRQs and peripheral timers! */ + while (ticks-- != 0u) { + /* clang-format off */ + __asm__ volatile ("nop"); + /* clang-format on */ + } +} + + +static void _imxrt_setPllBypass(u8 clk_pll, u8 enable) +{ + /* clang-format off */ + switch (clk_pll) { + case clk_pllarm: + *(imxrt_common.anadig_pll + arm_pll_ctrl) = (enable != 0) ? + (*(imxrt_common.anadig_pll + arm_pll_ctrl) | (1uL << 17u)) : + (*(imxrt_common.anadig_pll + arm_pll_ctrl) & ~(1uL << 17u)); + break; + case clk_pllsys1: + *(imxrt_common.anadig_pll + sys_pll1_ctrl) = (enable != 0) ? + (*(imxrt_common.anadig_pll + sys_pll1_ctrl) | (1uL << 16u)) : + (*(imxrt_common.anadig_pll + sys_pll1_ctrl) & ~(1uL << 16u)); + break; + case clk_pllsys2: + *(imxrt_common.anadig_pll + sys_pll2_ctrl) = (enable != 0) ? + (*(imxrt_common.anadig_pll + sys_pll2_ctrl) | (1uL << 16u)) : + (*(imxrt_common.anadig_pll + sys_pll2_ctrl) & ~(1uL << 16u)); + break; + case clk_pllsys3: + *(imxrt_common.anadig_pll + sys_pll3_ctrl) = (enable != 0) ? + (*(imxrt_common.anadig_pll + sys_pll3_ctrl) | (1uL << 16u)) : + (*(imxrt_common.anadig_pll + sys_pll3_ctrl) & ~(1uL << 16u)); + break; + case clk_pllaudio: + /* TODO: access through ANATOP AI */ + break; + case clk_pllvideo: + /* TODO: access through ANATOP AI */ + break; + default: + break; + } + /* clang-format on */ +} + + +#ifdef BYPASS_ANADIG_LDO +static void _imxrt_pmuBypassAnaLdo(void) +{ + /* HP mode */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_ana) &= ~1u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); + + /* Tracking mode */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_ana) |= 1uL << 19u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); + + /* Enable bypass mode */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_ana) |= 1uL << 5u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); + + /* Disable ana_lpsr regulator */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_ana) |= 1uL << 2u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); +} +#endif + + +#ifdef BYPASS_ANADIG_LDO +static void _imxrt_pmuBypassDigLdo(void) +{ + /* Tracking mode */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_dig) |= 1uL << 17u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); + + /* Set bypass mode */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_dig) |= 1uL << 18u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); + + /* Disable dig_lpsr regulator */ + *(imxrt_common.anadig_pll + pmu_ldo_lpsr_dig) |= 1uL << 2u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(1000u * 1000u); +} +#endif + + +static void _imxrt_pmuEnablePllLdo(void) +{ + u32 val; + + /* Set address of PHY_LDO_CTRL0 */ + *(imxrt_common.anadig_pll + vddsoc_ai_ctrl) |= (1uL << 16u); + + val = *(imxrt_common.anadig_pll + vddsoc_ai_ctrl) & ~(0xffu); + *(imxrt_common.anadig_pll + vddsoc_ai_ctrl) = val | (0u); /* PHY_LDO_CTRL0 = 0 */ + + /* Toggle ldo PLL AI */ + *(imxrt_common.anadig_pll + pmu_ldo_pll) ^= 1uL << 16u; + /* Read data */ + val = *(imxrt_common.anadig_pll + vddsoc_ai_rdata); + + if (val == ((0x10uL << 4u) | (1uL << 2u) | 1u)) { + /* Already set PHY_LDO_CTRL0 LDO */ + return; + } + + *(imxrt_common.anadig_pll + vddsoc_ai_ctrl) &= ~(1uL << 16u); + + val = *(imxrt_common.anadig_pll + vddsoc_ai_ctrl) & ~(0xffu); + *(imxrt_common.anadig_pll + vddsoc_ai_ctrl) = val | (0u); /* PHY_LDO_CTRL0 = 0 */ + + /* Write data */ + *(imxrt_common.anadig_pll + vddsoc_ai_wdata) = (0x10uL << 4u) | (1uL << 2u) | 1u; + /* Toggle ldo PLL AI */ + *(imxrt_common.anadig_pll + pmu_ldo_pll) ^= 1uL << 16u; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(300u * 1000u); + + /* Enable Voltage Reference for PLLs before those PLLs were enabled */ + *(imxrt_common.anadig_pll + pmu_ref_ctrl) = 1uL << 4u; +} + + +static u32 _imxrt_deinitArmPll(void) +{ + u32 reg = *(imxrt_common.anadig_pll + arm_pll_ctrl) & ~(1uL << 29u); + + /* Disable and gate clock if not already */ + if ((reg & ((1uL << 13u) | (1uL << 14u))) != 0u) { + /* Power down the PLL, disable clock */ + reg &= ~((1uL << 13u) | (1uL << 14u)); + /* Gate the clock */ + reg |= 1uL << 30u; + *(imxrt_common.anadig_pll + arm_pll_ctrl) = reg; + + hal_cpuDataSyncBarrier(); + hal_cpuInstrBarrier(); + } + + return reg; +} + + +static int _imxrt_initArmPll(u8 loopDivider, u8 postDivider) +{ + u32 reg; + + /* + * Fin = XTALOSC = 24MHz + * Fout = Fin * (loopDivider / (2 * postDivider)) + */ + + if ((loopDivider < 104u) || (208u < loopDivider)) { + return -1; + } + + reg = _imxrt_deinitArmPll(); + + /* Set the configuration. */ + reg &= ~((3uL << 15u) | 0xffu); + reg |= ((u32)(loopDivider & 0xffu) | (((u32)postDivider & 3uL) << 15u)) | (1uL << 30u) | (1uL << 13u); + *(imxrt_common.anadig_pll + arm_pll_ctrl) = reg; + + hal_cpuDataSyncBarrier(); + hal_cpuInstrBarrier(); + + _imxrt_delay(300u * 1000u); + + /* Wait for stable PLL */ + while ((*(imxrt_common.anadig_pll + arm_pll_ctrl) & (1uL << 29u)) == 0u) { + } + + /* Enable the clock. */ + reg |= 1uL << 14u; + + /* Ungate the clock */ + reg &= ~(1uL << 30u); + + *(imxrt_common.anadig_pll + arm_pll_ctrl) = reg; + + return 0; +} + + +static void _imxrt_initSysPll3(void) +{ + u32 reg; + + /* check if configuration is the same, then only enable clock */ + if ((*(imxrt_common.anadig_pll + sys_pll3_ctrl) & (1uL << 21u)) != 0u) { + /* if clock disable -> enable it */ + if ((*(imxrt_common.anadig_pll + sys_pll3_ctrl) & (1uL << 13u)) == 0u) { + *(imxrt_common.anadig_pll + sys_pll3_ctrl) |= (1uL << 13u); + } + + /* if clock is gated -> ungate */ + if ((*(imxrt_common.anadig_pll + sys_pll3_ctrl) & (1uL << 30u)) != 0u) { + *(imxrt_common.anadig_pll + sys_pll3_ctrl) &= ~(1uL << 30u); + } + + return; + } + + /* Gate all PFDs */ + *(imxrt_common.anadig_pll + sys_pll3_pfd) |= (1uL << 31u) | (1uL << 23u) | (1uL << 15u) | (1uL << 7u); + + /* Enable, but gate clock */ + reg = (1uL << 4u) | (1uL << 30u); + *(imxrt_common.anadig_pll + sys_pll3_pfd) = reg; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(300u * 1000u); + + /* Power off and hold ring off */ + reg |= (1uL << 21u) | (1uL << 11u); + *(imxrt_common.anadig_pll + sys_pll3_pfd) = reg; + hal_cpuDataMemoryBarrier(); + + _imxrt_delay(300u * 1000u); + + /* Deassert hold ring off */ + reg &= ~(1uL << 11u); + *(imxrt_common.anadig_pll + sys_pll3_pfd) = reg; + + /* Wait for stable PLL */ + while ((*(imxrt_common.anadig_pll + sys_pll3_ctrl) & (1uL << 29u)) == 0u) { + } + + /* Enable system pll3 and div2 clocks */ + reg |= (1uL << 13u) | (1uL << 3u); + + /* un-gate sys pll3 */ + reg &= ~(1uL << 30u); + *(imxrt_common.anadig_pll + sys_pll3_pfd) = reg; +} + + +int _imxrt_setPfdPllFracClock(u8 pfd, u8 clk_pll, u8 frac) +{ + volatile u32 *ctrl; + volatile u32 *update; + volatile u32 stable; + u32 fracval; + u8 gatedpfd; + + if ((pfd > 3u) || (frac > 35u)) { + return -1; + } + + switch (clk_pll) { + case clk_pllsys2: + if ((frac < 13u)) { + return -1; + } + ctrl = imxrt_common.anadig_pll + sys_pll2_pfd; + update = imxrt_common.anadig_pll + sys_pll2_update; + break; + + case clk_pllsys3: + if (((pfd == 3u) && (frac < 12u)) || ((pfd < 3u) && (frac < 13u))) { + return -1; + } + ctrl = imxrt_common.anadig_pll + sys_pll3_pfd; + update = imxrt_common.anadig_pll + sys_pll3_update; + break; + + default: + return -1; + } + + fracval = ((*ctrl) & (0x3fuL << (8u * pfd))) >> (8u * pfd); + gatedpfd = ((*ctrl) & (0x80uL << (8u * pfd))) >> (8u * pfd); + + if ((fracval == (u32)frac) && (gatedpfd == 0u)) { + return 0; + } + + stable = *ctrl & (0x40uL << (8u * pfd)); + *ctrl |= 0x80uL << (8u * pfd); + + *ctrl &= ~(0x3fuL << (8u * pfd)); + *ctrl |= (u32)(frac & 0x3fuL) << (8u * pfd); + + *update ^= 2uL << pfd; + *ctrl &= ~(0x80uL << (8u * pfd)); + + while ((*ctrl & (0x40uL << (8u * pfd))) == stable) { + } + + return 0; +} + + +static void _imxrt_deinitSysPll1(void) +{ + /* Disable PLL1 and div2, div5 */ + *(imxrt_common.anadig_pll + sys_pll1_ctrl) &= ~((1uL << 26u) | (1uL << 25u) | (1uL << 13u)); + + /* Gate PLL1 */ + *(imxrt_common.anadig_pll + sys_pll1_ctrl) |= 1uL << 14u; +} + + +static void _imxrt_initClockTree(void) +{ + unsigned n; + static const struct { + u8 root; + u8 mux; + u8 div; + u8 isOn; + } clktree[] = { + { pctl_clk_m7, mux_clkroot_m7_armpllout, 1, 1 }, + { pctl_clk_m4, mux_clkroot_m4_syspll3pfd3, 1, 1 }, + { pctl_clk_bus, mux_clkroot_bus_syspll3out, 2, 1 }, + { pctl_clk_bus_lpsr, mux_clkroot_bus_lpsr_syspll3out, 3, 1 }, + /* NOTE: not using "pctl_clk_semc" is disabled by bootrom */ + { pctl_clk_cssys, mux_clkroot_cssys_osc24mout, 1, 1 }, + { pctl_clk_cstrace, mux_clkroot_cstrace_syspll2out, 4, 1 }, + { pctl_clk_m4_systick, mux_clkroot_m4_systick_osc24mout, 1, 1 }, + { pctl_clk_m7_systick, mux_clkroot_m7_systick_osc24mout, 2, 1 }, + { pctl_clk_adc1, mux_clkroot_adc1_osc24mout, 1, 1 }, + { pctl_clk_adc2, mux_clkroot_adc2_osc24mout, 1, 1 }, + { pctl_clk_acmp, mux_clkroot_acmp_osc24mout, 1, 1 }, + { pctl_clk_flexio1, mux_clkroot_flexio1_osc24mout, 1, 1 }, + { pctl_clk_flexio2, mux_clkroot_flexio2_osc24mout, 1, 1 }, + { pctl_clk_gpt1, mux_clkroot_gpt1_osc24mout, 1, 1 }, + { pctl_clk_gpt2, mux_clkroot_gpt2_osc24mout, 1, 1 }, + { pctl_clk_gpt3, mux_clkroot_gpt3_osc24mout, 1, 1 }, + { pctl_clk_gpt4, mux_clkroot_gpt4_osc24mout, 1, 1 }, + { pctl_clk_gpt5, mux_clkroot_gpt5_osc24mout, 1, 1 }, + { pctl_clk_gpt6, mux_clkroot_gpt6_osc24mout, 1, 1 }, + /* NOTE: "pctl_clk_flexspi1" is changed by imxrt-flash driver */ + /* NOTE: "pctl_clk_flexspi2" is changed by imxrt-flash driver */ + { pctl_clk_can1, mux_clkroot_can1_osc24mout, 1, 1 }, + { pctl_clk_can2, mux_clkroot_can2_osc24mout, 1, 1 }, + { pctl_clk_can3, mux_clkroot_can3_osc24mout, 1, 1 }, + { pctl_clk_lpuart1, mux_clkroot_lpuart1_osc24mout, 2, 1 }, + { pctl_clk_lpuart2, mux_clkroot_lpuart2_osc24mout, 2, 1 }, + { pctl_clk_lpuart3, mux_clkroot_lpuart3_osc24mout, 1, 1 }, + { pctl_clk_lpuart4, mux_clkroot_lpuart4_osc24mout, 1, 1 }, + { pctl_clk_lpuart5, mux_clkroot_lpuart5_osc24mout, 1, 1 }, + { pctl_clk_lpuart6, mux_clkroot_lpuart6_osc24mout, 1, 1 }, + { pctl_clk_lpuart7, mux_clkroot_lpuart7_osc24mout, 1, 1 }, + { pctl_clk_lpuart8, mux_clkroot_lpuart8_osc24mout, 1, 1 }, + { pctl_clk_lpuart9, mux_clkroot_lpuart9_osc24mout, 1, 1 }, + { pctl_clk_lpuart10, mux_clkroot_lpuart10_osc24mout, 1, 1 }, + { pctl_clk_lpuart11, mux_clkroot_lpuart11_osc24mout, 1, 1 }, + { pctl_clk_lpuart12, mux_clkroot_lpuart12_osc24mout, 1, 1 }, + { pctl_clk_lpi2c1, mux_clkroot_lpi2c1_osc24mout, 1, 1 }, + { pctl_clk_lpi2c2, mux_clkroot_lpi2c2_osc24mout, 1, 1 }, + { pctl_clk_lpi2c3, mux_clkroot_lpi2c3_osc24mout, 1, 1 }, + { pctl_clk_lpi2c4, mux_clkroot_lpi2c4_osc24mout, 1, 1 }, + { pctl_clk_lpi2c5, mux_clkroot_lpi2c5_osc24mout, 1, 1 }, + { pctl_clk_lpi2c6, mux_clkroot_lpi2c6_osc24mout, 1, 1 }, + { pctl_clk_lpspi1, mux_clkroot_lpspi1_osc24mout, 1, 1 }, + { pctl_clk_lpspi2, mux_clkroot_lpspi2_osc24mout, 1, 1 }, + { pctl_clk_lpspi3, mux_clkroot_lpspi3_osc24mout, 1, 1 }, + { pctl_clk_lpspi4, mux_clkroot_lpspi4_osc24mout, 1, 1 }, + { pctl_clk_lpspi5, mux_clkroot_lpspi5_osc24mout, 1, 1 }, + { pctl_clk_lpspi6, mux_clkroot_lpspi6_osc24mout, 1, 1 }, + { pctl_clk_emv1, mux_clkroot_emv1_osc24mout, 1, 1 }, + { pctl_clk_emv2, mux_clkroot_emv2_osc24mout, 1, 1 }, + { pctl_clk_enet1, mux_clkroot_enet1_osc24mout, 1, 1 }, + { pctl_clk_enet2, mux_clkroot_enet2_osc24mout, 1, 1 }, + { pctl_clk_enet_qos, mux_clkroot_enet_qos_osc24mout, 1, 1 }, + { pctl_clk_enet_25m, mux_clkroot_enet_25m_osc24mout, 1, 1 }, + { pctl_clk_enet_timer1, mux_clkroot_enet_timer1_osc24mout, 1, 1 }, + { pctl_clk_enet_timer2, mux_clkroot_enet_timer2_osc24mout, 1, 1 }, + { pctl_clk_enet_timer3, mux_clkroot_enet_timer3_osc24mout, 1, 1 }, + { pctl_clk_usdhc1, mux_clkroot_usdhc1_osc24mout, 1, 1 }, + { pctl_clk_usdhc2, mux_clkroot_usdhc2_osc24mout, 1, 1 }, + { pctl_clk_asrc, mux_clkroot_asrc_osc24mout, 1, 1 }, + { pctl_clk_mqs, mux_clkroot_mqs_osc24mout, 1, 1 }, + { pctl_clk_mic, mux_clkroot_mic_osc24mout, 1, 1 }, + { pctl_clk_spdif, mux_clkroot_spdif_osc24mout, 1, 1 }, + { pctl_clk_sai1, mux_clkroot_sai1_osc24mout, 1, 1 }, + { pctl_clk_sai2, mux_clkroot_sai2_osc24mout, 1, 1 }, + { pctl_clk_sai3, mux_clkroot_sai3_osc24mout, 1, 1 }, + { pctl_clk_sai4, mux_clkroot_sai4_osc24mout, 1, 1 }, + /* NOTE: "pctl_clk_gpu2d" not using video peripheral - clock turned off */ + { pctl_clk_gpu2d, mux_clkroot_gpu2d_videopllout, 2, 0 }, + { pctl_clk_lcdif, mux_clkroot_lcdif_osc24mout, 1, 1 }, + { pctl_clk_lcdifv2, mux_clkroot_lcdifv2_osc24mout, 1, 1 }, + { pctl_clk_mipi_ref, mux_clkroot_mipi_ref_osc24mout, 1, 1 }, + { pctl_clk_mipi_esc, mux_clkroot_mipi_esc_osc24mout, 1, 1 }, + { pctl_clk_csi2, mux_clkroot_csi2_osc24mout, 1, 1 }, + { pctl_clk_csi2_esc, mux_clkroot_csi2_esc_osc24mout, 1, 1 }, + { pctl_clk_csi2_ui, mux_clkroot_csi2_ui_osc24mout, 1, 1 }, + { pctl_clk_csi, mux_clkroot_csi_osc24mout, 1, 1 }, + { pctl_clk_clko1, mux_clkroot_cko1_osc24mout, 1, 1 }, + { pctl_clk_clko2, mux_clkroot_cko2_osc24mout, 1, 1 }, + }; + + for (n = 0; n < sizeof(clktree) / sizeof(clktree[0]); n++) { + /* NOTE: fraction divider is not used */ + _imxrt_setDevClock(clktree[n].root, clktree[n].div - 1, clktree[n].mux, 0, 0, clktree[n].isOn); + } +} + + +static void _imxrt_initClocks(void) +{ +#ifdef BYPASS_ANADIG_LDO + _imxrt_pmuBypassAnaLdo(); + _imxrt_pmuBypassDigLdo(); +#endif + + /* Initialize 16 MHz RC osc */ + *(imxrt_common.anadig_pll + osc_16m_ctrl) |= 1uL << 1u; + + /* Init 400 MHz RC osc */ + *(imxrt_common.anadig_pll + osc_400m_ctrl1) &= ~1u; + *(imxrt_common.anadig_pll + osc_400m_ctrl2) |= 1u; + *(imxrt_common.anadig_pll + osc_400m_ctrl1) |= 1uL << 1u; + + /* Init 48 MHz RC osc */ + *(imxrt_common.anadig_pll + osc_48m_ctrl) |= 1uL << 1u; + + /* Enables 24MHz clock source from 48MHz RC osc */ + *(imxrt_common.anadig_pll + osc_48m_ctrl) |= 1uL << 24u; + + /* Configure 24 MHz RC osc */ + *(imxrt_common.anadig_pll + osc_24m_ctrl) |= (1uL << 4u) | (1uL << 2u); + hal_cpuDataSyncBarrier(); + + while ((*(imxrt_common.anadig_pll + osc_24m_ctrl) & (1uL << 30u)) == 0u) { + } + + /* Make sure main clocks are not using ARM PLL, PLL1, PLL2, PLL3 and XTAL */ + _imxrt_setDevClock(pctl_clk_m7, 0, mux_clkroot_m7_oscrc48mdiv2, 0, 0, 1); + _imxrt_setDevClock(pctl_clk_m7_systick, 239, mux_clkroot_m7_oscrc48mdiv2, 0, 0, 1); + _imxrt_setDevClock(pctl_clk_bus, 0, mux_clkroot_bus_oscrc48mdiv2, 0, 0, 1); + _imxrt_setDevClock(pctl_clk_bus_lpsr, 0, mux_clkroot_bus_lpsr_oscrc48mdiv2, 0, 0, 1); + + /* bootrom already configured M4 core to RC OSC if M4 core is present */ + /* _imxrt_setDevClock(pctl_clk_m4, 0, mux_clkroot_m4_oscrc48mdiv2, 0, 0, 1); */ + /* _imxrt_setDevClock(pctl_clk_m4_systick, 239, mux_clkroot_m4_systick_oscrc48mdiv2, 0, 0, 1); */ + + /* Power up ARM PLL, PLL3 slices */ + _imxrt_pmuEnablePllLdo(); + + /* FIXME: Improve target platform CPU speed selector */ + +#ifdef PLATFORM_CONSUMER_MARKET + /* commercial-qualified devices up to 1GHz */ + + /* Initialize ARM PLL to 996 MHz */ + _imxrt_initArmPll(166, 0); + imxrt_common.cpuclk = 996000000u; +#else + /* industrial-qualified devices up to 800MHz */ + + /* Initialize ARM PLL to 798 MHz */ + _imxrt_initArmPll(133, 0); + imxrt_common.cpuclk = 798000000u; + + /* Initialize ARM PLL to 696 MHz */ + /* _imxrt_initArmPll(116, 0); */ + /* imxrt_common.cpuclk = 696000000u; */ +#endif + + _imxrt_setPllBypass(clk_pllsys1, 1); + + /* Deinit 1Gig ethernet PLL */ + _imxrt_deinitSysPll1(); + + /* TODO: Init PLL2 fixed 528 MHz */ + /* _imxrt_initSysPll2(); */ + + _imxrt_setPfdPllFracClock(0, clk_pllsys2, 27); + _imxrt_setPfdPllFracClock(1, clk_pllsys2, 16); + _imxrt_setPfdPllFracClock(2, clk_pllsys2, 24); + _imxrt_setPfdPllFracClock(3, clk_pllsys2, 32); + + /* Init PLL3 fixed 480MHz */ + _imxrt_initSysPll3(); + + _imxrt_setPfdPllFracClock(0, clk_pllsys3, 13); + _imxrt_setPfdPllFracClock(1, clk_pllsys3, 17); + _imxrt_setPfdPllFracClock(2, clk_pllsys3, 32); + _imxrt_setPfdPllFracClock(3, clk_pllsys3, 24); + + /* Module clock root configurations */ + _imxrt_initClockTree(); +} + + /* CM4 */ @@ -462,6 +993,7 @@ void _imxrt_init(void) imxrt_common.iomuxc_gpr = (void *)0x400e4000; imxrt_common.iomuxc = (void *)0x400e8000; imxrt_common.ccm = (void *)0x40cc0000; + imxrt_common.anadig_pll = (void *)0x40c84000; imxrt_common.gpio[0] = (void *)0x4012c000; imxrt_common.gpio[1] = (void *)0x40130000; @@ -477,10 +1009,10 @@ void _imxrt_init(void) imxrt_common.gpio[11] = (void *)0x40c70000; imxrt_common.gpio[12] = (void *)0x40ca0000; - imxrt_common.cpuclk = 640000000; - imxrt_common.cm4state = (*(imxrt_common.src + src_scr) & 1u); + _imxrt_initClocks(); + /* Disable watchdogs */ if (*(imxrt_common.wdog1 + wdog_wcr) & (1 << 2)) *(imxrt_common.wdog1 + wdog_wcr) &= ~(1 << 2); diff --git a/hal/armv7m/imxrt/117x/imxrt.h b/hal/armv7m/imxrt/117x/imxrt.h index 47a72b89..684384e9 100644 --- a/hal/armv7m/imxrt/117x/imxrt.h +++ b/hal/armv7m/imxrt/117x/imxrt.h @@ -28,7 +28,7 @@ enum { gpio1 = 0, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7, gpio8, gpio9, gpio10 /* CCM - Root Clocks */ -enum { pctl_clk_cm7 = 0, pctl_clk_cm4, pctl_clk_bus, pctl_clk_bus_lpsr, pctl_clk_semc, pctl_clk_cssys, +enum { pctl_clk_m7 = 0, pctl_clk_m4, pctl_clk_bus, pctl_clk_bus_lpsr, pctl_clk_semc, pctl_clk_cssys, pctl_clk_cstrace, pctl_clk_m4_systick, pctl_clk_m7_systick, pctl_clk_adc1, pctl_clk_adc2, pctl_clk_acmp, pctl_clk_flexio1, pctl_clk_flexio2, pctl_clk_gpt1, pctl_clk_gpt2, pctl_clk_gpt3, pctl_clk_gpt4, pctl_clk_gpt5, pctl_clk_gpt6, pctl_clk_flexspi1, pctl_clk_flexspi2, pctl_clk_can1, pctl_clk_can2, pctl_clk_can3, pctl_clk_lpuart1, @@ -36,11 +36,11 @@ enum { pctl_clk_cm7 = 0, pctl_clk_cm4, pctl_clk_bus, pctl_clk_bus_lpsr, pctl_clk pctl_clk_lpuart8, pctl_clk_lpuart9, pctl_clk_lpuart10, pctl_clk_lpuart11, pctl_clk_lpuart12, pctl_clk_lpi2c1, pctl_clk_lpi2c2, pctl_clk_lpi2c3, pctl_clk_lpi2c4, pctl_clk_lpi2c5, pctl_clk_lpi2c6, pctl_clk_lpspi1, pctl_clk_lpspi2, pctl_clk_lpspi3, pctl_clk_lpspi4, pctl_clk_lpspi5, pctl_clk_lpspi6, pctl_clk_emv1, pctl_clk_emv2, pctl_clk_enet1, - pctl_clk_enet2, pctl_clk_enet_qos, pctl_clk_enet_25m, pctl_clk_enet_time1, pctl_clk_enet_time2, pctl_clk_enet_time3, - pctl_clk_usdhc1, pctl_clk_usdhc2, pctl_clk_asrc, pctl_clk_mqs, pctl_clk_pdm, pctl_clk_spdif, pctl_clk_sai1, - pctl_clk_sai2, pctl_clk_sai3, pctl_clk_sai4, pctl_clk_gpu2d, pctl_clk_elcdif, pctl_clk_lcdifv2, pctl_clk_mipi_ref, - pctl_clk_mipi_esc, pctl_clk_csi2, pctl_clk_csi2_esc, pctl_clk_csi2_ui, pctl_clk_csi, pctl_clk_ccm_clko1, - pctl_clk_ccm_clko2 }; + pctl_clk_enet2, pctl_clk_enet_qos, pctl_clk_enet_25m, pctl_clk_enet_timer1, pctl_clk_enet_timer2, pctl_clk_enet_timer3, + pctl_clk_usdhc1, pctl_clk_usdhc2, pctl_clk_asrc, pctl_clk_mqs, pctl_clk_mic, pctl_clk_spdif, pctl_clk_sai1, + pctl_clk_sai2, pctl_clk_sai3, pctl_clk_sai4, pctl_clk_gpu2d, pctl_clk_lcdif, pctl_clk_lcdifv2, pctl_clk_mipi_ref, + pctl_clk_mipi_esc, pctl_clk_csi2, pctl_clk_csi2_esc, pctl_clk_csi2_ui, pctl_clk_csi, pctl_clk_clko1, + pctl_clk_clko2 }; /* CCM - Low Power Clock Gates */ @@ -320,6 +320,328 @@ enum { cti0_err_irq = 17 + 16, cti1_err_irq, core_irq, lpuart1_irq, lpuart2_irq, xecc_flexspi1_fatal_irq, xecc_flexspi2_irq, xecc_flexspi2_fatal_irq, xecc_semc_irq, xecc_semc_fatal_irq, enet_qos_irq, enet_pmt_irq }; + +/* Mux selector: M7 */ +enum { mux_clkroot_m7_oscrc48mdiv2 = 0, mux_clkroot_m7_osc24mout, mux_clkroot_m7_oscrc400m, mux_clkroot_m7_oscrc16m, + mux_clkroot_m7_armpllout, mux_clkroot_m7_syspll1out, mux_clkroot_m7_syspll3out, mux_clkroot_m7_videopllout }; + +/* Mux selector: M4 */ +enum { mux_clkroot_m4_oscrc48mdiv2 = 0, mux_clkroot_m4_osc24mout, mux_clkroot_m4_oscrc400m, mux_clkroot_m4_oscrc16m, + mux_clkroot_m4_syspll3pfd3, mux_clkroot_m4_syspll3out, mux_clkroot_m4_syspll2out, mux_clkroot_m4_syspll1div5 }; + +/* Mux selector: BUS */ +enum { mux_clkroot_bus_oscrc48mdiv2 = 0, mux_clkroot_bus_osc24mout, mux_clkroot_bus_oscrc400m, mux_clkroot_bus_oscrc16m, + mux_clkroot_bus_syspll3out, mux_clkroot_bus_syspll1div5, mux_clkroot_bus_syspll2out, mux_clkroot_bus_syspll2pfd3 }; + +/* Mux selector: BUS_LPSR */ +enum { mux_clkroot_bus_lpsr_oscrc48mdiv2 = 0, mux_clkroot_bus_lpsr_osc24mout, mux_clkroot_bus_lpsr_oscrc400m, mux_clkroot_bus_lpsr_oscrc16m, + mux_clkroot_bus_lpsr_syspll3pfd3, mux_clkroot_bus_lpsr_syspll3out, mux_clkroot_bus_lpsr_syspll2out, mux_clkroot_bus_lpsr_syspll1div5 }; + +/* Mux selector: SEMC */ +enum { mux_clkroot_semc_oscrc48mdiv2 = 0, mux_clkroot_semc_osc24mout, mux_clkroot_semc_oscrc400m, mux_clkroot_semc_oscrc16m, + mux_clkroot_semc_syspll1div5, mux_clkroot_semc_syspll2out, mux_clkroot_semc_syspll2pfd1, mux_clkroot_semc_syspll3pfd0 }; + +/* Mux selector: CSSYS */ +enum { mux_clkroot_cssys_oscrc48mdiv2 = 0, mux_clkroot_cssys_osc24mout, mux_clkroot_cssys_oscrc400m, mux_clkroot_cssys_oscrc16m, + mux_clkroot_cssys_syspll3div2, mux_clkroot_cssys_syspll1div5, mux_clkroot_cssys_syspll2out, mux_clkroot_cssys_syspll2pfd3 }; + +/* Mux selector: CSTRACE */ +enum { mux_clkroot_cstrace_oscrc48mdiv2 = 0, mux_clkroot_cstrace_osc24mout, mux_clkroot_cstrace_oscrc400m, mux_clkroot_cstrace_oscrc16m, + mux_clkroot_cstrace_syspll3div2, mux_clkroot_cstrace_syspll1div5, mux_clkroot_cstrace_syspll2pfd1, mux_clkroot_cstrace_syspll2out }; + +/* Mux selector: M4_SYSTICK */ +enum { mux_clkroot_m4_systick_oscrc48mdiv2 = 0, mux_clkroot_m4_systick_osc24mout, mux_clkroot_m4_systick_oscrc400m, mux_clkroot_m4_systick_oscrc16m, + mux_clkroot_m4_systick_syspll3pfd3, mux_clkroot_m4_systick_syspll3out, mux_clkroot_m4_systick_syspll2pfd0, mux_clkroot_m4_systick_syspll1div5 }; + +/* Mux selector: M7_SYSTICK */ +enum { mux_clkroot_m7_systick_oscrc48mdiv2 = 0, mux_clkroot_m7_systick_osc24mout, mux_clkroot_m7_systick_oscrc400m, mux_clkroot_m7_systick_oscrc16m, + mux_clkroot_m7_systick_syspll2out, mux_clkroot_m7_systick_syspll3div2, mux_clkroot_m7_systick_syspll1div5, mux_clkroot_m7_systick_syspll2pfd0 }; + +/* Mux selector: ADC1 */ +enum { mux_clkroot_adc1_oscrc48mdiv2 = 0, mux_clkroot_adc1_osc24mout, mux_clkroot_adc1_oscrc400m, mux_clkroot_adc1_oscrc16m, + mux_clkroot_adc1_syspll3div2, mux_clkroot_adc1_syspll1div5, mux_clkroot_adc1_syspll2out, mux_clkroot_adc1_syspll2pfd3 }; + +/* Mux selector: ADC2 */ +enum { mux_clkroot_adc2_oscrc48mdiv2 = 0, mux_clkroot_adc2_osc24mout, mux_clkroot_adc2_oscrc400m, mux_clkroot_adc2_oscrc16m, + mux_clkroot_adc2_syspll3div2, mux_clkroot_adc2_syspll1div5, mux_clkroot_adc2_syspll2out, mux_clkroot_adc2_syspll2pfd3 }; + +/* Mux selector: ACMP */ +enum { mux_clkroot_acmp_oscrc48mdiv2 = 0, mux_clkroot_acmp_osc24mout, mux_clkroot_acmp_oscrc400m, mux_clkroot_acmp_oscrc16m, + mux_clkroot_acmp_syspll3out, mux_clkroot_acmp_syspll1div5, mux_clkroot_acmp_audiopllout, mux_clkroot_acmp_syspll2pfd3 }; + +/* Mux selector: FLEXIO1 */ +enum { mux_clkroot_flexio1_oscrc48mdiv2 = 0, mux_clkroot_flexio1_osc24mout, mux_clkroot_flexio1_oscrc400m, mux_clkroot_flexio1_oscrc16m, + mux_clkroot_flexio1_syspll3div2, mux_clkroot_flexio1_syspll1div5, mux_clkroot_flexio1_syspll2out, mux_clkroot_flexio1_syspll2pfd3 }; + +/* Mux selector: FLEXIO2 */ +enum { mux_clkroot_flexio2_oscrc48mdiv2 = 0, mux_clkroot_flexio2_osc24mout, mux_clkroot_flexio2_oscrc400m, mux_clkroot_flexio2_oscrc16m, + mux_clkroot_flexio2_syspll3div2, mux_clkroot_flexio2_syspll1div5, mux_clkroot_flexio2_syspll2out, mux_clkroot_flexio2_syspll2pfd3 }; + +/* Mux selector: GPT1 */ +enum { mux_clkroot_gpt1_oscrc48mdiv2 = 0, mux_clkroot_gpt1_osc24mout, mux_clkroot_gpt1_oscrc400m, mux_clkroot_gpt1_oscrc16m, + mux_clkroot_gpt1_syspll3div2, mux_clkroot_gpt1_syspll1div5, mux_clkroot_gpt1_syspll3pfd2, mux_clkroot_gpt1_syspll3pfd3 }; + +/* Mux selector: GPT2 */ +enum { mux_clkroot_gpt2_oscrc48mdiv2 = 0, mux_clkroot_gpt2_osc24mout, mux_clkroot_gpt2_oscrc400m, mux_clkroot_gpt2_oscrc16m, + mux_clkroot_gpt2_syspll3div2, mux_clkroot_gpt2_syspll1div5, mux_clkroot_gpt2_audiopllout, mux_clkroot_gpt2_videopllout }; + +/* Mux selector: GPT3 */ +enum { mux_clkroot_gpt3_oscrc48mdiv2 = 0, mux_clkroot_gpt3_osc24mout, mux_clkroot_gpt3_oscrc400m, mux_clkroot_gpt3_oscrc16m, + mux_clkroot_gpt3_syspll3div2, mux_clkroot_gpt3_syspll1div5, mux_clkroot_gpt3_audiopllout, mux_clkroot_gpt3_videopllout }; + +/* Mux selector: GPT4 */ +enum { mux_clkroot_gpt4_oscrc48mdiv2 = 0, mux_clkroot_gpt4_osc24mout, mux_clkroot_gpt4_oscrc400m, mux_clkroot_gpt4_oscrc16m, + mux_clkroot_gpt4_syspll3div2, mux_clkroot_gpt4_syspll1div5, mux_clkroot_gpt4_syspll3pfd2, mux_clkroot_gpt4_syspll3pfd3 }; + +/* Mux selector: GPT5 */ +enum { mux_clkroot_gpt5_oscrc48mdiv2 = 0, mux_clkroot_gpt5_osc24mout, mux_clkroot_gpt5_oscrc400m, mux_clkroot_gpt5_oscrc16m, + mux_clkroot_gpt5_syspll3div2, mux_clkroot_gpt5_syspll1div5, mux_clkroot_gpt5_syspll3pfd2, mux_clkroot_gpt5_syspll3pfd3 }; + +/* Mux selector: GPT6 */ +enum { mux_clkroot_gpt6_oscrc48mdiv2 = 0, mux_clkroot_gpt6_osc24mout, mux_clkroot_gpt6_oscrc400m, mux_clkroot_gpt6_oscrc16m, + mux_clkroot_gpt6_syspll3div2, mux_clkroot_gpt6_syspll1div5, mux_clkroot_gpt6_syspll3pfd2, mux_clkroot_gpt6_syspll3pfd3 }; + +/* Mux selector: FLEXSPI1 */ +enum { mux_clkroot_flexspi1_oscrc48mdiv2 = 0, mux_clkroot_flexspi1_osc24mout, mux_clkroot_flexspi1_oscrc400m, mux_clkroot_flexspi1_oscrc16m, + mux_clkroot_flexspi1_syspll3pfd0, mux_clkroot_flexspi1_syspll2out, mux_clkroot_flexspi1_syspll2pfd2, mux_clkroot_flexspi1_syspll3out }; + +/* Mux selector: FLEXSPI2 */ +enum { mux_clkroot_flexspi2_oscrc48mdiv2 = 0, mux_clkroot_flexspi2_osc24mout, mux_clkroot_flexspi2_oscrc400m, mux_clkroot_flexspi2_oscrc16m, + mux_clkroot_flexspi2_syspll3pfd0, mux_clkroot_flexspi2_syspll2out, mux_clkroot_flexspi2_syspll2pfd2, mux_clkroot_flexspi2_syspll3out }; + +/* Mux selector: CAN1 */ +enum { mux_clkroot_can1_oscrc48mdiv2 = 0, mux_clkroot_can1_osc24mout, mux_clkroot_can1_oscrc400m, mux_clkroot_can1_oscrc16m, + mux_clkroot_can1_syspll3div2, mux_clkroot_can1_syspll1div5, mux_clkroot_can1_syspll2out, mux_clkroot_can1_syspll2pfd3 }; + +/* Mux selector: CAN2 */ +enum { mux_clkroot_can2_oscrc48mdiv2 = 0, mux_clkroot_can2_osc24mout, mux_clkroot_can2_oscrc400m, mux_clkroot_can2_oscrc16m, + mux_clkroot_can2_syspll3div2, mux_clkroot_can2_syspll1div5, mux_clkroot_can2_syspll2out, mux_clkroot_can2_syspll2pfd3 }; + +/* Mux selector: CAN3 */ +enum { mux_clkroot_can3_oscrc48mdiv2 = 0, mux_clkroot_can3_osc24mout, mux_clkroot_can3_oscrc400m, mux_clkroot_can3_oscrc16m, + mux_clkroot_can3_syspll3pfd3, mux_clkroot_can3_syspll3out, mux_clkroot_can3_syspll2pfd3, mux_clkroot_can3_syspll1div5 }; + +/* Mux selector: LPUART1 */ +enum { mux_clkroot_lpuart1_oscrc48mdiv2 = 0, mux_clkroot_lpuart1_osc24mout, mux_clkroot_lpuart1_oscrc400m, mux_clkroot_lpuart1_oscrc16m, + mux_clkroot_lpuart1_syspll3div2, mux_clkroot_lpuart1_syspll1div5, mux_clkroot_lpuart1_syspll2out, mux_clkroot_lpuart1_syspll2pfd3 }; + +/* Mux selector: LPUART2 */ +enum { mux_clkroot_lpuart2_oscrc48mdiv2 = 0, mux_clkroot_lpuart2_osc24mout, mux_clkroot_lpuart2_oscrc400m, mux_clkroot_lpuart2_oscrc16m, + mux_clkroot_lpuart2_syspll3div2, mux_clkroot_lpuart2_syspll1div5, mux_clkroot_lpuart2_syspll2out, mux_clkroot_lpuart2_syspll2pfd3 }; + +/* Mux selector: LPUART3 */ +enum { mux_clkroot_lpuart3_oscrc48mdiv2 = 0, mux_clkroot_lpuart3_osc24mout, mux_clkroot_lpuart3_oscrc400m, mux_clkroot_lpuart3_oscrc16m, + mux_clkroot_lpuart3_syspll3div2, mux_clkroot_lpuart3_syspll1div5, mux_clkroot_lpuart3_syspll2out, mux_clkroot_lpuart3_syspll2pfd3 }; + +/* Mux selector: LPUART4 */ +enum { mux_clkroot_lpuart4_oscrc48mdiv2 = 0, mux_clkroot_lpuart4_osc24mout, mux_clkroot_lpuart4_oscrc400m, mux_clkroot_lpuart4_oscrc16m, + mux_clkroot_lpuart4_syspll3div2, mux_clkroot_lpuart4_syspll1div5, mux_clkroot_lpuart4_syspll2out, mux_clkroot_lpuart4_syspll2pfd3 }; + +/* Mux selector: LPUART5 */ +enum { mux_clkroot_lpuart5_oscrc48mdiv2 = 0, mux_clkroot_lpuart5_osc24mout, mux_clkroot_lpuart5_oscrc400m, mux_clkroot_lpuart5_oscrc16m, + mux_clkroot_lpuart5_syspll3div2, mux_clkroot_lpuart5_syspll1div5, mux_clkroot_lpuart5_syspll2out, mux_clkroot_lpuart5_syspll2pfd3 }; + +/* Mux selector: LPUART6 */ +enum { mux_clkroot_lpuart6_oscrc48mdiv2 = 0, mux_clkroot_lpuart6_osc24mout, mux_clkroot_lpuart6_oscrc400m, mux_clkroot_lpuart6_oscrc16m, + mux_clkroot_lpuart6_syspll3div2, mux_clkroot_lpuart6_syspll1div5, mux_clkroot_lpuart6_syspll2out, mux_clkroot_lpuart6_syspll2pfd3 }; + +/* Mux selector: LPUART7 */ +enum { mux_clkroot_lpuart7_oscrc48mdiv2 = 0, mux_clkroot_lpuart7_osc24mout, mux_clkroot_lpuart7_oscrc400m, mux_clkroot_lpuart7_oscrc16m, + mux_clkroot_lpuart7_syspll3div2, mux_clkroot_lpuart7_syspll1div5, mux_clkroot_lpuart7_syspll2out, mux_clkroot_lpuart7_syspll2pfd3 }; + +/* Mux selector: LPUART8 */ +enum { mux_clkroot_lpuart8_oscrc48mdiv2 = 0, mux_clkroot_lpuart8_osc24mout, mux_clkroot_lpuart8_oscrc400m, mux_clkroot_lpuart8_oscrc16m, + mux_clkroot_lpuart8_syspll3div2, mux_clkroot_lpuart8_syspll1div5, mux_clkroot_lpuart8_syspll2out, mux_clkroot_lpuart8_syspll2pfd3 }; + +/* Mux selector: LPUART9 */ +enum { mux_clkroot_lpuart9_oscrc48mdiv2 = 0, mux_clkroot_lpuart9_osc24mout, mux_clkroot_lpuart9_oscrc400m, mux_clkroot_lpuart9_oscrc16m, + mux_clkroot_lpuart9_syspll3div2, mux_clkroot_lpuart9_syspll1div5, mux_clkroot_lpuart9_syspll2out, mux_clkroot_lpuart9_syspll2pfd3 }; + +/* Mux selector: LPUART10 */ +enum { mux_clkroot_lpuart10_oscrc48mdiv2 = 0, mux_clkroot_lpuart10_osc24mout, mux_clkroot_lpuart10_oscrc400m, mux_clkroot_lpuart10_oscrc16m, + mux_clkroot_lpuart10_syspll3div2, mux_clkroot_lpuart10_syspll1div5, mux_clkroot_lpuart10_syspll2out, mux_clkroot_lpuart10_syspll2pfd3 }; + +/* Mux selector: LPUART11 */ +enum { mux_clkroot_lpuart11_oscrc48mdiv2 = 0, mux_clkroot_lpuart11_osc24mout, mux_clkroot_lpuart11_oscrc400m, mux_clkroot_lpuart11_oscrc16m, + mux_clkroot_lpuart11_syspll3pfd3, mux_clkroot_lpuart11_syspll3out, mux_clkroot_lpuart11_syspll2pfd3, mux_clkroot_lpuart11_syspll1div5 }; + +/* Mux selector: LPUART12 */ +enum { mux_clkroot_lpuart12_oscrc48mdiv2 = 0, mux_clkroot_lpuart12_osc24mout, mux_clkroot_lpuart12_oscrc400m, mux_clkroot_lpuart12_oscrc16m, + mux_clkroot_lpuart12_syspll3pfd3, mux_clkroot_lpuart12_syspll3out, mux_clkroot_lpuart12_syspll2pfd3, mux_clkroot_lpuart12_syspll1div5 }; + +/* Mux selector: LPI2C1 */ +enum { mux_clkroot_lpi2c1_oscrc48mdiv2 = 0, mux_clkroot_lpi2c1_osc24mout, mux_clkroot_lpi2c1_oscrc400m, mux_clkroot_lpi2c1_oscrc16m, + mux_clkroot_lpi2c1_syspll3div2, mux_clkroot_lpi2c1_syspll1div5, mux_clkroot_lpi2c1_syspll2out, mux_clkroot_lpi2c1_syspll2pfd3 }; + +/* Mux selector: LPI2C2 */ +enum { mux_clkroot_lpi2c2_oscrc48mdiv2 = 0, mux_clkroot_lpi2c2_osc24mout, mux_clkroot_lpi2c2_oscrc400m, mux_clkroot_lpi2c2_oscrc16m, + mux_clkroot_lpi2c2_syspll3div2, mux_clkroot_lpi2c2_syspll1div5, mux_clkroot_lpi2c2_syspll2out, mux_clkroot_lpi2c2_syspll2pfd3 }; + +/* Mux selector: LPI2C3 */ +enum { mux_clkroot_lpi2c3_oscrc48mdiv2 = 0, mux_clkroot_lpi2c3_osc24mout, mux_clkroot_lpi2c3_oscrc400m, mux_clkroot_lpi2c3_oscrc16m, + mux_clkroot_lpi2c3_syspll3div2, mux_clkroot_lpi2c3_syspll1div5, mux_clkroot_lpi2c3_syspll2out, mux_clkroot_lpi2c3_syspll2pfd3 }; + +/* Mux selector: LPI2C4 */ +enum { mux_clkroot_lpi2c4_oscrc48mdiv2 = 0, mux_clkroot_lpi2c4_osc24mout, mux_clkroot_lpi2c4_oscrc400m, mux_clkroot_lpi2c4_oscrc16m, + mux_clkroot_lpi2c4_syspll3div2, mux_clkroot_lpi2c4_syspll1div5, mux_clkroot_lpi2c4_syspll2out, mux_clkroot_lpi2c4_syspll2pfd3 }; + +/* Mux selector: LPI2C5 */ +enum { mux_clkroot_lpi2c5_oscrc48mdiv2 = 0, mux_clkroot_lpi2c5_osc24mout, mux_clkroot_lpi2c5_oscrc400m, mux_clkroot_lpi2c5_oscrc16m, + mux_clkroot_lpi2c5_syspll3pfd3, mux_clkroot_lpi2c5_syspll3out, mux_clkroot_lpi2c5_syspll2pfd3, mux_clkroot_lpi2c5_syspll1div5 }; + +/* Mux selector: LPI2C6 */ +enum { mux_clkroot_lpi2c6_oscrc48mdiv2 = 0, mux_clkroot_lpi2c6_osc24mout, mux_clkroot_lpi2c6_oscrc400m, mux_clkroot_lpi2c6_oscrc16m, + mux_clkroot_lpi2c6_syspll3pfd3, mux_clkroot_lpi2c6_syspll3out, mux_clkroot_lpi2c6_syspll2pfd3, mux_clkroot_lpi2c6_syspll1div5 }; + +/* Mux selector: LPSPI1 */ +enum { mux_clkroot_lpspi1_oscrc48mdiv2 = 0, mux_clkroot_lpspi1_osc24mout, mux_clkroot_lpspi1_oscrc400m, mux_clkroot_lpspi1_oscrc16m, + mux_clkroot_lpspi1_syspll3pfd2, mux_clkroot_lpspi1_syspll1div5, mux_clkroot_lpspi1_syspll2out, mux_clkroot_lpspi1_syspll2pfd3 }; + +/* Mux selector: LPSPI2 */ +enum { mux_clkroot_lpspi2_oscrc48mdiv2 = 0, mux_clkroot_lpspi2_osc24mout, mux_clkroot_lpspi2_oscrc400m, mux_clkroot_lpspi2_oscrc16m, + mux_clkroot_lpspi2_syspll3pfd2, mux_clkroot_lpspi2_syspll1div5, mux_clkroot_lpspi2_syspll2out, mux_clkroot_lpspi2_syspll2pfd3 }; + +/* Mux selector: LPSPI3 */ +enum { mux_clkroot_lpspi3_oscrc48mdiv2 = 0, mux_clkroot_lpspi3_osc24mout, mux_clkroot_lpspi3_oscrc400m, mux_clkroot_lpspi3_oscrc16m, + mux_clkroot_lpspi3_syspll3pfd2, mux_clkroot_lpspi3_syspll1div5, mux_clkroot_lpspi3_syspll2out, mux_clkroot_lpspi3_syspll2pfd3 }; + +/* Mux selector: LPSPI4 */ +enum { mux_clkroot_lpspi4_oscrc48mdiv2 = 0, mux_clkroot_lpspi4_osc24mout, mux_clkroot_lpspi4_oscrc400m, mux_clkroot_lpspi4_oscrc16m, + mux_clkroot_lpspi4_syspll3pfd2, mux_clkroot_lpspi4_syspll1div5, mux_clkroot_lpspi4_syspll2out, mux_clkroot_lpspi4_syspll2pfd3 }; + +/* Mux selector: LPSPI5 */ +enum { mux_clkroot_lpspi5_oscrc48mdiv2 = 0, mux_clkroot_lpspi5_osc24mout, mux_clkroot_lpspi5_oscrc400m, mux_clkroot_lpspi5_oscrc16m, + mux_clkroot_lpspi5_syspll3pfd3, mux_clkroot_lpspi5_syspll3out, mux_clkroot_lpspi5_syspll3pfd2, mux_clkroot_lpspi5_syspll1div5 }; + +/* Mux selector: LPSPI6 */ +enum { mux_clkroot_lpspi6_oscrc48mdiv2 = 0, mux_clkroot_lpspi6_osc24mout, mux_clkroot_lpspi6_oscrc400m, mux_clkroot_lpspi6_oscrc16m, + mux_clkroot_lpspi6_syspll3pfd3, mux_clkroot_lpspi6_syspll3out, mux_clkroot_lpspi6_syspll3pfd2, mux_clkroot_lpspi6_syspll1div5 }; + +/* Mux selector: EMV1 */ +enum { mux_clkroot_emv1_oscrc48mdiv2 = 0, mux_clkroot_emv1_osc24mout, mux_clkroot_emv1_oscrc400m, mux_clkroot_emv1_oscrc16m, + mux_clkroot_emv1_syspll3div2, mux_clkroot_emv1_syspll1div5, mux_clkroot_emv1_syspll2out, mux_clkroot_emv1_syspll2pfd3 }; + +/* Mux selector: EMV2 */ +enum { mux_clkroot_emv2_oscrc48mdiv2 = 0, mux_clkroot_emv2_osc24mout, mux_clkroot_emv2_oscrc400m, mux_clkroot_emv2_oscrc16m, + mux_clkroot_emv2_syspll3div2, mux_clkroot_emv2_syspll1div5, mux_clkroot_emv2_syspll2out, mux_clkroot_emv2_syspll2pfd3 }; + +/* Mux selector: ENET1 */ +enum { mux_clkroot_enet1_oscrc48mdiv2 = 0, mux_clkroot_enet1_osc24mout, mux_clkroot_enet1_oscrc400m, mux_clkroot_enet1_oscrc16m, + mux_clkroot_enet1_syspll1div2, mux_clkroot_enet1_audiopllout, mux_clkroot_enet1_syspll1div5, mux_clkroot_enet1_syspll2pfd1 }; + +/* Mux selector: ENET2 */ +enum { mux_clkroot_enet2_oscrc48mdiv2 = 0, mux_clkroot_enet2_osc24mout, mux_clkroot_enet2_oscrc400m, mux_clkroot_enet2_oscrc16m, + mux_clkroot_enet2_syspll1div2, mux_clkroot_enet2_audiopllout, mux_clkroot_enet2_syspll1div5, mux_clkroot_enet2_syspll2pfd1 }; + +/* Mux selector: ENET_QOS */ +enum { mux_clkroot_enet_qos_oscrc48mdiv2 = 0, mux_clkroot_enet_qos_osc24mout, mux_clkroot_enet_qos_oscrc400m, mux_clkroot_enet_qos_oscrc16m, + mux_clkroot_enet_qos_syspll1div2, mux_clkroot_enet_qos_audiopllout, mux_clkroot_enet_qos_syspll1div5, mux_clkroot_enet_qos_syspll2pfd1 }; + +/* Mux selector: ENET_25M */ +enum { mux_clkroot_enet_25m_oscrc48mdiv2 = 0, mux_clkroot_enet_25m_osc24mout, mux_clkroot_enet_25m_oscrc400m, mux_clkroot_enet_25m_oscrc16m, + mux_clkroot_enet_25m_syspll1div2, mux_clkroot_enet_25m_audiopllout, mux_clkroot_enet_25m_syspll1div5, mux_clkroot_enet_25m_syspll2pfd1 }; + +/* Mux selector: ENET_TIMER1 */ +enum { mux_clkroot_enet_timer1_oscrc48mdiv2 = 0, mux_clkroot_enet_timer1_osc24mout, mux_clkroot_enet_timer1_oscrc400m, mux_clkroot_enet_timer1_oscrc16m, + mux_clkroot_enet_timer1_syspll1div2, mux_clkroot_enet_timer1_audiopllout, mux_clkroot_enet_timer1_syspll1div5, mux_clkroot_enet_timer1_syspll2pfd1 }; + +/* Mux selector: ENET_TIMER2 */ +enum { mux_clkroot_enet_timer2_oscrc48mdiv2 = 0, mux_clkroot_enet_timer2_osc24mout, mux_clkroot_enet_timer2_oscrc400m, mux_clkroot_enet_timer2_oscrc16m, + mux_clkroot_enet_timer2_syspll1div2, mux_clkroot_enet_timer2_audiopllout, mux_clkroot_enet_timer2_syspll1div5, mux_clkroot_enet_timer2_syspll2pfd1 }; + +/* Mux selector: ENET_TIMER3 */ +enum { mux_clkroot_enet_timer3_oscrc48mdiv2 = 0, mux_clkroot_enet_timer3_osc24mout, mux_clkroot_enet_timer3_oscrc400m, mux_clkroot_enet_timer3_oscrc16m, + mux_clkroot_enet_timer3_syspll1div2, mux_clkroot_enet_timer3_audiopllout, mux_clkroot_enet_timer3_syspll1div5, mux_clkroot_enet_timer3_syspll2pfd1 }; + +/* Mux selector: USDHC1 */ +enum { mux_clkroot_usdhc1_oscrc48mdiv2 = 0, mux_clkroot_usdhc1_osc24mout, mux_clkroot_usdhc1_oscrc400m, mux_clkroot_usdhc1_oscrc16m, + mux_clkroot_usdhc1_syspll2pfd2, mux_clkroot_usdhc1_syspll2pfd0, mux_clkroot_usdhc1_syspll1div5, mux_clkroot_usdhc1_armpllout }; + +/* Mux selector: USDHC2 */ +enum { mux_clkroot_usdhc2_oscrc48mdiv2 = 0, mux_clkroot_usdhc2_osc24mout, mux_clkroot_usdhc2_oscrc400m, mux_clkroot_usdhc2_oscrc16m, + mux_clkroot_usdhc2_syspll2pfd2, mux_clkroot_usdhc2_syspll2pfd0, mux_clkroot_usdhc2_syspll1div5, mux_clkroot_usdhc2_armpllout }; + +/* Mux selector: ASRC */ +enum { mux_clkroot_asrc_oscrc48mdiv2 = 0, mux_clkroot_asrc_osc24mout, mux_clkroot_asrc_oscrc400m, mux_clkroot_asrc_oscrc16m, + mux_clkroot_asrc_syspll1div5, mux_clkroot_asrc_syspll3div2, mux_clkroot_asrc_audiopllout, mux_clkroot_asrc_syspll2pfd3 }; + +/* Mux selector: MQS */ +enum { mux_clkroot_mqs_oscrc48mdiv2 = 0, mux_clkroot_mqs_osc24mout, mux_clkroot_mqs_oscrc400m, mux_clkroot_mqs_oscrc16m, + mux_clkroot_mqs_syspll1div5, mux_clkroot_mqs_syspll3div2, mux_clkroot_mqs_audiopllout, mux_clkroot_mqs_syspll2pfd3 }; + +/* Mux selector: MIC */ +enum { mux_clkroot_mic_oscrc48mdiv2 = 0, mux_clkroot_mic_osc24mout, mux_clkroot_mic_oscrc400m, mux_clkroot_mic_oscrc16m, + mux_clkroot_mic_syspll3pfd3, mux_clkroot_mic_syspll3out, mux_clkroot_mic_audiopllout, mux_clkroot_mic_syspll1div5 }; + +/* Mux selector: SPDIF */ +enum { mux_clkroot_spdif_oscrc48mdiv2 = 0, mux_clkroot_spdif_osc24mout, mux_clkroot_spdif_oscrc400m, mux_clkroot_spdif_oscrc16m, + mux_clkroot_spdif_audiopllout, mux_clkroot_spdif_syspll3out, mux_clkroot_spdif_syspll3pfd2, mux_clkroot_spdif_syspll2pfd3 }; + +/* Mux selector: SAI1 */ +enum { mux_clkroot_sai1_oscrc48mdiv2 = 0, mux_clkroot_sai1_osc24mout, mux_clkroot_sai1_oscrc400m, mux_clkroot_sai1_oscrc16m, + mux_clkroot_sai1_audiopllout, mux_clkroot_sai1_syspll3pfd2, mux_clkroot_sai1_syspll1div5, mux_clkroot_sai1_syspll2pfd3 }; + +/* Mux selector: SAI2 */ +enum { mux_clkroot_sai2_oscrc48mdiv2 = 0, mux_clkroot_sai2_osc24mout, mux_clkroot_sai2_oscrc400m, mux_clkroot_sai2_oscrc16m, + mux_clkroot_sai2_audiopllout, mux_clkroot_sai2_syspll3pfd2, mux_clkroot_sai2_syspll1div5, mux_clkroot_sai2_syspll2pfd3 }; + +/* Mux selector: SAI3 */ +enum { mux_clkroot_sai3_oscrc48mdiv2 = 0, mux_clkroot_sai3_osc24mout, mux_clkroot_sai3_oscrc400m, mux_clkroot_sai3_oscrc16m, + mux_clkroot_sai3_audiopllout, mux_clkroot_sai3_syspll3pfd2, mux_clkroot_sai3_syspll1div5, mux_clkroot_sai3_syspll2pfd3 }; + +/* Mux selector: SAI4 */ +enum { mux_clkroot_sai4_oscrc48mdiv2 = 0, mux_clkroot_sai4_osc24mout, mux_clkroot_sai4_oscrc400m, mux_clkroot_sai4_oscrc16m, + mux_clkroot_sai4_syspll3pfd3, mux_clkroot_sai4_syspll3out, mux_clkroot_sai4_audiopllout, mux_clkroot_sai4_syspll1div5 }; + +/* Mux selector: GPU2D */ +enum { mux_clkroot_gpu2d_oscrc48mdiv2 = 0, mux_clkroot_gpu2d_osc24mout, mux_clkroot_gpu2d_oscrc400m, mux_clkroot_gpu2d_oscrc16m, + mux_clkroot_gpu2d_syspll2out, mux_clkroot_gpu2d_syspll2pfd1, mux_clkroot_gpu2d_syspll3out, mux_clkroot_gpu2d_videopllout }; + +/* Mux selector: LCDIF */ +enum { mux_clkroot_lcdif_oscrc48mdiv2 = 0, mux_clkroot_lcdif_osc24mout, mux_clkroot_lcdif_oscrc400m, mux_clkroot_lcdif_oscrc16m, + mux_clkroot_lcdif_syspll2out, mux_clkroot_lcdif_syspll2pfd2, mux_clkroot_lcdif_syspll3pfd0, mux_clkroot_lcdif_videopllout }; + +/* Mux selector: LCDIFV2 */ +enum { mux_clkroot_lcdifv2_oscrc48mdiv2 = 0, mux_clkroot_lcdifv2_osc24mout, mux_clkroot_lcdifv2_oscrc400m, mux_clkroot_lcdifv2_oscrc16m, + mux_clkroot_lcdifv2_syspll2out, mux_clkroot_lcdifv2_syspll2pfd2, mux_clkroot_lcdifv2_syspll3pfd0, mux_clkroot_lcdifv2_videopllout }; + +/* Mux selector: MIPI_REF */ +enum { mux_clkroot_mipi_ref_oscrc48mdiv2 = 0, mux_clkroot_mipi_ref_osc24mout, mux_clkroot_mipi_ref_oscrc400m, mux_clkroot_mipi_ref_oscrc16m, + mux_clkroot_mipi_ref_syspll2out, mux_clkroot_mipi_ref_syspll2pfd0, mux_clkroot_mipi_ref_syspll3pfd0, mux_clkroot_mipi_ref_videopllout }; + +/* Mux selector: MIPI_ESC */ +enum { mux_clkroot_mipi_esc_oscrc48mdiv2 = 0, mux_clkroot_mipi_esc_osc24mout, mux_clkroot_mipi_esc_oscrc400m, mux_clkroot_mipi_esc_oscrc16m, + mux_clkroot_mipi_esc_syspll2out, mux_clkroot_mipi_esc_syspll2pfd0, mux_clkroot_mipi_esc_syspll3pfd0, mux_clkroot_mipi_esc_videopllout }; + +/* Mux selector: CSI2 */ +enum { mux_clkroot_csi2_oscrc48mdiv2 = 0, mux_clkroot_csi2_osc24mout, mux_clkroot_csi2_oscrc400m, mux_clkroot_csi2_oscrc16m, + mux_clkroot_csi2_syspll2pfd2, mux_clkroot_csi2_syspll3out, mux_clkroot_csi2_syspll2pfd0, mux_clkroot_csi2_videopllout }; + +/* Mux selector: CSI2_ESC */ +enum { mux_clkroot_csi2_esc_oscrc48mdiv2 = 0, mux_clkroot_csi2_esc_osc24mout, mux_clkroot_csi2_esc_oscrc400m, mux_clkroot_csi2_esc_oscrc16m, + mux_clkroot_csi2_esc_syspll2pfd2, mux_clkroot_csi2_esc_syspll3out, mux_clkroot_csi2_esc_syspll2pfd0, mux_clkroot_csi2_esc_videopllout }; + +/* Mux selector: CSI2_UI */ +enum { mux_clkroot_csi2_ui_oscrc48mdiv2 = 0, mux_clkroot_csi2_ui_osc24mout, mux_clkroot_csi2_ui_oscrc400m, mux_clkroot_csi2_ui_oscrc16m, + mux_clkroot_csi2_ui_syspll2pfd2, mux_clkroot_csi2_ui_syspll3out, mux_clkroot_csi2_ui_syspll2pfd0, mux_clkroot_csi2_ui_videopllout }; + +/* Mux selector: CSI */ +enum { mux_clkroot_csi_oscrc48mdiv2 = 0, mux_clkroot_csi_osc24mout, mux_clkroot_csi_oscrc400m, mux_clkroot_csi_oscrc16m, + mux_clkroot_csi_syspll2pfd2, mux_clkroot_csi_syspll3out, mux_clkroot_csi_syspll3pfd1, mux_clkroot_csi_videopllout }; + +/* Mux selector: CKO1 */ +enum { mux_clkroot_cko1_oscrc48mdiv2 = 0, mux_clkroot_cko1_osc24mout, mux_clkroot_cko1_oscrc400m, mux_clkroot_cko1_oscrc16m, + mux_clkroot_cko1_syspll2pfd2, mux_clkroot_cko1_syspll2out, mux_clkroot_cko1_syspll3pfd1, mux_clkroot_cko1_syspll1div5 }; + +/* Mux selector: CKO2 */ +enum { mux_clkroot_cko2_oscrc48mdiv2 = 0, mux_clkroot_cko2_osc24mout, mux_clkroot_cko2_oscrc400m, mux_clkroot_cko2_oscrc16m, + mux_clkroot_cko2_syspll2pfd3, mux_clkroot_cko2_oscrc48m, mux_clkroot_cko2_syspll3pfd1, mux_clkroot_cko2_audiopllout }; + + +/* PLL clock source */ +enum { clk_pllarm = 0, clk_pllsys1, clk_pllsys2, clk_pllsys3, clk_pllaudio, clk_pllvideo }; + + /* clang-format on */ @@ -353,6 +675,9 @@ extern int _imxrt_getDevClock(int clock, int *div, int *mux, int *mfd, int *mfn, extern int _imxrt_setDevClock(int clock, int div, int mux, int mfd, int mfn, int state); +extern int _imxrt_setPfdPllFracClock(u8 pfd, u8 clk_pll, u8 frac); + + extern void _imxrt_init(void); diff --git a/hal/armv7m/imxrt/117x/timer.c b/hal/armv7m/imxrt/117x/timer.c index 80c36218..1d52183f 100644 --- a/hal/armv7m/imxrt/117x/timer.c +++ b/hal/armv7m/imxrt/117x/timer.c @@ -72,10 +72,9 @@ void timer_init(void) /* FIXME */ //freq = _imxrt_ccmGetFreq(clk_ipg) / 2; - freq = 400 * 1000 * 1000; + freq = 24 * 1000 * 1000; ticksPerMs = freq / 1000; - - _imxrt_setDevClock(GPT1_CLK, 0, 2, 0, 0, 1); + /* NOTE: clock initialized during clock root setup in hal */ *(timer_common.base + gpt_cr) |= 1 << 15;