diff --git a/riscv-elf.adoc b/riscv-elf.adoc
index 16214b94..e0d9fbfe 100644
--- a/riscv-elf.adoc
+++ b/riscv-elf.adoc
@@ -1567,6 +1567,55 @@ optimize code size and performance of the symbol accessing.
 
 NOTE: Tag_RISCV_x3_reg_usage is treated as 0 if it is not present.
 
+==== GOT load relaxation
+
+  Target Relocation:: R_RISCV_GOT_HI20, R_RISCV_PCREL_LO12_I
+
+  Description:: This relaxation can relax a GOT indirection into PC-relative
+  addressing. This relaxation is intended to optimize the `la` assembly
+  pseudo-instruction, which loads a symbol's address from a GOT entry.
+
+  Condition::
+  - Both `R_RISCV_GOT_HI20` and `R_RISCV_PCREL_LO12_I` are annotated with
+  `R_RISCV_RELAX`.
+
+  - `R_RISCV_GOT_HI20` refers to the location 4 bytes before where
+  `R_RISCV_PCREL_LO12_I` points.
+
+  - The symbol pointed to by `R_RISCV_PCREL_LO12_I` is at the location to
+  which `R_RISCV_GOT_HI20` refers.
+
+  - The symbol's PC-relative address is a link-time constant.
+
+  - The offset between the location to which `R_RISCV_GOT_HI20` refers and
+  the target symbol is within +-2GiB.
+
+  Relaxation::
+  - Instruction sequence associated with `R_RISCV_GOT_HI20` and
+  `R_RISCV_PCREL_LO12_I` can be rewritten to a `auipc` and `addi` to
+  materialize the symbol's address in the PC-relative manner, eliminating
+  a load from the GOT.
+
+  - If this relaxation eliminates all references to the symbol's GOT slot,
+  the linker may opt not to create a GOT slot for that symbol.
+
+  Example::
++
+--
+[,asm]
+----
+label:
+    auipc   t0, 0      # R_RISCV_GOT_HI20 (symbol), R_RISCV_RELAX
+    ld      t0, 0(t0)  # R_RISCV_PCREL_LO12_I (label), R_RISCV_RELAX
+----
+Relaxation result:
+[,asm]
+----
+    auipc   t0, <hi>
+    addi    t0, <lo>
+----
+--
+
 ==== Zero-page Relaxation
 
   Target Relocation:: R_RISCV_HI20, R_RISCV_LO12_I, R_RISCV_LO12_S