diff --git a/cfi_backward.adoc b/cfi_backward.adoc
index 8797df3..4373c35 100644
--- a/cfi_backward.adoc
+++ b/cfi_backward.adoc
@@ -133,7 +133,7 @@ A shadow stack pop operation is defined as a `XLEN` wide read from the
 current top of the shadow stack followed by an increment of the `ssp` by
 `XLEN`.
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -144,7 +144,7 @@ current top of the shadow stack followed by an increment of the `ssp` by
 ], config:{lanes: 1, hspace:1024}}
 ....
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -155,7 +155,7 @@ current top of the shadow stack followed by an increment of the `ssp` by
 ], config:{lanes: 1, hspace:1024}}
 ....
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -167,7 +167,7 @@ current top of the shadow stack followed by an increment of the `ssp` by
 ], config:{lanes: 1, hspace:1024}}
 ....
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  2, name: 'op', attr:'C1'},
@@ -561,7 +561,7 @@ back_cfi_not_enabled:
 The `ssprr` instruction is provided to move the contents of `ssp` to the destination
 register.
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -613,7 +613,7 @@ bits of the `src` register and the `XLEN` bits located on the shadow stack at th
 address specified in the `addr` register. The resulting value from the swap
 operation is then stored into the register specified in the `dst` operand.
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
diff --git a/cfi_csrs.adoc b/cfi_csrs.adoc
index 9e9f435..61beae6 100644
--- a/cfi_csrs.adoc
+++ b/cfi_csrs.adoc
@@ -6,7 +6,7 @@ This chapter specifies the CSR state of the Zicfisslp extension.
 === Machine environment configuration registers (`menvcfg and menvcfgh`)
 
 .Machine environment configuration register (`menvcfg`) for MXLEN=64
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  1, name: 'FIOM'},
@@ -57,7 +57,7 @@ backward-edge and forward-edge CFI at S-mode and at U-mode for each application.
 === Hypervisor environment configuration registers (`henvcfg and henvcfgh`)
 
 .Hypervisor environment configuration register (`henvcfg`) for MXLEN=64
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  1, name: 'FIOM'},
@@ -92,7 +92,7 @@ forward-edge CFI at VS-mode.
 === Machine status registers (`mstatus`)
 
 .Machine-mode status register (`mstatus`) for RV64
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  1, name: 'WPRI'},
@@ -141,7 +141,7 @@ encoded as follows:
 === Supervisor status registers (`sstatus`)
 
 .Supervisor-mode status register (`sstatus`) when `SXLEN=64`
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  1, name: 'WPRI'},
@@ -180,7 +180,7 @@ read-only zero.
 === Virtual supervisor status registers (`vsstatus`)
 
 .Virtual supervisor status register (`vsstatus`) when `VSXLEN=64`
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  1, name: 'WPRI'},
@@ -229,7 +229,7 @@ in `vsstatus` when the CSR is accessed in HS-mode.
 === Machine Security Configuration (`mseccfg`)
 
 .Machine security configuration register (`mseccfg`) when `MXLEN=64`
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  1, name: 'MML'},
@@ -259,7 +259,7 @@ is split into an 8-bit upper label (`UL`), an 8-bit middle label (`ML`), and a
 9-bit lower label (`LL`).
 
 .`lpl` for RV32 and RV64
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits: 9, name: 'LL'},
diff --git a/cfi_forward.adoc b/cfi_forward.adoc
index ae2598f..184ad9c 100644
--- a/cfi_forward.adoc
+++ b/cfi_forward.adoc
@@ -182,7 +182,7 @@ The `lpcll` has the lower landing pad label embedded in the `LLPL` field.
 `lpcll` causes an illegal-instruction exception if the `LLPL` field in the
 instruction does not match the `lpl.LL` field.
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -246,7 +246,7 @@ The `lpcul` instruction matches the 8-bit wide upper label in its `ULPL` field w
 the `lpl.UL` field and causes an illegal-instruction exception on a mismatch. The
 `lpcul` is not a valid target for an indirect call or jump.
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -291,7 +291,7 @@ Before performing an indirect call or indirect jump to a labeled landing pad,
 the `lpl` is loaded with the expected landing pad label. The label is a constant
 encoded into the instructions used to setup the `lpl`.
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
@@ -303,7 +303,7 @@ encoded into the instructions used to setup the `lpl`.
 ], config:{lanes: 1, hspace:1024}}
 ....
 
-[wavedrom, , ]
+[wavedrom, ,svg]
 ....
 {reg: [
   {bits:  7, name: 'opcode', attr:'SYSTEM'},
diff --git a/riscv-cfi.pdf b/riscv-cfi.pdf
index 5785181..634b194 100644
Binary files a/riscv-cfi.pdf and b/riscv-cfi.pdf differ