From c0287c277b8f0e75debb3e62a2e2a1a0c82531ac Mon Sep 17 00:00:00 2001 From: Jiuyang Liu Date: Fri, 30 Aug 2024 11:57:55 +0800 Subject: [PATCH] fixup: release the constraint to enable e8mf8 in EEW=32 --- src/v-st-ext.adoc | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/src/v-st-ext.adoc b/src/v-st-ext.adoc index bfc71ba66..b3f21409f 100644 --- a/src/v-st-ext.adoc +++ b/src/v-st-ext.adoc @@ -271,22 +271,24 @@ vector registers are unused, but in some cases, having more shorter register-resident vectors improves efficiency relative to fewer longer register-resident vectors. -Implementations must provide fractional LMUL settings that allow the -narrowest supported type to occupy a fraction of a vector register -corresponding to the ratio of the narrowest supported type's width to -that of the vector register width. In general, the requirement is to +Implementations must provide fractional LMUL settings that allow at least one +element of the narrowest supported type to occupy a fraction of a vector +register corresponding to the ratio of the narrowest supported type's width to +that of the largest supported type's width. In general, the requirement is to support LMUL {ge} SEW~MIN~/VLEN, where SEW~MIN~ is the narrowest supported SEW value and VLEN is the length of vector register. In the standard -extensions, SEW~MIN~=8. For standard vector extensions with VLEN=32, -fractional LMULs of 1/2 and 1/4 must be supported. For standard vector -extensions with VLEN=64, fractional LMULs of 1/2, 1/4, and 1/8 must be -supported. +extensions, SEW~MIN~=8. For standard vector extensions with EEW=64, fractional +LMULs of 1/2, 1/4 and 1/8 must be supported. For standard vector extensions +with EEW=32, fractional LMULs of 1/2 and 1/4 must be supported, and for EEW=32, +VLEN>=64, fractional LMULs of 1/8 can be supported. NOTE: When LMUL < SEW~MIN~/VLEN, there is no guarantee an implementation would have enough bits in the fractional vector register to store at least one element, as VLEN=ELEN=32, SEW~MIN~=8 is a valid implementation choice, an LMUL of 1/8 would only provide four bits of -storage in a vector register. +storage in a vector register. However, for VLEN>=64, ELEN=32, an LMUL of 1/8 +doesn't provide enough usability due to that the pair of +(e8mf8, e16mf4, e32mf2) can always be replaced by (e8mf4, e16mf2, e32m1). For a given supported fractional LMUL setting, implementations must support SEW settings between SEW~MIN~ and LMUL * ELEN, inclusive.