diff --git a/librz/analysis/arch/hexagon/hexagon_analysis.c b/librz/analysis/arch/hexagon/hexagon_analysis.c deleted file mode 100644 index 180360f627c..00000000000 --- a/librz/analysis/arch/hexagon/hexagon_analysis.c +++ /dev/null @@ -1,1817 +0,0 @@ -// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE - -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -#include -#include -#include -#include -#include -#include -#include "hexagon.h" -#include "hexagon_insn.h" - -int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op) { - switch (hi->instruction) { - case HEX_INS_CALL__R22_2: { - // call #r22:2 - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - op->jump = op->addr + (st32)hi->ops[0].op.imm; - break; - } - case HEX_INS_IF__PU__CALL__R15_2: { - // if (Pu) call #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - break; - } - case HEX_INS_IF__NOT_PU_CALL__R15_2: { - // if !Pu call #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = tstbit (Rs, #0) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = tstbit (Rs, #0) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = tstbit (Rs, #0) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = tstbit (Rs, #0) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = tstbit (Rs, #0) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = tstbit (Rs, #0) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = tstbit (Rs, #0) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = tstbit (Rs, #0) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2: { - // p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2: { - // p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_JUMP__R22_2: { - // jump #r22:2 - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = op->addr + (st32)hi->ops[0].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU__JUMP_NT__R15_2: { - // if (Pu) jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU__JUMP_T__R15_2: { - // if (Pu) jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_JUMP_NT__R15_2: { - // if !Pu jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_JUMP_T__R15_2: { - // if !Pu jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU_NEW__JUMP_NT__R15_2: { - // if (Pu.new) jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__PU_NEW__JUMP_T__R15_2: { - // if (Pu.new) jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_NEW_JUMP_NT__R15_2: { - // if !Pu.new jump:nt #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__NOT_PU_NEW_JUMP_T__R15_2: { - // if !Pu.new jump:t #r15:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__NOT____0__JUMP_NT__R13_2: { - // if (Rs != #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__NOT____0__JUMP_T__R13_2: { - // if (Rs != #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_GT_EQ___0__JUMP_NT__R13_2: { - // if (Rs> = #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_GT_EQ___0__JUMP_T__R13_2: { - // if (Rs> = #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__EQ___0__JUMP_NT__R13_2: { - // if (Rs == #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS__EQ___0__JUMP_T__R13_2: { - // if (Rs == #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_LT_EQ___0__JUMP_NT__R13_2: { - // if (Rs< = #0) jump:nt #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__RS_LT_EQ___0__JUMP_T__R13_2: { - // if (Rs< = #0) jump:t #r13:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_RD____U6___JUMP__R9_2: { - // Rd = #U6 ; jump #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_MULT_RD___RS___JUMP__R9_2: { - // Rd = Rs ; jump #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_DEALLOC_RETURN: { - // dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__PS_NEW__DEALLOC_RETURN_NT: { - // if (Ps.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__PS__DEALLOC_RETURN: { - // if (Ps) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__PS_NEW__DEALLOC_RETURN_T: { - // if (Ps.new) dealloc_return:t - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_NT: { - // if !Ps.new dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__NOT_PS_DEALLOC_RETURN: { - // if !Ps dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_T: { - // if !Ps.new dealloc_return:t - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2: { - // if (cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_T__R9_2: { - // if (cmp.eq (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2: { - // if (!cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_T__R9_2: { - // if (!cmp.eq (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_NT__R9_2: { - // if (cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_T__R9_2: { - // if (cmp.gt (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_NT__R9_2: { - // if (!cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_T__R9_2: { - // if (!cmp.gt (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2: { - // if (cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_T__R9_2: { - // if (cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2: { - // if (!cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_T__R9_2: { - // if (!cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_NT__R9_2: { - // if (cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_T__R9_2: { - // if (cmp.gt (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_NT__R9_2: { - // if (!cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_T__R9_2: { - // if (!cmp.gt (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2: { - // if (cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_T__R9_2: { - // if (cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2: { - // if (!cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_T__R9_2: { - // if (!cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2: { - // if (cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_T__R9_2: { - // if (cmp.eq (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2: { - // if (!cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_T__R9_2: { - // if (!cmp.eq (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_NT__R9_2: { - // if (cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_T__R9_2: { - // if (cmp.gt (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_NT__R9_2: { - // if (!cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_T__R9_2: { - // if (!cmp.gt (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2: { - // if (cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_T__R9_2: { - // if (cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2: { - // if (!cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_T__R9_2: { - // if (!cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[2].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_NT__R9_2: { - // if (tstbit (Ns.new, #0)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_T__R9_2: { - // if (tstbit (Ns.new, #0)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_NT__R9_2: { - // if (!tstbit (Ns.new, #0)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_T__R9_2: { - // if (!tstbit (Ns.new, #0)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_NT__R9_2: { - // if (cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_T__R9_2: { - // if (cmp.eq (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_NT__R9_2: { - // if (!cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_T__R9_2: { - // if (!cmp.eq (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_NT__R9_2: { - // if (cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_T__R9_2: { - // if (cmp.gt (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_NT__R9_2: { - // if (!cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_T__R9_2: { - // if (!cmp.gt (Ns.new, #-1)) jump:t #r9:2 - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = op->addr + (st32)hi->ops[1].op.imm; - op->fail = op->addr + op->size; - break; - } - case HEX_INS_DUPLEX_RD_____1___DEALLOC_RETURN: { - // Rd = #-1 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF___NOT__P0__DEALLOC_RETURN: { - // Rd = #-1 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #-1 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF__P0__DEALLOC_RETURN: { - // Rd = #-1 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD_____1___IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #-1 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___DEALLOC_RETURN: { - // Rd = #u6 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF___NOT__P0__DEALLOC_RETURN: { - // Rd = #u6 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #u6 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF__P0__DEALLOC_RETURN: { - // Rd = #u6 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD____U6___IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = #u6 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___DEALLOC_RETURN: { - // Rd = Rs ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__DEALLOC_RETURN: { - // Rd = Rs ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = Rs ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF__P0__DEALLOC_RETURN: { - // Rd = Rs ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = Rs ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____DEALLOC_RETURN: { - // Rd = add (Rs, #-1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #-1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #-1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #-1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #-1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOC_RETURN: { - // Rd = add (Rs, #1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__DEALLOC_RETURN: { - // Rd = add (Rs, #1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Rs, #1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____DEALLOC_RETURN: { - // Rd = add (Sp, #u6:2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = add (Sp, #u6:2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Sp, #u6:2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__DEALLOC_RETURN: { - // Rd = add (Sp, #u6:2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = add (Sp, #u6:2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOC_RETURN: { - // Rd = and (Rs, #1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOC_RETURN: { - // Rd = and (Rs, #255) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #255) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #255) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__DEALLOC_RETURN: { - // Rd = and (Rs, #255) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = and (Rs, #255) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOC_RETURN: { - // Rd = memb (Rs + #u3:0) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memb (Rs + #u3:0) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memb (Rs + #u3:0) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__DEALLOC_RETURN: { - // Rd = memb (Rs + #u3:0) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memb (Rs + #u3:0) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOC_RETURN: { - // Rd = memh (Rs + #u3:1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memh (Rs + #u3:1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__DEALLOC_RETURN: { - // Rd = memh (Rs + #u3:1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOC_RETURN: { - // Rd = memub (Rs + #u4:0) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memub (Rs + #u4:0) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memub (Rs + #u4:0) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__DEALLOC_RETURN: { - // Rd = memub (Rs + #u4:0) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memub (Rs + #u4:0) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOC_RETURN: { - // Rd = memuh (Rs + #u3:1) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memuh (Rs + #u3:1) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memuh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__DEALLOC_RETURN: { - // Rd = memuh (Rs + #u3:1) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memuh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOC_RETURN: { - // Rd = memw (Rs + #u4:2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memw (Rs + #u4:2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Rs + #u4:2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__DEALLOC_RETURN: { - // Rd = memw (Rs + #u4:2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Rs + #u4:2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN: { - // Rd = memw (Sp + #u5:2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = memw (Sp + #u5:2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Sp + #u5:2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN: { - // Rd = memw (Sp + #u5:2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = memw (Sp + #u5:2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN: { - // Rd = sxtb (Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = sxtb (Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxtb (Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN: { - // Rd = sxtb (Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxtb (Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN: { - // Rd = sxth (Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = sxth (Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxth (Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN: { - // Rd = sxth (Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = sxth (Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN: { - // Rd = zxth (Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rd = zxth (Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = zxth (Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN: { - // Rd = zxth (Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rd = zxth (Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN: { - // Rdd = combine (#0, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN: { - // Rdd = combine (#0, Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#0, Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#0, Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN: { - // Rdd = combine (#1, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#1, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#1, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#1, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#1, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN: { - // Rdd = combine (#2, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#2, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#2, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#2, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#2, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN: { - // Rdd = combine (#3, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (#3, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#3, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (#3, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (#3, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN: { - // Rdd = combine (Rs, #0) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = combine (Rs, #0) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (Rs, #0) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN: { - // Rdd = combine (Rs, #0) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = combine (Rs, #0) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOC_RETURN: { - // Rdd = memd (Sp + #u5:3) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__DEALLOC_RETURN: { - // Rdd = memd (Sp + #u5:3) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = memd (Sp + #u5:3) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__DEALLOC_RETURN: { - // Rdd = memd (Sp + #u5:3) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rdd = memd (Sp + #u5:3) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOC_RETURN: { - // Rx = add (Rs, Rx) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__DEALLOC_RETURN: { - // Rx = add (Rs, Rx) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rs, Rx) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__DEALLOC_RETURN: { - // Rx = add (Rs, Rx) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rs, Rx) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOC_RETURN: { - // Rx = add (Rx, #s7) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__DEALLOC_RETURN: { - // Rx = add (Rx, #s7) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, #s7) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__DEALLOC_RETURN: { - // Rx = add (Rx, #s7) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, #s7) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOC_RETURN: { - // Rx = add (Rx, Rs) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__DEALLOC_RETURN: { - // Rx = add (Rx, Rs) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, Rs) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__DEALLOC_RETURN: { - // Rx = add (Rx, Rs) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__DEALLOC_RETURN_NT: { - // Rx = add (Rx, Rs) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOC_RETURN: { - // if (! p0) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (! p0) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__DEALLOC_RETURN: { - // if (! p0) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOC_RETURN: { - // if (! p0.new) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (! p0.new) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN: { - // if (! p0.new) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (! p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOC_RETURN: { - // if (p0) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (p0) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__DEALLOC_RETURN: { - // if (p0) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOC_RETURN: { - // if (p0.new) Rd = #0 ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN: { - // if (p0.new) Rd = #0 ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN: { - // if (p0.new) Rd = #0 ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT: { - // if (p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____DEALLOC_RETURN: { - // p0 = cmp.eq (Rs, #u2) ; dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__DEALLOC_RETURN: { - // p0 = cmp.eq (Rs, #u2) ; if (! p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT: { - // p0 = cmp.eq (Rs, #u2) ; if (! p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__DEALLOC_RETURN: { - // p0 = cmp.eq (Rs, #u2) ; if (p0) dealloc_return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - case HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__DEALLOC_RETURN_NT: { - // p0 = cmp.eq (Rs, #u2) ; if (p0.new) dealloc_return:nt - op->type = RZ_ANALYSIS_OP_TYPE_RET; - break; - } - } - return op->size; -} diff --git a/librz/analysis/arch/hexagon/hexagon_analysis.h b/librz/analysis/arch/hexagon/hexagon_analysis.h deleted file mode 100644 index da674bfeef0..00000000000 --- a/librz/analysis/arch/hexagon/hexagon_analysis.h +++ /dev/null @@ -1,4 +0,0 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov -// SPDX-License-Identifier: LGPL-3.0-only - -int hexagon_analysis_instruction(HexInsn *hi, RzAnalysisOp *op); diff --git a/librz/analysis/d/cc-hexagon-32.sdb.txt b/librz/analysis/d/cc-hexagon-32.sdb.txt index f6ea3532176..eba9cb0e7e8 100644 --- a/librz/analysis/d/cc-hexagon-32.sdb.txt +++ b/librz/analysis/d/cc-hexagon-32.sdb.txt @@ -9,3 +9,23 @@ cc.hexagon.arg4=r4 cc.hexagon.arg5=r5 cc.hexagon.argn=stack_rev cc.hexagon.ret=r0 + +hvx=cc +cc.hvx.name=hvx +cc.hvx.arg0=v0 +cc.hvx.arg1=v1 +cc.hvx.arg2=v2 +cc.hvx.arg3=v3 +cc.hvx.arg4=v4 +cc.hvx.arg5=v5 +cc.hvx.arg6=v6 +cc.hvx.arg7=v7 +cc.hvx.arg8=v8 +cc.hvx.arg9=v9 +cc.hvx.arg10=v10 +cc.hvx.arg11=v11 +cc.hvx.arg12=v12 +cc.hvx.arg13=v13 +cc.hvx.arg14=v14 +cc.hvx.arg15=v15 +cc.hvx.ret=v0 diff --git a/librz/analysis/d/meson.build b/librz/analysis/d/meson.build index 6835759aede..1b8a3eb38be 100644 --- a/librz/analysis/d/meson.build +++ b/librz/analysis/d/meson.build @@ -3,6 +3,7 @@ sdb_files = [ 'cc-arm-32', 'cc-arm-64', 'cc-avr-8', + 'cc-hexagon-32', 'cc-m68k-32', 'cc-mips-32', 'cc-mips-64', diff --git a/librz/analysis/meson.build b/librz/analysis/meson.build index 289fa94ea95..f9d09721dc4 100644 --- a/librz/analysis/meson.build +++ b/librz/analysis/meson.build @@ -99,15 +99,12 @@ rz_analysis_sources = [ 'p/analysis_xtensa.c', 'p/analysis_z80.c', #'arch/gb/meta_gb_cmt.c', - 'arch/hexagon/hexagon_analysis.c', '../asm/arch/amd29k/amd29k.c', '../asm/arch/arm/winedbg/be_arm.c', '../asm/arch/avr/disassembler.c', '../asm/arch/cr16/cr16_disas.c', '../asm/arch/ebc/ebc_disas.c', '../asm/arch/h8300/h8300_disas.c', - '../asm/arch/hexagon/hexagon.c', - '../asm/arch/hexagon/hexagon_disas.c', '../asm/arch/java/jvm.c', '../asm/arch/mcore/mcore.c', '../asm/arch/msp430/msp430_disas.c', @@ -172,7 +169,6 @@ rz_analysis_inc = [ platform_inc, include_directories( 'arch/gb', - 'arch/hexagon', ) ] diff --git a/librz/analysis/p/analysis_hexagon.c b/librz/analysis/p/analysis_hexagon.c index b7ab04146cd..23cf4ccfc24 100644 --- a/librz/analysis/p/analysis_hexagon.c +++ b/librz/analysis/p/analysis_hexagon.c @@ -1,6 +1,11 @@ -// SPDX-FileCopyrightText: 2018 xvilka +// SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + #include #include #include @@ -8,86 +13,368 @@ #include #include "hexagon.h" #include "hexagon_insn.h" -#include "hexagon_analysis.h" - -static int hexagon_v6_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { - HexInsn hi = { 0 }; - ; - ut32 data = 0; - data = rz_read_le32(buf); - int size = hexagon_disasm_instruction(data, &hi, (ut32)addr); - op->size = size; - if (size <= 0) { - return size; +#include "hexagon_arch.h" + +RZ_API int hexagon_v6_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { + if (analysis->pcalign == 0) { + analysis->pcalign = 0x4; } - op->addr = addr; - return hexagon_analysis_instruction(&hi, op); + HexReversedOpcode rev = { .action = HEXAGON_ANALYSIS, .ana_op = op, .asm_op = NULL }; + + hexagon_reverse_opcode(NULL, &rev, buf, addr); + + return op->size; } -static bool set_reg_profile(RzAnalysis *analysis) { - // TODO: Add missing registers +RZ_API bool set_reg_profile(RzAnalysis *analysis) { const char *p = + "=PC pc\n" - "=SP r29\n" + "=SP R29\n" + "=BP R30\n" + "=LR R31\n" + "=SR usr\n" + "=SN r0\n" "=A0 r0\n" "=A1 r1\n" "=A2 r2\n" "=A3 r3\n" "=A4 r4\n" "=A5 r5\n" - "=BP r30\n" - "=LR r31\n" - "=SN r6\n" - "=ZF z\n" - "=SF s\n" - "=OF ov\n" - "=CF cy\n" - - "gpr r0 .32 0 0\n" - "gpr r1 .32 4 0\n" - "gpr r2 .32 8 0\n" - "gpr r3 .32 12 0\n" - "gpr r4 .32 16 0\n" - "gpr r5 .32 20 0\n" - "gpr r6 .32 24 0\n" - "gpr r7 .32 28 0\n" - "gpr r8 .32 32 0\n" - "gpr r9 .32 36 0\n" - "gpr r10 .32 40 0\n" - "gpr r11 .32 44 0\n" - "gpr r12 .32 48 0\n" - "gpr r13 .32 52 0\n" - "gpr r14 .32 56 0\n" - "gpr r15 .32 60 0\n" - "gpr r16 .32 64 0\n" - "gpr r17 .32 68 0\n" - "gpr r18 .32 72 0\n" - "gpr r19 .32 76 0\n" - "gpr r20 .32 80 0\n" - "gpr r21 .32 84 0\n" - "gpr r22 .32 88 0\n" - "gpr r23 .32 92 0\n" - "gpr r24 .32 96 0\n" - "gpr r25 .32 100 0\n" - "gpr r26 .32 104 0\n" - "gpr r27 .32 108 0\n" - "gpr r28 .32 112 0\n" - "gpr r29 .32 116 0\n" - "gpr r30 .32 120 0\n" - "gpr r31 .32 124 0\n" - "gpr pc .32 128 0\n" - - "gpr psw .32 132 0\n" - "gpr np .1 132.16 0\n" - "gpr ep .1 132.17 0\n" - "gpr ae .1 132.18 0\n" - "gpr id .1 132.19 0\n" - "flg cy .1 132.28 0\n" - "flg ov .1 132.29 0\n" - "flg s .1 132.30 0\n" - "flg z .1 132.31 0\n"; + "=A6 r1:0\n" + "=A7 r3:2\n" + "=A8 r5:4\n" + "=R0 r0\n" + "=R1 r1\n" + "=R2 r1:0\n" + + "gpr lc0 .32 0 0\n" + "gpr sa0 .32 4 0\n" + "gpr lc1 .32 8 0\n" + "gpr sa1 .32 12 0\n" + "gpr p3:0 .32 16 0\n" + "gpr c5 .32 20 0\n" + "gpr pc .32 24 0\n" + "gpr ugp .32 28 0\n" + "gpr gp .32 32 0\n" + "gpr cs0 .32 36 0\n" + "gpr cs1 .32 40 0\n" + "gpr upcyclelo .32 44 0\n" + "gpr upcyclehi .32 48 0\n" + "gpr framelimit .32 52 0\n" + "gpr framekey .32 56 0\n" + "gpr pktcountlo .32 60 0\n" + "gpr pktcounthi .32 64 0\n" + "gpr utimerlo .32 68 0\n" + "gpr utimerhi .32 72 0\n" + "gpr m0 .32 76 0\n" + "gpr m1 .32 80 0\n" + "gpr usr .32 84 0\n" + + "gpr c1:0 .64 88 0\n" + "gpr c3:2 .64 96 0\n" + "gpr c5:4 .64 104 0\n" + "gpr c7:6 .64 112 0\n" + "gpr c9:8 .64 120 0\n" + "gpr c11:10 .64 128 0\n" + "gpr c13:12 .64 136 0\n" + "gpr c15:14 .64 144 0\n" + "gpr c17:16 .64 152 0\n" + "gpr c19:18 .64 160 0\n" + "gpr c31:30 .64 168 0\n" + + "gpr r1:0 .64 176 0\n" + "gpr r3:2 .64 184 0\n" + "gpr r5:4 .64 192 0\n" + "gpr r7:6 .64 200 0\n" + "gpr r9:8 .64 208 0\n" + "gpr r13:12 .64 216 0\n" + "gpr r15:14 .64 224 0\n" + "gpr r17:16 .64 232 0\n" + "gpr r19:18 .64 240 0\n" + "gpr r21:20 .64 248 0\n" + "gpr r23:22 .64 256 0\n" + "gpr r25:24 .64 264 0\n" + "gpr r27:26 .64 272 0\n" + "gpr r11:10 .64 280 0\n" + "gpr r29:28 .64 288 0\n" + "gpr r31:30 .64 296 0\n" + + "gpr gelr .32 304 0\n" + "gpr gsr .32 308 0\n" + "gpr gosp .32 312 0\n" + "gpr gbadva .32 316 0\n" + "gpr g4 .32 320 0\n" + "gpr g5 .32 324 0\n" + "gpr g6 .32 328 0\n" + "gpr g7 .32 332 0\n" + "gpr g8 .32 336 0\n" + "gpr g9 .32 340 0\n" + "gpr g10 .32 344 0\n" + "gpr g11 .32 348 0\n" + "gpr g12 .32 352 0\n" + "gpr g13 .32 356 0\n" + "gpr g14 .32 360 0\n" + "gpr g15 .32 364 0\n" + "gpr gpmucnt4 .32 368 0\n" + "gpr gpmucnt5 .32 372 0\n" + "gpr gpmucnt6 .32 376 0\n" + "gpr gpmucnt7 .32 380 0\n" + "gpr g20 .32 384 0\n" + "gpr g21 .32 388 0\n" + "gpr g22 .32 392 0\n" + "gpr g23 .32 396 0\n" + "gpr gpcyclelo .32 400 0\n" + "gpr gpcyclehi .32 404 0\n" + "gpr gpmucnt0 .32 408 0\n" + "gpr gpmucnt1 .32 412 0\n" + "gpr gpmucnt2 .32 416 0\n" + "gpr gpmucnt3 .32 420 0\n" + "gpr g30 .32 424 0\n" + "gpr g31 .32 428 0\n" + + "gpr g1:0 .64 432 0\n" + "gpr g3:2 .64 440 0\n" + "gpr g5:4 .64 448 0\n" + "gpr g7:6 .64 456 0\n" + "gpr g9:8 .64 464 0\n" + "gpr g11:10 .64 472 0\n" + "gpr g13:12 .64 480 0\n" + "gpr g15:14 .64 488 0\n" + "gpr g17:16 .64 496 0\n" + "gpr g19:18 .64 504 0\n" + "gpr g21:20 .64 512 0\n" + "gpr g23:22 .64 520 0\n" + "gpr g25:24 .64 528 0\n" + "gpr g27:26 .64 536 0\n" + "gpr g29:28 .64 544 0\n" + "gpr g31:30 .64 552 0\n" + + "gpr q0 .128 560 0\n" + "gpr q1 .128 576 0\n" + "gpr q2 .128 592 0\n" + "gpr q3 .128 608 0\n" + + "gpr v3:0 .4096 624 0\n" + "gpr v7:4 .4096 1136 0\n" + "gpr v11:8 .4096 1648 0\n" + "gpr v15:12 .4096 2160 0\n" + "gpr v19:16 .4096 2672 0\n" + "gpr v23:20 .4096 3184 0\n" + "gpr v27:24 .4096 3696 0\n" + "gpr v31:28 .4096 4208 0\n" + + "gpr v0 .1024 4720 0\n" + "gpr v1 .1024 4848 0\n" + "gpr v2 .1024 4976 0\n" + "gpr v3 .1024 5104 0\n" + "gpr v4 .1024 5232 0\n" + "gpr v5 .1024 5360 0\n" + "gpr v6 .1024 5488 0\n" + "gpr v7 .1024 5616 0\n" + "gpr v8 .1024 5744 0\n" + "gpr v9 .1024 5872 0\n" + "gpr v10 .1024 6000 0\n" + "gpr v11 .1024 6128 0\n" + "gpr v12 .1024 6256 0\n" + "gpr v13 .1024 6384 0\n" + "gpr v14 .1024 6512 0\n" + "gpr v15 .1024 6640 0\n" + "gpr v16 .1024 6768 0\n" + "gpr v17 .1024 6896 0\n" + "gpr v18 .1024 7024 0\n" + "gpr v19 .1024 7152 0\n" + "gpr v20 .1024 7280 0\n" + "gpr v21 .1024 7408 0\n" + "gpr v22 .1024 7536 0\n" + "gpr v23 .1024 7664 0\n" + "gpr v24 .1024 7792 0\n" + "gpr v25 .1024 7920 0\n" + "gpr v26 .1024 8048 0\n" + "gpr v27 .1024 8176 0\n" + "gpr v28 .1024 8304 0\n" + "gpr v29 .1024 8432 0\n" + "gpr v30 .1024 8560 0\n" + "gpr v31 .1024 8688 0\n" + + "gpr v1:0 .2048 8816 0\n" + "gpr v3:2 .2048 9072 0\n" + "gpr v5:4 .2048 9328 0\n" + "gpr v7:6 .2048 9584 0\n" + "gpr v9:8 .2048 9840 0\n" + "gpr v11:10 .2048 10096 0\n" + "gpr v13:12 .2048 10352 0\n" + "gpr v15:14 .2048 10608 0\n" + "gpr v17:16 .2048 10864 0\n" + "gpr v19:18 .2048 11120 0\n" + "gpr v21:20 .2048 11376 0\n" + "gpr v23:22 .2048 11632 0\n" + "gpr v25:24 .2048 11888 0\n" + "gpr v27:26 .2048 12144 0\n" + "gpr v29:28 .2048 12400 0\n" + "gpr v31:30 .2048 12656 0\n" + + "gpr r0 .32 12912 0\n" + "gpr r1 .32 12916 0\n" + "gpr r2 .32 12920 0\n" + "gpr r3 .32 12924 0\n" + "gpr r4 .32 12928 0\n" + "gpr r5 .32 12932 0\n" + "gpr r6 .32 12936 0\n" + "gpr r7 .32 12940 0\n" + "gpr r8 .32 12944 0\n" + "gpr r9 .32 12948 0\n" + "gpr r12 .32 12952 0\n" + "gpr r13 .32 12956 0\n" + "gpr r14 .32 12960 0\n" + "gpr r15 .32 12964 0\n" + "gpr r16 .32 12968 0\n" + "gpr r17 .32 12972 0\n" + "gpr r18 .32 12976 0\n" + "gpr r19 .32 12980 0\n" + "gpr r20 .32 12984 0\n" + "gpr r21 .32 12988 0\n" + "gpr r22 .32 12992 0\n" + "gpr r23 .32 12996 0\n" + "gpr r24 .32 13000 0\n" + "gpr r25 .32 13004 0\n" + "gpr r26 .32 13008 0\n" + "gpr r27 .32 13012 0\n" + "gpr r28 .32 13016 0\n" + "gpr r10 .32 13020 0\n" + "gpr r11 .32 13024 0\n" + "gpr r29 .32 13028 0\n" + "gpr r30 .32 13032 0\n" + "gpr r31 .32 13036 0\n" + + "gpr p0 .32 13040 0\n" + "gpr p1 .32 13044 0\n" + "gpr p2 .32 13048 0\n" + "gpr p3 .32 13052 0\n" + + "gpr sgp0 .32 13056 0\n" + "gpr sgp1 .32 13060 0\n" + "gpr stid .32 13064 0\n" + "gpr elr .32 13068 0\n" + "gpr badva0 .32 13072 0\n" + "gpr badva1 .32 13076 0\n" + "gpr ssr .32 13080 0\n" + "gpr ccr .32 13084 0\n" + "gpr htid .32 13088 0\n" + "gpr badva .32 13092 0\n" + "gpr imask .32 13096 0\n" + "gpr gevb .32 13100 0\n" + "gpr s12 .32 13104 0\n" + "gpr s13 .32 13108 0\n" + "gpr s14 .32 13112 0\n" + "gpr s15 .32 13116 0\n" + "gpr evb .32 13120 0\n" + "gpr modectl .32 13124 0\n" + "gpr syscfg .32 13128 0\n" + "gpr s19 .32 13132 0\n" + "gpr ipendad .32 13136 0\n" + "gpr vid .32 13140 0\n" + "gpr vid1 .32 13144 0\n" + "gpr bestwait .32 13148 0\n" + "gpr s24 .32 13152 0\n" + "gpr schedcfg .32 13156 0\n" + "gpr s26 .32 13160 0\n" + "gpr cfgbase .32 13164 0\n" + "gpr diag .32 13168 0\n" + "gpr rev .32 13172 0\n" + "gpr pcyclelo .32 13176 0\n" + "gpr pcyclehi .32 13180 0\n" + "gpr isdbst .32 13184 0\n" + "gpr isdbcfg0 .32 13188 0\n" + "gpr isdbcfg1 .32 13192 0\n" + "gpr livelock .32 13196 0\n" + "gpr brkptpc0 .32 13200 0\n" + "gpr brkptcfg0 .32 13204 0\n" + "gpr brkptpc1 .32 13208 0\n" + "gpr brkptcfg1 .32 13212 0\n" + "gpr isdbmbxin .32 13216 0\n" + "gpr isdbmbxout .32 13220 0\n" + "gpr isdben .32 13224 0\n" + "gpr isdbgpr .32 13228 0\n" + "gpr pmucnt4 .32 13232 0\n" + "gpr pmucnt5 .32 13236 0\n" + "gpr pmucnt6 .32 13240 0\n" + "gpr pmucnt7 .32 13244 0\n" + "gpr pmucnt0 .32 13248 0\n" + "gpr pmucnt1 .32 13252 0\n" + "gpr pmucnt2 .32 13256 0\n" + "gpr pmucnt3 .32 13260 0\n" + "gpr pmuevtcfg .32 13264 0\n" + "gpr s53 .32 13268 0\n" + "gpr pmuevtcfg1 .32 13272 0\n" + "gpr pmustid1 .32 13276 0\n" + "gpr timerlo .32 13280 0\n" + "gpr timerhi .32 13284 0\n" + "gpr s58 .32 13288 0\n" + "gpr s59 .32 13292 0\n" + "gpr s60 .32 13296 0\n" + "gpr s61 .32 13300 0\n" + "gpr s62 .32 13304 0\n" + "gpr s63 .32 13308 0\n" + "gpr commit1t .32 13312 0\n" + "gpr commit2t .32 13316 0\n" + "gpr commit3t .32 13320 0\n" + "gpr commit4t .32 13324 0\n" + "gpr commit5t .32 13328 0\n" + "gpr commit6t .32 13332 0\n" + "gpr pcycle1t .32 13336 0\n" + "gpr pcycle2t .32 13340 0\n" + "gpr pcycle3t .32 13344 0\n" + "gpr pcycle4t .32 13348 0\n" + "gpr pcycle5t .32 13352 0\n" + "gpr pcycle6t .32 13356 0\n" + "gpr stfinst .32 13360 0\n" + "gpr isdbcmd .32 13364 0\n" + "gpr isdbver .32 13368 0\n" + "gpr brkptinfo .32 13372 0\n" + "gpr rgdr3 .32 13376 0\n" + "gpr s1:0 .64 13380 0\n" + "gpr s3:2 .64 13388 0\n" + "gpr s5:4 .64 13396 0\n" + "gpr s7:6 .64 13404 0\n" + "gpr s9:8 .64 13412 0\n" + "gpr s11:10 .64 13420 0\n" + "gpr s13:12 .64 13428 0\n" + "gpr s15:14 .64 13436 0\n" + "gpr s17:16 .64 13444 0\n" + "gpr s19:18 .64 13452 0\n" + "gpr s21:20 .64 13460 0\n" + "gpr s23:22 .64 13468 0\n" + "gpr s25:24 .64 13476 0\n" + "gpr s27:26 .64 13484 0\n" + "gpr s29:28 .64 13492 0\n" + "gpr s31:30 .64 13500 0\n" + "gpr s33:32 .64 13508 0\n" + "gpr s35:34 .64 13516 0\n" + "gpr s37:36 .64 13524 0\n" + "gpr s39:38 .64 13532 0\n" + "gpr s41:40 .64 13540 0\n" + "gpr s43:42 .64 13548 0\n" + "gpr s45:44 .64 13556 0\n" + "gpr s47:46 .64 13564 0\n" + "gpr s49:48 .64 13572 0\n" + "gpr s51:50 .64 13580 0\n" + "gpr s53:52 .64 13588 0\n" + "gpr s55:54 .64 13596 0\n" + "gpr s57:56 .64 13604 0\n" + "gpr s59:58 .64 13612 0\n" + "gpr s61:60 .64 13620 0\n" + "gpr s63:62 .64 13628 0\n" + "gpr s65:64 .64 13636 0\n" + "gpr s67:66 .64 13644 0\n" + "gpr s69:68 .64 13652 0\n" + "gpr s71:70 .64 13660 0\n" + "gpr s73:72 .64 13668 0\n" + "gpr s75:74 .64 13676 0\n" + "gpr s77:76 .64 13684 0\n" + "gpr s79:78 .64 13692 0\n"; return rz_reg_set_profile_string(analysis->reg, p); } diff --git a/librz/asm/arch/hexagon/hexagon.c b/librz/asm/arch/hexagon/hexagon.c index 2ab1afaa7c0..ff016648bf7 100644 --- a/librz/asm/arch/hexagon/hexagon.c +++ b/librz/asm/arch/hexagon/hexagon.c @@ -1,237 +1,897 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov +// SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + #include #include #include #include #include #include +#include +#include #include "hexagon.h" +#include "hexagon_insn.h" +#include "hexagon_arch.h" -// TODO: Handle also control reg pairs -char *hex_get_cntl_reg(int opreg) { - switch (opreg) { - case HEX_REG_SA0: - return "SA0"; - case HEX_REG_LC0: +char *hex_get_ctr_regs(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_CTR_REGS_LC0: return "LC0"; - case HEX_REG_SA1: - return "SA1"; - case HEX_REG_LC1: + case HEX_REG_CTR_REGS_SA0: + return "SA0"; + case HEX_REG_CTR_REGS_LC1: return "LC1"; - case HEX_REG_P: - return "P"; - case HEX_REG_M0: - return "M0"; - case HEX_REG_M1: - return "M1"; - case HEX_REG_USR: - return "USR"; - case HEX_REG_PC: + case HEX_REG_CTR_REGS_SA1: + return "SA1"; + case HEX_REG_CTR_REGS_P3_0: + return "P3:0"; + case HEX_REG_CTR_REGS_C5: + return "C5"; + case HEX_REG_CTR_REGS_PC: return "PC"; - case HEX_REG_UGP: + case HEX_REG_CTR_REGS_UGP: return "UGP"; - case HEX_REG_GP: + case HEX_REG_CTR_REGS_GP: return "GP"; - case HEX_REG_CS0: + case HEX_REG_CTR_REGS_CS0: return "CS0"; - case HEX_REG_CS1: + case HEX_REG_CTR_REGS_CS1: return "CS1"; - case HEX_REG_UPCYCLELO: + case HEX_REG_CTR_REGS_UPCYCLELO: return "UPCYCLELO"; - case HEX_REG_UPCYCLEHI: + case HEX_REG_CTR_REGS_UPCYCLEHI: return "UPCYCLEHI"; - case HEX_REG_FRAMELIMIT: + case HEX_REG_CTR_REGS_FRAMELIMIT: return "FRAMELIMIT"; - case HEX_REG_FRAMEKEY: + case HEX_REG_CTR_REGS_FRAMEKEY: return "FRAMEKEY"; - case HEX_REG_PKTCOUNTLO: + case HEX_REG_CTR_REGS_PKTCOUNTLO: return "PKTCOUNTLO"; - case HEX_REG_PKTCOUNTHI: + case HEX_REG_CTR_REGS_PKTCOUNTHI: return "PKTCOUNTHI"; - case HEX_REG_UTIMERLO: + case HEX_REG_CTR_REGS_UTIMERLO: return "UTIMERLO"; - case HEX_REG_UTIMERHI: + case HEX_REG_CTR_REGS_UTIMERHI: return "UTIMERHI"; + case HEX_REG_CTR_REGS_M0: + return "M0"; + case HEX_REG_CTR_REGS_M1: + return "M1"; + case HEX_REG_CTR_REGS_USR: + return "USR"; + } +} + +char *hex_get_ctr_regs64(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_CTR_REGS64_C1_0: + return "C1:0"; + case HEX_REG_CTR_REGS64_C3_2: + return "C3:2"; + case HEX_REG_CTR_REGS64_C5_4: + return "C5:4"; + case HEX_REG_CTR_REGS64_C7_6: + return "C7:6"; + case HEX_REG_CTR_REGS64_C9_8: + return "C9:8"; + case HEX_REG_CTR_REGS64_C11_10: + return "C11:10"; + case HEX_REG_CTR_REGS64_CS: + return "C13:12"; + case HEX_REG_CTR_REGS64_UPCYCLE: + return "C15:14"; + case HEX_REG_CTR_REGS64_C17_16: + return "C17:16"; + case HEX_REG_CTR_REGS64_PKTCOUNT: + return "C19:18"; + case HEX_REG_CTR_REGS64_UTIMER: + return "C31:30"; + } +} + +char *hex_get_double_regs(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_DOUBLE_REGS_D0: + return "R1:0"; + case HEX_REG_DOUBLE_REGS_D1: + return "R3:2"; + case HEX_REG_DOUBLE_REGS_D2: + return "R5:4"; + case HEX_REG_DOUBLE_REGS_D3: + return "R7:6"; + case HEX_REG_DOUBLE_REGS_D4: + return "R9:8"; + case HEX_REG_DOUBLE_REGS_D6: + return "R13:12"; + case HEX_REG_DOUBLE_REGS_D7: + return "R15:14"; + case HEX_REG_DOUBLE_REGS_D8: + return "R17:16"; + case HEX_REG_DOUBLE_REGS_D9: + return "R19:18"; + case HEX_REG_DOUBLE_REGS_D10: + return "R21:20"; + case HEX_REG_DOUBLE_REGS_D11: + return "R23:22"; + case HEX_REG_DOUBLE_REGS_D12: + return "R25:24"; + case HEX_REG_DOUBLE_REGS_D13: + return "R27:26"; + case HEX_REG_DOUBLE_REGS_D5: + return "R11:10"; + case HEX_REG_DOUBLE_REGS_D14: + return "R29:28"; + case HEX_REG_DOUBLE_REGS_D15: + return "R31:30"; + } +} + +char *hex_get_general_double_low8_regs(int opcode_reg) { + opcode_reg = opcode_reg << 1; + if (opcode_reg > 6) { // HEX_REG_D3 == 6 + opcode_reg = (opcode_reg & 0x7) | 0x10; + } + switch (opcode_reg) { + default: + return ""; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D11: + return "R23:22"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D10: + return "R21:20"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D9: + return "R19:18"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D8: + return "R17:16"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D3: + return "R7:6"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D2: + return "R5:4"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D1: + return "R3:2"; + case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D0: + return "R1:0"; + } +} + +char *hex_get_general_sub_regs(int opcode_reg) { + if (opcode_reg > 7) { // HEX_REG_R7 == 7 + opcode_reg = (opcode_reg & 0x7) | 0x10; + } + switch (opcode_reg) { + default: + return ""; + case HEX_REG_GENERAL_SUB_REGS_R23: + return "R23"; + case HEX_REG_GENERAL_SUB_REGS_R22: + return "R22"; + case HEX_REG_GENERAL_SUB_REGS_R21: + return "R21"; + case HEX_REG_GENERAL_SUB_REGS_R20: + return "R20"; + case HEX_REG_GENERAL_SUB_REGS_R19: + return "R19"; + case HEX_REG_GENERAL_SUB_REGS_R18: + return "R18"; + case HEX_REG_GENERAL_SUB_REGS_R17: + return "R17"; + case HEX_REG_GENERAL_SUB_REGS_R16: + return "R16"; + case HEX_REG_GENERAL_SUB_REGS_R7: + return "R7"; + case HEX_REG_GENERAL_SUB_REGS_R6: + return "R6"; + case HEX_REG_GENERAL_SUB_REGS_R5: + return "R5"; + case HEX_REG_GENERAL_SUB_REGS_R4: + return "R4"; + case HEX_REG_GENERAL_SUB_REGS_R3: + return "R3"; + case HEX_REG_GENERAL_SUB_REGS_R2: + return "R2"; + case HEX_REG_GENERAL_SUB_REGS_R1: + return "R1"; + case HEX_REG_GENERAL_SUB_REGS_R0: + return "R0"; + } +} + +char *hex_get_guest_regs(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_GUEST_REGS_GELR: + return "GELR"; + case HEX_REG_GUEST_REGS_GSR: + return "GSR"; + case HEX_REG_GUEST_REGS_GOSP: + return "GOSP"; + case HEX_REG_GUEST_REGS_G3: + return "GBADVA"; + case HEX_REG_GUEST_REGS_G4: + return "G4"; + case HEX_REG_GUEST_REGS_G5: + return "G5"; + case HEX_REG_GUEST_REGS_G6: + return "G6"; + case HEX_REG_GUEST_REGS_G7: + return "G7"; + case HEX_REG_GUEST_REGS_G8: + return "G8"; + case HEX_REG_GUEST_REGS_G9: + return "G9"; + case HEX_REG_GUEST_REGS_G10: + return "G10"; + case HEX_REG_GUEST_REGS_G11: + return "G11"; + case HEX_REG_GUEST_REGS_G12: + return "G12"; + case HEX_REG_GUEST_REGS_G13: + return "G13"; + case HEX_REG_GUEST_REGS_G14: + return "G14"; + case HEX_REG_GUEST_REGS_G15: + return "G15"; + case HEX_REG_GUEST_REGS_GPMUCNT4: + return "GPMUCNT4"; + case HEX_REG_GUEST_REGS_GPMUCNT5: + return "GPMUCNT5"; + case HEX_REG_GUEST_REGS_GPMUCNT6: + return "GPMUCNT6"; + case HEX_REG_GUEST_REGS_GPMUCNT7: + return "GPMUCNT7"; + case HEX_REG_GUEST_REGS_G20: + return "G20"; + case HEX_REG_GUEST_REGS_G21: + return "G21"; + case HEX_REG_GUEST_REGS_G22: + return "G22"; + case HEX_REG_GUEST_REGS_G23: + return "G23"; + case HEX_REG_GUEST_REGS_GPCYCLELO: + return "GPCYCLELO"; + case HEX_REG_GUEST_REGS_GPCYCLEHI: + return "GPCYCLEHI"; + case HEX_REG_GUEST_REGS_GPMUCNT0: + return "GPMUCNT0"; + case HEX_REG_GUEST_REGS_GPMUCNT1: + return "GPMUCNT1"; + case HEX_REG_GUEST_REGS_GPMUCNT2: + return "GPMUCNT2"; + case HEX_REG_GUEST_REGS_GPMUCNT3: + return "GPMUCNT3"; + case HEX_REG_GUEST_REGS_G30: + return "G30"; + case HEX_REG_GUEST_REGS_G31: + return "G31"; + } +} + +char *hex_get_guest_regs64(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_GUEST_REGS64_G1_0: + return "G1:0"; + case HEX_REG_GUEST_REGS64_G3_2: + return "G3:2"; + case HEX_REG_GUEST_REGS64_G5_4: + return "G5:4"; + case HEX_REG_GUEST_REGS64_G7_6: + return "G7:6"; + case HEX_REG_GUEST_REGS64_G9_8: + return "G9:8"; + case HEX_REG_GUEST_REGS64_G11_10: + return "G11:10"; + case HEX_REG_GUEST_REGS64_G13_12: + return "G13:12"; + case HEX_REG_GUEST_REGS64_G15_14: + return "G15:14"; + case HEX_REG_GUEST_REGS64_G17_16: + return "G17:16"; + case HEX_REG_GUEST_REGS64_G19_18: + return "G19:18"; + case HEX_REG_GUEST_REGS64_G21_20: + return "G21:20"; + case HEX_REG_GUEST_REGS64_G23_22: + return "G23:22"; + case HEX_REG_GUEST_REGS64_G25_24: + return "G25:24"; + case HEX_REG_GUEST_REGS64_G27_26: + return "G27:26"; + case HEX_REG_GUEST_REGS64_G29_28: + return "G29:28"; + case HEX_REG_GUEST_REGS64_G31_30: + return "G31:30"; + } +} + +char *hex_get_hvx_qr(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_HVX_QR_Q0: + return "Q0"; + case HEX_REG_HVX_QR_Q1: + return "Q1"; + case HEX_REG_HVX_QR_Q2: + return "Q2"; + case HEX_REG_HVX_QR_Q3: + return "Q3"; + } +} + +char *hex_get_hvx_vqr(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_HVX_VQR_VQ0: + return "V3:0"; + case HEX_REG_HVX_VQR_VQ1: + return "V7:4"; + case HEX_REG_HVX_VQR_VQ2: + return "V11:8"; + case HEX_REG_HVX_VQR_VQ3: + return "V15:12"; + case HEX_REG_HVX_VQR_VQ4: + return "V19:16"; + case HEX_REG_HVX_VQR_VQ5: + return "V23:20"; + case HEX_REG_HVX_VQR_VQ6: + return "V27:24"; + case HEX_REG_HVX_VQR_VQ7: + return "V31:28"; + } +} + +char *hex_get_hvx_vr(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_HVX_VR_V0: + return "V0"; + case HEX_REG_HVX_VR_V1: + return "V1"; + case HEX_REG_HVX_VR_V2: + return "V2"; + case HEX_REG_HVX_VR_V3: + return "V3"; + case HEX_REG_HVX_VR_V4: + return "V4"; + case HEX_REG_HVX_VR_V5: + return "V5"; + case HEX_REG_HVX_VR_V6: + return "V6"; + case HEX_REG_HVX_VR_V7: + return "V7"; + case HEX_REG_HVX_VR_V8: + return "V8"; + case HEX_REG_HVX_VR_V9: + return "V9"; + case HEX_REG_HVX_VR_V10: + return "V10"; + case HEX_REG_HVX_VR_V11: + return "V11"; + case HEX_REG_HVX_VR_V12: + return "V12"; + case HEX_REG_HVX_VR_V13: + return "V13"; + case HEX_REG_HVX_VR_V14: + return "V14"; + case HEX_REG_HVX_VR_V15: + return "V15"; + case HEX_REG_HVX_VR_V16: + return "V16"; + case HEX_REG_HVX_VR_V17: + return "V17"; + case HEX_REG_HVX_VR_V18: + return "V18"; + case HEX_REG_HVX_VR_V19: + return "V19"; + case HEX_REG_HVX_VR_V20: + return "V20"; + case HEX_REG_HVX_VR_V21: + return "V21"; + case HEX_REG_HVX_VR_V22: + return "V22"; + case HEX_REG_HVX_VR_V23: + return "V23"; + case HEX_REG_HVX_VR_V24: + return "V24"; + case HEX_REG_HVX_VR_V25: + return "V25"; + case HEX_REG_HVX_VR_V26: + return "V26"; + case HEX_REG_HVX_VR_V27: + return "V27"; + case HEX_REG_HVX_VR_V28: + return "V28"; + case HEX_REG_HVX_VR_V29: + return "V29"; + case HEX_REG_HVX_VR_V30: + return "V30"; + case HEX_REG_HVX_VR_V31: + return "V31"; + } +} + +char *hex_get_hvx_wr(int opcode_reg) { + switch (opcode_reg) { default: - return ""; + return ""; + case HEX_REG_HVX_WR_W0: + return "V1:0"; + case HEX_REG_HVX_WR_W1: + return "V3:2"; + case HEX_REG_HVX_WR_W2: + return "V5:4"; + case HEX_REG_HVX_WR_W3: + return "V7:6"; + case HEX_REG_HVX_WR_W4: + return "V9:8"; + case HEX_REG_HVX_WR_W5: + return "V11:10"; + case HEX_REG_HVX_WR_W6: + return "V13:12"; + case HEX_REG_HVX_WR_W7: + return "V15:14"; + case HEX_REG_HVX_WR_W8: + return "V17:16"; + case HEX_REG_HVX_WR_W9: + return "V19:18"; + case HEX_REG_HVX_WR_W10: + return "V21:20"; + case HEX_REG_HVX_WR_W11: + return "V23:22"; + case HEX_REG_HVX_WR_W12: + return "V25:24"; + case HEX_REG_HVX_WR_W13: + return "V27:26"; + case HEX_REG_HVX_WR_W14: + return "V29:28"; + case HEX_REG_HVX_WR_W15: + return "V31:30"; } } -char *hex_get_sys_reg(int opreg) { - static char tmp[5]; - switch (opreg) { - case HEX_REG_SGP0: +char *hex_get_int_regs(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_INT_REGS_R0: + return "R0"; + case HEX_REG_INT_REGS_R1: + return "R1"; + case HEX_REG_INT_REGS_R2: + return "R2"; + case HEX_REG_INT_REGS_R3: + return "R3"; + case HEX_REG_INT_REGS_R4: + return "R4"; + case HEX_REG_INT_REGS_R5: + return "R5"; + case HEX_REG_INT_REGS_R6: + return "R6"; + case HEX_REG_INT_REGS_R7: + return "R7"; + case HEX_REG_INT_REGS_R8: + return "R8"; + case HEX_REG_INT_REGS_R9: + return "R9"; + case HEX_REG_INT_REGS_R12: + return "R12"; + case HEX_REG_INT_REGS_R13: + return "R13"; + case HEX_REG_INT_REGS_R14: + return "R14"; + case HEX_REG_INT_REGS_R15: + return "R15"; + case HEX_REG_INT_REGS_R16: + return "R16"; + case HEX_REG_INT_REGS_R17: + return "R17"; + case HEX_REG_INT_REGS_R18: + return "R18"; + case HEX_REG_INT_REGS_R19: + return "R19"; + case HEX_REG_INT_REGS_R20: + return "R20"; + case HEX_REG_INT_REGS_R21: + return "R21"; + case HEX_REG_INT_REGS_R22: + return "R22"; + case HEX_REG_INT_REGS_R23: + return "R23"; + case HEX_REG_INT_REGS_R24: + return "R24"; + case HEX_REG_INT_REGS_R25: + return "R25"; + case HEX_REG_INT_REGS_R26: + return "R26"; + case HEX_REG_INT_REGS_R27: + return "R27"; + case HEX_REG_INT_REGS_R28: + return "R28"; + case HEX_REG_INT_REGS_R10: + return "R10"; + case HEX_REG_INT_REGS_R11: + return "R11"; + case HEX_REG_INT_REGS_R29: + return "R29"; + case HEX_REG_INT_REGS_R30: + return "R30"; + case HEX_REG_INT_REGS_R31: + return "R31"; + } +} + +char *hex_get_int_regs_low8(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_INT_REGS_LOW8_R7: + return "R7"; + case HEX_REG_INT_REGS_LOW8_R6: + return "R6"; + case HEX_REG_INT_REGS_LOW8_R5: + return "R5"; + case HEX_REG_INT_REGS_LOW8_R4: + return "R4"; + case HEX_REG_INT_REGS_LOW8_R3: + return "R3"; + case HEX_REG_INT_REGS_LOW8_R2: + return "R2"; + case HEX_REG_INT_REGS_LOW8_R1: + return "R1"; + case HEX_REG_INT_REGS_LOW8_R0: + return "R0"; + } +} + +char *hex_get_mod_regs(int opcode_reg) { + opcode_reg |= 6; + + switch (opcode_reg) { + default: + return ""; + case HEX_REG_MOD_REGS_M0: + return "M0"; + case HEX_REG_MOD_REGS_M1: + return "M1"; + } +} + +char *hex_get_pred_regs(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_PRED_REGS_P0: + return "P0"; + case HEX_REG_PRED_REGS_P1: + return "P1"; + case HEX_REG_PRED_REGS_P2: + return "P2"; + case HEX_REG_PRED_REGS_P3: + return "P3"; + } +} + +char *hex_get_sys_regs(int opcode_reg) { + switch (opcode_reg) { + default: + return ""; + case HEX_REG_SYS_REGS_SGP0: return "SGP0"; - case HEX_REG_SGP1: + case HEX_REG_SYS_REGS_SGP1: return "SGP1"; - case HEX_REG_STID: + case HEX_REG_SYS_REGS_STID: return "STID"; - case HEX_REG_ELR: + case HEX_REG_SYS_REGS_ELR: return "ELR"; - case HEX_REG_BADVA0: + case HEX_REG_SYS_REGS_BADVA0: return "BADVA0"; - case HEX_REG_BADVA1: + case HEX_REG_SYS_REGS_BADVA1: return "BADVA1"; - case HEX_REG_SSR: + case HEX_REG_SYS_REGS_SSR: return "SSR"; - case HEX_REG_CCR: + case HEX_REG_SYS_REGS_CCR: return "CCR"; - case HEX_REG_HTID: + case HEX_REG_SYS_REGS_HTID: return "HTID"; - case HEX_REG_BADVA: + case HEX_REG_SYS_REGS_BADVA: return "BADVA"; - case HEX_REG_IMASK: + case HEX_REG_SYS_REGS_IMASK: return "IMASK"; - case HEX_REG_EVB: + case HEX_REG_SYS_REGS_GEVB: + return "GEVB"; + case HEX_REG_SYS_REGS_S12: + return "S12"; + case HEX_REG_SYS_REGS_S13: + return "S13"; + case HEX_REG_SYS_REGS_S14: + return "S14"; + case HEX_REG_SYS_REGS_S15: + return "S15"; + case HEX_REG_SYS_REGS_EVB: return "EVB"; - case HEX_REG_MODECTL: + case HEX_REG_SYS_REGS_MODECTL: return "MODECTL"; - case HEX_REG_SYSCFG: + case HEX_REG_SYS_REGS_SYSCFG: return "SYSCFG"; - case HEX_REG_IPEND: - return "IPEND"; - case HEX_REG_VID: + case HEX_REG_SYS_REGS_S19: + return "S19"; + case HEX_REG_SYS_REGS_IPENDAD: + return "IPENDAD"; + case HEX_REG_SYS_REGS_VID: return "VID"; - case HEX_REG_IAD: - return "IAD"; - case HEX_REG_IEL: - return "IEL"; - case HEX_REG_IAHL: - return "IAHL"; - case HEX_REG_CFGBASE: + case HEX_REG_SYS_REGS_VID1: + return "VID1"; + case HEX_REG_SYS_REGS_BESTWAIT: + return "BESTWAIT"; + case HEX_REG_SYS_REGS_S24: + return "S24"; + case HEX_REG_SYS_REGS_SCHEDCFG: + return "SCHEDCFG"; + case HEX_REG_SYS_REGS_S26: + return "S26"; + case HEX_REG_SYS_REGS_CFGBASE: return "CFGBASE"; - case HEX_REG_DIAG: + case HEX_REG_SYS_REGS_DIAG: return "DIAG"; - case HEX_REG_REV: + case HEX_REG_SYS_REGS_REV: return "REV"; - case HEX_REG_PCYCLELO: + case HEX_REG_SYS_REGS_PCYCLELO: return "PCYCLELO"; - case HEX_REG_PCYCLEHI: + case HEX_REG_SYS_REGS_PCYCLEHI: return "PCYCLEHI"; - case HEX_REG_ISDBST: + case HEX_REG_SYS_REGS_ISDBST: return "ISDBST"; - case HEX_REG_ISDBCFG0: + case HEX_REG_SYS_REGS_ISDBCFG0: return "ISDBCFG0"; - case HEX_REG_ISDBCFG1: + case HEX_REG_SYS_REGS_ISDBCFG1: return "ISDBCFG1"; - case HEX_REG_BRKPTPC0: + case HEX_REG_SYS_REGS_LIVELOCK: + return "LIVELOCK"; + case HEX_REG_SYS_REGS_BRKPTPC0: return "BRKPTPC0"; - case HEX_REG_BRKPTCFG0: + case HEX_REG_SYS_REGS_BRKPTCFG0: return "BRKPTCFG0"; - case HEX_REG_BRKPTPC1: + case HEX_REG_SYS_REGS_BRKPTPC1: return "BRKPTPC1"; - case HEX_REG_BRKPTCFG1: + case HEX_REG_SYS_REGS_BRKPTCFG1: return "BRKPTCFG1"; - case HEX_REG_ISDBMBXIN: + case HEX_REG_SYS_REGS_ISDBMBXIN: return "ISDBMBXIN"; - case HEX_REG_ISDBMBXOUT: + case HEX_REG_SYS_REGS_ISDBMBXOUT: return "ISDBMBXOUT"; - case HEX_REG_ISDBEN: + case HEX_REG_SYS_REGS_ISDBEN: return "ISDBEN"; - case HEX_REG_ISDBGPR: + case HEX_REG_SYS_REGS_ISDBGPR: return "ISDBGPR"; - case HEX_REG_PMUCNT0: + case HEX_REG_SYS_REGS_PMUCNT4: + return "PMUCNT4"; + case HEX_REG_SYS_REGS_PMUCNT5: + return "PMUCNT5"; + case HEX_REG_SYS_REGS_PMUCNT6: + return "PMUCNT6"; + case HEX_REG_SYS_REGS_PMUCNT7: + return "PMUCNT7"; + case HEX_REG_SYS_REGS_PMUCNT0: return "PMUCNT0"; - case HEX_REG_PMUCNT1: + case HEX_REG_SYS_REGS_PMUCNT1: return "PMUCNT1"; - case HEX_REG_PMUCNT2: + case HEX_REG_SYS_REGS_PMUCNT2: return "PMUCNT2"; - case HEX_REG_PMUCNT3: + case HEX_REG_SYS_REGS_PMUCNT3: return "PMUCNT3"; - case HEX_REG_PMUEVTCFG: + case HEX_REG_SYS_REGS_PMUEVTCFG: return "PMUEVTCFG"; - case HEX_REG_PMUCFG: - return "PMUCFG"; - default: - sprintf(tmp, "S%d", opreg); - return tmp; + case HEX_REG_SYS_REGS_S53: + return "S53"; + case HEX_REG_SYS_REGS_PMUEVTCFG1: + return "PMUEVTCFG1"; + case HEX_REG_SYS_REGS_PMUSTID1: + return "PMUSTID1"; + case HEX_REG_SYS_REGS_TIMERLO: + return "TIMERLO"; + case HEX_REG_SYS_REGS_TIMERHI: + return "TIMERHI"; + case HEX_REG_SYS_REGS_S58: + return "S58"; + case HEX_REG_SYS_REGS_S59: + return "S59"; + case HEX_REG_SYS_REGS_S60: + return "S60"; + case HEX_REG_SYS_REGS_S61: + return "S61"; + case HEX_REG_SYS_REGS_S62: + return "S62"; + case HEX_REG_SYS_REGS_S63: + return "S63"; + case HEX_REG_SYS_REGS_COMMIT1T: + return "COMMIT1T"; + case HEX_REG_SYS_REGS_COMMIT2T: + return "COMMIT2T"; + case HEX_REG_SYS_REGS_COMMIT3T: + return "COMMIT3T"; + case HEX_REG_SYS_REGS_COMMIT4T: + return "COMMIT4T"; + case HEX_REG_SYS_REGS_COMMIT5T: + return "COMMIT5T"; + case HEX_REG_SYS_REGS_COMMIT6T: + return "COMMIT6T"; + case HEX_REG_SYS_REGS_PCYCLE1T: + return "PCYCLE1T"; + case HEX_REG_SYS_REGS_PCYCLE2T: + return "PCYCLE2T"; + case HEX_REG_SYS_REGS_PCYCLE3T: + return "PCYCLE3T"; + case HEX_REG_SYS_REGS_PCYCLE4T: + return "PCYCLE4T"; + case HEX_REG_SYS_REGS_PCYCLE5T: + return "PCYCLE5T"; + case HEX_REG_SYS_REGS_PCYCLE6T: + return "PCYCLE6T"; + case HEX_REG_SYS_REGS_STFINST: + return "STFINST"; + case HEX_REG_SYS_REGS_ISDBCMD: + return "ISDBCMD"; + case HEX_REG_SYS_REGS_ISDBVER: + return "ISDBVER"; + case HEX_REG_SYS_REGS_BRKPTINFO: + return "BRKPTINFO"; + case HEX_REG_SYS_REGS_RGDR3: + return "RGDR3"; } } -char *hex_get_sub_reg(int opreg) { - switch (opreg) { - case HEX_SUB_REG_R0: - return "R0"; - case HEX_SUB_REG_R1: - return "R1"; - case HEX_SUB_REG_R2: - return "R2"; - case HEX_SUB_REG_R3: - return "R3"; - case HEX_SUB_REG_R4: - return "R4"; - case HEX_SUB_REG_R5: - return "R5"; - case HEX_SUB_REG_R6: - return "R6"; - case HEX_SUB_REG_R7: - return "R7"; - case HEX_SUB_REG_R16: - return "R16"; - case HEX_SUB_REG_R17: - return "R17"; - case HEX_SUB_REG_R18: - return "R18"; - case HEX_SUB_REG_R19: - return "R19"; - case HEX_SUB_REG_R20: - return "R20"; - case HEX_SUB_REG_R21: - return "R21"; - case HEX_SUB_REG_R22: - return "R22"; - case HEX_SUB_REG_R23: - return "R23"; +char *hex_get_sys_regs64(int opcode_reg) { + switch (opcode_reg) { default: return ""; + case HEX_REG_SYS_REGS64_S1_0: + return "S1:0"; + case HEX_REG_SYS_REGS64_S3_2: + return "S3:2"; + case HEX_REG_SYS_REGS64_S5_4: + return "S5:4"; + case HEX_REG_SYS_REGS64_S7_6: + return "S7:6"; + case HEX_REG_SYS_REGS64_S9_8: + return "S9:8"; + case HEX_REG_SYS_REGS64_S11_10: + return "S11:10"; + case HEX_REG_SYS_REGS64_S13_12: + return "S13:12"; + case HEX_REG_SYS_REGS64_S15_14: + return "S15:14"; + case HEX_REG_SYS_REGS64_S17_16: + return "S17:16"; + case HEX_REG_SYS_REGS64_S19_18: + return "S19:18"; + case HEX_REG_SYS_REGS64_S21_20: + return "S21:20"; + case HEX_REG_SYS_REGS64_S23_22: + return "S23:22"; + case HEX_REG_SYS_REGS64_S25_24: + return "S25:24"; + case HEX_REG_SYS_REGS64_S27_26: + return "S27:26"; + case HEX_REG_SYS_REGS64_S29_28: + return "S29:28"; + case HEX_REG_SYS_REGS64_S31_30: + return "S31:30"; + case HEX_REG_SYS_REGS64_S33_32: + return "S33:32"; + case HEX_REG_SYS_REGS64_S35_34: + return "S35:34"; + case HEX_REG_SYS_REGS64_S37_36: + return "S37:36"; + case HEX_REG_SYS_REGS64_S39_38: + return "S39:38"; + case HEX_REG_SYS_REGS64_S41_40: + return "S41:40"; + case HEX_REG_SYS_REGS64_S43_42: + return "S43:42"; + case HEX_REG_SYS_REGS64_S45_44: + return "S45:44"; + case HEX_REG_SYS_REGS64_S47_46: + return "S47:46"; + case HEX_REG_SYS_REGS64_S49_48: + return "S49:48"; + case HEX_REG_SYS_REGS64_S51_50: + return "S51:50"; + case HEX_REG_SYS_REGS64_S53_52: + return "S53:52"; + case HEX_REG_SYS_REGS64_S55_54: + return "S55:54"; + case HEX_REG_SYS_REGS64_S57_56: + return "S57:56"; + case HEX_REG_SYS_REGS64_S59_58: + return "S59:58"; + case HEX_REG_SYS_REGS64_S61_60: + return "S61:60"; + case HEX_REG_SYS_REGS64_S63_62: + return "S63:62"; + case HEX_REG_SYS_REGS64_S65_64: + return "S65:64"; + case HEX_REG_SYS_REGS64_S67_66: + return "S67:66"; + case HEX_REG_SYS_REGS64_S69_68: + return "S69:68"; + case HEX_REG_SYS_REGS64_S71_70: + return "S71:70"; + case HEX_REG_SYS_REGS64_S73_72: + return "S73:72"; + case HEX_REG_SYS_REGS64_S75_74: + return "S75:74"; + case HEX_REG_SYS_REGS64_S77_76: + return "S77:76"; + case HEX_REG_SYS_REGS64_S79_78: + return "S79:78"; } } -char *hex_get_sub_regpair(int opreg) { - switch (opreg) { - case HEX_SUB_REGPAIR_R1_R0: - return "R1:R0"; - case HEX_SUB_REGPAIR_R3_R2: - return "R3:R2"; - case HEX_SUB_REGPAIR_R5_R4: - return "R5:R4"; - case HEX_SUB_REGPAIR_R7_R6: - return "R7:R6"; - case HEX_SUB_REGPAIR_R17_R16: - return "R17:R16"; - case HEX_SUB_REGPAIR_R19_R18: - return "R19:R18"; - case HEX_SUB_REGPAIR_R21_R20: - return "R21:R20"; - case HEX_SUB_REGPAIR_R23_R22: - return "R23:R22"; - default: - return ""; +/** + * \brief Resolves the 3 bit value of an Nt.new reg to the general register of the producer. + * + * \param addr The address of the current instruction. + * \param reg_num Bits of Nt.new reg. + * \param p The current packet. + * \return int The number of the general register. Or UT32_MAX if any error occured. + */ +int resolve_n_register(const int reg_num, const ut32 addr, const HexPkt *p) { + // .new values are documented in Programmers Reference Manual + if (reg_num <= 1 || reg_num >= 8) { + return UT32_MAX; } -} -inline bool hex_if_duplex(uint32_t insn_word) { - if ((insn_word & (3 << 14)) == 0) { - return true; + ut8 ahead = (reg_num >> 1); + ut8 i = hexagon_get_pkt_index_of_addr(addr, p); + if (i == UT8_MAX) { + return UT32_MAX; } - return false; -} -// Constant extender value -ut32 constant_extender = 1; + ut8 prod_i = i; // Producer index + HexInsn *hi; + RzListIter *it; + rz_list_foreach_prev(p->insn, it, hi) { + if (ahead == 0) { + break; + } + if (hi->addr < addr) { + if (hi->instruction == HEX_INS_A4_EXT) { + --prod_i; + continue; + } + --ahead; + --prod_i; + } + } + + hi = rz_list_get_n(p->insn, prod_i); -void hex_op_extend(HexOp *op) { - if ((constant_extender != 1) && (op->type == HEX_OP_TYPE_IMM)) { - op->op.imm = ((op->op.imm) & 0x3F) | (constant_extender); + if (!hi) { + return UT32_MAX; + } + if (hi->instruction == HEX_INS_A4_EXT) { + return UT32_MAX; } - constant_extender = 1; -} -void hex_op_extend_off(HexOp *op, int offset) { - if ((constant_extender != 1) && (op->type == HEX_OP_TYPE_IMM)) { - op->op.imm = (op->op.imm) >> offset; - hex_op_extend(op); + for (ut8 i = 0; i < 6; ++i) { + if (hi->ops[i].attr & HEX_OP_REG_OUT) { + return hi->ops[i].op.reg; + } } + return UT32_MAX; } diff --git a/librz/asm/arch/hexagon/hexagon.h b/librz/asm/arch/hexagon/hexagon.h index 2670ce2ee72..953aa34dd12 100644 --- a/librz/asm/arch/hexagon/hexagon.h +++ b/librz/asm/arch/hexagon/hexagon.h @@ -1,18 +1,26 @@ -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov +// SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + #ifndef HEXAGON_H #define HEXAGON_H +#define MAX_CONST_EXT 512 +#define HEXAGON_STATE_PKTS 8 + // Predicates - declare the predicate state typedef enum { HEX_NOPRED, // no conditional execution HEX_PRED_TRUE, // if (Pd) ... HEX_PRED_FALSE, // if (!Pd) ... - HEX_PRED_TRUE_NEW, // if (Pd.new) ... - HEX_PRED_FALSE_NEW, // if (!Pd.new) ... + HEX_PRED_NEW, // if (Pd.new) or if (!Pd.new) } HexPred; +// TODO NOT IN USE // Pre/post-fixes, different types typedef enum { HEX_PF_RND = 1, // :rnd @@ -34,10 +42,7 @@ typedef enum { typedef enum { HEX_OP_TYPE_IMM, HEX_OP_TYPE_REG, - HEX_OP_TYPE_PREDICATE, - HEX_OP_TYPE_CONTROL, - HEX_OP_TYPE_SYSTEM, - HEX_OP_TYPE_OPT, // Do not really use in the C code + // TODO It might be useful to differ between control, HVX, guest regs etc. Also see HexOp } HexOpType; // Attributes - .H/.L, const extender @@ -46,223 +51,477 @@ typedef enum { HEX_OP_REG_HI = 1 << 1, // Rn.H marker HEX_OP_REG_LO = 1 << 2, // Rn.L marker HEX_OP_REG_PAIR = 1 << 3, // Is this a register pair? + HEX_OP_REG_QUADRUPLE = 1 << 4, // Is it a register with 4 sub registers? + HEX_OP_REG_OUT = 1 << 5, // Is the register the destination register? + HEX_OP_IMM_SCALED = 1 << 6 // Is the immediate shifted? } HexOpAttr; +typedef enum { + HEX_NO_LOOP = 0, + HEX_LOOP_0 = 1, // Is packet of loop0 + HEX_LOOP_1 = 1 << 1, // Is packet of loop1 + HEX_LOOP_01 = 1 << 2 // Belongs to loop 0 and 1 +} HexLoopAttr; + +typedef struct { + bool first_insn; + bool last_insn; + char syntax_prefix[8]; // Package indicator + char syntax_postfix[24]; // for ":endloop" string. +} HexPktInfo; + typedef struct { ut8 type; union { ut8 reg; // + additional Hi or Lo selector // + additional shift // + additional :brev // - ut32 imm; - ut8 pred; // predicates - P0-P3 registers - ut8 cr; // control register - ut8 sys; // system control register + st64 imm; } op; - ut8 attr; + HexOpAttr attr; + ut8 shift; } HexOp; typedef struct { + ut32 opcode; + ut8 parse_bits; int instruction; ut32 mask; - HexPred predicate; // predicate set if set - ut16 pf; // additional prefixes (bitmap) + HexPred pred; // Predicate type bool duplex; // is part of duplex container? bool compound; // is part of compound instruction? - bool last; // is last in instruction packet? int shift; // Optional shift left is it true? + HexPktInfo pkt_info; // Packet related information. First/last instr., prefix and postfix for mnemonic etc. ut8 op_count; HexOp ops[6]; - char mnem[128]; // Instruction mnemonic + char mnem_infix[128]; // The mnemonic without the pre- and postfix. + char mnem[192]; // Instruction mnemonic + ut32 addr; // Memory address the instruction is located. + RzAsmOp asm_op; + RzAnalysisOp ana_op; } HexInsn; -// Instruction container (currently only 2 instructions) -// Can handle duplexes typedef struct { - bool duplex; - HexInsn ins[2]; // Or make it pointer + size? -} HexInsnCont; + RzList *insn; // List of instructions. + bool last_instr_present; // Has an instruction the parsing bits 0b11 set (is last instruction). + bool is_valid; // Is it a valid packet? Do we know which instruction is the first? + ut32 hw_loop0_addr; // Start address of hardware loop 0 + ut32 hw_loop1_addr; // Start address of hardware loop 1 + ut64 last_access; // Last time accessed in milliseconds + ut32 pkt_addr; // Address of the packet. Equals the address of the first instruction. + bool is_eob; // Is this packet the end of a code block? E.g. contains unconditional jmp. +} HexPkt; + +typedef struct { + ut32 addr; // Address of the instruction which gets the extender applied. + ut32 const_ext; // The constant extender value. +} HexConstExt; -// Instruction packet (Maximum - 4 instructions) -// Can handle up to 4 instructions or 1 duplex + 2 instructions -// Can have a loop marks +/** + * \brief Buffer packets for reversed instructions. + * + */ typedef struct { - bool loop0; // :endloop0 marker - bool loop1; // :endloop1 marker - int cont_cnt; - HexInsnCont ins[4]; // Or make it pointer + size? -} HexInsnPkt; + HexPkt pkts[HEXAGON_STATE_PKTS]; // buffered instructions + RzList *const_ext_l; // Constant extender values. + RzAsm rz_asm; // Copy of RzAsm struct. Holds certain flags of interesed for disassembly formatting. +} HexState; +typedef enum { + HEX_REG_CTR_REGS_SA0 = 0, // c0 + HEX_REG_CTR_REGS_LC0 = 1, // c1 + HEX_REG_CTR_REGS_SA1 = 2, // c2 + HEX_REG_CTR_REGS_LC1 = 3, // c3 + HEX_REG_CTR_REGS_P3_0 = 4, // c4 + HEX_REG_CTR_REGS_C5 = 5, // c5 + HEX_REG_CTR_REGS_M0 = 6, // c6 + HEX_REG_CTR_REGS_M1 = 7, // c7 + HEX_REG_CTR_REGS_USR = 8, // c8 + HEX_REG_CTR_REGS_PC = 9, // c9 + HEX_REG_CTR_REGS_UGP = 10, // c10 + HEX_REG_CTR_REGS_GP = 11, // c11 + HEX_REG_CTR_REGS_CS0 = 12, // c12 + HEX_REG_CTR_REGS_CS1 = 13, // c13 + HEX_REG_CTR_REGS_UPCYCLELO = 14, // c14 + HEX_REG_CTR_REGS_UPCYCLEHI = 15, // c15 + HEX_REG_CTR_REGS_FRAMELIMIT = 16, // c16 + HEX_REG_CTR_REGS_FRAMEKEY = 17, // c17 + HEX_REG_CTR_REGS_PKTCOUNTLO = 18, // c18 + HEX_REG_CTR_REGS_PKTCOUNTHI = 19, // c19 + HEX_REG_CTR_REGS_UTIMERLO = 30, // c30 + HEX_REG_CTR_REGS_UTIMERHI = 31, // c31 +} HEX_CTR_REGS; // CtrRegs + +typedef enum { + HEX_REG_CTR_REGS64_C1_0 = 0, // lc0:sa0 + HEX_REG_CTR_REGS64_C3_2 = 2, // lc1:sa1 + HEX_REG_CTR_REGS64_C5_4 = 4, + HEX_REG_CTR_REGS64_C7_6 = 6, // m1:0 + HEX_REG_CTR_REGS64_C9_8 = 8, + HEX_REG_CTR_REGS64_C11_10 = 10, + HEX_REG_CTR_REGS64_CS = 12, // cs1:0 + HEX_REG_CTR_REGS64_UPCYCLE = 14, // upcycle + HEX_REG_CTR_REGS64_C17_16 = 16, + HEX_REG_CTR_REGS64_PKTCOUNT = 18, // pktcount + HEX_REG_CTR_REGS64_UTIMER = 30, // utimer +} HEX_CTR_REGS64; // CtrRegs64 + +typedef enum { + HEX_REG_DOUBLE_REGS_D0 = 0, + HEX_REG_DOUBLE_REGS_D1 = 2, + HEX_REG_DOUBLE_REGS_D2 = 4, + HEX_REG_DOUBLE_REGS_D3 = 6, + HEX_REG_DOUBLE_REGS_D4 = 8, + HEX_REG_DOUBLE_REGS_D5 = 10, + HEX_REG_DOUBLE_REGS_D6 = 12, + HEX_REG_DOUBLE_REGS_D7 = 14, + HEX_REG_DOUBLE_REGS_D8 = 16, + HEX_REG_DOUBLE_REGS_D9 = 18, + HEX_REG_DOUBLE_REGS_D10 = 20, + HEX_REG_DOUBLE_REGS_D11 = 22, + HEX_REG_DOUBLE_REGS_D12 = 24, + HEX_REG_DOUBLE_REGS_D13 = 26, + HEX_REG_DOUBLE_REGS_D14 = 28, + HEX_REG_DOUBLE_REGS_D15 = 30, // lr:fp +} HEX_DOUBLE_REGS; // DoubleRegs + +typedef enum { + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D0 = 0, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D1 = 2, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D2 = 4, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D3 = 6, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D8 = 16, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D9 = 18, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D10 = 20, + HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D11 = 22, +} HEX_GENERAL_DOUBLE_LOW8_REGS; // GeneralDoubleLow8Regs typedef enum { - HEX_INSN_CLASS_CEXT = 0, // Constant extender - HEX_INSN_CLASS_J1 = 1, // Jump - HEX_INSN_CLASS_J2 = 2, // Jump - HEX_INSN_CLASS_LD_ST = 3, // Load/Store - HEX_INSN_CLASS_LD_ST_COND_GP = 4, // Load/Store conditional or GP relative - HEX_INSN_CLASS_J3 = 5, // Jump - HEX_INSN_CLASS_CR = 6, // Control register instructions - HEX_INSN_CLASS_ALU32 = 7, // ALU32 - HEX_INSN_CLASS_XTYPE = 8, // XTYPE - HEX_INSN_CLASS_LD = 9, // Just load instructions - HEX_INSN_CLASS_ST = 10, // Just store instructions - HEX_INSN_CLASS_ALU32_1 = 11, // ALU32 - HEX_INSN_CLASS_XTYPE_1 = 12, // XTYPE again - HEX_INSN_CLASS_XTYPE_2 = 13, // XTYPE one more time - HEX_INSN_CLASS_XTYPE_3 = 14, // And again, XTYPE - HEX_INSN_CLASS_ALU32_2 = 12, // ALU32 again -} HEX_INSN_CLASS; + HEX_REG_GENERAL_SUB_REGS_R0 = 0, + HEX_REG_GENERAL_SUB_REGS_R1 = 1, + HEX_REG_GENERAL_SUB_REGS_R2 = 2, + HEX_REG_GENERAL_SUB_REGS_R3 = 3, + HEX_REG_GENERAL_SUB_REGS_R4 = 4, + HEX_REG_GENERAL_SUB_REGS_R5 = 5, + HEX_REG_GENERAL_SUB_REGS_R6 = 6, + HEX_REG_GENERAL_SUB_REGS_R7 = 7, + HEX_REG_GENERAL_SUB_REGS_R16 = 16, + HEX_REG_GENERAL_SUB_REGS_R17 = 17, + HEX_REG_GENERAL_SUB_REGS_R18 = 18, + HEX_REG_GENERAL_SUB_REGS_R19 = 19, + HEX_REG_GENERAL_SUB_REGS_R20 = 20, + HEX_REG_GENERAL_SUB_REGS_R21 = 21, + HEX_REG_GENERAL_SUB_REGS_R22 = 22, + HEX_REG_GENERAL_SUB_REGS_R23 = 23, +} HEX_GENERAL_SUB_REGS; // GeneralSubRegs typedef enum { - HEX_REG_R0 = 0, - HEX_REG_R1 = 1, - HEX_REG_R2 = 2, - HEX_REG_R3 = 3, - HEX_REG_R4 = 4, - HEX_REG_R5 = 5, - HEX_REG_R6 = 6, - HEX_REG_R7 = 7, - HEX_REG_R8 = 8, - HEX_REG_R9 = 9, - HEX_REG_R10 = 10, - HEX_REG_R11 = 11, - HEX_REG_R12 = 12, - HEX_REG_R13 = 13, - HEX_REG_R14 = 14, - HEX_REG_R15 = 15, - HEX_REG_R16 = 16, - HEX_REG_R17 = 17, - HEX_REG_R18 = 18, - HEX_REG_R19 = 19, - HEX_REG_R20 = 20, - HEX_REG_R21 = 21, - HEX_REG_R22 = 22, - HEX_REG_R23 = 23, - HEX_REG_R24 = 24, - HEX_REG_R25 = 25, - HEX_REG_R26 = 26, - HEX_REG_R27 = 27, - HEX_REG_R28 = 28, - HEX_REG_R29 = 29, - HEX_REG_R30 = 30, - HEX_REG_R31 = 31, -} HEX_REG; - -// TODO: Also add regpair values - -// Control registers + HEX_REG_GUEST_REGS_GELR = 0, // g0 + HEX_REG_GUEST_REGS_GSR = 1, // g1 + HEX_REG_GUEST_REGS_GOSP = 2, // g2 + HEX_REG_GUEST_REGS_G3 = 3, // g3 + HEX_REG_GUEST_REGS_G4 = 4, + HEX_REG_GUEST_REGS_G5 = 5, + HEX_REG_GUEST_REGS_G6 = 6, + HEX_REG_GUEST_REGS_G7 = 7, + HEX_REG_GUEST_REGS_G8 = 8, + HEX_REG_GUEST_REGS_G9 = 9, + HEX_REG_GUEST_REGS_G10 = 10, + HEX_REG_GUEST_REGS_G11 = 11, + HEX_REG_GUEST_REGS_G12 = 12, + HEX_REG_GUEST_REGS_G13 = 13, + HEX_REG_GUEST_REGS_G14 = 14, + HEX_REG_GUEST_REGS_G15 = 15, + HEX_REG_GUEST_REGS_GPMUCNT4 = 16, // g16 + HEX_REG_GUEST_REGS_GPMUCNT5 = 17, // g17 + HEX_REG_GUEST_REGS_GPMUCNT6 = 18, // g18 + HEX_REG_GUEST_REGS_GPMUCNT7 = 19, // g19 + HEX_REG_GUEST_REGS_G20 = 20, + HEX_REG_GUEST_REGS_G21 = 21, + HEX_REG_GUEST_REGS_G22 = 22, + HEX_REG_GUEST_REGS_G23 = 23, + HEX_REG_GUEST_REGS_GPCYCLELO = 24, // g24 + HEX_REG_GUEST_REGS_GPCYCLEHI = 25, // g25 + HEX_REG_GUEST_REGS_GPMUCNT0 = 26, // g26 + HEX_REG_GUEST_REGS_GPMUCNT1 = 27, // g27 + HEX_REG_GUEST_REGS_GPMUCNT2 = 28, // g28 + HEX_REG_GUEST_REGS_GPMUCNT3 = 29, // g29 + HEX_REG_GUEST_REGS_G30 = 30, + HEX_REG_GUEST_REGS_G31 = 31, +} HEX_GUEST_REGS; // GuestRegs + typedef enum { - // Loop registers - HEX_REG_SA0 = 0, // C0 - HEX_REG_LC0 = 1, // C1 - HEX_REG_SA1 = 2, // C2 - HEX_REG_LC1 = 3, // C3 - HEX_REG_P = 4, // C4 - 4 of 8bit registers - // C5 is reserved - // Modifier registers - HEX_REG_M0 = 6, // C6 - HEX_REG_M1 = 7, // C7 - HEX_REG_USR = 8, // C8 // User Status Register - HEX_REG_PC = 9, // C9 // Program counter - HEX_REG_UGP = 10, // C10 // User General Pointer - HEX_REG_GP = 11, // C11 // Global Pointer - // Circular Start registers - HEX_REG_CS0 = 12, // C12 - HEX_REG_CS1 = 13, // C13 - // Cycle Count registers - HEX_REG_UPCYCLELO = 14, // C14 - HEX_REG_UPCYCLEHI = 15, // C15 - HEX_REG_FRAMELIMIT = 16, // C16 // Stack Bounds register - HEX_REG_FRAMEKEY = 17, // C17 // Stack Smash register - // Packet Count registers - HEX_REG_PKTCOUNTLO = 18, // C18 - HEX_REG_PKTCOUNTHI = 19, // C19 - // C20 - C29 are reserved - // Qtimer registers - HEX_REG_UTIMERLO = 30, // C30 - HEX_REG_UTIMERHI = 31, // C31 -} HEX_CR_REG; - -// Supervisor control registers + HEX_REG_GUEST_REGS64_G1_0 = 0, + HEX_REG_GUEST_REGS64_G3_2 = 2, + HEX_REG_GUEST_REGS64_G5_4 = 4, + HEX_REG_GUEST_REGS64_G7_6 = 6, + HEX_REG_GUEST_REGS64_G9_8 = 8, + HEX_REG_GUEST_REGS64_G11_10 = 10, + HEX_REG_GUEST_REGS64_G13_12 = 12, + HEX_REG_GUEST_REGS64_G15_14 = 14, + HEX_REG_GUEST_REGS64_G17_16 = 16, + HEX_REG_GUEST_REGS64_G19_18 = 18, + HEX_REG_GUEST_REGS64_G21_20 = 20, + HEX_REG_GUEST_REGS64_G23_22 = 22, + HEX_REG_GUEST_REGS64_G25_24 = 24, + HEX_REG_GUEST_REGS64_G27_26 = 26, + HEX_REG_GUEST_REGS64_G29_28 = 28, + HEX_REG_GUEST_REGS64_G31_30 = 30, +} HEX_GUEST_REGS64; // GuestRegs64 + +typedef enum { + HEX_REG_HVX_QR_Q0 = 0, + HEX_REG_HVX_QR_Q1 = 1, + HEX_REG_HVX_QR_Q2 = 2, + HEX_REG_HVX_QR_Q3 = 3, +} HEX_HVX_QR; // HvxQR + +typedef enum { + HEX_REG_HVX_VQR_VQ0 = 0, + HEX_REG_HVX_VQR_VQ1 = 4, + HEX_REG_HVX_VQR_VQ2 = 8, + HEX_REG_HVX_VQR_VQ3 = 12, + HEX_REG_HVX_VQR_VQ4 = 16, + HEX_REG_HVX_VQR_VQ5 = 20, + HEX_REG_HVX_VQR_VQ6 = 24, + HEX_REG_HVX_VQR_VQ7 = 28, +} HEX_HVX_VQR; // HvxVQR + +typedef enum { + HEX_REG_HVX_VR_V0 = 0, + HEX_REG_HVX_VR_V1 = 1, + HEX_REG_HVX_VR_V2 = 2, + HEX_REG_HVX_VR_V3 = 3, + HEX_REG_HVX_VR_V4 = 4, + HEX_REG_HVX_VR_V5 = 5, + HEX_REG_HVX_VR_V6 = 6, + HEX_REG_HVX_VR_V7 = 7, + HEX_REG_HVX_VR_V8 = 8, + HEX_REG_HVX_VR_V9 = 9, + HEX_REG_HVX_VR_V10 = 10, + HEX_REG_HVX_VR_V11 = 11, + HEX_REG_HVX_VR_V12 = 12, + HEX_REG_HVX_VR_V13 = 13, + HEX_REG_HVX_VR_V14 = 14, + HEX_REG_HVX_VR_V15 = 15, + HEX_REG_HVX_VR_V16 = 16, + HEX_REG_HVX_VR_V17 = 17, + HEX_REG_HVX_VR_V18 = 18, + HEX_REG_HVX_VR_V19 = 19, + HEX_REG_HVX_VR_V20 = 20, + HEX_REG_HVX_VR_V21 = 21, + HEX_REG_HVX_VR_V22 = 22, + HEX_REG_HVX_VR_V23 = 23, + HEX_REG_HVX_VR_V24 = 24, + HEX_REG_HVX_VR_V25 = 25, + HEX_REG_HVX_VR_V26 = 26, + HEX_REG_HVX_VR_V27 = 27, + HEX_REG_HVX_VR_V28 = 28, + HEX_REG_HVX_VR_V29 = 29, + HEX_REG_HVX_VR_V30 = 30, + HEX_REG_HVX_VR_V31 = 31, +} HEX_HVX_VR; // HvxVR + +typedef enum { + HEX_REG_HVX_WR_W0 = 0, + HEX_REG_HVX_WR_W1 = 2, + HEX_REG_HVX_WR_W2 = 4, + HEX_REG_HVX_WR_W3 = 6, + HEX_REG_HVX_WR_W4 = 8, + HEX_REG_HVX_WR_W5 = 10, + HEX_REG_HVX_WR_W6 = 12, + HEX_REG_HVX_WR_W7 = 14, + HEX_REG_HVX_WR_W8 = 16, + HEX_REG_HVX_WR_W9 = 18, + HEX_REG_HVX_WR_W10 = 20, + HEX_REG_HVX_WR_W11 = 22, + HEX_REG_HVX_WR_W12 = 24, + HEX_REG_HVX_WR_W13 = 26, + HEX_REG_HVX_WR_W14 = 28, + HEX_REG_HVX_WR_W15 = 30, +} HEX_HVX_WR; // HvxWR + +typedef enum { + HEX_REG_INT_REGS_R0 = 0, + HEX_REG_INT_REGS_R1 = 1, + HEX_REG_INT_REGS_R2 = 2, + HEX_REG_INT_REGS_R3 = 3, + HEX_REG_INT_REGS_R4 = 4, + HEX_REG_INT_REGS_R5 = 5, + HEX_REG_INT_REGS_R6 = 6, + HEX_REG_INT_REGS_R7 = 7, + HEX_REG_INT_REGS_R8 = 8, + HEX_REG_INT_REGS_R9 = 9, + HEX_REG_INT_REGS_R10 = 10, + HEX_REG_INT_REGS_R11 = 11, + HEX_REG_INT_REGS_R12 = 12, + HEX_REG_INT_REGS_R13 = 13, + HEX_REG_INT_REGS_R14 = 14, + HEX_REG_INT_REGS_R15 = 15, + HEX_REG_INT_REGS_R16 = 16, + HEX_REG_INT_REGS_R17 = 17, + HEX_REG_INT_REGS_R18 = 18, + HEX_REG_INT_REGS_R19 = 19, + HEX_REG_INT_REGS_R20 = 20, + HEX_REG_INT_REGS_R21 = 21, + HEX_REG_INT_REGS_R22 = 22, + HEX_REG_INT_REGS_R23 = 23, + HEX_REG_INT_REGS_R24 = 24, + HEX_REG_INT_REGS_R25 = 25, + HEX_REG_INT_REGS_R26 = 26, + HEX_REG_INT_REGS_R27 = 27, + HEX_REG_INT_REGS_R28 = 28, + HEX_REG_INT_REGS_R29 = 29, // sp + HEX_REG_INT_REGS_R30 = 30, // fp + HEX_REG_INT_REGS_R31 = 31, // lr +} HEX_INT_REGS; // IntRegs + +typedef enum { + HEX_REG_INT_REGS_LOW8_R0 = 0, + HEX_REG_INT_REGS_LOW8_R1 = 1, + HEX_REG_INT_REGS_LOW8_R2 = 2, + HEX_REG_INT_REGS_LOW8_R3 = 3, + HEX_REG_INT_REGS_LOW8_R4 = 4, + HEX_REG_INT_REGS_LOW8_R5 = 5, + HEX_REG_INT_REGS_LOW8_R6 = 6, + HEX_REG_INT_REGS_LOW8_R7 = 7, +} HEX_INT_REGS_LOW8; // IntRegsLow8 + +typedef enum { + HEX_REG_MOD_REGS_M0 = 6, // c6 + HEX_REG_MOD_REGS_M1 = 7, // c7 +} HEX_MOD_REGS; // ModRegs + typedef enum { - HEX_REG_SGP0 = 0, // S0 - HEX_REG_SGP1 = 1, // S1 - HEX_REG_STID = 2, // S2 - HEX_REG_ELR = 3, // S3 - HEX_REG_BADVA0 = 4, // S4 - HEX_REG_BADVA1 = 5, // S5 - HEX_REG_SSR = 6, // S6 - HEX_REG_CCR = 7, // S7 - HEX_REG_HTID = 8, // S8 - HEX_REG_BADVA = 9, // S9 - HEX_REG_IMASK = 10, // S10 - // S11 - S15 are reserved - HEX_REG_EVB = 16, // S16 - HEX_REG_MODECTL = 17, // S17 - HEX_REG_SYSCFG = 18, // S18 - // S19 is reserved - HEX_REG_IPEND = 20, // S20 - HEX_REG_VID = 21, // S21 - HEX_REG_IAD = 22, // S22 - // S23 is reserved - HEX_REG_IEL = 24, // S24 - // S25 is reserved - HEX_REG_IAHL = 26, // S26 - HEX_REG_CFGBASE = 27, // S27 - HEX_REG_DIAG = 28, // S28 - HEX_REG_REV = 29, // S29 - HEX_REG_PCYCLELO = 30, // S30 - HEX_REG_PCYCLEHI = 31, // S31 - HEX_REG_ISDBST = 32, // S32 - HEX_REG_ISDBCFG0 = 33, // S33 - HEX_REG_ISDBCFG1 = 34, // S34 - // S35 is reserved - HEX_REG_BRKPTPC0 = 36, // S36 - HEX_REG_BRKPTCFG0 = 37, // S37 - HEX_REG_BRKPTPC1 = 38, // S38 - HEX_REG_BRKPTCFG1 = 39, // S39 - HEX_REG_ISDBMBXIN = 40, // S40 - HEX_REG_ISDBMBXOUT = 41, // S41 - HEX_REG_ISDBEN = 42, // S42 - HEX_REG_ISDBGPR = 43, // S43 - // S44 - S47 are reserved - HEX_REG_PMUCNT0 = 48, // S48 - HEX_REG_PMUCNT1 = 49, // S49 - HEX_REG_PMUCNT2 = 50, // S50 - HEX_REG_PMUCNT3 = 51, // S51 - HEX_REG_PMUEVTCFG = 52, // S52 - HEX_REG_PMUCFG = 53, // S53 - // S54 - S63 are reserved -} HEX_SYSCR_REG; - -// Here are the register field values for subinstructions + HEX_REG_PRED_REGS_P0 = 0, + HEX_REG_PRED_REGS_P1 = 1, + HEX_REG_PRED_REGS_P2 = 2, + HEX_REG_PRED_REGS_P3 = 3, +} HEX_PRED_REGS; // PredRegs typedef enum { - HEX_SUB_REG_R0 = 0, // 0b0000 - HEX_SUB_REG_R1 = 1, // 0b0001 - HEX_SUB_REG_R2 = 2, // 0b0010 - HEX_SUB_REG_R3 = 3, // 0b0011 - HEX_SUB_REG_R4 = 4, // 0b0100 - HEX_SUB_REG_R5 = 5, // 0b0101 - HEX_SUB_REG_R6 = 6, // 0b0110 - HEX_SUB_REG_R7 = 7, // 0b0111 - HEX_SUB_REG_R16 = 8, // 0b1000 - HEX_SUB_REG_R17 = 9, // 0b1001 - HEX_SUB_REG_R18 = 10, // 0b1010 - HEX_SUB_REG_R19 = 11, // 0b1011 - HEX_SUB_REG_R20 = 12, // 0b1100 - HEX_SUB_REG_R21 = 13, // 0b1101 - HEX_SUB_REG_R22 = 14, // 0b1110 - HEX_SUB_REG_R23 = 15, // 0b1111 -} HEX_SUB_REG; + HEX_REG_SYS_REGS_SGP0 = 0, // s0 + HEX_REG_SYS_REGS_SGP1 = 1, // s1 + HEX_REG_SYS_REGS_STID = 2, // s2 + HEX_REG_SYS_REGS_ELR = 3, // s3 + HEX_REG_SYS_REGS_BADVA0 = 4, // s4 + HEX_REG_SYS_REGS_BADVA1 = 5, // s5 + HEX_REG_SYS_REGS_SSR = 6, // s6 + HEX_REG_SYS_REGS_CCR = 7, // s7 + HEX_REG_SYS_REGS_HTID = 8, // s8 + HEX_REG_SYS_REGS_BADVA = 9, // s9 + HEX_REG_SYS_REGS_IMASK = 10, // s10 + HEX_REG_SYS_REGS_GEVB = 11, // s11 + HEX_REG_SYS_REGS_S12 = 12, // s11 + HEX_REG_SYS_REGS_S13 = 13, // s11 + HEX_REG_SYS_REGS_S14 = 14, // s11 + HEX_REG_SYS_REGS_S15 = 15, // s11 + HEX_REG_SYS_REGS_EVB = 16, // s16 + HEX_REG_SYS_REGS_MODECTL = 17, // s17 + HEX_REG_SYS_REGS_SYSCFG = 18, // s18 + HEX_REG_SYS_REGS_S19 = 19, // s18 + HEX_REG_SYS_REGS_IPENDAD = 20, // s20 + HEX_REG_SYS_REGS_VID = 21, // s21 + HEX_REG_SYS_REGS_VID1 = 22, // s22 + HEX_REG_SYS_REGS_BESTWAIT = 23, // s23 + HEX_REG_SYS_REGS_S24 = 24, // s23 + HEX_REG_SYS_REGS_SCHEDCFG = 25, // s25 + HEX_REG_SYS_REGS_S26 = 26, // s25 + HEX_REG_SYS_REGS_CFGBASE = 27, // s27 + HEX_REG_SYS_REGS_DIAG = 28, // s28 + HEX_REG_SYS_REGS_REV = 29, // s29 + HEX_REG_SYS_REGS_PCYCLELO = 30, // s30 + HEX_REG_SYS_REGS_PCYCLEHI = 31, // s31 + HEX_REG_SYS_REGS_ISDBST = 32, // s32 + HEX_REG_SYS_REGS_ISDBCFG0 = 33, // s33 + HEX_REG_SYS_REGS_ISDBCFG1 = 34, // s34 + HEX_REG_SYS_REGS_LIVELOCK = 35, // s35 + HEX_REG_SYS_REGS_BRKPTPC0 = 36, // s36 + HEX_REG_SYS_REGS_BRKPTCFG0 = 37, // s37 + HEX_REG_SYS_REGS_BRKPTPC1 = 38, // s38 + HEX_REG_SYS_REGS_BRKPTCFG1 = 39, // s39 + HEX_REG_SYS_REGS_ISDBMBXIN = 40, // s40 + HEX_REG_SYS_REGS_ISDBMBXOUT = 41, // s41 + HEX_REG_SYS_REGS_ISDBEN = 42, // s42 + HEX_REG_SYS_REGS_ISDBGPR = 43, // s43 + HEX_REG_SYS_REGS_PMUCNT4 = 44, // s44 + HEX_REG_SYS_REGS_PMUCNT5 = 45, // s45 + HEX_REG_SYS_REGS_PMUCNT6 = 46, // s46 + HEX_REG_SYS_REGS_PMUCNT7 = 47, // s47 + HEX_REG_SYS_REGS_PMUCNT0 = 48, // s48 + HEX_REG_SYS_REGS_PMUCNT1 = 49, // s49 + HEX_REG_SYS_REGS_PMUCNT2 = 50, // s50 + HEX_REG_SYS_REGS_PMUCNT3 = 51, // s51 + HEX_REG_SYS_REGS_PMUEVTCFG = 52, // s52 + HEX_REG_SYS_REGS_S53 = 53, // s52 + HEX_REG_SYS_REGS_PMUEVTCFG1 = 54, // s54 + HEX_REG_SYS_REGS_PMUSTID1 = 55, // s55 + HEX_REG_SYS_REGS_TIMERLO = 56, // s56 + HEX_REG_SYS_REGS_TIMERHI = 57, // s57 + HEX_REG_SYS_REGS_S58 = 58, // s57 + HEX_REG_SYS_REGS_S59 = 59, // s57 + HEX_REG_SYS_REGS_S60 = 60, // s57 + HEX_REG_SYS_REGS_S61 = 61, // s57 + HEX_REG_SYS_REGS_S62 = 62, // s57 + HEX_REG_SYS_REGS_S63 = 63, // s57 + HEX_REG_SYS_REGS_COMMIT1T = 64, // s64 + HEX_REG_SYS_REGS_COMMIT2T = 65, // s65 + HEX_REG_SYS_REGS_COMMIT3T = 66, // s66 + HEX_REG_SYS_REGS_COMMIT4T = 67, // s67 + HEX_REG_SYS_REGS_COMMIT5T = 68, // s68 + HEX_REG_SYS_REGS_COMMIT6T = 69, // s69 + HEX_REG_SYS_REGS_PCYCLE1T = 70, // s70 + HEX_REG_SYS_REGS_PCYCLE2T = 71, // s71 + HEX_REG_SYS_REGS_PCYCLE3T = 72, // s72 + HEX_REG_SYS_REGS_PCYCLE4T = 73, // s73 + HEX_REG_SYS_REGS_PCYCLE5T = 74, // s74 + HEX_REG_SYS_REGS_PCYCLE6T = 75, // s75 + HEX_REG_SYS_REGS_STFINST = 76, // s76 + HEX_REG_SYS_REGS_ISDBCMD = 77, // s77 + HEX_REG_SYS_REGS_ISDBVER = 78, // s78 + HEX_REG_SYS_REGS_BRKPTINFO = 79, // s79 + HEX_REG_SYS_REGS_RGDR3 = 80, // s80 +} HEX_SYS_REGS; // SysRegs typedef enum { - HEX_SUB_REGPAIR_R1_R0 = 0, // 0b000 - HEX_SUB_REGPAIR_R3_R2 = 1, // 0b001 - HEX_SUB_REGPAIR_R5_R4 = 2, // 0b010 - HEX_SUB_REGPAIR_R7_R6 = 3, // 0b011 - HEX_SUB_REGPAIR_R17_R16 = 4, // 0b100 - HEX_SUB_REGPAIR_R19_R18 = 5, // 0b101 - HEX_SUB_REGPAIR_R21_R20 = 6, // 0b110 - HEX_SUB_REGPAIR_R23_R22 = 7, // 0b111 -} HEX_SUB_REGPAIR; + HEX_REG_SYS_REGS64_S1_0 = 0, // s1 + HEX_REG_SYS_REGS64_S3_2 = 2, // s3 + HEX_REG_SYS_REGS64_S5_4 = 4, // s5 + HEX_REG_SYS_REGS64_S7_6 = 6, // s7 + HEX_REG_SYS_REGS64_S9_8 = 8, // s9 + HEX_REG_SYS_REGS64_S11_10 = 10, // s11 + HEX_REG_SYS_REGS64_S13_12 = 12, // s11 + HEX_REG_SYS_REGS64_S15_14 = 14, // s11 + HEX_REG_SYS_REGS64_S17_16 = 16, // s17 + HEX_REG_SYS_REGS64_S19_18 = 18, // s18 + HEX_REG_SYS_REGS64_S21_20 = 20, // s21 + HEX_REG_SYS_REGS64_S23_22 = 22, // s23 + HEX_REG_SYS_REGS64_S25_24 = 24, // s25 + HEX_REG_SYS_REGS64_S27_26 = 26, // s27 + HEX_REG_SYS_REGS64_S29_28 = 28, // s29 + HEX_REG_SYS_REGS64_S31_30 = 30, // s31 + HEX_REG_SYS_REGS64_S33_32 = 32, // s33 + HEX_REG_SYS_REGS64_S35_34 = 34, // s35 + HEX_REG_SYS_REGS64_S37_36 = 36, // s37 + HEX_REG_SYS_REGS64_S39_38 = 38, // s39 + HEX_REG_SYS_REGS64_S41_40 = 40, // s41 + HEX_REG_SYS_REGS64_S43_42 = 42, // s43 + HEX_REG_SYS_REGS64_S45_44 = 44, // s45 + HEX_REG_SYS_REGS64_S47_46 = 46, // s47 + HEX_REG_SYS_REGS64_S49_48 = 48, // s49 + HEX_REG_SYS_REGS64_S51_50 = 50, // s51 + HEX_REG_SYS_REGS64_S53_52 = 52, // s52 + HEX_REG_SYS_REGS64_S55_54 = 54, // s55 + HEX_REG_SYS_REGS64_S57_56 = 56, // s57 + HEX_REG_SYS_REGS64_S59_58 = 58, // s57 + HEX_REG_SYS_REGS64_S61_60 = 60, // s57 + HEX_REG_SYS_REGS64_S63_62 = 62, // s57 + HEX_REG_SYS_REGS64_S65_64 = 64, // s65 + HEX_REG_SYS_REGS64_S67_66 = 66, // s67 + HEX_REG_SYS_REGS64_S69_68 = 68, // s69 + HEX_REG_SYS_REGS64_S71_70 = 70, // s71 + HEX_REG_SYS_REGS64_S73_72 = 72, // s73 + HEX_REG_SYS_REGS64_S75_74 = 74, // s75 + HEX_REG_SYS_REGS64_S77_76 = 76, // s77 + HEX_REG_SYS_REGS64_S79_78 = 78, // s79 +} HEX_SYS_REGS64; // SysRegs64 #define BIT_MASK(len) (BIT(len) - 1) #define BF_MASK(start, len) (BIT_MASK(len) << (start)) @@ -270,13 +529,55 @@ typedef enum { #define BF_GET(y, start, len) (((y) >> (start)) & BIT_MASK(len)) #define BF_GETB(y, start, end) (BF_GET((y), (start), (end) - (start) + 1) -char *hex_get_cntl_reg(int opreg); -char *hex_get_sys_reg(int opreg); -char *hex_get_sub_reg(int opreg); -char *hex_get_sub_regpair(int opreg); -bool hex_if_duplex(ut32 insn_word); -void hex_op_extend(HexOp *op); -void hex_op_extend_off(HexOp *op, int offset); -int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr); +char *hex_get_ctr_regs(int opcode_reg); +char *hex_get_ctr_regs64(int opcode_reg); +char *hex_get_double_regs(int opcode_reg); +char *hex_get_general_double_low8_regs(int opcode_reg); +char *hex_get_general_sub_regs(int opcode_reg); +char *hex_get_guest_regs(int opcode_reg); +char *hex_get_guest_regs64(int opcode_reg); +char *hex_get_hvx_qr(int opcode_reg); +char *hex_get_hvx_vqr(int opcode_reg); +char *hex_get_hvx_vr(int opcode_reg); +char *hex_get_hvx_wr(int opcode_reg); +char *hex_get_int_regs(int opcode_reg); +char *hex_get_int_regs_low8(int opcode_reg); +char *hex_get_mod_regs(int opcode_reg); +char *hex_get_pred_regs(int opcode_reg); +char *hex_get_sys_regs(int opcode_reg); +char *hex_get_sys_regs64(int opcode_reg); -#endif +RZ_API void hex_extend_op(HexState *state, RZ_INOUT HexOp *op, const bool set_new_extender, const ut32 addr); +int resolve_n_register(const int reg_num, const ut32 addr, const HexPkt *p); +int hexagon_disasm_instruction(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, HexPkt *pkt); +void hexagon_disasm_0x0(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x1(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x2(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x3(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x4(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x5(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x6(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x7(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x8(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0x9(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0xa(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0xb(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0xc(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0xd(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_0xe(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x0(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x1(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x2(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x3(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x4(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x5(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x6(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x7(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x8(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0x9(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0xa(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0xb(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0xc(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0xd(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +void hexagon_disasm_duplex_0xe(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, const ut32 addr, HexPkt *pkt); +#endif \ No newline at end of file diff --git a/librz/asm/arch/hexagon/hexagon_arch.c b/librz/asm/arch/hexagon/hexagon_arch.c new file mode 100644 index 00000000000..56013b1d313 --- /dev/null +++ b/librz/asm/arch/hexagon/hexagon_arch.c @@ -0,0 +1,702 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + +#include +#include +#include +#include "hexagon.h" +#include "hexagon_insn.h" +#include "hexagon_arch.h" + +static inline bool is_last_instr(const ut8 parse_bits) { + // Duplex instr. (parse bits = 0) are always the last. + return ((parse_bits == 0x3) || (parse_bits == 0x0)); +} + +/** + * \brief Checks if packet ends hardware loop 0. + * + * \param pb_hi_0 Parse bits instruction 0. + * \param pb_hi_1 Parse bits instruction 1. + * \return true Packet ends hardware loop 0. + * \return false Packet does not end hardware loop 0. + */ +static inline bool is_endloop0_pkt(const ut8 pb_hi_0, const ut8 pb_hi_1) { + return ((pb_hi_0 == 0x2) && ((pb_hi_1 == 0x1) || (pb_hi_1 == 0x3))); +} + +/** + * \brief Checks if packet ends hardware loop 0. But for an undocumented variant + * where the packet has only two instructions and the last one is a Duplex. + * + * \param pb_hi_0 Parse bits instruction 0. + * \param pb_hi_1 Parse bits instruction 1 (duplex and end of packet). + * \return true Packet ends hardware loop 0. + * \return false Packet does not end hardware loop 0. + */ +static inline bool is_undoc_endloop0_pkt(const ut8 pb_hi_0, const ut8 pb_hi_1) { + return ((pb_hi_0 == 0x2) && (pb_hi_1 == 0x0)); +} + +/** + * \brief Checks if packet ends hardware loop 1. + * + * \param pb_hi_0 Parse bits instruction 0. + * \param pb_hi_1 Parse bits instruction 1. + * \return true Packet ends hardware loop 1. + * \return false Packet does not end hardware loop 1. + */ +static inline bool is_endloop1_pkt(const ut8 pb_hi_0, const ut8 pb_hi_1) { + return ((pb_hi_0 == 0x1) && (pb_hi_1 == 0x2)); +} + +/** + * \brief Checks if packet ends hardware loop 0 and hw-loop 1. + * + * \param pb_hi_0 Parse bits instruction 0. + * \param pb_hi_1 Parse bits instruction 1. + * \return true Packet ends hardware loop 0 and hw-loop 1. + * \return false Packet does not end hardware loop 0 and hw-loop 1. + */ +static inline bool is_endloop01_pkt(const ut8 pb_hi_0, const ut8 pb_hi_1) { + return ((pb_hi_0 == 0x2) && (pb_hi_1 == 0x2)); +} + +/** + * \brief Gives the instruction at a given address from the state. + * + * \param state The state to operade on. + * \param addr The address of the instruction. + * \return Pointer to instruction or NULL if none was found. + */ +static HexInsn *hex_get_instr_at_addr(HexState *state, const ut32 addr) { + HexPkt *p; + for (ut8 i = 0; i < HEXAGON_STATE_PKTS; ++i) { + p = &state->pkts[i]; + HexInsn *pi = NULL; + RzListIter *iter = NULL; + rz_list_foreach (p->insn, iter, pi) { + if (addr == pi->addr) { + p->last_access = rz_time_now(); + return pi; + } + } + } + return NULL; +} + +/** + * \brief Returns the index of an addr in a given packet. + * + * \param addr Address of an instruction. + * \param p The packet. to search in. + * \return ut8 The index of the addr if it is in the packet. UT8_MAX otherwise. + */ +RZ_API ut8 hexagon_get_pkt_index_of_addr(const ut32 addr, const HexPkt *p) { + rz_return_val_if_fail(p, UT8_MAX); + + HexInsn *hi = NULL; + RzListIter *it = NULL; + ut8 i = 0; + rz_list_foreach (p->insn, it, hi) { + if (hi->addr == addr) { + return i; + } + ++i; + } + return UT8_MAX; +} + +/** + * \brief Clears a packet and sets its attributes to invalid values. + * + * \param p The packet to clear. + */ +static void hex_clear_pkt(RZ_NONNULL HexPkt *p) { + p->last_instr_present = false; + p->is_valid = false; + p->last_access = 0; + rz_list_purge(p->insn); +} + +/** + * \brief Gives the least used packet. + * + * \param state The state to operade on. + * \return HexPkt* Pointer to the least used packet. + */ +static HexPkt *hex_get_stale_pkt(HexState *state) { + HexPkt *stale_state_pkt = &state->pkts[0]; + ut64 oldest = UT64_MAX; + + for (ut8 i = 0; i < HEXAGON_STATE_PKTS; ++i) { + if (state->pkts[i].last_access < oldest) { + stale_state_pkt = &state->pkts[i]; + } + } + return stale_state_pkt; +} + +/** + * \brief Returns the packet which covers the given address. + * + * \param state The state to operade on. + * \param addr The address of an instruction. + * \return HexPkt* The packet to which this address belongs to or NULL if no packet was found. + */ +static HexPkt *hex_get_pkt(HexState *state, const ut32 addr) { + HexPkt *p = NULL; + HexInsn *pi = NULL; + RzListIter *iter = NULL; + for (ut8 i = 0; i < HEXAGON_STATE_PKTS; ++i) { + p = &state->pkts[i]; + rz_list_foreach (p->insn, iter, pi) { + if (addr == pi->addr) { + return p; + } + } + } + return NULL; +} + +/** + * \brief Frees an instruction. + * + * \param i The instruction to be freed. + */ +RZ_API void hex_insn_free(RZ_NULLABLE HexInsn *i) { + if (!i) { + return; + } + free(i); +} + +/** + * \brief Frees an constant extender. + * + * \param ce The constant extender to be freed. + */ +RZ_API void hex_const_ext_free(RZ_NULLABLE HexConstExt *ce) { + if (!ce) { + return; + } + free(ce); +} + +/** + * \brief Get the index of a packet in the state + * + * \param state The state to operade on. + * \param p The packet whichs index should be determined. + * \return ut8 The index of the packet in the given state. UT8_MAX if it is not in the state. + */ +static ut8 get_state_pkt_index(HexState *state, const HexPkt *p) { + HexPkt *sp; + for (ut8 i = 0; i < HEXAGON_STATE_PKTS; ++i) { + sp = &state->pkts[i]; + if (sp->pkt_addr == p->pkt_addr) { + return i; + } + } + return UT8_MAX; +} + +/** + * \brief Initializes each packet of the state once. + * + * \return The initialized state of the plugins. + */ +RZ_API HexState *hexagon_get_state() { + static HexState *state = NULL; + if (state) { + return state; + } + + state = calloc(1, sizeof(HexState)); + if (!state) { + RZ_LOG_FATAL("Could not allocate memory for HexState!"); + } + for (int i = 0; i < HEXAGON_STATE_PKTS; ++i) { + state->pkts[i].insn = rz_list_newf((RzListFree)hex_insn_free); + if (!state->pkts[i].insn) { + RZ_LOG_FATAL("Could not initialize instruction list!"); + } + hex_clear_pkt(&(state->pkts[i])); + } + state->const_ext_l = rz_list_newf((RzListFree)hex_const_ext_free); + return state; +} + +/** + * \brief Checks if the packet has 4 instructions set. + * + * \param p The packet to check. + * \return true The packet stores already 4 instructions. + * \return false The packet stores less than 4 instructions. + */ +static inline bool is_pkt_full(const HexPkt *p) { + return rz_list_length(p->insn) >= 4; +} + +/** + * \brief Sets the packet related information in an instruction. + * + * \param hi The instruction. + * \param p The packet the instruction belongs to. + * \param k The index of the instruction within the packet. + */ +static void hex_set_pkt_info(const RzAsm *rz_asm, RZ_INOUT HexInsn *hi, const HexPkt *p, const ut8 k, const bool update_mnemonic) { + rz_return_if_fail(hi && p); + bool is_first = (k == 0); + HexPktInfo *hi_pi = &hi->pkt_info; + + strncpy(hi_pi->syntax_postfix, "", 16); + // Parse instr. position in pkt + if (is_first && is_last_instr(hi->parse_bits)) { // Single instruction packet. + hi_pi->first_insn = true; + hi_pi->last_insn = true; + // TODO No indent in visual mode for "[" without spaces. + if (p->is_valid) { + strncpy(hi_pi->syntax_prefix, HEX_PKT_SINGLE, 8); + } else { + strncpy(hi_pi->syntax_prefix, HEX_PKT_UNK, 8); + } + } else if (is_first) { + hi_pi->first_insn = true; + hi_pi->last_insn = false; + if (p->is_valid) { + strncpy(hi_pi->syntax_prefix, rz_asm->utf8 ? HEX_PKT_FIRST_UTF8 : HEX_PKT_FIRST, 8); + } else { + strncpy(hi_pi->syntax_prefix, HEX_PKT_UNK, 8); + } + } else if (is_last_instr(hi->parse_bits)) { + hi_pi->first_insn = false; + hi_pi->last_insn = true; + if (p->is_valid) { + strncpy(hi_pi->syntax_prefix, rz_asm->utf8 ? HEX_PKT_LAST_UTF8 : HEX_PKT_LAST, 8); + + switch (hex_get_loop_flag(p)) { + default: + break; + case HEX_LOOP_01: + strncpy(hi_pi->syntax_postfix, rz_asm->utf8 ? HEX_PKT_ELOOP_01_UTF8 : HEX_PKT_ELOOP_01, 24); + break; + case HEX_LOOP_0: + strncpy(hi_pi->syntax_postfix, rz_asm->utf8 ? HEX_PKT_ELOOP_0_UTF8 : HEX_PKT_ELOOP_0, 24); + break; + case HEX_LOOP_1: + strncpy(hi_pi->syntax_postfix, rz_asm->utf8 ? HEX_PKT_ELOOP_1_UTF8 : HEX_PKT_ELOOP_1, 24); + break; + } + } else { + strncpy(hi_pi->syntax_prefix, HEX_PKT_UNK, 8); + } + } else { + hi_pi->first_insn = false; + hi_pi->last_insn = false; + if (p->is_valid) { + strncpy(hi_pi->syntax_prefix, rz_asm->utf8 ? HEX_PKT_MID_UTF8 : HEX_PKT_MID, 8); + } else { + strncpy(hi_pi->syntax_prefix, HEX_PKT_UNK, 8); + } + } + if (update_mnemonic) { + sprintf(hi->mnem, "%s%s%s", hi_pi->syntax_prefix, hi->mnem_infix, hi_pi->syntax_postfix); + } +} + +/** + * \brief Returns the loop type of a packet. Though only if this packet is + * the last packet in last packet in a hardware loop. Otherwise it returns + * HEX_NO_LOOP. + * + * \param p The instruction packet. + * \return HexLoopAttr The loop type this packet belongs to. + */ +RZ_API HexLoopAttr hex_get_loop_flag(const HexPkt *p) { + if (!p || rz_list_length(p->insn) < 2) { + return HEX_NO_LOOP; + } + + ut8 pb_0 = ((HexInsn *)rz_list_get_n(p->insn, 0))->parse_bits; + ut8 pb_1 = ((HexInsn *)rz_list_get_n(p->insn, 1))->parse_bits; + + if (is_endloop0_pkt(pb_0, pb_1)) { + return HEX_LOOP_0; + } else if (is_endloop1_pkt(pb_0, pb_1)) { + return HEX_LOOP_1; + } else if (is_endloop01_pkt(pb_0, pb_1)) { + return HEX_LOOP_01; + } else if (is_undoc_endloop0_pkt(pb_0, pb_1)) { + RZ_LOG_VERBOSE("Undocumented hardware loop 0 endloop packet."); + return HEX_LOOP_0; + } else { + return HEX_NO_LOOP; + } +} + +/** + * \brief Sets the packet after pkt to valid and updates its mnemonic. + * + * \param state The state to operade on. + * \param pkt The packet which predecessor will be updated. + */ +static void make_next_packet_valid(HexState *state, const HexPkt *pkt) { + HexInsn *tmp = rz_list_get_top(pkt->insn); + if (!tmp) { + return; + } + ut32 pkt_addr = tmp->addr + 4; + + HexPkt *p; + for (int i = 0; i < HEXAGON_STATE_PKTS; ++i) { + p = &state->pkts[i]; + if (p->pkt_addr == pkt_addr) { + if (p->is_valid) { + break; + } + p->is_valid = true; + HexInsn *hi = NULL; + RzListIter *it = NULL; + ut8 k = 0; + rz_list_foreach (p->insn, it, hi) { + hex_set_pkt_info(&state->rz_asm, hi, p, k, true); + ++k; + } + p->last_access = rz_time_now(); + break; + } + } +} + +/** + * \brief Allocates a new instruction on the heap. + * + * \return HexInsn* The new instruction. + */ +RZ_API HexInsn *alloc_instr() { + HexInsn *hi = calloc(1, sizeof(HexInsn)); + if (!hi) { + RZ_LOG_FATAL("Could not allocate memory for new instruction.\n"); + } + + return hi; +} + +/** + * \brief Copies an instruction to the packet p at position k. + * + * \param state The state to operade on. + * \param new_ins The instruction to copy. + * \param p The packet in which the instruction will hold the instruction. + * \param k The index of the instruction in the packet. + * \return HexInsn* Pointer to the copied instruction on the heap. + */ +static HexInsn *hex_add_to_pkt(HexState *state, const HexInsn *new_ins, RZ_INOUT HexPkt *p, const ut8 k) { + if (k > 3) { + RZ_LOG_FATAL("Instruction could not be set! A packet can only hold four instructions but k=%d.", k); + } + HexInsn *hi = alloc_instr(); + memcpy(hi, new_ins, sizeof(HexInsn)); + rz_list_insert(p->insn, k, hi); + + if (k == 0) { + p->pkt_addr = hi->addr; + } + p->last_instr_present |= is_last_instr(hi->parse_bits); + ut32 p_l = rz_list_length(p->insn); + hex_set_pkt_info(&state->rz_asm, hi, p, k, false); + if (k == 0 && p_l > 1) { + // Update the instruction which was previously the first one. + hex_set_pkt_info(&state->rz_asm, rz_list_get_n(p->insn, 1), p, 1, true); + } + p->last_access = rz_time_now(); + if (p->last_instr_present) { + make_next_packet_valid(state, p); + } + return hi; +} + +/** + * \brief Cleans the packet \p new_p, copies the instruction \p new_ins and the attributes of \p p to it. + * + * \param state The state to operade on. + * \param new_ins The instruction to copy. + * \param p The old packet which attributes are copied to the new one. + * \param new_p The new packet will hold the instruction. + * \return HexInsn* Pointer to the copied instruction on the heap. + */ +static HexInsn *hex_to_new_pkt(HexState *state, const HexInsn *new_ins, const HexPkt *p, RZ_INOUT HexPkt *new_p) { + hex_clear_pkt(new_p); + + HexInsn *hi = alloc_instr(); + memcpy(hi, new_ins, sizeof(HexInsn)); + rz_list_insert(new_p->insn, 0, hi); + + new_p->last_instr_present |= is_last_instr(hi->parse_bits); + new_p->hw_loop0_addr = p->hw_loop0_addr; + new_p->hw_loop1_addr = p->hw_loop1_addr; + new_p->is_valid = (p->is_valid || p->last_instr_present); + new_p->pkt_addr = hi->addr; + new_p->last_access = rz_time_now(); + hex_set_pkt_info(&state->rz_asm, hi, new_p, 0, false); + if (new_p->last_instr_present) { + make_next_packet_valid(state, new_p); + } + return hi; +} + +/** + * \brief Cleans the least accessed packet and copies the given instruction into it. + * + * \param state The state to operade on. + * \param new_ins The instruction to copy. + * \return HexInsn* Pointer to the copied instruction on the heap. + */ +static HexInsn *hex_add_to_stale_pkt(HexState *state, const HexInsn *new_ins) { + HexPkt *p = hex_get_stale_pkt(state); + hex_clear_pkt(p); + + HexInsn *hi = alloc_instr(); + memcpy(hi, new_ins, sizeof(HexInsn)); + rz_list_insert(p->insn, 0, hi); + + p->last_instr_present |= is_last_instr(hi->parse_bits); + p->pkt_addr = new_ins->addr; + // p->is_valid = true; // Setting it true also detects a lot of data as valid assembly. + p->last_access = rz_time_now(); + hex_set_pkt_info(&state->rz_asm, hi, p, 0, false); + if (p->last_instr_present) { + make_next_packet_valid(state, p); + } + return hi; +} + +/** + * \brief Copies the given instruction to a state packet it belongs to. + * If the instruction does not fit to any packet, it will be written to a stale one. + * + * The instruction __must__ have its address and parse bits set! + * + * \param state The state to operade on. + * \param new_ins The instruction to be copied. + * \return The pointer to the added instruction. Null if the instruction could not be copied. + */ +static HexInsn *hex_add_instr_to_state(HexState *state, const HexInsn *new_ins) { + if (!new_ins) { + return NULL; + } + bool add_to_pkt = false; + bool new_pkt = false; + bool write_to_stale_pkt = false; + bool insert_before_pkt_hi = false; + ut8 k = 0; // New instruction position in packet. + + HexPkt *p; + if (new_ins->addr == 0x0) { + return hex_add_to_stale_pkt(state, new_ins); + } + + for (ut8 i = 0; i < HEXAGON_STATE_PKTS; ++i, k = 0) { + p = &(state->pkts[i]); + + HexInsn *pkt_instr = NULL; // Instructions already in the packet. + RzListIter *iter = NULL; + rz_list_foreach (p->insn, iter, pkt_instr) { + if (new_ins->addr == (pkt_instr->addr - 4)) { + // Instruction preceeds one in the packet. + if (is_last_instr(new_ins->parse_bits) || is_pkt_full(p)) { + write_to_stale_pkt = true; + break; + } else { + insert_before_pkt_hi = true; + add_to_pkt = true; + break; + } + } else if (new_ins->addr == (pkt_instr->addr + 4)) { + if (is_last_instr(pkt_instr->parse_bits) || is_pkt_full(p)) { + new_pkt = true; + break; + } else { + add_to_pkt = true; + break; + } + } + ++k; + } + if (add_to_pkt || new_pkt || write_to_stale_pkt) { + break; + } + } + + // Add the instruction to packet p + if (add_to_pkt) { + if (insert_before_pkt_hi) { + return hex_add_to_pkt(state, new_ins, p, k); + } + return hex_add_to_pkt(state, new_ins, p, k + 1); + + } else if (new_pkt) { + ut8 ni = (get_state_pkt_index(state, p) + 1) % HEXAGON_STATE_PKTS; + return hex_to_new_pkt(state, new_ins, p, &state->pkts[ni]); + } else { + return hex_add_to_stale_pkt(state, new_ins); + } +} + +/** + * \brief Set the up new instr. + * + * \param hi The instruction to set up. + * \param rz_reverse RzAsmOp and RzAnalysisOp which could have some data, which needs to be copied. + * \param addr The address of the instruction. + * \param parse_bits The parse bits of the instruction + */ +static void setup_new_instr(HexInsn *hi, const HexReversedOpcode *rz_reverse, const ut32 addr, const ut8 parse_bits) { + hi->instruction = HEX_INS_INVALID_DECODE; + hi->addr = addr; + hi->parse_bits = parse_bits; + if (rz_reverse->asm_op) { + memcpy(&(hi->asm_op), rz_reverse->asm_op, sizeof(RzAsmOp)); + } + if (rz_reverse->ana_op) { + memcpy(&(hi->ana_op), rz_reverse->ana_op, sizeof(RzAnalysisOp)); + } + + hi->ana_op.val = UT64_MAX; + for (ut8 i = 0; i < 6; ++i) { + hi->ana_op.analysis_vals[i].imm = ST64_MAX; + } + hi->ana_op.jump = UT64_MAX; + hi->ana_op.fail = UT64_MAX; + hi->ana_op.ptr = UT64_MAX; + + hi->asm_op.size = 4; + hi->ana_op.size = 4; +} + +static inline bool imm_is_scaled(const HexOpAttr attr) { + return (attr & HEX_OP_IMM_SCALED); +} + +/** + * \brief Searched the constant extender in the ce_list, where addr is the key. + * + * \param ce_list The list with constant extender values. + * \param addr The address of the instruction which gets the constant extender applied. + * \return HexConstExt* A const. ext., if there is one which should be applied on the instruction at addr. Otherwise NULL. + */ +static HexConstExt *get_const_ext_from_addr(const RzList *ce_list, const ut32 addr) { + HexConstExt *ce = NULL; + RzListIter *iter = NULL; + rz_list_foreach (ce_list, iter, ce) { + if (addr == ce->addr) { + return ce; + } + } + return NULL; +} + +/** + * \brief Applies the constant extender to the immediate value in op. + * + * \param state The state to operade on. + * \param op The operand the extender is applied to or taken from. + * \param set_new_extender True if the immediate value of the op comes from immext() and sets the a new constant extender. False otherwise. + * \param addr The address of the currently disassembled instruction. + */ +RZ_API void hex_extend_op(HexState *state, RZ_INOUT HexOp *op, const bool set_new_extender, const ut32 addr) { + if (rz_list_length(state->const_ext_l) > MAX_CONST_EXT) { + rz_list_purge(state->const_ext_l); + } + + if (op->type != HEX_OP_TYPE_IMM) { + return; + } + + HexConstExt *ce; + if (set_new_extender) { + ce = calloc(1, sizeof(HexConstExt)); + ce->addr = addr + 4; + ce->const_ext = op->op.imm; + rz_list_append(state->const_ext_l, ce); + return; + } + + ce = get_const_ext_from_addr(state->const_ext_l, addr); + if (ce) { + op->op.imm = imm_is_scaled(op->attr) ? (op->op.imm >> op->shift) : op->op.imm; + op->op.imm = ((op->op.imm & 0x3F) | ce->const_ext); + rz_list_delete_data(state->const_ext_l, ce); + return; + } +} + +/** + * \brief Reverses a given opcode and copies the result into one of the rizin structs in rz_reverse. + * + * \param rz_reverse Rizin core structs which store asm and analysis information. + * \param buf The buffer which stores the current opcode. + * \param addr The address of the current opcode. + */ +RZ_API void hexagon_reverse_opcode(const RzAsm *rz_asm, HexReversedOpcode *rz_reverse, const ut8 *buf, const ut64 addr) { + HexState *state = hexagon_get_state(); + if (!state) { + RZ_LOG_FATAL("HexState was NULL."); + } + if (rz_asm) { + memcpy(&state->rz_asm, rz_asm, sizeof(RzAsm)); + } + HexInsn *hi = hex_get_instr_at_addr(state, addr); + if (hi) { + // Opcode was already reversed and is still in the state. Copy the result and return. + switch (rz_reverse->action) { + default: + memcpy(rz_reverse->asm_op, &(hi->asm_op), sizeof(RzAsmOp)); + memcpy(rz_reverse->ana_op, &(hi->ana_op), sizeof(RzAnalysisOp)); + rz_strbuf_set(&rz_reverse->asm_op->buf_asm, hi->mnem); + return; + case HEXAGON_DISAS: + memcpy(rz_reverse->asm_op, &(hi->asm_op), sizeof(RzAsmOp)); + rz_strbuf_set(&rz_reverse->asm_op->buf_asm, hi->mnem); + return; + case HEXAGON_ANALYSIS: + memcpy(rz_reverse->ana_op, &(hi->ana_op), sizeof(RzAnalysisOp)); + return; + } + } + + ut32 data = rz_read_le32(buf); + ut8 parse_bits = (data & 0x0000c000) >> 14; + HexInsn instr = { 0 }; + setup_new_instr(&instr, rz_reverse, addr, parse_bits); + // Add to state + hi = hex_add_instr_to_state(state, &instr); + if (!hi) { + return; + } + HexPkt *p = hex_get_pkt(state, hi->addr); + + // Do disasassembly and analysis + hexagon_disasm_instruction(&state->rz_asm, state, data, hi, p); + + switch (rz_reverse->action) { + default: + memcpy(rz_reverse->asm_op, &hi->asm_op, sizeof(RzAsmOp)); + memcpy(rz_reverse->ana_op, &hi->ana_op, sizeof(RzAnalysisOp)); + rz_strbuf_set(&rz_reverse->asm_op->buf_asm, hi->mnem); + break; + case HEXAGON_DISAS: + memcpy(rz_reverse->asm_op, &hi->asm_op, sizeof(RzAsmOp)); + rz_strbuf_set(&rz_reverse->asm_op->buf_asm, hi->mnem); + break; + case HEXAGON_ANALYSIS: + memcpy(rz_reverse->ana_op, &hi->ana_op, sizeof(RzAnalysisOp)); + break; + } +} \ No newline at end of file diff --git a/librz/asm/arch/hexagon/hexagon_arch.h b/librz/asm/arch/hexagon/hexagon_arch.h new file mode 100644 index 00000000000..5961c74b94d --- /dev/null +++ b/librz/asm/arch/hexagon/hexagon_arch.h @@ -0,0 +1,50 @@ +// SPDX-FileCopyrightText: 2021 Rot127 +// SPDX-License-Identifier: LGPL-3.0-only + +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon +#ifndef HEXAGON_ARCH_H +#define HEXAGON_ARCH_H + +#include "hexagon.h" + +// The type of opcode reversing which is be done on the opcode. +typedef enum { + HEXAGON_ANALYSIS, + HEXAGON_DISAS, +} HexReverseAction; + +/** + * \brief Pointer to the rizin structs for disassembled and analysed instructions. + * + */ +typedef struct { + HexReverseAction action; // Whether ana_op, asm_op or both should be filled. + RzAnalysisOp *ana_op; + RzAsmOp *asm_op; +} HexReversedOpcode; + +#define HEX_PKT_UNK "? " +#define HEX_PKT_SINGLE "[ " +#define HEX_PKT_FIRST_UTF8 "┌ " +#define HEX_PKT_MID_UTF8 "│ " +#define HEX_PKT_LAST_UTF8 "└ " +#define HEX_PKT_FIRST "/ " +#define HEX_PKT_MID "| " +#define HEX_PKT_LAST "\\ " +#define HEX_PKT_ELOOP_01_UTF8 " ∎ endloop01" +#define HEX_PKT_ELOOP_1_UTF8 " ∎ endloop1" +#define HEX_PKT_ELOOP_0_UTF8 " ∎ endloop0" +#define HEX_PKT_ELOOP_01 " < endloop01" +#define HEX_PKT_ELOOP_1 " < endloop1" +#define HEX_PKT_ELOOP_0 " < endloop0" + +RZ_API void hex_insn_free(HexInsn *i); +RZ_API void hex_const_ext_free(HexConstExt *ce); +RZ_API HexState *hexagon_get_state(); +RZ_API void hexagon_reverse_opcode(const RzAsm *rz_asm, HexReversedOpcode *rz_reverse, const ut8 *buf, const ut64 addr); +RZ_API ut8 hexagon_get_pkt_index_of_addr(const ut32 addr, const HexPkt *p); +RZ_API HexLoopAttr hex_get_loop_flag(const HexPkt *p); +#endif diff --git a/librz/asm/arch/hexagon/hexagon_disas.c b/librz/asm/arch/hexagon/hexagon_disas.c index e7de2c7f26e..7b4e80d8cc9 100644 --- a/librz/asm/arch/hexagon/hexagon_disas.c +++ b/librz/asm/arch/hexagon/hexagon_disas.c @@ -1,17 +1,21 @@ -// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE - -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov +// SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + #include #include #include #include #include +#include +#include #include "hexagon.h" #include "hexagon_insn.h" - -extern ut32 constant_extender; +#include "hexagon_arch.h" #if ASAN && !defined(__clang__) #define NO_OPT_IF_ASAN __attribute__((optimize(0))) @@ -19,45382 +23,98051 @@ extern ut32 constant_extender; #define NO_OPT_IF_ASAN #endif -NO_OPT_IF_ASAN int hexagon_disasm_instruction(ut32 hi_u32, HexInsn *hi, ut32 addr) { - // DUPLEXES - if (((hi_u32 >> 14) & 0x3) == 0) { - switch ((((hi_u32 >> 29) & 0xF) << 1) | ((hi_u32 >> 13) & 1)) { - case 0x0: { - if ((hi_u32 & 0xf000f000) == 0x10001000) { - // Instruction: 0: 0001IIIIuuuueeee0001iiiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMUB__RS____U4_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f000) == 0x1000) { - // Instruction: 0: 0000IIIIuuuueeee0001iiiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMUB__RS____U4_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f000) == 0x0) { - // Instruction: 0: 0000IIIIuuuueeee0000iiiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMW__RS____U4_2_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - break; - } - case 0x1: { - if ((hi_u32 & 0xf000ffc4) == 0x10003f40) { - // Instruction: 1: 0001iiiissssdddd0011111101---0-- | Rd = memub (Rs + #u4:0) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x10003f00) { - // Instruction: 1: 0001iiiissssdddd0011111100---0-- | Rd = memub (Rs + #u4:0) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f45) { - // Instruction: 1: 0001iiiissssdddd0011111101---101 | Rd = memub (Rs + #u4:0) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc5) { - // Instruction: 1: 0001iiiissssdddd0011111111---101 | Rd = memub (Rs + #u4:0) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f47) { - // Instruction: 1: 0001iiiissssdddd0011111101---111 | Rd = memub (Rs + #u4:0) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc7) { - // Instruction: 1: 0001iiiissssdddd0011111111---111 | Rd = memub (Rs + #u4:0) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f44) { - // Instruction: 1: 0001iiiissssdddd0011111101---100 | Rd = memub (Rs + #u4:0) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc4) { - // Instruction: 1: 0001iiiissssdddd0011111111---100 | Rd = memub (Rs + #u4:0) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003f46) { - // Instruction: 1: 0001iiiissssdddd0011111101---110 | Rd = memub (Rs + #u4:0) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x10003fc6) { - // Instruction: 1: 0001iiiissssdddd0011111111---110 | Rd = memub (Rs + #u4:0) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x10003fc0) { - // Instruction: 1: 0001iiiissssdddd0011111111---0-- | Rd = memub (Rs + #u4:0) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x3f40) { - // Instruction: 1: 0000iiiissssdddd0011111101---0-- | Rd = memw (Rs + #u4:2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x3f00) { - // Instruction: 1: 0000iiiissssdddd0011111100---0-- | Rd = memw (Rs + #u4:2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f45) { - // Instruction: 1: 0000iiiissssdddd0011111101---101 | Rd = memw (Rs + #u4:2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc5) { - // Instruction: 1: 0000iiiissssdddd0011111111---101 | Rd = memw (Rs + #u4:2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f47) { - // Instruction: 1: 0000iiiissssdddd0011111101---111 | Rd = memw (Rs + #u4:2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc7) { - // Instruction: 1: 0000iiiissssdddd0011111111---111 | Rd = memw (Rs + #u4:2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f44) { - // Instruction: 1: 0000iiiissssdddd0011111101---100 | Rd = memw (Rs + #u4:2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc4) { - // Instruction: 1: 0000iiiissssdddd0011111111---100 | Rd = memw (Rs + #u4:2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3f46) { - // Instruction: 1: 0000iiiissssdddd0011111101---110 | Rd = memw (Rs + #u4:2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc7) == 0x3fc6) { - // Instruction: 1: 0000iiiissssdddd0011111111---110 | Rd = memw (Rs + #u4:2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000ffc4) == 0x3fc0) { - // Instruction: 1: 0000iiiissssdddd0011111111---0-- | Rd = memw (Rs + #u4:2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0x10003c00) { - // Instruction: 1: 0001IIIIsssseeee0011110iiiiidddd | Re = memub (Rs + #U4:0) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RS____U4_0____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0x10003e00) { - // Instruction: 1: 0001IIIIsssseeee00111110iiiiiddd | Re = memub (Rs + #U4:0) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RS____U4_0____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x10003000) { - // Instruction: 1: 0001IIIIuuuueeee00110iiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x10002000) { - // Instruction: 1: 0001IIIIuuuueeee00100iiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x10002800) { - // Instruction: 1: 0001IIIIuuuueeee00101iiissssdddd | Re = memub (Ru + #U4:0) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUB__RU____U4_0____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0x3c00) { - // Instruction: 1: 0000IIIIsssseeee0011110iiiiidddd | Re = memw (Rs + #U4:2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RS____U4_2____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0x3e00) { - // Instruction: 1: 0000IIIIsssseeee00111110iiiiiddd | Re = memw (Rs + #U4:2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RS____U4_2____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x3000) { - // Instruction: 1: 0000IIIIuuuueeee00110iiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x2000) { - // Instruction: 1: 0000IIIIuuuueeee00100iiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0x2800) { - // Instruction: 1: 0000IIIIuuuueeee00101iiissssdddd | Re = memw (Ru + #U4:2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__RU____U4_2____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - break; - } - case 0x2: { - if ((hi_u32 & 0xf800ffc4) == 0x30001f40) { - // Instruction: 2: 00110iiissssdddd0001111101---0-- | Rd = memb (Rs + #u3:0) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x30001f00) { - // Instruction: 2: 00110iiissssdddd0001111100---0-- | Rd = memb (Rs + #u3:0) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f45) { - // Instruction: 2: 00110iiissssdddd0001111101---101 | Rd = memb (Rs + #u3:0) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc5) { - // Instruction: 2: 00110iiissssdddd0001111111---101 | Rd = memb (Rs + #u3:0) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f47) { - // Instruction: 2: 00110iiissssdddd0001111101---111 | Rd = memb (Rs + #u3:0) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc7) { - // Instruction: 2: 00110iiissssdddd0001111111---111 | Rd = memb (Rs + #u3:0) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f44) { - // Instruction: 2: 00110iiissssdddd0001111101---100 | Rd = memb (Rs + #u3:0) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc4) { - // Instruction: 2: 00110iiissssdddd0001111111---100 | Rd = memb (Rs + #u3:0) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001f46) { - // Instruction: 2: 00110iiissssdddd0001111101---110 | Rd = memb (Rs + #u3:0) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x30001fc6) { - // Instruction: 2: 00110iiissssdddd0001111111---110 | Rd = memb (Rs + #u3:0) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x30001fc0) { - // Instruction: 2: 00110iiissssdddd0001111111---0-- | Rd = memb (Rs + #u3:0) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x20001f40) { - // Instruction: 2: 00100iiissssdddd0001111101---0-- | Rd = memh (Rs + #u3:1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x20001f00) { - // Instruction: 2: 00100iiissssdddd0001111100---0-- | Rd = memh (Rs + #u3:1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f45) { - // Instruction: 2: 00100iiissssdddd0001111101---101 | Rd = memh (Rs + #u3:1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc5) { - // Instruction: 2: 00100iiissssdddd0001111111---101 | Rd = memh (Rs + #u3:1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f47) { - // Instruction: 2: 00100iiissssdddd0001111101---111 | Rd = memh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc7) { - // Instruction: 2: 00100iiissssdddd0001111111---111 | Rd = memh (Rs + #u3:1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f44) { - // Instruction: 2: 00100iiissssdddd0001111101---100 | Rd = memh (Rs + #u3:1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc4) { - // Instruction: 2: 00100iiissssdddd0001111111---100 | Rd = memh (Rs + #u3:1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001f46) { - // Instruction: 2: 00100iiissssdddd0001111101---110 | Rd = memh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x20001fc6) { - // Instruction: 2: 00100iiissssdddd0001111111---110 | Rd = memh (Rs + #u3:1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x20001fc0) { - // Instruction: 2: 00100iiissssdddd0001111111---0-- | Rd = memh (Rs + #u3:1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x28001f40) { - // Instruction: 2: 00101iiissssdddd0001111101---0-- | Rd = memuh (Rs + #u3:1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x28001f00) { - // Instruction: 2: 00101iiissssdddd0001111100---0-- | Rd = memuh (Rs + #u3:1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____DEALLOCFRAME; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f45) { - // Instruction: 2: 00101iiissssdddd0001111101---101 | Rd = memuh (Rs + #u3:1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc5) { - // Instruction: 2: 00101iiissssdddd0001111111---101 | Rd = memuh (Rs + #u3:1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f47) { - // Instruction: 2: 00101iiissssdddd0001111101---111 | Rd = memuh (Rs + #u3:1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc7) { - // Instruction: 2: 00101iiissssdddd0001111111---111 | Rd = memuh (Rs + #u3:1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f44) { - // Instruction: 2: 00101iiissssdddd0001111101---100 | Rd = memuh (Rs + #u3:1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__DEALLOC_RETURN; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc4) { - // Instruction: 2: 00101iiissssdddd0001111111---100 | Rd = memuh (Rs + #u3:1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001f46) { - // Instruction: 2: 00101iiissssdddd0001111101---110 | Rd = memuh (Rs + #u3:1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x28001fc6) { - // Instruction: 2: 00101iiissssdddd0001111111---110 | Rd = memuh (Rs + #u3:1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x28001fc0) { - // Instruction: 2: 00101iiissssdddd0001111111---0-- | Rd = memuh (Rs + #u3:1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____JUMPR_LR; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc4) == 0x3c001f40) { - // Instruction: 2: 0011110iiiiidddd0001111101---0-- | Rd = memw (Sp + #u5:2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc4) == 0x3c001f00) { - // Instruction: 2: 0011110iiiiidddd0001111100---0-- | Rd = memw (Sp + #u5:2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f45) { - // Instruction: 2: 0011110iiiiidddd0001111101---101 | Rd = memw (Sp + #u5:2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc5) { - // Instruction: 2: 0011110iiiiidddd0001111111---101 | Rd = memw (Sp + #u5:2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f47) { - // Instruction: 2: 0011110iiiiidddd0001111101---111 | Rd = memw (Sp + #u5:2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc7) { - // Instruction: 2: 0011110iiiiidddd0001111111---111 | Rd = memw (Sp + #u5:2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f44) { - // Instruction: 2: 0011110iiiiidddd0001111101---100 | Rd = memw (Sp + #u5:2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc4) { - // Instruction: 2: 0011110iiiiidddd0001111111---100 | Rd = memw (Sp + #u5:2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001f46) { - // Instruction: 2: 0011110iiiiidddd0001111101---110 | Rd = memw (Sp + #u5:2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc7) == 0x3c001fc6) { - // Instruction: 2: 0011110iiiiidddd0001111111---110 | Rd = memw (Sp + #u5:2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00ffc4) == 0x3c001fc0) { - // Instruction: 2: 0011110iiiiidddd0001111111---0-- | Rd = memw (Sp + #u5:2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x3e001f40) { - // Instruction: 2: 00111110iiiiiddd0001111101---0-- | Rdd = memd (Sp + #u5:3) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x3e001f00) { - // Instruction: 2: 00111110iiiiiddd0001111100---0-- | Rdd = memd (Sp + #u5:3) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f45) { - // Instruction: 2: 00111110iiiiiddd0001111101---101 | Rdd = memd (Sp + #u5:3) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc5) { - // Instruction: 2: 00111110iiiiiddd0001111111---101 | Rdd = memd (Sp + #u5:3) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f47) { - // Instruction: 2: 00111110iiiiiddd0001111101---111 | Rdd = memd (Sp + #u5:3) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc7) { - // Instruction: 2: 00111110iiiiiddd0001111111---111 | Rdd = memd (Sp + #u5:3) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f44) { - // Instruction: 2: 00111110iiiiiddd0001111101---100 | Rdd = memd (Sp + #u5:3) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc4) { - // Instruction: 2: 00111110iiiiiddd0001111111---100 | Rdd = memd (Sp + #u5:3) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001f46) { - // Instruction: 2: 00111110iiiiiddd0001111101---110 | Rdd = memd (Sp + #u5:3) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x3e001fc6) { - // Instruction: 2: 00111110iiiiiddd0001111111---110 | Rdd = memd (Sp + #u5:3) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x3e001fc0) { - // Instruction: 2: 00111110iiiiiddd0001111111---0-- | Rdd = memd (Sp + #u5:3) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x30001c00) { - // Instruction: 2: 00110IIIsssseeee0001110iiiiidddd | Re = memb (Rs + #U3:0) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMB__RS____U3_0____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x30001e00) { - // Instruction: 2: 00110IIIsssseeee00011110iiiiiddd | Re = memb (Rs + #U3:0) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMB__RS____U3_0____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x30001000) { - // Instruction: 2: 00110IIIuuuueeee00010iiissssdddd | Re = memb (Ru + #U3:0) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMB__RU____U3_0____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x20001c00) { - // Instruction: 2: 00100IIIsssseeee0001110iiiiidddd | Re = memh (Rs + #U3:1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RS____U3_1____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20001e00) { - // Instruction: 2: 00100IIIsssseeee00011110iiiiiddd | Re = memh (Rs + #U3:1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RS____U3_1____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20001000) { - // Instruction: 2: 00100IIIuuuueeee00010iiissssdddd | Re = memh (Ru + #U3:1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20000000) { - // Instruction: 2: 00100IIIuuuueeee00000iiissssdddd | Re = memh (Ru + #U3:1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20000800) { - // Instruction: 2: 00100IIIuuuueeee00001iiissssdddd | Re = memh (Ru + #U3:1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMH__RU____U3_1____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x28001c00) { - // Instruction: 2: 00101IIIsssseeee0001110iiiiidddd | Re = memuh (Rs + #U3:1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RS____U3_1____RD___MEMW__SP____U5_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x28001e00) { - // Instruction: 2: 00101IIIsssseeee00011110iiiiiddd | Re = memuh (Rs + #U3:1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RS____U3_1____RDD___MEMD__SP____U5_3_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x28001000) { - // Instruction: 2: 00101IIIuuuueeee00010iiissssdddd | Re = memuh (Ru + #U3:1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RU____U3_1____RD___MEMB__RS____U3_0_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x28000800) { - // Instruction: 2: 00101IIIuuuueeee00001iiissssdddd | Re = memuh (Ru + #U3:1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___MEMUH__RU____U3_1____RD___MEMUH__RS____U3_1_; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[5].type = HEX_OP_TYPE_IMM; - hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hex_get_sub_reg(hi->ops[4].op.reg), hi->ops[5].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0x3c001c00) { - // Instruction: 2: 0011110IIIIIeeee0001110iiiiidddd | Re = memw (Sp + #U5:2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__SP____U5_2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0x3c001e00) { - // Instruction: 2: 0011110IIIIIeeee00011110iiiiiddd | Re = memw (Sp + #U5:2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___MEMW__SP____U5_2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x3e001e00) { - // Instruction: 2: 00111110IIIIIeee00011110iiiiiddd | Ree = memd (Sp + #U5:3) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___MEMD__SP____U5_3____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc5) { - // Instruction: 2: 0011111100---0--0001111111---101 | deallocframe ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF___NOT__P0__JUMPR_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (! p0) jumpr Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc7) { - // Instruction: 2: 0011111100---0--0001111111---111 | deallocframe ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (! p0.new) jumpr:nt Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc4) { - // Instruction: 2: 0011111100---0--0001111111---100 | deallocframe ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF__P0__JUMPR_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (p0) jumpr Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc7) == 0x3f001fc6) { - // Instruction: 2: 0011111100---0--0001111111---110 | deallocframe ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; if (p0.new) jumpr:nt Lr"); - break; - } - if ((hi_u32 & 0xffc4ffc4) == 0x3f001fc0) { - // Instruction: 2: 0011111100---0--0001111111---0-- | deallocframe ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___JUMPR_LR; - hi->op_count = 0; - hi->duplex = true; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; jumpr Lr"); - break; - } - break; - } - case 0x3: { - if ((hi_u32 & 0xfc00ff00) == 0x28003900) { - // Instruction: 3: 001010IIIIIIdddd00111001ssss--ii | Rd = #U6 ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD____U6___P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003800) { - // Instruction: 3: 001010iiiiiidddd00111000ssssxxxx | Rd = #u6 ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD____U6___RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003800) { - // Instruction: 3: 001010iiiiiidddd00111000ssssxxxx | Rd = #u6 ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD____U6___RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003800) { - // Instruction: 3: 00110000uuuudddd00111000ssssxxxx | Rd = Ru ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___RU___RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003800) { - // Instruction: 3: 00110000uuuudddd00111000ssssxxxx | Rd = Ru ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___RU___RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003900) { - // Instruction: 3: 00110000uuuudddd00111001ssss--ii | Rd = Ru ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___RU___P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003800) { - // Instruction: 3: 00110011uuuudddd00111000ssssxxxx | Rd = add (Ru, #-1) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003800) { - // Instruction: 3: 00110011uuuudddd00111000ssssxxxx | Rd = add (Ru, #-1) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003900) { - // Instruction: 3: 00110011uuuudddd00111001ssss--ii | Rd = add (Ru, #-1) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003800) { - // Instruction: 3: 00110001uuuudddd00111000ssssxxxx | Rd = add (Ru, #1) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003800) { - // Instruction: 3: 00110001uuuudddd00111000ssssxxxx | Rd = add (Ru, #1) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003900) { - // Instruction: 3: 00110001uuuudddd00111001ssss--ii | Rd = add (Ru, #1) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003900) { - // Instruction: 3: 001011IIIIIIdddd00111001ssss--ii | Rd = add (Sp, #U6:2) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003800) { - // Instruction: 3: 001011iiiiiidddd00111000ssssxxxx | Rd = add (Sp, #u6:2) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003800) { - // Instruction: 3: 001011iiiiiidddd00111000ssssxxxx | Rd = add (Sp, #u6:2) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003800) { - // Instruction: 3: 00110010uuuudddd00111000ssssxxxx | Rd = and (Ru, #1) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003800) { - // Instruction: 3: 00110010uuuudddd00111000ssssxxxx | Rd = and (Ru, #1) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003900) { - // Instruction: 3: 00110010uuuudddd00111001ssss--ii | Rd = and (Ru, #1) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003800) { - // Instruction: 3: 00110111uuuudddd00111000ssssxxxx | Rd = and (Ru, #255) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003800) { - // Instruction: 3: 00110111uuuudddd00111000ssssxxxx | Rd = and (Ru, #255) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003900) { - // Instruction: 3: 00110111uuuudddd00111001ssss--ii | Rd = and (Ru, #255) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003800) { - // Instruction: 3: 00110101uuuudddd00111000ssssxxxx | Rd = sxtb (Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003800) { - // Instruction: 3: 00110101uuuudddd00111000ssssxxxx | Rd = sxtb (Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003900) { - // Instruction: 3: 00110101uuuudddd00111001ssss--ii | Rd = sxtb (Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003800) { - // Instruction: 3: 00110100uuuudddd00111000ssssxxxx | Rd = sxth (Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003800) { - // Instruction: 3: 00110100uuuudddd00111000ssssxxxx | Rd = sxth (Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003900) { - // Instruction: 3: 00110100uuuudddd00111001ssss--ii | Rd = sxth (Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003800) { - // Instruction: 3: 00110110uuuudddd00111000ssssxxxx | Rd = zxth (Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003800) { - // Instruction: 3: 00110110uuuudddd00111000ssssxxxx | Rd = zxth (Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003900) { - // Instruction: 3: 00110110uuuudddd00111001ssss--ii | Rd = zxth (Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe40) == 0x3a003a00) { - // Instruction: 3: 0011101--0--eeee0011101--0--dddd | Re = #-1 ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD_____1; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c00) { - // Instruction: 3: 0011101--0--eeee001111-0-ii00ddd | Re = #-1 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd08) == 0x3a003d00) { - // Instruction: 3: 0011101--0--eeee001111-1ssss0ddd | Re = #-1 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c08) { - // Instruction: 3: 0011101--0--eeee001111-0-ii01ddd | Re = #-1 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c10) { - // Instruction: 3: 0011101--0--eeee001111-0-ii10ddd | Re = #-1 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd18) == 0x3a003c18) { - // Instruction: 3: 0011101--0--eeee001111-0-ii11ddd | Re = #-1 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fd08) == 0x3a003d08) { - // Instruction: 3: 0011101--0--eeee001111-1ssss1ddd | Re = #-1 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a70) { - // Instruction: 3: 0011101--0--eeee0011101--111dddd | Re = #-1 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a50) { - // Instruction: 3: 0011101--0--eeee0011101--101dddd | Re = #-1 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF___NOT__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a60) { - // Instruction: 3: 0011101--0--eeee0011101--110dddd | Re = #-1 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40fe70) == 0x3a003a40) { - // Instruction: 3: 0011101--0--eeee0011101--100dddd | Re = #-1 ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE_____1___IF__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe40) == 0x28003a00) { - // Instruction: 3: 001010IIIIIIeeee0011101--0--dddd | Re = #U6 ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fc00) == 0x28002800) { - // Instruction: 3: 001010IIIIIIeeee001010iiiiiidddd | Re = #U6 ; Rd = #u6 - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD____U6; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = 0x%x", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003300) { - // Instruction: 3: 001010IIIIIIeeee00110011ssssdddd | Re = #U6 ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003100) { - // Instruction: 3: 001010IIIIIIeeee00110001ssssdddd | Re = #U6 ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fc00) == 0x28002c00) { - // Instruction: 3: 001010IIIIIIeeee001011iiiiiidddd | Re = #U6 ; Rd = add (Sp, #u6:2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ADD__SP___U6_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = add (Sp, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003200) { - // Instruction: 3: 001010IIIIIIeeee00110010ssssdddd | Re = #U6 ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003700) { - // Instruction: 3: 001010IIIIIIeeee00110111ssssdddd | Re = #U6 ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c00) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii00ddd | Re = #U6 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x28003d00) { - // Instruction: 3: 001010IIIIIIeeee001111-1ssss0ddd | Re = #U6 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c08) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii01ddd | Re = #U6 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c10) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii10ddd | Re = #U6 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x28003c18) { - // Instruction: 3: 001010IIIIIIeeee001111-0-ii11ddd | Re = #U6 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x28003d08) { - // Instruction: 3: 001010IIIIIIeeee001111-1ssss1ddd | Re = #U6 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a70) { - // Instruction: 3: 001010IIIIIIeeee0011101--111dddd | Re = #U6 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a50) { - // Instruction: 3: 001010IIIIIIeeee0011101--101dddd | Re = #U6 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a60) { - // Instruction: 3: 001010IIIIIIeeee0011101--110dddd | Re = #U6 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x28003a40) { - // Instruction: 3: 001010IIIIIIeeee0011101--100dddd | Re = #U6 ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE____U6___IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003000) { - // Instruction: 3: 001010iiiiiieeee00110000ssssdddd | Re = #u6 ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003500) { - // Instruction: 3: 001010iiiiiieeee00110101ssssdddd | Re = #u6 ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003400) { - // Instruction: 3: 001010iiiiiieeee00110100ssssdddd | Re = #u6 ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x28003600) { - // Instruction: 3: 001010iiiiiieeee00110110ssssdddd | Re = #u6 ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x30003a00) { - // Instruction: 3: 00110000sssseeee0011101--0--dddd | Re = Rs ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___RS___RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c00) { - // Instruction: 3: 00110000sssseeee001111-0-ii00ddd | Re = Rs ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c08) { - // Instruction: 3: 00110000sssseeee001111-0-ii01ddd | Re = Rs ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c10) { - // Instruction: 3: 00110000sssseeee001111-0-ii10ddd | Re = Rs ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x30003c18) { - // Instruction: 3: 00110000sssseeee001111-0-ii11ddd | Re = Rs ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a70) { - // Instruction: 3: 00110000sssseeee0011101--111dddd | Re = Rs ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a50) { - // Instruction: 3: 00110000sssseeee0011101--101dddd | Re = Rs ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a60) { - // Instruction: 3: 00110000sssseeee0011101--110dddd | Re = Rs ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x30003a40) { - // Instruction: 3: 00110000sssseeee0011101--100dddd | Re = Rs ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___RS___IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003000) { - // Instruction: 3: 00110000uuuueeee00110000ssssdddd | Re = Ru ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003300) { - // Instruction: 3: 00110000uuuueeee00110011ssssdddd | Re = Ru ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003100) { - // Instruction: 3: 00110000uuuueeee00110001ssssdddd | Re = Ru ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003200) { - // Instruction: 3: 00110000uuuueeee00110010ssssdddd | Re = Ru ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003700) { - // Instruction: 3: 00110000uuuueeee00110111ssssdddd | Re = Ru ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003500) { - // Instruction: 3: 00110000uuuueeee00110101ssssdddd | Re = Ru ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003400) { - // Instruction: 3: 00110000uuuueeee00110100ssssdddd | Re = Ru ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x30003600) { - // Instruction: 3: 00110000uuuueeee00110110ssssdddd | Re = Ru ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x30003d00) { - // Instruction: 3: 00110000uuuueeee001111-1ssss0ddd | Re = Ru ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x30003d08) { - // Instruction: 3: 00110000uuuueeee001111-1ssss1ddd | Re = Ru ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x33003a00) { - // Instruction: 3: 00110011sssseeee0011101--0--dddd | Re = add (Rs, #-1) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c00) { - // Instruction: 3: 00110011sssseeee001111-0-ii00ddd | Re = add (Rs, #-1) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c08) { - // Instruction: 3: 00110011sssseeee001111-0-ii01ddd | Re = add (Rs, #-1) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c10) { - // Instruction: 3: 00110011sssseeee001111-0-ii10ddd | Re = add (Rs, #-1) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x33003c18) { - // Instruction: 3: 00110011sssseeee001111-0-ii11ddd | Re = add (Rs, #-1) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a70) { - // Instruction: 3: 00110011sssseeee0011101--111dddd | Re = add (Rs, #-1) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a50) { - // Instruction: 3: 00110011sssseeee0011101--101dddd | Re = add (Rs, #-1) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a60) { - // Instruction: 3: 00110011sssseeee0011101--110dddd | Re = add (Rs, #-1) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x33003a40) { - // Instruction: 3: 00110011sssseeee0011101--100dddd | Re = add (Rs, #-1) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x31003a00) { - // Instruction: 3: 00110001sssseeee0011101--0--dddd | Re = add (Rs, #1) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c00) { - // Instruction: 3: 00110001sssseeee001111-0-ii00ddd | Re = add (Rs, #1) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c08) { - // Instruction: 3: 00110001sssseeee001111-0-ii01ddd | Re = add (Rs, #1) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c10) { - // Instruction: 3: 00110001sssseeee001111-0-ii10ddd | Re = add (Rs, #1) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x31003c18) { - // Instruction: 3: 00110001sssseeee001111-0-ii11ddd | Re = add (Rs, #1) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a70) { - // Instruction: 3: 00110001sssseeee0011101--111dddd | Re = add (Rs, #1) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a50) { - // Instruction: 3: 00110001sssseeee0011101--101dddd | Re = add (Rs, #1) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a60) { - // Instruction: 3: 00110001sssseeee0011101--110dddd | Re = add (Rs, #1) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x31003a40) { - // Instruction: 3: 00110001sssseeee0011101--100dddd | Re = add (Rs, #1) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003300) { - // Instruction: 3: 00110011uuuueeee00110011ssssdddd | Re = add (Ru, #-1) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003700) { - // Instruction: 3: 00110011uuuueeee00110111ssssdddd | Re = add (Ru, #-1) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003500) { - // Instruction: 3: 00110011uuuueeee00110101ssssdddd | Re = add (Ru, #-1) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003400) { - // Instruction: 3: 00110011uuuueeee00110100ssssdddd | Re = add (Ru, #-1) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x33003600) { - // Instruction: 3: 00110011uuuueeee00110110ssssdddd | Re = add (Ru, #-1) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x33003d00) { - // Instruction: 3: 00110011uuuueeee001111-1ssss0ddd | Re = add (Ru, #-1) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x33003d08) { - // Instruction: 3: 00110011uuuueeee001111-1ssss1ddd | Re = add (Ru, #-1) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003300) { - // Instruction: 3: 00110001uuuueeee00110011ssssdddd | Re = add (Ru, #1) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003100) { - // Instruction: 3: 00110001uuuueeee00110001ssssdddd | Re = add (Ru, #1) ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003200) { - // Instruction: 3: 00110001uuuueeee00110010ssssdddd | Re = add (Ru, #1) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003700) { - // Instruction: 3: 00110001uuuueeee00110111ssssdddd | Re = add (Ru, #1) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003500) { - // Instruction: 3: 00110001uuuueeee00110101ssssdddd | Re = add (Ru, #1) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003400) { - // Instruction: 3: 00110001uuuueeee00110100ssssdddd | Re = add (Ru, #1) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x31003600) { - // Instruction: 3: 00110001uuuueeee00110110ssssdddd | Re = add (Ru, #1) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x31003d00) { - // Instruction: 3: 00110001uuuueeee001111-1ssss0ddd | Re = add (Ru, #1) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x31003d08) { - // Instruction: 3: 00110001uuuueeee001111-1ssss1ddd | Re = add (Ru, #1) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe40) == 0x2c003a00) { - // Instruction: 3: 001011IIIIIIeeee0011101--0--dddd | Re = add (Sp, #U6:2) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003300) { - // Instruction: 3: 001011IIIIIIeeee00110011ssssdddd | Re = add (Sp, #U6:2) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003100) { - // Instruction: 3: 001011IIIIIIeeee00110001ssssdddd | Re = add (Sp, #U6:2) ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fc00) == 0x2c002c00) { - // Instruction: 3: 001011IIIIIIeeee001011iiiiiidddd | Re = add (Sp, #U6:2) ; Rd = add (Sp, #u6:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__SP___U6_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = add (Sp, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003200) { - // Instruction: 3: 001011IIIIIIeeee00110010ssssdddd | Re = add (Sp, #U6:2) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003700) { - // Instruction: 3: 001011IIIIIIeeee00110111ssssdddd | Re = add (Sp, #U6:2) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c00) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii00ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x2c003d00) { - // Instruction: 3: 001011IIIIIIeeee001111-1ssss0ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c08) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii01ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c10) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii10ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd18) == 0x2c003c18) { - // Instruction: 3: 001011IIIIIIeeee001111-0-ii11ddd | Re = add (Sp, #U6:2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fd08) == 0x2c003d08) { - // Instruction: 3: 001011IIIIIIeeee001111-1ssss1ddd | Re = add (Sp, #U6:2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a70) { - // Instruction: 3: 001011IIIIIIeeee0011101--111dddd | Re = add (Sp, #U6:2) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a50) { - // Instruction: 3: 001011IIIIIIeeee0011101--101dddd | Re = add (Sp, #U6:2) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a60) { - // Instruction: 3: 001011IIIIIIeeee0011101--110dddd | Re = add (Sp, #U6:2) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe70) == 0x2c003a40) { - // Instruction: 3: 001011IIIIIIeeee0011101--100dddd | Re = add (Sp, #U6:2) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003000) { - // Instruction: 3: 001011iiiiiieeee00110000ssssdddd | Re = add (Sp, #u6:2) ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003500) { - // Instruction: 3: 001011iiiiiieeee00110101ssssdddd | Re = add (Sp, #u6:2) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003400) { - // Instruction: 3: 001011iiiiiieeee00110100ssssdddd | Re = add (Sp, #u6:2) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x2c003600) { - // Instruction: 3: 001011iiiiiieeee00110110ssssdddd | Re = add (Sp, #u6:2) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x32003a00) { - // Instruction: 3: 00110010sssseeee0011101--0--dddd | Re = and (Rs, #1) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c00) { - // Instruction: 3: 00110010sssseeee001111-0-ii00ddd | Re = and (Rs, #1) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c08) { - // Instruction: 3: 00110010sssseeee001111-0-ii01ddd | Re = and (Rs, #1) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c10) { - // Instruction: 3: 00110010sssseeee001111-0-ii10ddd | Re = and (Rs, #1) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x32003c18) { - // Instruction: 3: 00110010sssseeee001111-0-ii11ddd | Re = and (Rs, #1) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a70) { - // Instruction: 3: 00110010sssseeee0011101--111dddd | Re = and (Rs, #1) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a50) { - // Instruction: 3: 00110010sssseeee0011101--101dddd | Re = and (Rs, #1) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a60) { - // Instruction: 3: 00110010sssseeee0011101--110dddd | Re = and (Rs, #1) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x32003a40) { - // Instruction: 3: 00110010sssseeee0011101--100dddd | Re = and (Rs, #1) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x37003a00) { - // Instruction: 3: 00110111sssseeee0011101--0--dddd | Re = and (Rs, #255) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c00) { - // Instruction: 3: 00110111sssseeee001111-0-ii00ddd | Re = and (Rs, #255) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c08) { - // Instruction: 3: 00110111sssseeee001111-0-ii01ddd | Re = and (Rs, #255) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c10) { - // Instruction: 3: 00110111sssseeee001111-0-ii10ddd | Re = and (Rs, #255) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x37003c18) { - // Instruction: 3: 00110111sssseeee001111-0-ii11ddd | Re = and (Rs, #255) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a70) { - // Instruction: 3: 00110111sssseeee0011101--111dddd | Re = and (Rs, #255) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a50) { - // Instruction: 3: 00110111sssseeee0011101--101dddd | Re = and (Rs, #255) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a60) { - // Instruction: 3: 00110111sssseeee0011101--110dddd | Re = and (Rs, #255) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x37003a40) { - // Instruction: 3: 00110111sssseeee0011101--100dddd | Re = and (Rs, #255) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003300) { - // Instruction: 3: 00110010uuuueeee00110011ssssdddd | Re = and (Ru, #1) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003200) { - // Instruction: 3: 00110010uuuueeee00110010ssssdddd | Re = and (Ru, #1) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003700) { - // Instruction: 3: 00110010uuuueeee00110111ssssdddd | Re = and (Ru, #1) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003500) { - // Instruction: 3: 00110010uuuueeee00110101ssssdddd | Re = and (Ru, #1) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003400) { - // Instruction: 3: 00110010uuuueeee00110100ssssdddd | Re = and (Ru, #1) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x32003600) { - // Instruction: 3: 00110010uuuueeee00110110ssssdddd | Re = and (Ru, #1) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x32003d00) { - // Instruction: 3: 00110010uuuueeee001111-1ssss0ddd | Re = and (Ru, #1) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x32003d08) { - // Instruction: 3: 00110010uuuueeee001111-1ssss1ddd | Re = and (Ru, #1) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x37003700) { - // Instruction: 3: 00110111uuuueeee00110111ssssdddd | Re = and (Ru, #255) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x37003d00) { - // Instruction: 3: 00110111uuuueeee001111-1ssss0ddd | Re = and (Ru, #255) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x37003d08) { - // Instruction: 3: 00110111uuuueeee001111-1ssss1ddd | Re = and (Ru, #255) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x35003a00) { - // Instruction: 3: 00110101sssseeee0011101--0--dddd | Re = sxtb (Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c00) { - // Instruction: 3: 00110101sssseeee001111-0-ii00ddd | Re = sxtb (Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c08) { - // Instruction: 3: 00110101sssseeee001111-0-ii01ddd | Re = sxtb (Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c10) { - // Instruction: 3: 00110101sssseeee001111-0-ii10ddd | Re = sxtb (Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x35003c18) { - // Instruction: 3: 00110101sssseeee001111-0-ii11ddd | Re = sxtb (Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a70) { - // Instruction: 3: 00110101sssseeee0011101--111dddd | Re = sxtb (Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a50) { - // Instruction: 3: 00110101sssseeee0011101--101dddd | Re = sxtb (Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a60) { - // Instruction: 3: 00110101sssseeee0011101--110dddd | Re = sxtb (Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x35003a40) { - // Instruction: 3: 00110101sssseeee0011101--100dddd | Re = sxtb (Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003700) { - // Instruction: 3: 00110101uuuueeee00110111ssssdddd | Re = sxtb (Ru) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003500) { - // Instruction: 3: 00110101uuuueeee00110101ssssdddd | Re = sxtb (Ru) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x35003600) { - // Instruction: 3: 00110101uuuueeee00110110ssssdddd | Re = sxtb (Ru) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x35003d00) { - // Instruction: 3: 00110101uuuueeee001111-1ssss0ddd | Re = sxtb (Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x35003d08) { - // Instruction: 3: 00110101uuuueeee001111-1ssss1ddd | Re = sxtb (Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x34003a00) { - // Instruction: 3: 00110100sssseeee0011101--0--dddd | Re = sxth (Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c00) { - // Instruction: 3: 00110100sssseeee001111-0-ii00ddd | Re = sxth (Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c08) { - // Instruction: 3: 00110100sssseeee001111-0-ii01ddd | Re = sxth (Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c10) { - // Instruction: 3: 00110100sssseeee001111-0-ii10ddd | Re = sxth (Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x34003c18) { - // Instruction: 3: 00110100sssseeee001111-0-ii11ddd | Re = sxth (Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a70) { - // Instruction: 3: 00110100sssseeee0011101--111dddd | Re = sxth (Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a50) { - // Instruction: 3: 00110100sssseeee0011101--101dddd | Re = sxth (Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a60) { - // Instruction: 3: 00110100sssseeee0011101--110dddd | Re = sxth (Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x34003a40) { - // Instruction: 3: 00110100sssseeee0011101--100dddd | Re = sxth (Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003700) { - // Instruction: 3: 00110100uuuueeee00110111ssssdddd | Re = sxth (Ru) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003500) { - // Instruction: 3: 00110100uuuueeee00110101ssssdddd | Re = sxth (Ru) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003400) { - // Instruction: 3: 00110100uuuueeee00110100ssssdddd | Re = sxth (Ru) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x34003600) { - // Instruction: 3: 00110100uuuueeee00110110ssssdddd | Re = sxth (Ru) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x34003d00) { - // Instruction: 3: 00110100uuuueeee001111-1ssss0ddd | Re = sxth (Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x34003d08) { - // Instruction: 3: 00110100uuuueeee001111-1ssss1ddd | Re = sxth (Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x36003a00) { - // Instruction: 3: 00110110sssseeee0011101--0--dddd | Re = zxth (Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c00) { - // Instruction: 3: 00110110sssseeee001111-0-ii00ddd | Re = zxth (Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c08) { - // Instruction: 3: 00110110sssseeee001111-0-ii01ddd | Re = zxth (Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c10) { - // Instruction: 3: 00110110sssseeee001111-0-ii10ddd | Re = zxth (Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x36003c18) { - // Instruction: 3: 00110110sssseeee001111-0-ii11ddd | Re = zxth (Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a70) { - // Instruction: 3: 00110110sssseeee0011101--111dddd | Re = zxth (Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a50) { - // Instruction: 3: 00110110sssseeee0011101--101dddd | Re = zxth (Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a60) { - // Instruction: 3: 00110110sssseeee0011101--110dddd | Re = zxth (Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x36003a40) { - // Instruction: 3: 00110110sssseeee0011101--100dddd | Re = zxth (Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003700) { - // Instruction: 3: 00110110uuuueeee00110111ssssdddd | Re = zxth (Ru) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x36003600) { - // Instruction: 3: 00110110uuuueeee00110110ssssdddd | Re = zxth (Ru) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x36003d00) { - // Instruction: 3: 00110110uuuueeee001111-1ssss0ddd | Re = zxth (Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x36003d08) { - // Instruction: 3: 00110110uuuueeee001111-1ssss1ddd | Re = zxth (Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c00) { - // Instruction: 3: 001111-0-II00eee001111-0-ii00ddd | Ree = combine (#0, #U2) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#0, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c003d00) { - // Instruction: 3: 001111-0-II00eee001111-1ssss0ddd | Ree = combine (#0, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c08) { - // Instruction: 3: 001111-0-II00eee001111-0-ii01ddd | Ree = combine (#0, #U2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c10) { - // Instruction: 3: 001111-0-II00eee001111-0-ii10ddd | Ree = combine (#0, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c003c18) { - // Instruction: 3: 001111-0-II00eee001111-0-ii11ddd | Ree = combine (#0, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c003d08) { - // Instruction: 3: 001111-0-II00eee001111-1ssss1ddd | Ree = combine (#0, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fd08) == 0x3d003d00) { - // Instruction: 3: 001111-1uuuu0eee001111-1ssss0ddd | Ree = combine (#0, Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fd08) == 0x3d003d08) { - // Instruction: 3: 001111-1uuuu0eee001111-1ssss1ddd | Ree = combine (#0, Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c083d00) { - // Instruction: 3: 001111-0-II01eee001111-1ssss0ddd | Ree = combine (#1, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c083c08) { - // Instruction: 3: 001111-0-II01eee001111-0-ii01ddd | Ree = combine (#1, #U2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c083c10) { - // Instruction: 3: 001111-0-II01eee001111-0-ii10ddd | Ree = combine (#1, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c083c18) { - // Instruction: 3: 001111-0-II01eee001111-0-ii11ddd | Ree = combine (#1, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c083d08) { - // Instruction: 3: 001111-0-II01eee001111-1ssss1ddd | Ree = combine (#1, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c103d00) { - // Instruction: 3: 001111-0-II10eee001111-1ssss0ddd | Ree = combine (#2, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c103c10) { - // Instruction: 3: 001111-0-II10eee001111-0-ii10ddd | Ree = combine (#2, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c103c18) { - // Instruction: 3: 001111-0-II10eee001111-0-ii11ddd | Ree = combine (#2, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c103d08) { - // Instruction: 3: 001111-0-II10eee001111-1ssss1ddd | Ree = combine (#2, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c183d00) { - // Instruction: 3: 001111-0-II11eee001111-1ssss0ddd | Ree = combine (#3, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fd18) == 0x3c183c18) { - // Instruction: 3: 001111-0-II11eee001111-0-ii11ddd | Ree = combine (#3, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fd08) == 0x3c183d08) { - // Instruction: 3: 001111-0-II11eee001111-1ssss1ddd | Ree = combine (#3, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fd08) == 0x3d083d08) { - // Instruction: 3: 001111-1uuuu1eee001111-1ssss1ddd | Ree = combine (Ru, #0) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = combine (%s, #0)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x38003a00) { - // Instruction: 3: 00111000ssssxxxx0011101--0--dddd | Rx = add (Rs, Rx) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c00) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii00ddd | Rx = add (Rs, Rx) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c08) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii01ddd | Rx = add (Rs, Rx) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c10) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii10ddd | Rx = add (Rs, Rx) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c18) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii11ddd | Rx = add (Rs, Rx) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a70) { - // Instruction: 3: 00111000ssssxxxx0011101--111dddd | Rx = add (Rs, Rx) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a50) { - // Instruction: 3: 00111000ssssxxxx0011101--101dddd | Rx = add (Rs, Rx) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a60) { - // Instruction: 3: 00111000ssssxxxx0011101--110dddd | Rx = add (Rs, Rx) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a40) { - // Instruction: 3: 00111000ssssxxxx0011101--100dddd | Rx = add (Rs, Rx) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d00) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss0ddd | Rx = add (Ru, Rx) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d08) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss1ddd | Rx = add (Ru, Rx) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003900) { - // Instruction: 3: 00111000uuuuxxxx00111001ssss--ii | Rx = add (Ru, Rx) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe40) == 0x20003a00) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--0--dddd | Rx = add (Rx, #S7) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fc00) == 0x20002800) { - // Instruction: 3: 00100IIIIIIIxxxx001010iiiiiidddd | Rx = add (Rx, #S7) ; Rd = #u6 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD____U6; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = 0x%x", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003300) { - // Instruction: 3: 00100IIIIIIIxxxx00110011ssssdddd | Rx = add (Rx, #S7) ; Rd = add (Rs, #-1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__RS____1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = add (%s, #-1)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003100) { - // Instruction: 3: 00100IIIIIIIxxxx00110001ssssdddd | Rx = add (Rx, #S7) ; Rd = add (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = add (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fc00) == 0x20002c00) { - // Instruction: 3: 00100IIIIIIIxxxx001011iiiiiidddd | Rx = add (Rx, #S7) ; Rd = add (Sp, #u6:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ADD__SP___U6_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = add (Sp, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003200) { - // Instruction: 3: 00100IIIIIIIxxxx00110010ssssdddd | Rx = add (Rx, #S7) ; Rd = and (Rs, #1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___AND__RS___1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = and (%s, #1)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003700) { - // Instruction: 3: 00100IIIIIIIxxxx00110111ssssdddd | Rx = add (Rx, #S7) ; Rd = and (Rs, #255) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___AND__RS___255_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = and (%s, #255)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c00) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii00ddd | Rx = add (Rx, #S7) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd08) == 0x20003d00) { - // Instruction: 3: 00100IIIIIIIxxxx001111-1ssss0ddd | Rx = add (Rx, #S7) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c08) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii01ddd | Rx = add (Rx, #S7) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c10) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii10ddd | Rx = add (Rx, #S7) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd18) == 0x20003c18) { - // Instruction: 3: 00100IIIIIIIxxxx001111-0-ii11ddd | Rx = add (Rx, #S7) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fd08) == 0x20003d08) { - // Instruction: 3: 00100IIIIIIIxxxx001111-1ssss1ddd | Rx = add (Rx, #S7) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a70) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--111dddd | Rx = add (Rx, #S7) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a50) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--101dddd | Rx = add (Rx, #S7) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a60) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--110dddd | Rx = add (Rx, #S7) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe70) == 0x20003a40) { - // Instruction: 3: 00100IIIIIIIxxxx0011101--100dddd | Rx = add (Rx, #S7) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003900) { - // Instruction: 3: 00100IIIIIIIxxxx00111001ssss--ii | Rx = add (Rx, #S7) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003000) { - // Instruction: 3: 00100iiiiiiixxxx00110000ssssdddd | Rx = add (Rx, #s7) ; Rd = Rs - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___RS; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003500) { - // Instruction: 3: 00100iiiiiiixxxx00110101ssssdddd | Rx = add (Rx, #s7) ; Rd = sxtb (Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___SXTB__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = sxtb (%s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003400) { - // Instruction: 3: 00100iiiiiiixxxx00110100ssssdddd | Rx = add (Rx, #s7) ; Rd = sxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___SXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = sxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003600) { - // Instruction: 3: 00100iiiiiiixxxx00110110ssssdddd | Rx = add (Rx, #s7) ; Rd = zxth (Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___ZXTH__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = zxth (%s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x38003a00) { - // Instruction: 3: 00111000ssssxxxx0011101--0--dddd | Rx = add (Rx, Rs) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c00) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii00ddd | Rx = add (Rx, Rs) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c08) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii01ddd | Rx = add (Rx, Rs) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c10) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii10ddd | Rx = add (Rx, Rs) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x38003c18) { - // Instruction: 3: 00111000ssssxxxx001111-0-ii11ddd | Rx = add (Rx, Rs) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a70) { - // Instruction: 3: 00111000ssssxxxx0011101--111dddd | Rx = add (Rx, Rs) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a50) { - // Instruction: 3: 00111000ssssxxxx0011101--101dddd | Rx = add (Rx, Rs) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a60) { - // Instruction: 3: 00111000ssssxxxx0011101--110dddd | Rx = add (Rx, Rs) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x38003a40) { - // Instruction: 3: 00111000ssssxxxx0011101--100dddd | Rx = add (Rx, Rs) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d00) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss0ddd | Rx = add (Rx, Ru) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x38003d08) { - // Instruction: 3: 00111000uuuuxxxx001111-1ssss1ddd | Rx = add (Rx, Ru) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003900) { - // Instruction: 3: 00111000uuuuxxxx00111001ssss--ii | Rx = add (Rx, Ru) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ru, Ry) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RU__RY____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Ry) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ru, Ry) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RU__RY____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Ry) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800f800) == 0x20002000) { - // Instruction: 3: 00100IIIIIIIyyyy00100iiiiiiixxxx | Ry = add (Ry, #S7) ; Rx = add (Rx, #s7) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RX___S7_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7f0) >> 4); - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %d) ; %s = add (Rx, %d)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003800) { - // Instruction: 3: 00100iiiiiiiyyyy00111000ssssxxxx | Ry = add (Ry, #s7) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %d) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x20003800) { - // Instruction: 3: 00100iiiiiiiyyyy00111000ssssxxxx | Ry = add (Ry, #s7) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY___S7____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %d) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ry, Ru) ; Rx = add (Rs, Rx) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY__RU____RX___ADD__RS__RX_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %s) ; %s = add (%s, Rx)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x38003800) { - // Instruction: 3: 00111000uuuuyyyy00111000ssssxxxx | Ry = add (Ry, Ru) ; Rx = add (Rx, Rs) - hi->instruction = HEX_INS_DUPLEX_RY___ADD__RY__RU____RX___ADD__RX__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Ry, %s) ; %s = add (Rx, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c00) { - // Instruction: 3: 0011101--111eeee001111-0-ii00ddd | if (! p0) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a703d00) { - // Instruction: 3: 0011101--111eeee001111-1ssss0ddd | if (! p0) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c08) { - // Instruction: 3: 0011101--111eeee001111-0-ii01ddd | if (! p0) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c10) { - // Instruction: 3: 0011101--111eeee001111-0-ii10ddd | if (! p0) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a703c18) { - // Instruction: 3: 0011101--111eeee001111-0-ii11ddd | if (! p0) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a703d08) { - // Instruction: 3: 0011101--111eeee001111-1ssss1ddd | if (! p0) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a703a70) { - // Instruction: 3: 0011101--111eeee0011101--111dddd | if (! p0) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c00) { - // Instruction: 3: 0011101--101eeee001111-0-ii00ddd | if (! p0.new) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a503d00) { - // Instruction: 3: 0011101--101eeee001111-1ssss0ddd | if (! p0.new) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c08) { - // Instruction: 3: 0011101--101eeee001111-0-ii01ddd | if (! p0.new) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c10) { - // Instruction: 3: 0011101--101eeee001111-0-ii10ddd | if (! p0.new) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a503c18) { - // Instruction: 3: 0011101--101eeee001111-0-ii11ddd | if (! p0.new) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a503d08) { - // Instruction: 3: 0011101--101eeee001111-1ssss1ddd | if (! p0.new) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a503a70) { - // Instruction: 3: 0011101--101eeee0011101--111dddd | if (! p0.new) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a503a50) { - // Instruction: 3: 0011101--101eeee0011101--101dddd | if (! p0.new) Re = #0 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF___NOT__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a503a60) { - // Instruction: 3: 0011101--101eeee0011101--110dddd | if (! p0.new) Re = #0 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c00) { - // Instruction: 3: 0011101--110eeee001111-0-ii00ddd | if (p0) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a603d00) { - // Instruction: 3: 0011101--110eeee001111-1ssss0ddd | if (p0) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c08) { - // Instruction: 3: 0011101--110eeee001111-0-ii01ddd | if (p0) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c10) { - // Instruction: 3: 0011101--110eeee001111-0-ii10ddd | if (p0) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a603c18) { - // Instruction: 3: 0011101--110eeee001111-0-ii11ddd | if (p0) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a603d08) { - // Instruction: 3: 0011101--110eeee001111-1ssss1ddd | if (p0) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a603a70) { - // Instruction: 3: 0011101--110eeee0011101--111dddd | if (p0) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a603a60) { - // Instruction: 3: 0011101--110eeee0011101--110dddd | if (p0) Re = #0 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c00) { - // Instruction: 3: 0011101--100eeee001111-0-ii00ddd | if (p0.new) Re = #0 ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___0___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a403d00) { - // Instruction: 3: 0011101--100eeee001111-1ssss0ddd | if (p0.new) Re = #0 ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___0__RS_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c08) { - // Instruction: 3: 0011101--100eeee001111-0-ii01ddd | if (p0.new) Re = #0 ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___1___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c10) { - // Instruction: 3: 0011101--100eeee001111-0-ii10ddd | if (p0.new) Re = #0 ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___2___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd18) == 0x3a403c18) { - // Instruction: 3: 0011101--100eeee001111-0-ii11ddd | if (p0.new) Re = #0 ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE___3___U2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fd08) == 0x3a403d08) { - // Instruction: 3: 0011101--100eeee001111-1ssss1ddd | if (p0.new) Re = #0 ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___COMBINE__RS___0_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a70) { - // Instruction: 3: 0011101--100eeee0011101--111dddd | if (p0.new) Re = #0 ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF___NOT__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a50) { - // Instruction: 3: 0011101--100eeee0011101--101dddd | if (p0.new) Re = #0 ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF___NOT__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a60) { - // Instruction: 3: 0011101--100eeee0011101--110dddd | if (p0.new) Re = #0 ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF__P0__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe70) == 0x3a403a40) { - // Instruction: 3: 0011101--100eeee0011101--100dddd | if (p0.new) Re = #0 ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___IF__P0_NEW__RD____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe40) == 0x39003a00) { - // Instruction: 3: 00111001ssss--II0011101--0--dddd | p0 = cmp.eq (Rs, #U2) ; Rd = #-1 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RD_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = #-1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c00) { - // Instruction: 3: 00111001ssss--II001111-0-ii00ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#0, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___0___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#0, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c08) { - // Instruction: 3: 00111001ssss--II001111-0-ii01ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#1, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___1___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#1, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c10) { - // Instruction: 3: 00111001ssss--II001111-0-ii10ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#2, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___2___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#2, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fd18) == 0x39003c18) { - // Instruction: 3: 00111001ssss--II001111-0-ii11ddd | p0 = cmp.eq (Rs, #U2) ; Rdd = combine (#3, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___COMBINE___3___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#3, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a70) { - // Instruction: 3: 00111001ssss--II0011101--111dddd | p0 = cmp.eq (Rs, #U2) ; if (! p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a50) { - // Instruction: 3: 00111001ssss--II0011101--101dddd | p0 = cmp.eq (Rs, #U2) ; if (! p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a60) { - // Instruction: 3: 00111001ssss--II0011101--110dddd | p0 = cmp.eq (Rs, #U2) ; if (p0) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe70) == 0x39003a40) { - // Instruction: 3: 00111001ssss--II0011101--100dddd | p0 = cmp.eq (Rs, #U2) ; if (p0.new) Rd = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__RD____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0.new) %s = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x39003d00) { - // Instruction: 3: 00111001uuuu--II001111-1ssss0ddd | p0 = cmp.eq (Ru, #U2) ; Rdd = combine (#0, Rs) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RDD___COMBINE___0__RS_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (#0, %s)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fd08) == 0x39003d08) { - // Instruction: 3: 00111001uuuu--II001111-1ssss1ddd | p0 = cmp.eq (Ru, #U2) ; Rdd = combine (Rs, #0) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RDD___COMBINE__RS___0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = combine (%s, #0)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x39003900) { - // Instruction: 3: 00111001uuuu--II00111001ssss--ii | p0 = cmp.eq (Ru, #U2) ; p0 = cmp.eq (Rs, #u2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____P0___CMP_EQ__RS___U2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; p0 = cmp.eq (%s, 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - break; - } - case 0x4: { - if ((hi_u32 & 0xfe40f000) == 0x5a001000) { - // Instruction: 4: 0101101--0--eeee0001iiiissssdddd | Re = #-1 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40f000) == 0x5a000000) { - // Instruction: 4: 0101101--0--eeee0000iiiissssdddd | Re = #-1 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x48001000) { - // Instruction: 4: 010010IIIIIIeeee0001iiiissssdddd | Re = #U6 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x48000000) { - // Instruction: 4: 010010IIIIIIeeee0000iiiissssdddd | Re = #U6 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x50001000) { - // Instruction: 4: 01010000uuuueeee0001iiiissssdddd | Re = Ru ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x50000000) { - // Instruction: 4: 01010000uuuueeee0000iiiissssdddd | Re = Ru ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x53001000) { - // Instruction: 4: 01010011uuuueeee0001iiiissssdddd | Re = add (Ru, #-1) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x53000000) { - // Instruction: 4: 01010011uuuueeee0000iiiissssdddd | Re = add (Ru, #-1) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x51001000) { - // Instruction: 4: 01010001uuuueeee0001iiiissssdddd | Re = add (Ru, #1) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x51000000) { - // Instruction: 4: 01010001uuuueeee0000iiiissssdddd | Re = add (Ru, #1) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x4c001000) { - // Instruction: 4: 010011IIIIIIeeee0001iiiissssdddd | Re = add (Sp, #U6:2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x4c000000) { - // Instruction: 4: 010011IIIIIIeeee0000iiiissssdddd | Re = add (Sp, #U6:2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x52001000) { - // Instruction: 4: 01010010uuuueeee0001iiiissssdddd | Re = and (Ru, #1) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x52000000) { - // Instruction: 4: 01010010uuuueeee0000iiiissssdddd | Re = and (Ru, #1) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x57001000) { - // Instruction: 4: 01010111uuuueeee0001iiiissssdddd | Re = and (Ru, #255) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x57000000) { - // Instruction: 4: 01010111uuuueeee0000iiiissssdddd | Re = and (Ru, #255) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x55001000) { - // Instruction: 4: 01010101uuuueeee0001iiiissssdddd | Re = sxtb (Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x55000000) { - // Instruction: 4: 01010101uuuueeee0000iiiissssdddd | Re = sxtb (Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x54001000) { - // Instruction: 4: 01010100uuuueeee0001iiiissssdddd | Re = sxth (Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x54000000) { - // Instruction: 4: 01010100uuuueeee0000iiiissssdddd | Re = sxth (Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x56001000) { - // Instruction: 4: 01010110uuuueeee0001iiiissssdddd | Re = zxth (Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x56000000) { - // Instruction: 4: 01010110uuuueeee0000iiiissssdddd | Re = zxth (Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c001000) { - // Instruction: 4: 010111-0-II00eee0001iiiissssdddd | Ree = combine (#0, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c000000) { - // Instruction: 4: 010111-0-II00eee0000iiiissssdddd | Ree = combine (#0, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d001000) { - // Instruction: 4: 010111-1uuuu0eee0001iiiissssdddd | Ree = combine (#0, Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d000000) { - // Instruction: 4: 010111-1uuuu0eee0000iiiissssdddd | Ree = combine (#0, Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c081000) { - // Instruction: 4: 010111-0-II01eee0001iiiissssdddd | Ree = combine (#1, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c080000) { - // Instruction: 4: 010111-0-II01eee0000iiiissssdddd | Ree = combine (#1, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c101000) { - // Instruction: 4: 010111-0-II10eee0001iiiissssdddd | Ree = combine (#2, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c100000) { - // Instruction: 4: 010111-0-II10eee0000iiiissssdddd | Ree = combine (#2, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c181000) { - // Instruction: 4: 010111-0-II11eee0001iiiissssdddd | Ree = combine (#3, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x5c180000) { - // Instruction: 4: 010111-0-II11eee0000iiiissssdddd | Ree = combine (#3, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d081000) { - // Instruction: 4: 010111-1uuuu1eee0001iiiissssdddd | Ree = combine (Ru, #0) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memub (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x5d080000) { - // Instruction: 4: 010111-1uuuu1eee0000iiiissssdddd | Ree = combine (Ru, #0) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memw (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58001000) { - // Instruction: 4: 01011000uuuuxxxx0001iiiissssdddd | Rx = add (Ru, Rx) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58000000) { - // Instruction: 4: 01011000uuuuxxxx0000iiiissssdddd | Rx = add (Ru, Rx) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f000) == 0x40001000) { - // Instruction: 4: 01000IIIIIIIxxxx0001iiiissssdddd | Rx = add (Rx, #S7) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f000) == 0x40000000) { - // Instruction: 4: 01000IIIIIIIxxxx0000iiiissssdddd | Rx = add (Rx, #S7) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58001000) { - // Instruction: 4: 01011000uuuuxxxx0001iiiissssdddd | Rx = add (Rx, Ru) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x58000000) { - // Instruction: 4: 01011000uuuuxxxx0000iiiissssdddd | Rx = add (Rx, Ru) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a701000) { - // Instruction: 4: 0101101--111eeee0001iiiissssdddd | if (! p0) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a700000) { - // Instruction: 4: 0101101--111eeee0000iiiissssdddd | if (! p0) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a501000) { - // Instruction: 4: 0101101--101eeee0001iiiissssdddd | if (! p0.new) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a500000) { - // Instruction: 4: 0101101--101eeee0000iiiissssdddd | if (! p0.new) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a601000) { - // Instruction: 4: 0101101--110eeee0001iiiissssdddd | if (p0) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a600000) { - // Instruction: 4: 0101101--110eeee0000iiiissssdddd | if (p0) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a401000) { - // Instruction: 4: 0101101--100eeee0001iiiissssdddd | if (p0.new) Re = #0 ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMUB__RS____U4_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x5a400000) { - // Instruction: 4: 0101101--100eeee0000iiiissssdddd | if (p0.new) Re = #0 ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMW__RS____U4_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x59001000) { - // Instruction: 4: 01011001uuuu--II0001iiiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memub (Rs + #u4:0) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMUB__RS____U4_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memub (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f000) == 0x59000000) { - // Instruction: 4: 01011001uuuu--II0000iiiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memw (Rs + #u4:2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMW__RS____U4_2_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memw (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - break; - } - case 0x5: { - if ((hi_u32 & 0xfe40ffc4) == 0x5a003f40) { - // Instruction: 5: 0101101--0--dddd0011111101---0-- | Rd = #-1 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD_____1___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc4) == 0x5a003f00) { - // Instruction: 5: 0101101--0--dddd0011111100---0-- | Rd = #-1 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD_____1___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f45) { - // Instruction: 5: 0101101--0--dddd0011111101---101 | Rd = #-1 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc5) { - // Instruction: 5: 0101101--0--dddd0011111111---101 | Rd = #-1 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f47) { - // Instruction: 5: 0101101--0--dddd0011111101---111 | Rd = #-1 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc7) { - // Instruction: 5: 0101101--0--dddd0011111111---111 | Rd = #-1 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f44) { - // Instruction: 5: 0101101--0--dddd0011111101---100 | Rd = #-1 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc4) { - // Instruction: 5: 0101101--0--dddd0011111111---100 | Rd = #-1 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003f46) { - // Instruction: 5: 0101101--0--dddd0011111101---110 | Rd = #-1 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc7) == 0x5a003fc6) { - // Instruction: 5: 0101101--0--dddd0011111111---110 | Rd = #-1 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ffc4) == 0x5a003fc0) { - // Instruction: 5: 0101101--0--dddd0011111111---0-- | Rd = #-1 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD_____1___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x48003f40) { - // Instruction: 5: 010010iiiiiidddd0011111101---0-- | Rd = #u6 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD____U6___DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x48003f00) { - // Instruction: 5: 010010iiiiiidddd0011111100---0-- | Rd = #u6 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD____U6___DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f45) { - // Instruction: 5: 010010iiiiiidddd0011111101---101 | Rd = #u6 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc5) { - // Instruction: 5: 010010iiiiiidddd0011111111---101 | Rd = #u6 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f47) { - // Instruction: 5: 010010iiiiiidddd0011111101---111 | Rd = #u6 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc7) { - // Instruction: 5: 010010iiiiiidddd0011111111---111 | Rd = #u6 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f44) { - // Instruction: 5: 010010iiiiiidddd0011111101---100 | Rd = #u6 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc4) { - // Instruction: 5: 010010iiiiiidddd0011111111---100 | Rd = #u6 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003f46) { - // Instruction: 5: 010010iiiiiidddd0011111101---110 | Rd = #u6 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x48003fc6) { - // Instruction: 5: 010010iiiiiidddd0011111111---110 | Rd = #u6 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x48003fc0) { - // Instruction: 5: 010010iiiiiidddd0011111111---0-- | Rd = #u6 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD____U6___JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x50003f40) { - // Instruction: 5: 01010000ssssdddd0011111101---0-- | Rd = Rs ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___RS___DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x50003f00) { - // Instruction: 5: 01010000ssssdddd0011111100---0-- | Rd = Rs ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___RS___DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f45) { - // Instruction: 5: 01010000ssssdddd0011111101---101 | Rd = Rs ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc5) { - // Instruction: 5: 01010000ssssdddd0011111111---101 | Rd = Rs ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f47) { - // Instruction: 5: 01010000ssssdddd0011111101---111 | Rd = Rs ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc7) { - // Instruction: 5: 01010000ssssdddd0011111111---111 | Rd = Rs ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f44) { - // Instruction: 5: 01010000ssssdddd0011111101---100 | Rd = Rs ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc4) { - // Instruction: 5: 01010000ssssdddd0011111111---100 | Rd = Rs ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003f46) { - // Instruction: 5: 01010000ssssdddd0011111101---110 | Rd = Rs ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x50003fc6) { - // Instruction: 5: 01010000ssssdddd0011111111---110 | Rd = Rs ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x50003fc0) { - // Instruction: 5: 01010000ssssdddd0011111111---0-- | Rd = Rs ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___RS___JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x53003f40) { - // Instruction: 5: 01010011ssssdddd0011111101---0-- | Rd = add (Rs, #-1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x53003f00) { - // Instruction: 5: 01010011ssssdddd0011111100---0-- | Rd = add (Rs, #-1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f45) { - // Instruction: 5: 01010011ssssdddd0011111101---101 | Rd = add (Rs, #-1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc5) { - // Instruction: 5: 01010011ssssdddd0011111111---101 | Rd = add (Rs, #-1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f47) { - // Instruction: 5: 01010011ssssdddd0011111101---111 | Rd = add (Rs, #-1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc7) { - // Instruction: 5: 01010011ssssdddd0011111111---111 | Rd = add (Rs, #-1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f44) { - // Instruction: 5: 01010011ssssdddd0011111101---100 | Rd = add (Rs, #-1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc4) { - // Instruction: 5: 01010011ssssdddd0011111111---100 | Rd = add (Rs, #-1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003f46) { - // Instruction: 5: 01010011ssssdddd0011111101---110 | Rd = add (Rs, #-1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x53003fc6) { - // Instruction: 5: 01010011ssssdddd0011111111---110 | Rd = add (Rs, #-1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x53003fc0) { - // Instruction: 5: 01010011ssssdddd0011111111---0-- | Rd = add (Rs, #-1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x51003f40) { - // Instruction: 5: 01010001ssssdddd0011111101---0-- | Rd = add (Rs, #1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x51003f00) { - // Instruction: 5: 01010001ssssdddd0011111100---0-- | Rd = add (Rs, #1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f45) { - // Instruction: 5: 01010001ssssdddd0011111101---101 | Rd = add (Rs, #1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc5) { - // Instruction: 5: 01010001ssssdddd0011111111---101 | Rd = add (Rs, #1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f47) { - // Instruction: 5: 01010001ssssdddd0011111101---111 | Rd = add (Rs, #1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc7) { - // Instruction: 5: 01010001ssssdddd0011111111---111 | Rd = add (Rs, #1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f44) { - // Instruction: 5: 01010001ssssdddd0011111101---100 | Rd = add (Rs, #1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc4) { - // Instruction: 5: 01010001ssssdddd0011111111---100 | Rd = add (Rs, #1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003f46) { - // Instruction: 5: 01010001ssssdddd0011111101---110 | Rd = add (Rs, #1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x51003fc6) { - // Instruction: 5: 01010001ssssdddd0011111111---110 | Rd = add (Rs, #1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x51003fc0) { - // Instruction: 5: 01010001ssssdddd0011111111---0-- | Rd = add (Rs, #1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x4c003f40) { - // Instruction: 5: 010011iiiiiidddd0011111101---0-- | Rd = add (Sp, #u6:2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x4c003f00) { - // Instruction: 5: 010011iiiiiidddd0011111100---0-- | Rd = add (Sp, #u6:2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f45) { - // Instruction: 5: 010011iiiiiidddd0011111101---101 | Rd = add (Sp, #u6:2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc5) { - // Instruction: 5: 010011iiiiiidddd0011111111---101 | Rd = add (Sp, #u6:2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f47) { - // Instruction: 5: 010011iiiiiidddd0011111101---111 | Rd = add (Sp, #u6:2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc7) { - // Instruction: 5: 010011iiiiiidddd0011111111---111 | Rd = add (Sp, #u6:2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f44) { - // Instruction: 5: 010011iiiiiidddd0011111101---100 | Rd = add (Sp, #u6:2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc4) { - // Instruction: 5: 010011iiiiiidddd0011111111---100 | Rd = add (Sp, #u6:2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003f46) { - // Instruction: 5: 010011iiiiiidddd0011111101---110 | Rd = add (Sp, #u6:2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc7) == 0x4c003fc6) { - // Instruction: 5: 010011iiiiiidddd0011111111---110 | Rd = add (Sp, #u6:2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00ffc4) == 0x4c003fc0) { - // Instruction: 5: 010011iiiiiidddd0011111111---0-- | Rd = add (Sp, #u6:2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x52003f40) { - // Instruction: 5: 01010010ssssdddd0011111101---0-- | Rd = and (Rs, #1) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x52003f00) { - // Instruction: 5: 01010010ssssdddd0011111100---0-- | Rd = and (Rs, #1) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f45) { - // Instruction: 5: 01010010ssssdddd0011111101---101 | Rd = and (Rs, #1) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc5) { - // Instruction: 5: 01010010ssssdddd0011111111---101 | Rd = and (Rs, #1) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f47) { - // Instruction: 5: 01010010ssssdddd0011111101---111 | Rd = and (Rs, #1) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc7) { - // Instruction: 5: 01010010ssssdddd0011111111---111 | Rd = and (Rs, #1) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f44) { - // Instruction: 5: 01010010ssssdddd0011111101---100 | Rd = and (Rs, #1) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc4) { - // Instruction: 5: 01010010ssssdddd0011111111---100 | Rd = and (Rs, #1) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003f46) { - // Instruction: 5: 01010010ssssdddd0011111101---110 | Rd = and (Rs, #1) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x52003fc6) { - // Instruction: 5: 01010010ssssdddd0011111111---110 | Rd = and (Rs, #1) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x52003fc0) { - // Instruction: 5: 01010010ssssdddd0011111111---0-- | Rd = and (Rs, #1) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x57003f40) { - // Instruction: 5: 01010111ssssdddd0011111101---0-- | Rd = and (Rs, #255) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x57003f00) { - // Instruction: 5: 01010111ssssdddd0011111100---0-- | Rd = and (Rs, #255) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f45) { - // Instruction: 5: 01010111ssssdddd0011111101---101 | Rd = and (Rs, #255) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc5) { - // Instruction: 5: 01010111ssssdddd0011111111---101 | Rd = and (Rs, #255) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f47) { - // Instruction: 5: 01010111ssssdddd0011111101---111 | Rd = and (Rs, #255) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc7) { - // Instruction: 5: 01010111ssssdddd0011111111---111 | Rd = and (Rs, #255) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f44) { - // Instruction: 5: 01010111ssssdddd0011111101---100 | Rd = and (Rs, #255) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc4) { - // Instruction: 5: 01010111ssssdddd0011111111---100 | Rd = and (Rs, #255) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003f46) { - // Instruction: 5: 01010111ssssdddd0011111101---110 | Rd = and (Rs, #255) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x57003fc6) { - // Instruction: 5: 01010111ssssdddd0011111111---110 | Rd = and (Rs, #255) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x57003fc0) { - // Instruction: 5: 01010111ssssdddd0011111111---0-- | Rd = and (Rs, #255) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x55003f40) { - // Instruction: 5: 01010101ssssdddd0011111101---0-- | Rd = sxtb (Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x55003f00) { - // Instruction: 5: 01010101ssssdddd0011111100---0-- | Rd = sxtb (Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f45) { - // Instruction: 5: 01010101ssssdddd0011111101---101 | Rd = sxtb (Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc5) { - // Instruction: 5: 01010101ssssdddd0011111111---101 | Rd = sxtb (Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f47) { - // Instruction: 5: 01010101ssssdddd0011111101---111 | Rd = sxtb (Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc7) { - // Instruction: 5: 01010101ssssdddd0011111111---111 | Rd = sxtb (Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f44) { - // Instruction: 5: 01010101ssssdddd0011111101---100 | Rd = sxtb (Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc4) { - // Instruction: 5: 01010101ssssdddd0011111111---100 | Rd = sxtb (Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003f46) { - // Instruction: 5: 01010101ssssdddd0011111101---110 | Rd = sxtb (Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x55003fc6) { - // Instruction: 5: 01010101ssssdddd0011111111---110 | Rd = sxtb (Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x55003fc0) { - // Instruction: 5: 01010101ssssdddd0011111111---0-- | Rd = sxtb (Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x54003f40) { - // Instruction: 5: 01010100ssssdddd0011111101---0-- | Rd = sxth (Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x54003f00) { - // Instruction: 5: 01010100ssssdddd0011111100---0-- | Rd = sxth (Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f45) { - // Instruction: 5: 01010100ssssdddd0011111101---101 | Rd = sxth (Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc5) { - // Instruction: 5: 01010100ssssdddd0011111111---101 | Rd = sxth (Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f47) { - // Instruction: 5: 01010100ssssdddd0011111101---111 | Rd = sxth (Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc7) { - // Instruction: 5: 01010100ssssdddd0011111111---111 | Rd = sxth (Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f44) { - // Instruction: 5: 01010100ssssdddd0011111101---100 | Rd = sxth (Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc4) { - // Instruction: 5: 01010100ssssdddd0011111111---100 | Rd = sxth (Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003f46) { - // Instruction: 5: 01010100ssssdddd0011111101---110 | Rd = sxth (Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x54003fc6) { - // Instruction: 5: 01010100ssssdddd0011111111---110 | Rd = sxth (Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x54003fc0) { - // Instruction: 5: 01010100ssssdddd0011111111---0-- | Rd = sxth (Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x56003f40) { - // Instruction: 5: 01010110ssssdddd0011111101---0-- | Rd = zxth (Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x56003f00) { - // Instruction: 5: 01010110ssssdddd0011111100---0-- | Rd = zxth (Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f45) { - // Instruction: 5: 01010110ssssdddd0011111101---101 | Rd = zxth (Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc5) { - // Instruction: 5: 01010110ssssdddd0011111111---101 | Rd = zxth (Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f47) { - // Instruction: 5: 01010110ssssdddd0011111101---111 | Rd = zxth (Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc7) { - // Instruction: 5: 01010110ssssdddd0011111111---111 | Rd = zxth (Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f44) { - // Instruction: 5: 01010110ssssdddd0011111101---100 | Rd = zxth (Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc4) { - // Instruction: 5: 01010110ssssdddd0011111111---100 | Rd = zxth (Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003f46) { - // Instruction: 5: 01010110ssssdddd0011111101---110 | Rd = zxth (Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x56003fc6) { - // Instruction: 5: 01010110ssssdddd0011111111---110 | Rd = zxth (Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x56003fc0) { - // Instruction: 5: 01010110ssssdddd0011111111---0-- | Rd = zxth (Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c003f40) { - // Instruction: 5: 010111-0-ii00ddd0011111101---0-- | Rdd = combine (#0, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c003f00) { - // Instruction: 5: 010111-0-ii00ddd0011111100---0-- | Rdd = combine (#0, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f45) { - // Instruction: 5: 010111-0-ii00ddd0011111101---101 | Rdd = combine (#0, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc5) { - // Instruction: 5: 010111-0-ii00ddd0011111111---101 | Rdd = combine (#0, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f47) { - // Instruction: 5: 010111-0-ii00ddd0011111101---111 | Rdd = combine (#0, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc7) { - // Instruction: 5: 010111-0-ii00ddd0011111111---111 | Rdd = combine (#0, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f44) { - // Instruction: 5: 010111-0-ii00ddd0011111101---100 | Rdd = combine (#0, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc4) { - // Instruction: 5: 010111-0-ii00ddd0011111111---100 | Rdd = combine (#0, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003f46) { - // Instruction: 5: 010111-0-ii00ddd0011111101---110 | Rdd = combine (#0, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c003fc6) { - // Instruction: 5: 010111-0-ii00ddd0011111111---110 | Rdd = combine (#0, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c003fc0) { - // Instruction: 5: 010111-0-ii00ddd0011111111---0-- | Rdd = combine (#0, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d003f40) { - // Instruction: 5: 010111-1ssss0ddd0011111101---0-- | Rdd = combine (#0, Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d003f00) { - // Instruction: 5: 010111-1ssss0ddd0011111100---0-- | Rdd = combine (#0, Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f45) { - // Instruction: 5: 010111-1ssss0ddd0011111101---101 | Rdd = combine (#0, Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc5) { - // Instruction: 5: 010111-1ssss0ddd0011111111---101 | Rdd = combine (#0, Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f47) { - // Instruction: 5: 010111-1ssss0ddd0011111101---111 | Rdd = combine (#0, Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc7) { - // Instruction: 5: 010111-1ssss0ddd0011111111---111 | Rdd = combine (#0, Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f44) { - // Instruction: 5: 010111-1ssss0ddd0011111101---100 | Rdd = combine (#0, Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc4) { - // Instruction: 5: 010111-1ssss0ddd0011111111---100 | Rdd = combine (#0, Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003f46) { - // Instruction: 5: 010111-1ssss0ddd0011111101---110 | Rdd = combine (#0, Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d003fc6) { - // Instruction: 5: 010111-1ssss0ddd0011111111---110 | Rdd = combine (#0, Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d003fc0) { - // Instruction: 5: 010111-1ssss0ddd0011111111---0-- | Rdd = combine (#0, Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c083f40) { - // Instruction: 5: 010111-0-ii01ddd0011111101---0-- | Rdd = combine (#1, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c083f00) { - // Instruction: 5: 010111-0-ii01ddd0011111100---0-- | Rdd = combine (#1, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f45) { - // Instruction: 5: 010111-0-ii01ddd0011111101---101 | Rdd = combine (#1, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc5) { - // Instruction: 5: 010111-0-ii01ddd0011111111---101 | Rdd = combine (#1, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f47) { - // Instruction: 5: 010111-0-ii01ddd0011111101---111 | Rdd = combine (#1, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc7) { - // Instruction: 5: 010111-0-ii01ddd0011111111---111 | Rdd = combine (#1, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f44) { - // Instruction: 5: 010111-0-ii01ddd0011111101---100 | Rdd = combine (#1, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc4) { - // Instruction: 5: 010111-0-ii01ddd0011111111---100 | Rdd = combine (#1, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083f46) { - // Instruction: 5: 010111-0-ii01ddd0011111101---110 | Rdd = combine (#1, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c083fc6) { - // Instruction: 5: 010111-0-ii01ddd0011111111---110 | Rdd = combine (#1, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c083fc0) { - // Instruction: 5: 010111-0-ii01ddd0011111111---0-- | Rdd = combine (#1, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c103f40) { - // Instruction: 5: 010111-0-ii10ddd0011111101---0-- | Rdd = combine (#2, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c103f00) { - // Instruction: 5: 010111-0-ii10ddd0011111100---0-- | Rdd = combine (#2, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f45) { - // Instruction: 5: 010111-0-ii10ddd0011111101---101 | Rdd = combine (#2, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc5) { - // Instruction: 5: 010111-0-ii10ddd0011111111---101 | Rdd = combine (#2, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f47) { - // Instruction: 5: 010111-0-ii10ddd0011111101---111 | Rdd = combine (#2, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc7) { - // Instruction: 5: 010111-0-ii10ddd0011111111---111 | Rdd = combine (#2, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f44) { - // Instruction: 5: 010111-0-ii10ddd0011111101---100 | Rdd = combine (#2, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc4) { - // Instruction: 5: 010111-0-ii10ddd0011111111---100 | Rdd = combine (#2, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103f46) { - // Instruction: 5: 010111-0-ii10ddd0011111101---110 | Rdd = combine (#2, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c103fc6) { - // Instruction: 5: 010111-0-ii10ddd0011111111---110 | Rdd = combine (#2, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c103fc0) { - // Instruction: 5: 010111-0-ii10ddd0011111111---0-- | Rdd = combine (#2, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c183f40) { - // Instruction: 5: 010111-0-ii11ddd0011111101---0-- | Rdd = combine (#3, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c183f00) { - // Instruction: 5: 010111-0-ii11ddd0011111100---0-- | Rdd = combine (#3, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f45) { - // Instruction: 5: 010111-0-ii11ddd0011111101---101 | Rdd = combine (#3, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc5) { - // Instruction: 5: 010111-0-ii11ddd0011111111---101 | Rdd = combine (#3, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f47) { - // Instruction: 5: 010111-0-ii11ddd0011111101---111 | Rdd = combine (#3, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc7) { - // Instruction: 5: 010111-0-ii11ddd0011111111---111 | Rdd = combine (#3, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f44) { - // Instruction: 5: 010111-0-ii11ddd0011111101---100 | Rdd = combine (#3, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc4) { - // Instruction: 5: 010111-0-ii11ddd0011111111---100 | Rdd = combine (#3, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183f46) { - // Instruction: 5: 010111-0-ii11ddd0011111101---110 | Rdd = combine (#3, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc7) == 0x5c183fc6) { - // Instruction: 5: 010111-0-ii11ddd0011111111---110 | Rdd = combine (#3, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd18ffc4) == 0x5c183fc0) { - // Instruction: 5: 010111-0-ii11ddd0011111111---0-- | Rdd = combine (#3, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d083f40) { - // Instruction: 5: 010111-1ssss1ddd0011111101---0-- | Rdd = combine (Rs, #0) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d083f00) { - // Instruction: 5: 010111-1ssss1ddd0011111100---0-- | Rdd = combine (Rs, #0) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; deallocframe", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f45) { - // Instruction: 5: 010111-1ssss1ddd0011111101---101 | Rdd = combine (Rs, #0) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc5) { - // Instruction: 5: 010111-1ssss1ddd0011111111---101 | Rdd = combine (Rs, #0) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f47) { - // Instruction: 5: 010111-1ssss1ddd0011111101---111 | Rdd = combine (Rs, #0) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc7) { - // Instruction: 5: 010111-1ssss1ddd0011111111---111 | Rdd = combine (Rs, #0) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f44) { - // Instruction: 5: 010111-1ssss1ddd0011111101---100 | Rdd = combine (Rs, #0) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0) dealloc_return", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc4) { - // Instruction: 5: 010111-1ssss1ddd0011111111---100 | Rdd = combine (Rs, #0) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0) jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083f46) { - // Instruction: 5: 010111-1ssss1ddd0011111101---110 | Rdd = combine (Rs, #0) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0.new) dealloc_return:nt", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc7) == 0x5d083fc6) { - // Instruction: 5: 010111-1ssss1ddd0011111111---110 | Rdd = combine (Rs, #0) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; if (p0.new) jumpr:nt Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ffc4) == 0x5d083fc0) { - // Instruction: 5: 010111-1ssss1ddd0011111111---0-- | Rdd = combine (Rs, #0) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; jumpr Lr", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x5a003000) { - // Instruction: 5: 0101101--0--eeee00110iiissssdddd | Re = #-1 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x5a002000) { - // Instruction: 5: 0101101--0--eeee00100iiissssdddd | Re = #-1 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x5a002800) { - // Instruction: 5: 0101101--0--eeee00101iiissssdddd | Re = #-1 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe00) == 0x5a003c00) { - // Instruction: 5: 0101101--0--eeee0011110iiiiidddd | Re = #-1 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x5a003e00) { - // Instruction: 5: 0101101--0--eeee00111110iiiiiddd | Re = #-1 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE_____1___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x48003000) { - // Instruction: 5: 010010IIIIIIeeee00110iiissssdddd | Re = #U6 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x48002000) { - // Instruction: 5: 010010IIIIIIeeee00100iiissssdddd | Re = #U6 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x48002800) { - // Instruction: 5: 010010IIIIIIeeee00101iiissssdddd | Re = #U6 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x48003c00) { - // Instruction: 5: 010010IIIIIIeeee0011110iiiiidddd | Re = #U6 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x48003e00) { - // Instruction: 5: 010010IIIIIIeeee00111110iiiiiddd | Re = #U6 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE____U6___RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x50003c00) { - // Instruction: 5: 01010000sssseeee0011110iiiiidddd | Re = Rs ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x50003e00) { - // Instruction: 5: 01010000sssseeee00111110iiiiiddd | Re = Rs ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___RS___RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x50003000) { - // Instruction: 5: 01010000uuuueeee00110iiissssdddd | Re = Ru ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x50002000) { - // Instruction: 5: 01010000uuuueeee00100iiissssdddd | Re = Ru ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x50002800) { - // Instruction: 5: 01010000uuuueeee00101iiissssdddd | Re = Ru ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___RU___RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x53003c00) { - // Instruction: 5: 01010011sssseeee0011110iiiiidddd | Re = add (Rs, #-1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x53003e00) { - // Instruction: 5: 01010011sssseeee00111110iiiiiddd | Re = add (Rs, #-1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x51003c00) { - // Instruction: 5: 01010001sssseeee0011110iiiiidddd | Re = add (Rs, #1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x51003e00) { - // Instruction: 5: 01010001sssseeee00111110iiiiiddd | Re = add (Rs, #1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x53003000) { - // Instruction: 5: 01010011uuuueeee00110iiissssdddd | Re = add (Ru, #-1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x53002000) { - // Instruction: 5: 01010011uuuueeee00100iiissssdddd | Re = add (Ru, #-1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x53002800) { - // Instruction: 5: 01010011uuuueeee00101iiissssdddd | Re = add (Ru, #-1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x51003000) { - // Instruction: 5: 01010001uuuueeee00110iiissssdddd | Re = add (Ru, #1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x51002000) { - // Instruction: 5: 01010001uuuueeee00100iiissssdddd | Re = add (Ru, #1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x51002800) { - // Instruction: 5: 01010001uuuueeee00101iiissssdddd | Re = add (Ru, #1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x4c003000) { - // Instruction: 5: 010011IIIIIIeeee00110iiissssdddd | Re = add (Sp, #U6:2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x4c002000) { - // Instruction: 5: 010011IIIIIIeeee00100iiissssdddd | Re = add (Sp, #U6:2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x4c002800) { - // Instruction: 5: 010011IIIIIIeeee00101iiissssdddd | Re = add (Sp, #U6:2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x4c003c00) { - // Instruction: 5: 010011IIIIIIeeee0011110iiiiidddd | Re = add (Sp, #U6:2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x4c003e00) { - // Instruction: 5: 010011IIIIIIeeee00111110iiiiiddd | Re = add (Sp, #U6:2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x52003c00) { - // Instruction: 5: 01010010sssseeee0011110iiiiidddd | Re = and (Rs, #1) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x52003e00) { - // Instruction: 5: 01010010sssseeee00111110iiiiiddd | Re = and (Rs, #1) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___1____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x57003c00) { - // Instruction: 5: 01010111sssseeee0011110iiiiidddd | Re = and (Rs, #255) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x57003e00) { - // Instruction: 5: 01010111sssseeee00111110iiiiiddd | Re = and (Rs, #255) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RS___255____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x52003000) { - // Instruction: 5: 01010010uuuueeee00110iiissssdddd | Re = and (Ru, #1) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x52002000) { - // Instruction: 5: 01010010uuuueeee00100iiissssdddd | Re = and (Ru, #1) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x52002800) { - // Instruction: 5: 01010010uuuueeee00101iiissssdddd | Re = and (Ru, #1) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___1____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x57003000) { - // Instruction: 5: 01010111uuuueeee00110iiissssdddd | Re = and (Ru, #255) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x57002000) { - // Instruction: 5: 01010111uuuueeee00100iiissssdddd | Re = and (Ru, #255) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x57002800) { - // Instruction: 5: 01010111uuuueeee00101iiissssdddd | Re = and (Ru, #255) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___AND__RU___255____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x55003c00) { - // Instruction: 5: 01010101sssseeee0011110iiiiidddd | Re = sxtb (Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x55003e00) { - // Instruction: 5: 01010101sssseeee00111110iiiiiddd | Re = sxtb (Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x55003000) { - // Instruction: 5: 01010101uuuueeee00110iiissssdddd | Re = sxtb (Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x55002000) { - // Instruction: 5: 01010101uuuueeee00100iiissssdddd | Re = sxtb (Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x55002800) { - // Instruction: 5: 01010101uuuueeee00101iiissssdddd | Re = sxtb (Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTB__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x54003c00) { - // Instruction: 5: 01010100sssseeee0011110iiiiidddd | Re = sxth (Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x54003e00) { - // Instruction: 5: 01010100sssseeee00111110iiiiiddd | Re = sxth (Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x54003000) { - // Instruction: 5: 01010100uuuueeee00110iiissssdddd | Re = sxth (Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x54002000) { - // Instruction: 5: 01010100uuuueeee00100iiissssdddd | Re = sxth (Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x54002800) { - // Instruction: 5: 01010100uuuueeee00101iiissssdddd | Re = sxth (Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___SXTH__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x56003c00) { - // Instruction: 5: 01010110sssseeee0011110iiiiidddd | Re = zxth (Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x56003e00) { - // Instruction: 5: 01010110sssseeee00111110iiiiiddd | Re = zxth (Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x56003000) { - // Instruction: 5: 01010110uuuueeee00110iiissssdddd | Re = zxth (Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x56002000) { - // Instruction: 5: 01010110uuuueeee00100iiissssdddd | Re = zxth (Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x56002800) { - // Instruction: 5: 01010110uuuueeee00101iiissssdddd | Re = zxth (Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RE___ZXTH__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c003000) { - // Instruction: 5: 010111-0-II00eee00110iiissssdddd | Ree = combine (#0, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c002000) { - // Instruction: 5: 010111-0-II00eee00100iiissssdddd | Ree = combine (#0, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c002800) { - // Instruction: 5: 010111-0-II00eee00101iiissssdddd | Ree = combine (#0, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c003c00) { - // Instruction: 5: 010111-0-II00eee0011110iiiiidddd | Ree = combine (#0, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c003e00) { - // Instruction: 5: 010111-0-II00eee00111110iiiiiddd | Ree = combine (#0, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x5d003c00) { - // Instruction: 5: 010111-1ssss0eee0011110iiiiidddd | Ree = combine (#0, Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x5d003e00) { - // Instruction: 5: 010111-1ssss0eee00111110iiiiiddd | Ree = combine (#0, Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d003000) { - // Instruction: 5: 010111-1uuuu0eee00110iiissssdddd | Ree = combine (#0, Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d002000) { - // Instruction: 5: 010111-1uuuu0eee00100iiissssdddd | Ree = combine (#0, Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d002800) { - // Instruction: 5: 010111-1uuuu0eee00101iiissssdddd | Ree = combine (#0, Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___0__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c083000) { - // Instruction: 5: 010111-0-II01eee00110iiissssdddd | Ree = combine (#1, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c082000) { - // Instruction: 5: 010111-0-II01eee00100iiissssdddd | Ree = combine (#1, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c082800) { - // Instruction: 5: 010111-0-II01eee00101iiissssdddd | Ree = combine (#1, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c083c00) { - // Instruction: 5: 010111-0-II01eee0011110iiiiidddd | Ree = combine (#1, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c083e00) { - // Instruction: 5: 010111-0-II01eee00111110iiiiiddd | Ree = combine (#1, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___1___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c103000) { - // Instruction: 5: 010111-0-II10eee00110iiissssdddd | Ree = combine (#2, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c102000) { - // Instruction: 5: 010111-0-II10eee00100iiissssdddd | Ree = combine (#2, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c102800) { - // Instruction: 5: 010111-0-II10eee00101iiissssdddd | Ree = combine (#2, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c103c00) { - // Instruction: 5: 010111-0-II10eee0011110iiiiidddd | Ree = combine (#2, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c103e00) { - // Instruction: 5: 010111-0-II10eee00111110iiiiiddd | Ree = combine (#2, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___2___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c183000) { - // Instruction: 5: 010111-0-II11eee00110iiissssdddd | Ree = combine (#3, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c182000) { - // Instruction: 5: 010111-0-II11eee00100iiissssdddd | Ree = combine (#3, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x5c182800) { - // Instruction: 5: 010111-0-II11eee00101iiissssdddd | Ree = combine (#3, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x5c183c00) { - // Instruction: 5: 010111-0-II11eee0011110iiiiidddd | Ree = combine (#3, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x5c183e00) { - // Instruction: 5: 010111-0-II11eee00111110iiiiiddd | Ree = combine (#3, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE___3___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x5d083c00) { - // Instruction: 5: 010111-1ssss1eee0011110iiiiidddd | Ree = combine (Rs, #0) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RS___0____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memw (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x5d083e00) { - // Instruction: 5: 010111-1ssss1eee00111110iiiiiddd | Ree = combine (Rs, #0) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RS___0____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memd (Sp + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d083000) { - // Instruction: 5: 010111-1uuuu1eee00110iiissssdddd | Ree = combine (Ru, #0) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memb (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d082000) { - // Instruction: 5: 010111-1uuuu1eee00100iiissssdddd | Ree = combine (Ru, #0) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x5d082800) { - // Instruction: 5: 010111-1uuuu1eee00101iiissssdddd | Ree = combine (Ru, #0) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_REE___COMBINE__RU___0____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; %s = memuh (%s + 0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x58003c00) { - // Instruction: 5: 01011000ssssxxxx0011110iiiiidddd | Rx = add (Rs, Rx) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x58003e00) { - // Instruction: 5: 01011000ssssxxxx00111110iiiiiddd | Rx = add (Rs, Rx) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f40) { - // Instruction: 5: 01011000ssssxxxx0011111101---0-- | Rx = add (Rs, Rx) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f00) { - // Instruction: 5: 01011000ssssxxxx0011111100---0-- | Rx = add (Rs, Rx) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f45) { - // Instruction: 5: 01011000ssssxxxx0011111101---101 | Rx = add (Rs, Rx) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc5) { - // Instruction: 5: 01011000ssssxxxx0011111111---101 | Rx = add (Rs, Rx) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f47) { - // Instruction: 5: 01011000ssssxxxx0011111101---111 | Rx = add (Rs, Rx) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc7) { - // Instruction: 5: 01011000ssssxxxx0011111111---111 | Rx = add (Rs, Rx) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f44) { - // Instruction: 5: 01011000ssssxxxx0011111101---100 | Rx = add (Rs, Rx) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc4) { - // Instruction: 5: 01011000ssssxxxx0011111111---100 | Rx = add (Rs, Rx) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f46) { - // Instruction: 5: 01011000ssssxxxx0011111101---110 | Rx = add (Rs, Rx) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc6) { - // Instruction: 5: 01011000ssssxxxx0011111111---110 | Rx = add (Rs, Rx) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003fc0) { - // Instruction: 5: 01011000ssssxxxx0011111111---0-- | Rx = add (Rs, Rx) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58003000) { - // Instruction: 5: 01011000uuuuxxxx00110iiissssdddd | Rx = add (Ru, Rx) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002000) { - // Instruction: 5: 01011000uuuuxxxx00100iiissssdddd | Rx = add (Ru, Rx) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002800) { - // Instruction: 5: 01011000uuuuxxxx00101iiissssdddd | Rx = add (Ru, Rx) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x40003000) { - // Instruction: 5: 01000IIIIIIIxxxx00110iiissssdddd | Rx = add (Rx, #S7) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x40002000) { - // Instruction: 5: 01000IIIIIIIxxxx00100iiissssdddd | Rx = add (Rx, #S7) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0x40002800) { - // Instruction: 5: 01000IIIIIIIxxxx00101iiissssdddd | Rx = add (Rx, #S7) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x40003c00) { - // Instruction: 5: 01000IIIIIIIxxxx0011110iiiiidddd | Rx = add (Rx, #S7) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x40003e00) { - // Instruction: 5: 01000IIIIIIIxxxx00111110iiiiiddd | Rx = add (Rx, #S7) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x40003f40) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---0-- | Rx = add (Rx, #s7) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x40003f00) { - // Instruction: 5: 01000iiiiiiixxxx0011111100---0-- | Rx = add (Rx, #s7) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f45) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---101 | Rx = add (Rx, #s7) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc5) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---101 | Rx = add (Rx, #s7) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f47) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---111 | Rx = add (Rx, #s7) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc7) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---111 | Rx = add (Rx, #s7) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f44) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---100 | Rx = add (Rx, #s7) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc4) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---100 | Rx = add (Rx, #s7) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003f46) { - // Instruction: 5: 01000iiiiiiixxxx0011111101---110 | Rx = add (Rx, #s7) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc7) == 0x40003fc6) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---110 | Rx = add (Rx, #s7) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800ffc4) == 0x40003fc0) { - // Instruction: 5: 01000iiiiiiixxxx0011111111---0-- | Rx = add (Rx, #s7) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x58003c00) { - // Instruction: 5: 01011000ssssxxxx0011110iiiiidddd | Rx = add (Rx, Rs) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x58003e00) { - // Instruction: 5: 01011000ssssxxxx00111110iiiiiddd | Rx = add (Rx, Rs) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f40) { - // Instruction: 5: 01011000ssssxxxx0011111101---0-- | Rx = add (Rx, Rs) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003f00) { - // Instruction: 5: 01011000ssssxxxx0011111100---0-- | Rx = add (Rx, Rs) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f45) { - // Instruction: 5: 01011000ssssxxxx0011111101---101 | Rx = add (Rx, Rs) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc5) { - // Instruction: 5: 01011000ssssxxxx0011111111---101 | Rx = add (Rx, Rs) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f47) { - // Instruction: 5: 01011000ssssxxxx0011111101---111 | Rx = add (Rx, Rs) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc7) { - // Instruction: 5: 01011000ssssxxxx0011111111---111 | Rx = add (Rx, Rs) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f44) { - // Instruction: 5: 01011000ssssxxxx0011111101---100 | Rx = add (Rx, Rs) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc4) { - // Instruction: 5: 01011000ssssxxxx0011111111---100 | Rx = add (Rx, Rs) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003f46) { - // Instruction: 5: 01011000ssssxxxx0011111101---110 | Rx = add (Rx, Rs) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x58003fc6) { - // Instruction: 5: 01011000ssssxxxx0011111111---110 | Rx = add (Rx, Rs) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x58003fc0) { - // Instruction: 5: 01011000ssssxxxx0011111111---0-- | Rx = add (Rx, Rs) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58003000) { - // Instruction: 5: 01011000uuuuxxxx00110iiissssdddd | Rx = add (Rx, Ru) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002000) { - // Instruction: 5: 01011000uuuuxxxx00100iiissssdddd | Rx = add (Rx, Ru) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x58002800) { - // Instruction: 5: 01011000uuuuxxxx00101iiissssdddd | Rx = add (Rx, Ru) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a703f40) { - // Instruction: 5: 0101101--111dddd0011111101---0-- | if (! p0) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a703f00) { - // Instruction: 5: 0101101--111dddd0011111100---0-- | if (! p0) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f45) { - // Instruction: 5: 0101101--111dddd0011111101---101 | if (! p0) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc5) { - // Instruction: 5: 0101101--111dddd0011111111---101 | if (! p0) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f47) { - // Instruction: 5: 0101101--111dddd0011111101---111 | if (! p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc7) { - // Instruction: 5: 0101101--111dddd0011111111---111 | if (! p0) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f44) { - // Instruction: 5: 0101101--111dddd0011111101---100 | if (! p0) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc4) { - // Instruction: 5: 0101101--111dddd0011111111---100 | if (! p0) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703f46) { - // Instruction: 5: 0101101--111dddd0011111101---110 | if (! p0) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a703fc6) { - // Instruction: 5: 0101101--111dddd0011111111---110 | if (! p0) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a703fc0) { - // Instruction: 5: 0101101--111dddd0011111111---0-- | if (! p0) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a703000) { - // Instruction: 5: 0101101--111eeee00110iiissssdddd | if (! p0) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a702000) { - // Instruction: 5: 0101101--111eeee00100iiissssdddd | if (! p0) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a702800) { - // Instruction: 5: 0101101--111eeee00101iiissssdddd | if (! p0) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a703c00) { - // Instruction: 5: 0101101--111eeee0011110iiiiidddd | if (! p0) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a703e00) { - // Instruction: 5: 0101101--111eeee00111110iiiiiddd | if (! p0) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a503f40) { - // Instruction: 5: 0101101--101dddd0011111101---0-- | if (! p0.new) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a503f00) { - // Instruction: 5: 0101101--101dddd0011111100---0-- | if (! p0.new) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f45) { - // Instruction: 5: 0101101--101dddd0011111101---101 | if (! p0.new) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc5) { - // Instruction: 5: 0101101--101dddd0011111111---101 | if (! p0.new) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f47) { - // Instruction: 5: 0101101--101dddd0011111101---111 | if (! p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc7) { - // Instruction: 5: 0101101--101dddd0011111111---111 | if (! p0.new) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f44) { - // Instruction: 5: 0101101--101dddd0011111101---100 | if (! p0.new) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc4) { - // Instruction: 5: 0101101--101dddd0011111111---100 | if (! p0.new) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503f46) { - // Instruction: 5: 0101101--101dddd0011111101---110 | if (! p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a503fc6) { - // Instruction: 5: 0101101--101dddd0011111111---110 | if (! p0.new) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a503fc0) { - // Instruction: 5: 0101101--101dddd0011111111---0-- | if (! p0.new) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a503000) { - // Instruction: 5: 0101101--101eeee00110iiissssdddd | if (! p0.new) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a502000) { - // Instruction: 5: 0101101--101eeee00100iiissssdddd | if (! p0.new) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a502800) { - // Instruction: 5: 0101101--101eeee00101iiissssdddd | if (! p0.new) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a503c00) { - // Instruction: 5: 0101101--101eeee0011110iiiiidddd | if (! p0.new) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a503e00) { - // Instruction: 5: 0101101--101eeee00111110iiiiiddd | if (! p0.new) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a603f40) { - // Instruction: 5: 0101101--110dddd0011111101---0-- | if (p0) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a603f00) { - // Instruction: 5: 0101101--110dddd0011111100---0-- | if (p0) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f45) { - // Instruction: 5: 0101101--110dddd0011111101---101 | if (p0) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc5) { - // Instruction: 5: 0101101--110dddd0011111111---101 | if (p0) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f47) { - // Instruction: 5: 0101101--110dddd0011111101---111 | if (p0) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc7) { - // Instruction: 5: 0101101--110dddd0011111111---111 | if (p0) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f44) { - // Instruction: 5: 0101101--110dddd0011111101---100 | if (p0) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc4) { - // Instruction: 5: 0101101--110dddd0011111111---100 | if (p0) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603f46) { - // Instruction: 5: 0101101--110dddd0011111101---110 | if (p0) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a603fc6) { - // Instruction: 5: 0101101--110dddd0011111111---110 | if (p0) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a603fc0) { - // Instruction: 5: 0101101--110dddd0011111111---0-- | if (p0) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a603000) { - // Instruction: 5: 0101101--110eeee00110iiissssdddd | if (p0) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a602000) { - // Instruction: 5: 0101101--110eeee00100iiissssdddd | if (p0) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a602800) { - // Instruction: 5: 0101101--110eeee00101iiissssdddd | if (p0) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a603c00) { - // Instruction: 5: 0101101--110eeee0011110iiiiidddd | if (p0) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a603e00) { - // Instruction: 5: 0101101--110eeee00111110iiiiiddd | if (p0) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a403f40) { - // Instruction: 5: 0101101--100dddd0011111101---0-- | if (p0.new) Rd = #0 ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a403f00) { - // Instruction: 5: 0101101--100dddd0011111100---0-- | if (p0.new) Rd = #0 ; deallocframe - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___DEALLOCFRAME; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f45) { - // Instruction: 5: 0101101--100dddd0011111101---101 | if (p0.new) Rd = #0 ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc5) { - // Instruction: 5: 0101101--100dddd0011111111---101 | if (p0.new) Rd = #0 ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f47) { - // Instruction: 5: 0101101--100dddd0011111101---111 | if (p0.new) Rd = #0 ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc7) { - // Instruction: 5: 0101101--100dddd0011111111---111 | if (p0.new) Rd = #0 ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f44) { - // Instruction: 5: 0101101--100dddd0011111101---100 | if (p0.new) Rd = #0 ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__DEALLOC_RETURN; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc4) { - // Instruction: 5: 0101101--100dddd0011111111---100 | if (p0.new) Rd = #0 ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0__JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403f46) { - // Instruction: 5: 0101101--100dddd0011111101---110 | if (p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc7) == 0x5a403fc6) { - // Instruction: 5: 0101101--100dddd0011111111---110 | if (p0.new) Rd = #0 ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ffc4) == 0x5a403fc0) { - // Instruction: 5: 0101101--100dddd0011111111---0-- | if (p0.new) Rd = #0 ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___JUMPR_LR; - hi->op_count = 1; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a403000) { - // Instruction: 5: 0101101--100eeee00110iiissssdddd | if (p0.new) Re = #0 ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMB__RS____U3_0_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a402000) { - // Instruction: 5: 0101101--100eeee00100iiissssdddd | if (p0.new) Re = #0 ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x5a402800) { - // Instruction: 5: 0101101--100eeee00101iiissssdddd | if (p0.new) Re = #0 ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMUH__RS____U3_1_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x5a403c00) { - // Instruction: 5: 0101101--100eeee0011110iiiiidddd | if (p0.new) Re = #0 ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RD___MEMW__SP____U5_2_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x5a403e00) { - // Instruction: 5: 0101101--100eeee00111110iiiiiddd | if (p0.new) Re = #0 ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RE____0___RDD___MEMD__SP____U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x59003c00) { - // Instruction: 5: 01011001ssss--II0011110iiiiidddd | p0 = cmp.eq (Rs, #U2) ; Rd = memw (Sp + #u5:2) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RD___MEMW__SP____U5_2_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memw (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x59003e00) { - // Instruction: 5: 01011001ssss--II00111110iiiiiddd | p0 = cmp.eq (Rs, #U2) ; Rdd = memd (Sp + #u5:3) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____RDD___MEMD__SP____U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memd (Sp + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x59003f40) { - // Instruction: 5: 01011001ssss--ii0011111101---0-- | p0 = cmp.eq (Rs, #u2) ; dealloc_return - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x59003f00) { - // Instruction: 5: 01011001ssss--ii0011111100---0-- | p0 = cmp.eq (Rs, #u2) ; deallocframe - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____DEALLOCFRAME; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; deallocframe", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f45) { - // Instruction: 5: 01011001ssss--ii0011111101---101 | p0 = cmp.eq (Rs, #u2) ; if (! p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc5) { - // Instruction: 5: 01011001ssss--ii0011111111---101 | p0 = cmp.eq (Rs, #u2) ; if (! p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f47) { - // Instruction: 5: 01011001ssss--ii0011111101---111 | p0 = cmp.eq (Rs, #u2) ; if (! p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc7) { - // Instruction: 5: 01011001ssss--ii0011111111---111 | p0 = cmp.eq (Rs, #u2) ; if (! p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF___NOT__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (! p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f44) { - // Instruction: 5: 01011001ssss--ii0011111101---100 | p0 = cmp.eq (Rs, #u2) ; if (p0) dealloc_return - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__DEALLOC_RETURN; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0) dealloc_return", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc4) { - // Instruction: 5: 01011001ssss--ii0011111111---100 | p0 = cmp.eq (Rs, #u2) ; if (p0) jumpr Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0__JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0) jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003f46) { - // Instruction: 5: 01011001ssss--ii0011111101---110 | p0 = cmp.eq (Rs, #u2) ; if (p0.new) dealloc_return:nt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__DEALLOC_RETURN_NT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0.new) dealloc_return:nt", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc7) == 0x59003fc6) { - // Instruction: 5: 01011001ssss--ii0011111111---110 | p0 = cmp.eq (Rs, #u2) ; if (p0.new) jumpr:nt Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____IF__P0_NEW__JUMPR_NT_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; if (p0.new) jumpr:nt Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00ffc4) == 0x59003fc0) { - // Instruction: 5: 01011001ssss--ii0011111111---0-- | p0 = cmp.eq (Rs, #u2) ; jumpr Lr - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____JUMPR_LR; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; jumpr Lr", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x59003000) { - // Instruction: 5: 01011001uuuu--II00110iiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memb (Rs + #u3:0) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMB__RS____U3_0_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memb (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x59002000) { - // Instruction: 5: 01011001uuuu--II00100iiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x59002800) { - // Instruction: 5: 01011001uuuu--II00101iiissssdddd | p0 = cmp.eq (Ru, #U2) ; Rd = memuh (Rs + #u3:1) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____RD___MEMUH__RS____U3_1_; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; %s = memuh (%s + 0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - break; - } - case 0x6: { - if ((hi_u32 & 0xfe40f000) == 0x7a001000) { - // Instruction: 6: 0111101--0--dddd0001iiiisssstttt | Rd = #-1 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe40f000) == 0x7a000000) { - // Instruction: 6: 0111101--0--dddd0000iiiisssstttt | Rd = #-1 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x68001000) { - // Instruction: 6: 011010IIIIIIdddd0001iiiisssstttt | Rd = #U6 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x68000000) { - // Instruction: 6: 011010IIIIIIdddd0000iiiisssstttt | Rd = #U6 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x70001000) { - // Instruction: 6: 01110000uuuudddd0001iiiisssstttt | Rd = Ru ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x70000000) { - // Instruction: 6: 01110000uuuudddd0000iiiisssstttt | Rd = Ru ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x73001000) { - // Instruction: 6: 01110011uuuudddd0001iiiisssstttt | Rd = add (Ru, #-1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x73000000) { - // Instruction: 6: 01110011uuuudddd0000iiiisssstttt | Rd = add (Ru, #-1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x71001000) { - // Instruction: 6: 01110001uuuudddd0001iiiisssstttt | Rd = add (Ru, #1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x71000000) { - // Instruction: 6: 01110001uuuudddd0000iiiisssstttt | Rd = add (Ru, #1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x6c001000) { - // Instruction: 6: 011011IIIIIIdddd0001iiiisssstttt | Rd = add (Sp, #U6:2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f000) == 0x6c000000) { - // Instruction: 6: 011011IIIIIIdddd0000iiiisssstttt | Rd = add (Sp, #U6:2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x72001000) { - // Instruction: 6: 01110010uuuudddd0001iiiisssstttt | Rd = and (Ru, #1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x72000000) { - // Instruction: 6: 01110010uuuudddd0000iiiisssstttt | Rd = and (Ru, #1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x77001000) { - // Instruction: 6: 01110111uuuudddd0001iiiisssstttt | Rd = and (Ru, #255) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x77000000) { - // Instruction: 6: 01110111uuuudddd0000iiiisssstttt | Rd = and (Ru, #255) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x75001000) { - // Instruction: 6: 01110101uuuudddd0001iiiisssstttt | Rd = sxtb (Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x75000000) { - // Instruction: 6: 01110101uuuudddd0000iiiisssstttt | Rd = sxtb (Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x74001000) { - // Instruction: 6: 01110100uuuudddd0001iiiisssstttt | Rd = sxth (Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x74000000) { - // Instruction: 6: 01110100uuuudddd0000iiiisssstttt | Rd = sxth (Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x76001000) { - // Instruction: 6: 01110110uuuudddd0001iiiisssstttt | Rd = zxth (Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x76000000) { - // Instruction: 6: 01110110uuuudddd0000iiiisssstttt | Rd = zxth (Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c001000) { - // Instruction: 6: 011111-0-II00ddd0001iiiisssstttt | Rdd = combine (#0, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c000000) { - // Instruction: 6: 011111-0-II00ddd0000iiiisssstttt | Rdd = combine (#0, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d001000) { - // Instruction: 6: 011111-1uuuu0ddd0001iiiisssstttt | Rdd = combine (#0, Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d000000) { - // Instruction: 6: 011111-1uuuu0ddd0000iiiisssstttt | Rdd = combine (#0, Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c081000) { - // Instruction: 6: 011111-0-II01ddd0001iiiisssstttt | Rdd = combine (#1, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c080000) { - // Instruction: 6: 011111-0-II01ddd0000iiiisssstttt | Rdd = combine (#1, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c101000) { - // Instruction: 6: 011111-0-II10ddd0001iiiisssstttt | Rdd = combine (#2, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c100000) { - // Instruction: 6: 011111-0-II10ddd0000iiiisssstttt | Rdd = combine (#2, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c181000) { - // Instruction: 6: 011111-0-II11ddd0001iiiisssstttt | Rdd = combine (#3, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f000) == 0x7c180000) { - // Instruction: 6: 011111-0-II11ddd0000iiiisssstttt | Rdd = combine (#3, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d081000) { - // Instruction: 6: 011111-1uuuu1ddd0001iiiisssstttt | Rdd = combine (Ru, #0) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08f000) == 0x7d080000) { - // Instruction: 6: 011111-1uuuu1ddd0000iiiisssstttt | Rdd = combine (Ru, #0) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78001000) { - // Instruction: 6: 01111000uuuuxxxx0001iiiisssstttt | Rx = add (Ru, Rx) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78000000) { - // Instruction: 6: 01111000uuuuxxxx0000iiiisssstttt | Rx = add (Ru, Rx) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x60001000) { - // Instruction: 6: 01100IIIIIIIxxxx0001iiiisssstttt | Rx = add (Rx, #S7) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x60000000) { - // Instruction: 6: 01100IIIIIIIxxxx0000iiiisssstttt | Rx = add (Rx, #S7) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78001000) { - // Instruction: 6: 01111000uuuuxxxx0001iiiisssstttt | Rx = add (Rx, Ru) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x78000000) { - // Instruction: 6: 01111000uuuuxxxx0000iiiisssstttt | Rx = add (Rx, Ru) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a701000) { - // Instruction: 6: 0111101--111dddd0001iiiisssstttt | if (! p0) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a700000) { - // Instruction: 6: 0111101--111dddd0000iiiisssstttt | if (! p0) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a501000) { - // Instruction: 6: 0111101--101dddd0001iiiisssstttt | if (! p0.new) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a500000) { - // Instruction: 6: 0111101--101dddd0000iiiisssstttt | if (! p0.new) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a601000) { - // Instruction: 6: 0111101--110dddd0001iiiisssstttt | if (p0) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a600000) { - // Instruction: 6: 0111101--110dddd0000iiiisssstttt | if (p0) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a401000) { - // Instruction: 6: 0111101--100dddd0001iiiisssstttt | if (p0.new) Rd = #0 ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f000) == 0x7a400000) { - // Instruction: 6: 0111101--100dddd0000iiiisssstttt | if (p0.new) Rd = #0 ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__RS____U4_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x79001000) { - // Instruction: 6: 01111001uuuu--II0001iiiisssstttt | p0 = cmp.eq (Ru, #U2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x79000000) { - // Instruction: 6: 01111001uuuu--II0000iiiisssstttt | p0 = cmp.eq (Ru, #U2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - break; - } - case 0x7: { - if ((hi_u32 & 0xfe40fe00) == 0x7a003c00) { - // Instruction: 7: 0111101--0--dddd0011110iiiii---- | Rd = #-1 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD_____1___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003200) { - // Instruction: 7: 0111101--0--dddd00110010ssssiiii | Rd = #-1 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003300) { - // Instruction: 7: 0111101--0--dddd00110011ssssiiii | Rd = #-1 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe00) == 0x7a002a00) { - // Instruction: 7: 0111101--0--dddd0010101iiiiiittt | Rd = #-1 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe40f800) == 0x7a002000) { - // Instruction: 7: 0111101--0--dddd00100iiisssstttt | Rd = #-1 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003000) { - // Instruction: 7: 0111101--0--dddd00110000ssssiiii | Rd = #-1 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40ff00) == 0x7a003100) { - // Instruction: 7: 0111101--0--dddd00110001ssssiiii | Rd = #-1 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe40fe00) == 0x7a002800) { - // Instruction: 7: 0111101--0--dddd0010100iiiiitttt | Rd = #-1 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD_____1___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = #-1 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x68003c00) { - // Instruction: 7: 011010IIIIIIdddd0011110iiiii---- | Rd = #U6 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD____U6___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003200) { - // Instruction: 7: 011010IIIIIIdddd00110010ssssiiii | Rd = #U6 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003300) { - // Instruction: 7: 011010IIIIIIdddd00110011ssssiiii | Rd = #U6 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x68002a00) { - // Instruction: 7: 011010IIIIIIdddd0010101iiiiiittt | Rd = #U6 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x68002000) { - // Instruction: 7: 011010IIIIIIdddd00100iiisssstttt | Rd = #U6 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003000) { - // Instruction: 7: 011010IIIIIIdddd00110000ssssiiii | Rd = #U6 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x68003100) { - // Instruction: 7: 011010IIIIIIdddd00110001ssssiiii | Rd = #U6 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x68002800) { - // Instruction: 7: 011010IIIIIIdddd0010100iiiiitttt | Rd = #U6 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD____U6___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = 0x%x ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x70003c00) { - // Instruction: 7: 01110000ssssdddd0011110iiiii---- | Rd = Rs ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___RS___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x70002a00) { - // Instruction: 7: 01110000ssssdddd0010101iiiiiittt | Rd = Rs ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___RS___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x70002800) { - // Instruction: 7: 01110000ssssdddd0010100iiiiitttt | Rd = Rs ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RS___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003200) { - // Instruction: 7: 01110000uuuudddd00110010ssssiiii | Rd = Ru ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003300) { - // Instruction: 7: 01110000uuuudddd00110011ssssiiii | Rd = Ru ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x70002000) { - // Instruction: 7: 01110000uuuudddd00100iiisssstttt | Rd = Ru ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003000) { - // Instruction: 7: 01110000uuuudddd00110000ssssiiii | Rd = Ru ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x70003100) { - // Instruction: 7: 01110000uuuudddd00110001ssssiiii | Rd = Ru ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___RU___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x73003c00) { - // Instruction: 7: 01110011ssssdddd0011110iiiii---- | Rd = add (Rs, #-1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x73002a00) { - // Instruction: 7: 01110011ssssdddd0010101iiiiiittt | Rd = add (Rs, #-1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x73002800) { - // Instruction: 7: 01110011ssssdddd0010100iiiiitttt | Rd = add (Rs, #-1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS____1____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x71003c00) { - // Instruction: 7: 01110001ssssdddd0011110iiiii---- | Rd = add (Rs, #1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x71002a00) { - // Instruction: 7: 01110001ssssdddd0010101iiiiiittt | Rd = add (Rs, #1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x71002800) { - // Instruction: 7: 01110001ssssdddd0010100iiiiitttt | Rd = add (Rs, #1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RS___1____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003200) { - // Instruction: 7: 01110011uuuudddd00110010ssssiiii | Rd = add (Ru, #-1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003300) { - // Instruction: 7: 01110011uuuudddd00110011ssssiiii | Rd = add (Ru, #-1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x73002000) { - // Instruction: 7: 01110011uuuudddd00100iiisssstttt | Rd = add (Ru, #-1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003000) { - // Instruction: 7: 01110011uuuudddd00110000ssssiiii | Rd = add (Ru, #-1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x73003100) { - // Instruction: 7: 01110011uuuudddd00110001ssssiiii | Rd = add (Ru, #-1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU____1____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #-1) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003200) { - // Instruction: 7: 01110001uuuudddd00110010ssssiiii | Rd = add (Ru, #1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003300) { - // Instruction: 7: 01110001uuuudddd00110011ssssiiii | Rd = add (Ru, #1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x71002000) { - // Instruction: 7: 01110001uuuudddd00100iiisssstttt | Rd = add (Ru, #1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003000) { - // Instruction: 7: 01110001uuuudddd00110000ssssiiii | Rd = add (Ru, #1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x71003100) { - // Instruction: 7: 01110001uuuudddd00110001ssssiiii | Rd = add (Ru, #1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__RU___1____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, #1) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x6c003c00) { - // Instruction: 7: 011011IIIIIIdddd0011110iiiii---- | Rd = add (Sp, #U6:2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003200) { - // Instruction: 7: 011011IIIIIIdddd00110010ssssiiii | Rd = add (Sp, #U6:2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003300) { - // Instruction: 7: 011011IIIIIIdddd00110011ssssiiii | Rd = add (Sp, #U6:2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x6c002a00) { - // Instruction: 7: 011011IIIIIIdddd0010101iiiiiittt | Rd = add (Sp, #U6:2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfc00f800) == 0x6c002000) { - // Instruction: 7: 011011IIIIIIdddd00100iiisssstttt | Rd = add (Sp, #U6:2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003000) { - // Instruction: 7: 011011IIIIIIdddd00110000ssssiiii | Rd = add (Sp, #U6:2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00ff00) == 0x6c003100) { - // Instruction: 7: 011011IIIIIIdddd00110001ssssiiii | Rd = add (Sp, #U6:2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00fe00) == 0x6c002800) { - // Instruction: 7: 011011IIIIIIdddd0010100iiiiitttt | Rd = add (Sp, #U6:2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ADD__SP___U6_2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Sp, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x72003c00) { - // Instruction: 7: 01110010ssssdddd0011110iiiii---- | Rd = and (Rs, #1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x72002a00) { - // Instruction: 7: 01110010ssssdddd0010101iiiiiittt | Rd = and (Rs, #1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x72002800) { - // Instruction: 7: 01110010ssssdddd0010100iiiiitttt | Rd = and (Rs, #1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___1____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x77003c00) { - // Instruction: 7: 01110111ssssdddd0011110iiiii---- | Rd = and (Rs, #255) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x77002a00) { - // Instruction: 7: 01110111ssssdddd0010101iiiiiittt | Rd = and (Rs, #255) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x77002800) { - // Instruction: 7: 01110111ssssdddd0010100iiiiitttt | Rd = and (Rs, #255) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RS___255____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003200) { - // Instruction: 7: 01110010uuuudddd00110010ssssiiii | Rd = and (Ru, #1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003300) { - // Instruction: 7: 01110010uuuudddd00110011ssssiiii | Rd = and (Ru, #1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x72002000) { - // Instruction: 7: 01110010uuuudddd00100iiisssstttt | Rd = and (Ru, #1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003000) { - // Instruction: 7: 01110010uuuudddd00110000ssssiiii | Rd = and (Ru, #1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x72003100) { - // Instruction: 7: 01110010uuuudddd00110001ssssiiii | Rd = and (Ru, #1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___1____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #1) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003200) { - // Instruction: 7: 01110111uuuudddd00110010ssssiiii | Rd = and (Ru, #255) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003300) { - // Instruction: 7: 01110111uuuudddd00110011ssssiiii | Rd = and (Ru, #255) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x77002000) { - // Instruction: 7: 01110111uuuudddd00100iiisssstttt | Rd = and (Ru, #255) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003000) { - // Instruction: 7: 01110111uuuudddd00110000ssssiiii | Rd = and (Ru, #255) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x77003100) { - // Instruction: 7: 01110111uuuudddd00110001ssssiiii | Rd = and (Ru, #255) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___AND__RU___255____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = and (%s, #255) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x75003c00) { - // Instruction: 7: 01110101ssssdddd0011110iiiii---- | Rd = sxtb (Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x75002a00) { - // Instruction: 7: 01110101ssssdddd0010101iiiiiittt | Rd = sxtb (Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x75002800) { - // Instruction: 7: 01110101ssssdddd0010100iiiiitttt | Rd = sxtb (Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003200) { - // Instruction: 7: 01110101uuuudddd00110010ssssiiii | Rd = sxtb (Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003300) { - // Instruction: 7: 01110101uuuudddd00110011ssssiiii | Rd = sxtb (Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x75002000) { - // Instruction: 7: 01110101uuuudddd00100iiisssstttt | Rd = sxtb (Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003000) { - // Instruction: 7: 01110101uuuudddd00110000ssssiiii | Rd = sxtb (Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x75003100) { - // Instruction: 7: 01110101uuuudddd00110001ssssiiii | Rd = sxtb (Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTB__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxtb (%s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x74003c00) { - // Instruction: 7: 01110100ssssdddd0011110iiiii---- | Rd = sxth (Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x74002a00) { - // Instruction: 7: 01110100ssssdddd0010101iiiiiittt | Rd = sxth (Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x74002800) { - // Instruction: 7: 01110100ssssdddd0010100iiiiitttt | Rd = sxth (Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003200) { - // Instruction: 7: 01110100uuuudddd00110010ssssiiii | Rd = sxth (Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003300) { - // Instruction: 7: 01110100uuuudddd00110011ssssiiii | Rd = sxth (Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x74002000) { - // Instruction: 7: 01110100uuuudddd00100iiisssstttt | Rd = sxth (Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003000) { - // Instruction: 7: 01110100uuuudddd00110000ssssiiii | Rd = sxth (Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x74003100) { - // Instruction: 7: 01110100uuuudddd00110001ssssiiii | Rd = sxth (Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___SXTH__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = sxth (%s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x76003c00) { - // Instruction: 7: 01110110ssssdddd0011110iiiii---- | Rd = zxth (Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x76002a00) { - // Instruction: 7: 01110110ssssdddd0010101iiiiiittt | Rd = zxth (Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x76002800) { - // Instruction: 7: 01110110ssssdddd0010100iiiiitttt | Rd = zxth (Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003200) { - // Instruction: 7: 01110110uuuudddd00110010ssssiiii | Rd = zxth (Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003300) { - // Instruction: 7: 01110110uuuudddd00110011ssssiiii | Rd = zxth (Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x76002000) { - // Instruction: 7: 01110110uuuudddd00100iiisssstttt | Rd = zxth (Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003000) { - // Instruction: 7: 01110110uuuudddd00110000ssssiiii | Rd = zxth (Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x76003100) { - // Instruction: 7: 01110110uuuudddd00110001ssssiiii | Rd = zxth (Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = zxth (%s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c003c00) { - // Instruction: 7: 011111-0-II00ddd0011110iiiii---- | Rdd = combine (#0, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003200) { - // Instruction: 7: 011111-0-II00ddd00110010ssssiiii | Rdd = combine (#0, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003300) { - // Instruction: 7: 011111-0-II00ddd00110011ssssiiii | Rdd = combine (#0, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c002a00) { - // Instruction: 7: 011111-0-II00ddd0010101iiiiiittt | Rdd = combine (#0, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c002000) { - // Instruction: 7: 011111-0-II00ddd00100iiisssstttt | Rdd = combine (#0, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003000) { - // Instruction: 7: 011111-0-II00ddd00110000ssssiiii | Rdd = combine (#0, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c003100) { - // Instruction: 7: 011111-0-II00ddd00110001ssssiiii | Rdd = combine (#0, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c002800) { - // Instruction: 7: 011111-0-II00ddd0010100iiiiitttt | Rdd = combine (#0, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d003c00) { - // Instruction: 7: 011111-1ssss0ddd0011110iiiii---- | Rdd = combine (#0, Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d002a00) { - // Instruction: 7: 011111-1ssss0ddd0010101iiiiiittt | Rdd = combine (#0, Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d002800) { - // Instruction: 7: 011111-1ssss0ddd0010100iiiiitttt | Rdd = combine (#0, Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003200) { - // Instruction: 7: 011111-1uuuu0ddd00110010ssssiiii | Rdd = combine (#0, Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003300) { - // Instruction: 7: 011111-1uuuu0ddd00110011ssssiiii | Rdd = combine (#0, Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x7d002000) { - // Instruction: 7: 011111-1uuuu0ddd00100iiisssstttt | Rdd = combine (#0, Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003000) { - // Instruction: 7: 011111-1uuuu0ddd00110000ssssiiii | Rdd = combine (#0, Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d003100) { - // Instruction: 7: 011111-1uuuu0ddd00110001ssssiiii | Rdd = combine (#0, Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#0, %s) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c083c00) { - // Instruction: 7: 011111-0-II01ddd0011110iiiii---- | Rdd = combine (#1, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083200) { - // Instruction: 7: 011111-0-II01ddd00110010ssssiiii | Rdd = combine (#1, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083300) { - // Instruction: 7: 011111-0-II01ddd00110011ssssiiii | Rdd = combine (#1, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c082a00) { - // Instruction: 7: 011111-0-II01ddd0010101iiiiiittt | Rdd = combine (#1, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c082000) { - // Instruction: 7: 011111-0-II01ddd00100iiisssstttt | Rdd = combine (#1, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083000) { - // Instruction: 7: 011111-0-II01ddd00110000ssssiiii | Rdd = combine (#1, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c083100) { - // Instruction: 7: 011111-0-II01ddd00110001ssssiiii | Rdd = combine (#1, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c082800) { - // Instruction: 7: 011111-0-II01ddd0010100iiiiitttt | Rdd = combine (#1, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#1, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c103c00) { - // Instruction: 7: 011111-0-II10ddd0011110iiiii---- | Rdd = combine (#2, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103200) { - // Instruction: 7: 011111-0-II10ddd00110010ssssiiii | Rdd = combine (#2, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103300) { - // Instruction: 7: 011111-0-II10ddd00110011ssssiiii | Rdd = combine (#2, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c102a00) { - // Instruction: 7: 011111-0-II10ddd0010101iiiiiittt | Rdd = combine (#2, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c102000) { - // Instruction: 7: 011111-0-II10ddd00100iiisssstttt | Rdd = combine (#2, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103000) { - // Instruction: 7: 011111-0-II10ddd00110000ssssiiii | Rdd = combine (#2, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c103100) { - // Instruction: 7: 011111-0-II10ddd00110001ssssiiii | Rdd = combine (#2, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c102800) { - // Instruction: 7: 011111-0-II10ddd0010100iiiiitttt | Rdd = combine (#2, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#2, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c183c00) { - // Instruction: 7: 011111-0-II11ddd0011110iiiii---- | Rdd = combine (#3, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183200) { - // Instruction: 7: 011111-0-II11ddd00110010ssssiiii | Rdd = combine (#3, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183300) { - // Instruction: 7: 011111-0-II11ddd00110011ssssiiii | Rdd = combine (#3, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c182a00) { - // Instruction: 7: 011111-0-II11ddd0010101iiiiiittt | Rdd = combine (#3, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd18f800) == 0x7c182000) { - // Instruction: 7: 011111-0-II11ddd00100iiisssstttt | Rdd = combine (#3, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183000) { - // Instruction: 7: 011111-0-II11ddd00110000ssssiiii | Rdd = combine (#3, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18ff00) == 0x7c183100) { - // Instruction: 7: 011111-0-II11ddd00110001ssssiiii | Rdd = combine (#3, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd18fe00) == 0x7c182800) { - // Instruction: 7: 011111-0-II11ddd0010100iiiiitttt | Rdd = combine (#3, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (#3, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d083c00) { - // Instruction: 7: 011111-1ssss1ddd0011110iiiii---- | Rdd = combine (Rs, #0) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d082a00) { - // Instruction: 7: 011111-1ssss1ddd0010101iiiiiittt | Rdd = combine (Rs, #0) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08fe00) == 0x7d082800) { - // Instruction: 7: 011111-1ssss1ddd0010100iiiiitttt | Rdd = combine (Rs, #0) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083200) { - // Instruction: 7: 011111-1uuuu1ddd00110010ssssiiii | Rdd = combine (Ru, #0) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083300) { - // Instruction: 7: 011111-1uuuu1ddd00110011ssssiiii | Rdd = combine (Ru, #0) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08f800) == 0x7d082000) { - // Instruction: 7: 011111-1uuuu1ddd00100iiisssstttt | Rdd = combine (Ru, #0) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083000) { - // Instruction: 7: 011111-1uuuu1ddd00110000ssssiiii | Rdd = combine (Ru, #0) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfd08ff00) == 0x7d083100) { - // Instruction: 7: 011111-1uuuu1ddd00110001ssssiiii | Rdd = combine (Ru, #0) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = combine (%s, #0) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78003c00) { - // Instruction: 7: 01111000ssssxxxx0011110iiiii---- | Rx = add (Rs, Rx) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002a00) { - // Instruction: 7: 01111000ssssxxxx0010101iiiiiittt | Rx = add (Rs, Rx) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002800) { - // Instruction: 7: 01111000ssssxxxx0010100iiiiitttt | Rx = add (Rs, Rx) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RS__RX____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003200) { - // Instruction: 7: 01111000uuuuxxxx00110010ssssiiii | Rx = add (Ru, Rx) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003300) { - // Instruction: 7: 01111000uuuuxxxx00110011ssssiiii | Rx = add (Ru, Rx) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x78002000) { - // Instruction: 7: 01111000uuuuxxxx00100iiisssstttt | Rx = add (Ru, Rx) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003000) { - // Instruction: 7: 01111000uuuuxxxx00110000ssssiiii | Rx = add (Ru, Rx) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003100) { - // Instruction: 7: 01111000uuuuxxxx00110001ssssiiii | Rx = add (Ru, Rx) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RU__RX____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (%s, Rx) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x60003c00) { - // Instruction: 7: 01100IIIIIIIxxxx0011110iiiii---- | Rx = add (Rx, #S7) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003200) { - // Instruction: 7: 01100IIIIIIIxxxx00110010ssssiiii | Rx = add (Rx, #S7) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003300) { - // Instruction: 7: 01100IIIIIIIxxxx00110011ssssiiii | Rx = add (Rx, #S7) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x60002a00) { - // Instruction: 7: 01100IIIIIIIxxxx0010101iiiiiittt | Rx = add (Rx, #S7) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800f800) == 0x60002000) { - // Instruction: 7: 01100IIIIIIIxxxx00100iiisssstttt | Rx = add (Rx, #S7) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003000) { - // Instruction: 7: 01100IIIIIIIxxxx00110000ssssiiii | Rx = add (Rx, #S7) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0x60003100) { - // Instruction: 7: 01100IIIIIIIxxxx00110001ssssiiii | Rx = add (Rx, #S7) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0x60002800) { - // Instruction: 7: 01100IIIIIIIxxxx0010100iiiiitttt | Rx = add (Rx, #S7) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX___S7____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7f00000) >> 20); - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "%s = add (Rx, %d) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78003c00) { - // Instruction: 7: 01111000ssssxxxx0011110iiiii---- | Rx = add (Rx, Rs) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002a00) { - // Instruction: 7: 01111000ssssxxxx0010101iiiiiittt | Rx = add (Rx, Rs) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x78002800) { - // Instruction: 7: 01111000ssssxxxx0010100iiiiitttt | Rx = add (Rx, Rs) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RS____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003200) { - // Instruction: 7: 01111000uuuuxxxx00110010ssssiiii | Rx = add (Rx, Ru) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003300) { - // Instruction: 7: 01111000uuuuxxxx00110011ssssiiii | Rx = add (Rx, Ru) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x78002000) { - // Instruction: 7: 01111000uuuuxxxx00100iiisssstttt | Rx = add (Rx, Ru) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003000) { - // Instruction: 7: 01111000uuuuxxxx00110000ssssiiii | Rx = add (Rx, Ru) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x78003100) { - // Instruction: 7: 01111000uuuuxxxx00110001ssssiiii | Rx = add (Rx, Ru) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RX___ADD__RX__RU____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = add (Rx, %s) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a703c00) { - // Instruction: 7: 0111101--111dddd0011110iiiii---- | if (! p0) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703200) { - // Instruction: 7: 0111101--111dddd00110010ssssiiii | if (! p0) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703300) { - // Instruction: 7: 0111101--111dddd00110011ssssiiii | if (! p0) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a702a00) { - // Instruction: 7: 0111101--111dddd0010101iiiiiittt | if (! p0) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a702000) { - // Instruction: 7: 0111101--111dddd00100iiisssstttt | if (! p0) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703000) { - // Instruction: 7: 0111101--111dddd00110000ssssiiii | if (! p0) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a703100) { - // Instruction: 7: 0111101--111dddd00110001ssssiiii | if (! p0) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a702800) { - // Instruction: 7: 0111101--111dddd0010100iiiiitttt | if (! p0) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a503c00) { - // Instruction: 7: 0111101--101dddd0011110iiiii---- | if (! p0.new) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503200) { - // Instruction: 7: 0111101--101dddd00110010ssssiiii | if (! p0.new) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503300) { - // Instruction: 7: 0111101--101dddd00110011ssssiiii | if (! p0.new) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a502a00) { - // Instruction: 7: 0111101--101dddd0010101iiiiiittt | if (! p0.new) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a502000) { - // Instruction: 7: 0111101--101dddd00100iiisssstttt | if (! p0.new) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503000) { - // Instruction: 7: 0111101--101dddd00110000ssssiiii | if (! p0.new) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a503100) { - // Instruction: 7: 0111101--101dddd00110001ssssiiii | if (! p0.new) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a502800) { - // Instruction: 7: 0111101--101dddd0010100iiiiitttt | if (! p0.new) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF___NOT__P0_NEW__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (! p0.new) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a603c00) { - // Instruction: 7: 0111101--110dddd0011110iiiii---- | if (p0) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603200) { - // Instruction: 7: 0111101--110dddd00110010ssssiiii | if (p0) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603300) { - // Instruction: 7: 0111101--110dddd00110011ssssiiii | if (p0) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a602a00) { - // Instruction: 7: 0111101--110dddd0010101iiiiiittt | if (p0) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a602000) { - // Instruction: 7: 0111101--110dddd00100iiisssstttt | if (p0) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603000) { - // Instruction: 7: 0111101--110dddd00110000ssssiiii | if (p0) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a603100) { - // Instruction: 7: 0111101--110dddd00110001ssssiiii | if (p0) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a602800) { - // Instruction: 7: 0111101--110dddd0010100iiiiitttt | if (p0) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a403c00) { - // Instruction: 7: 0111101--100dddd0011110iiiii---- | if (p0.new) Rd = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___ALLOCFRAME___U5_3_; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403200) { - // Instruction: 7: 0111101--100dddd00110010ssssiiii | if (p0.new) Rd = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403300) { - // Instruction: 7: 0111101--100dddd00110011ssssiiii | if (p0.new) Rd = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMB__RS____U4_0_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a402a00) { - // Instruction: 7: 0111101--100dddd0010101iiiiiittt | if (p0.new) Rd = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMD__SP____S6_3____RTT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 8)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), (st32)hi->ops[1].op.imm, hex_get_sub_regpair(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xfe70f800) == 0x7a402000) { - // Instruction: 7: 0111101--100dddd00100iiisssstttt | if (p0.new) Rd = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMH__RS____U3_1____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403000) { - // Instruction: 7: 0111101--100dddd00110000ssssiiii | if (p0.new) Rd = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__RS____U4_2_____0; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70ff00) == 0x7a403100) { - // Instruction: 7: 0111101--100dddd00110001ssssiiii | if (p0.new) Rd = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__RS____U4_2_____1; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe70fe00) == 0x7a402800) { - // Instruction: 7: 0111101--100dddd0010100iiiiitttt | if (p0.new) Rd = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_IF__P0_NEW__RD____0___MEMW__SP____U5_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (p0.new) %s = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x79003c00) { - // Instruction: 7: 01111001ssss--II0011110iiiii---- | p0 = cmp.eq (Rs, #U2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x79002a00) { - // Instruction: 7: 01111001ssss--II0010101iiiiiittt | p0 = cmp.eq (Rs, #U2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0x79002800) { - // Instruction: 7: 01111001ssss--II0010100iiiiitttt | p0 = cmp.eq (Rs, #U2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RS___U2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003200) { - // Instruction: 7: 01111001uuuu--II00110010ssssiiii | p0 = cmp.eq (Ru, #U2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003300) { - // Instruction: 7: 01111001uuuu--II00110011ssssiiii | p0 = cmp.eq (Ru, #U2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0x79002000) { - // Instruction: 7: 01111001uuuu--II00100iiisssstttt | p0 = cmp.eq (Ru, #U2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003000) { - // Instruction: 7: 01111001uuuu--II00110000ssssiiii | p0 = cmp.eq (Ru, #U2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0x79003100) { - // Instruction: 7: 01111001uuuu--II00110001ssssiiii | p0 = cmp.eq (Ru, #U2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_P0___CMP_EQ__RU___U2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (%s, 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - break; - } - case 0x8: { - if ((hi_u32 & 0xf000f000) == 0x90001000) { - // Instruction: 8: 1001IIIIuuuudddd0001iiiisssstttt | Rd = memub (Ru + #U4:0) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0x90000000) { - // Instruction: 8: 1001IIIIuuuudddd0000iiiisssstttt | Rd = memub (Ru + #U4:0) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0x80001000) { - // Instruction: 8: 1000IIIIuuuudddd0001iiiisssstttt | Rd = memw (Ru + #U4:2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0x80000000) { - // Instruction: 8: 1000IIIIuuuudddd0000iiiisssstttt | Rd = memw (Ru + #U4:2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - break; - } - case 0x9: { - if ((hi_u32 & 0xf800f000) == 0x90003000) { - // Instruction: 9: 10010IIIuuuudddd0011iiiisssstttt | Rd = memb (Ru + #U3:0) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x90002000) { - // Instruction: 9: 10010IIIuuuudddd0010iiiisssstttt | Rd = memb (Ru + #U3:0) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x80003000) { - // Instruction: 9: 10000IIIuuuudddd0011iiiisssstttt | Rd = memh (Ru + #U3:1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x80002000) { - // Instruction: 9: 10000IIIuuuudddd0010iiiisssstttt | Rd = memh (Ru + #U3:1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x88003000) { - // Instruction: 9: 10001IIIuuuudddd0011iiiisssstttt | Rd = memuh (Ru + #U3:1) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800f000) == 0x88002000) { - // Instruction: 9: 10001IIIuuuudddd0010iiiisssstttt | Rd = memuh (Ru + #U3:1) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f000) == 0x9c003000) { - // Instruction: 9: 1001110IIIIIdddd0011iiiisssstttt | Rd = memw (Sp + #U5:2) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f000) == 0x9c002000) { - // Instruction: 9: 1001110IIIIIdddd0010iiiisssstttt | Rd = memw (Sp + #U5:2) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x9e003000) { - // Instruction: 9: 10011110IIIIIddd0011iiiisssstttt | Rdd = memd (Sp + #U5:3) ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memb (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00f000) == 0x9e002000) { - // Instruction: 9: 10011110IIIIIddd0010iiiisssstttt | Rdd = memd (Sp + #U5:3) ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xffc4f000) == 0x9f003000) { - // Instruction: 9: 1001111100---0--0011iiiisssstttt | deallocframe ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xffc4f000) == 0x9f002000) { - // Instruction: 9: 1001111100---0--0010iiiisssstttt | deallocframe ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - break; - } - case 0xa: { - if ((hi_u32 & 0xf000f000) == 0xb0001000) { - // Instruction: 10: 1011IIIIuuuuvvvv0001iiiisssstttt | memb (Ru + #U4:0) = Rv ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RV___MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0xb0000000) { - // Instruction: 10: 1011IIIIuuuuvvvv0000iiiisssstttt | memb (Ru + #U4:0) = Rv ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RV___MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0xa0001000) { - // Instruction: 10: 1010IIIIuuuuvvvv0001iiiisssstttt | memw (Ru + #U4:2) = Rv ; memb (Rs + #u4:0) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RV___MEMB__RS____U4_0____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memb (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000f000) == 0xa0000000) { - // Instruction: 10: 1010IIIIuuuuvvvv0000iiiisssstttt | memw (Ru + #U4:2) = Rv ; memw (Rs + #u4:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RV___MEMW__RS____U4_2____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - break; - } - case 0xb: { - if ((hi_u32 & 0xf000fe00) == 0xb0003c00) { - // Instruction: 11: 1011IIIIsssstttt0011110iiiii---- | memb (Rs + #U4:0) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0____RT___ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xb0002a00) { - // Instruction: 11: 1011IIIIssssvvvv0010101iiiiiittt | memb (Rs + #U4:0) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xb0002800) { - // Instruction: 11: 1011IIIIssssvvvv0010100iiiiitttt | memb (Rs + #U4:0) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0____RV___MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003200) { - // Instruction: 11: 1011IIIIuuuutttt00110010ssssiiii | memb (Ru + #U4:0) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003300) { - // Instruction: 11: 1011IIIIuuuutttt00110011ssssiiii | memb (Ru + #U4:0) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003000) { - // Instruction: 11: 1011IIIIuuuutttt00110000ssssiiii | memb (Ru + #U4:0) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xb0003100) { - // Instruction: 11: 1011IIIIuuuutttt00110001ssssiiii | memb (Ru + #U4:0) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RT___MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xb0002000) { - // Instruction: 11: 1011IIIIuuuuvvvv00100iiisssstttt | memb (Ru + #U4:0) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0____RV___MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xa0003c00) { - // Instruction: 11: 1010IIIIsssstttt0011110iiiii---- | memw (Rs + #U4:2) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2____RT___ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xa0002a00) { - // Instruction: 11: 1010IIIIssssvvvv0010101iiiiiittt | memw (Rs + #U4:2) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xa0002800) { - // Instruction: 11: 1010IIIIssssvvvv0010100iiiiitttt | memw (Rs + #U4:2) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2____RV___MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003200) { - // Instruction: 11: 1010IIIIuuuutttt00110010ssssiiii | memw (Ru + #U4:2) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003300) { - // Instruction: 11: 1010IIIIuuuutttt00110011ssssiiii | memw (Ru + #U4:2) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003000) { - // Instruction: 11: 1010IIIIuuuutttt00110000ssssiiii | memw (Ru + #U4:2) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xa0003100) { - // Instruction: 11: 1010IIIIuuuutttt00110001ssssiiii | memw (Ru + #U4:2) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RT___MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xa0002000) { - // Instruction: 11: 1010IIIIuuuuvvvv00100iiisssstttt | memw (Ru + #U4:2) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2____RV___MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - break; - } - case 0xc: { - if ((hi_u32 & 0xf000fe00) == 0xd0001c00) { - // Instruction: 12: 1101IIIIssssdddd0001110iiiii---- | Rd = memub (Rs + #U4:0) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xd0000a00) { - // Instruction: 12: 1101IIIIssssdddd0000101iiiiiittt | Rd = memub (Rs + #U4:0) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xd0000800) { - // Instruction: 12: 1101IIIIssssdddd0000100iiiiitttt | Rd = memub (Rs + #U4:0) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RS____U4_0____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001200) { - // Instruction: 12: 1101IIIIuuuudddd00010010ssssiiii | Rd = memub (Ru + #U4:0) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001300) { - // Instruction: 12: 1101IIIIuuuudddd00010011ssssiiii | Rd = memub (Ru + #U4:0) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xd0000000) { - // Instruction: 12: 1101IIIIuuuudddd00000iiisssstttt | Rd = memub (Ru + #U4:0) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001000) { - // Instruction: 12: 1101IIIIuuuudddd00010000ssssiiii | Rd = memub (Ru + #U4:0) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xd0001100) { - // Instruction: 12: 1101IIIIuuuudddd00010001ssssiiii | Rd = memub (Ru + #U4:0) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUB__RU____U4_0____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memub (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xc0001c00) { - // Instruction: 12: 1100IIIIssssdddd0001110iiiii---- | Rd = memw (Rs + #U4:2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xc0000a00) { - // Instruction: 12: 1100IIIIssssdddd0000101iiiiiittt | Rd = memw (Rs + #U4:2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000fe00) == 0xc0000800) { - // Instruction: 12: 1100IIIIssssdddd0000100iiiiitttt | Rd = memw (Rs + #U4:2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RS____U4_2____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001200) { - // Instruction: 12: 1100IIIIuuuudddd00010010ssssiiii | Rd = memw (Ru + #U4:2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001300) { - // Instruction: 12: 1100IIIIuuuudddd00010011ssssiiii | Rd = memw (Ru + #U4:2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000f800) == 0xc0000000) { - // Instruction: 12: 1100IIIIuuuudddd00000iiisssstttt | Rd = memw (Ru + #U4:2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001000) { - // Instruction: 12: 1100IIIIuuuudddd00010000ssssiiii | Rd = memw (Ru + #U4:2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf000ff00) == 0xc0001100) { - // Instruction: 12: 1100IIIIuuuudddd00010001ssssiiii | Rd = memw (Ru + #U4:2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__RU____U4_2____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - break; - } - case 0xd: { - if ((hi_u32 & 0xf800fe00) == 0xd0003c00) { - // Instruction: 13: 11010IIIssssdddd0011110iiiii---- | Rd = memb (Rs + #U3:0) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xd0002a00) { - // Instruction: 13: 11010IIIssssdddd0010101iiiiiittt | Rd = memb (Rs + #U3:0) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xd0002800) { - // Instruction: 13: 11010IIIssssdddd0010100iiiiitttt | Rd = memb (Rs + #U3:0) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RS____U3_0____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003200) { - // Instruction: 13: 11010IIIuuuudddd00110010ssssiiii | Rd = memb (Ru + #U3:0) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003300) { - // Instruction: 13: 11010IIIuuuudddd00110011ssssiiii | Rd = memb (Ru + #U3:0) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xd0002000) { - // Instruction: 13: 11010IIIuuuudddd00100iiisssstttt | Rd = memb (Ru + #U3:0) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003000) { - // Instruction: 13: 11010IIIuuuudddd00110000ssssiiii | Rd = memb (Ru + #U3:0) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xd0003100) { - // Instruction: 13: 11010IIIuuuudddd00110001ssssiiii | Rd = memb (Ru + #U3:0) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMB__RU____U3_0____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memb (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc0003c00) { - // Instruction: 13: 11000IIIssssdddd0011110iiiii---- | Rd = memh (Rs + #U3:1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc0002a00) { - // Instruction: 13: 11000IIIssssdddd0010101iiiiiittt | Rd = memh (Rs + #U3:1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc0002800) { - // Instruction: 13: 11000IIIssssdddd0010100iiiiitttt | Rd = memh (Rs + #U3:1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RS____U3_1____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003200) { - // Instruction: 13: 11000IIIuuuudddd00110010ssssiiii | Rd = memh (Ru + #U3:1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003300) { - // Instruction: 13: 11000IIIuuuudddd00110011ssssiiii | Rd = memh (Ru + #U3:1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xc0002000) { - // Instruction: 13: 11000IIIuuuudddd00100iiisssstttt | Rd = memh (Ru + #U3:1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003000) { - // Instruction: 13: 11000IIIuuuudddd00110000ssssiiii | Rd = memh (Ru + #U3:1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc0003100) { - // Instruction: 13: 11000IIIuuuudddd00110001ssssiiii | Rd = memh (Ru + #U3:1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMH__RU____U3_1____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memh (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc8003c00) { - // Instruction: 13: 11001IIIssssdddd0011110iiiii---- | Rd = memuh (Rs + #U3:1) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc8002a00) { - // Instruction: 13: 11001IIIssssdddd0010101iiiiiittt | Rd = memuh (Rs + #U3:1) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xc8002800) { - // Instruction: 13: 11001IIIssssdddd0010100iiiiitttt | Rd = memuh (Rs + #U3:1) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003200) { - // Instruction: 13: 11001IIIuuuudddd00110010ssssiiii | Rd = memuh (Ru + #U3:1) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003300) { - // Instruction: 13: 11001IIIuuuudddd00110011ssssiiii | Rd = memuh (Ru + #U3:1) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xc8002000) { - // Instruction: 13: 11001IIIuuuudddd00100iiisssstttt | Rd = memuh (Ru + #U3:1) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003000) { - // Instruction: 13: 11001IIIuuuudddd00110000ssssiiii | Rd = memuh (Ru + #U3:1) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xc8003100) { - // Instruction: 13: 11001IIIuuuudddd00110001ssssiiii | Rd = memuh (Ru + #U3:1) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memuh (%s + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xdc003c00) { - // Instruction: 13: 1101110IIIIIdddd0011110iiiii---- | Rd = memw (Sp + #U5:2) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003200) { - // Instruction: 13: 1101110IIIIIdddd00110010ssssiiii | Rd = memw (Sp + #U5:2) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003300) { - // Instruction: 13: 1101110IIIIIdddd00110011ssssiiii | Rd = memw (Sp + #U5:2) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xdc002a00) { - // Instruction: 13: 1101110IIIIIdddd0010101iiiiiittt | Rd = memw (Sp + #U5:2) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f800) == 0xdc002000) { - // Instruction: 13: 1101110IIIIIdddd00100iiisssstttt | Rd = memw (Sp + #U5:2) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003000) { - // Instruction: 13: 1101110IIIIIdddd00110000ssssiiii | Rd = memw (Sp + #U5:2) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xdc003100) { - // Instruction: 13: 1101110IIIIIdddd00110001ssssiiii | Rd = memw (Sp + #U5:2) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xdc002800) { - // Instruction: 13: 1101110IIIIIdddd0010100iiiiitttt | Rd = memw (Sp + #U5:2) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RD___MEMW__SP____U5_2____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memw (Sp + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xde003c00) { - // Instruction: 13: 11011110IIIIIddd0011110iiiii---- | Rdd = memd (Sp + #U5:3) ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; allocframe (0x%x)", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003200) { - // Instruction: 13: 11011110IIIIIddd00110010ssssiiii | Rdd = memd (Sp + #U5:3) ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memb (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003300) { - // Instruction: 13: 11011110IIIIIddd00110011ssssiiii | Rdd = memd (Sp + #U5:3) ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memb (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xde002a00) { - // Instruction: 13: 11011110IIIIIddd0010101iiiiiittt | Rdd = memd (Sp + #U5:3) ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memd (Sp + %d) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00f800) == 0xde002000) { - // Instruction: 13: 11011110IIIIIddd00100iiisssstttt | Rdd = memd (Sp + #U5:3) ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memh (%s + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003000) { - // Instruction: 13: 11011110IIIIIddd00110000ssssiiii | Rdd = memd (Sp + #U5:3) ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (%s + 0x%x) = #0", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xde003100) { - // Instruction: 13: 11011110IIIIIddd00110001ssssiiii | Rdd = memd (Sp + #U5:3) ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (%s + 0x%x) = #1", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xde002800) { - // Instruction: 13: 11011110IIIIIddd0010100iiiiitttt | Rdd = memd (Sp + #U5:3) ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = memd (Sp + 0x%x) ; memw (Sp + 0x%x) = %s", hex_get_sub_regpair(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003200) { - // Instruction: 13: 1101111100---0--00110010ssssiiii | deallocframe ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0_____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003300) { - // Instruction: 13: 1101111100---0--00110011ssssiiii | deallocframe ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMB__RS____U4_0_____1; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4fe00) == 0xdf002a00) { - // Instruction: 13: 1101111100---0--0010101iiiiiittt | deallocframe ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMD__SP____S6_3____RTT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memd (Sp + %d) = %s", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg)); - break; - } - if ((hi_u32 & 0xffc4f800) == 0xdf002000) { - // Instruction: 13: 1101111100---0--00100iiisssstttt | deallocframe ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMH__RS____U3_1____RT; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg)); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003000) { - // Instruction: 13: 1101111100---0--00110000ssssiiii | deallocframe ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2_____0; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4ff00) == 0xdf003100) { - // Instruction: 13: 1101111100---0--00110001ssssiiii | deallocframe ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__RS____U4_2_____1; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xffc4fe00) == 0xdf002800) { - // Instruction: 13: 1101111100---0--0010100iiiiitttt | deallocframe ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_DEALLOCFRAME___MEMW__SP____U5_2____RT; - hi->op_count = 2; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe ; memw (Sp + 0x%x) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg)); - break; - } - break; - } - case 0xe: { - if ((hi_u32 & 0xff00fe00) == 0xf2001c00) { - // Instruction: 14: 11110010ssssIIII0001110iiiii---- | memb (Rs + #U4:0) = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____0___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf2000a00) { - // Instruction: 14: 11110010ssssIIII0000101iiiiiittt | memb (Rs + #U4:0) = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____0___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf2000800) { - // Instruction: 14: 11110010ssssIIII0000100iiiiitttt | memb (Rs + #U4:0) = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____0___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf3001c00) { - // Instruction: 14: 11110011ssssIIII0001110iiiii---- | memb (Rs + #U4:0) = #1 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____1___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf3000a00) { - // Instruction: 14: 11110011ssssIIII0000101iiiiiittt | memb (Rs + #U4:0) = #1 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____1___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf3000800) { - // Instruction: 14: 11110011ssssIIII0000100iiiiitttt | memb (Rs + #U4:0) = #1 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RS____U4_0_____1___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001200) { - // Instruction: 14: 11110010uuuuIIII00010010ssssiiii | memb (Ru + #U4:0) = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001300) { - // Instruction: 14: 11110010uuuuIIII00010011ssssiiii | memb (Ru + #U4:0) = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf2000000) { - // Instruction: 14: 11110010uuuuIIII00000iiisssstttt | memb (Ru + #U4:0) = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001000) { - // Instruction: 14: 11110010uuuuIIII00010000ssssiiii | memb (Ru + #U4:0) = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf2001100) { - // Instruction: 14: 11110010uuuuIIII00010001ssssiiii | memb (Ru + #U4:0) = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____0___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001200) { - // Instruction: 14: 11110011uuuuIIII00010010ssssiiii | memb (Ru + #U4:0) = #1 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001300) { - // Instruction: 14: 11110011uuuuIIII00010011ssssiiii | memb (Ru + #U4:0) = #1 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf3000000) { - // Instruction: 14: 11110011uuuuIIII00000iiisssstttt | memb (Ru + #U4:0) = #1 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001000) { - // Instruction: 14: 11110011uuuuIIII00010000ssssiiii | memb (Ru + #U4:0) = #1 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf3001100) { - // Instruction: 14: 11110011uuuuIIII00010001ssssiiii | memb (Ru + #U4:0) = #1 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMB__RU____U4_0_____1___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xea001c00) { - // Instruction: 14: 1110101IIIIIIttt0001110iiiii---- | memd (Sp + #S6:3) = Rtt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; allocframe (0x%x)", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001200) { - // Instruction: 14: 1110101IIIIIIttt00010010ssssiiii | memd (Sp + #S6:3) = Rtt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memb (%s + 0x%x) = #0", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001300) { - // Instruction: 14: 1110101IIIIIIttt00010011ssssiiii | memd (Sp + #S6:3) = Rtt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memb (%s + 0x%x) = #1", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001000) { - // Instruction: 14: 1110101IIIIIIttt00010000ssssiiii | memd (Sp + #S6:3) = Rtt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memw (%s + 0x%x) = #0", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xea001100) { - // Instruction: 14: 1110101IIIIIIttt00010001ssssiiii | memd (Sp + #S6:3) = Rtt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RTT___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memw (%s + 0x%x) = #1", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xea000a00) { - // Instruction: 14: 1110101IIIIIIvvv0000101iiiiiittt | memd (Sp + #S6:3) = Rvv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RVV___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memd (Sp + %d) = %s", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f800) == 0xea000000) { - // Instruction: 14: 1110101IIIIIIvvv00000iiisssstttt | memd (Sp + #S6:3) = Rvv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RVV___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memh (%s + 0x%x) = %s", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xea000800) { - // Instruction: 14: 1110101IIIIIIvvv0000100iiiiitttt | memd (Sp + #S6:3) = Rvv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMD__SP____S6_3____RVV___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (Sp + %d) = %s ; memw (Sp + 0x%x) = %s", (st32)hi->ops[0].op.imm, hex_get_sub_regpair(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xe0001c00) { - // Instruction: 14: 11100IIIsssstttt0001110iiiii---- | memh (Rs + #U3:1) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMH__RS____U3_1____RT___ALLOCFRAME___U5_3_; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xe0000a00) { - // Instruction: 14: 11100IIIssssvvvv0000101iiiiiittt | memh (Rs + #U3:1) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMH__RS____U3_1____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 8)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), (st32)hi->ops[3].op.imm, hex_get_sub_regpair(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800fe00) == 0xe0000800) { - // Instruction: 14: 11100IIIssssvvvv0000100iiiiitttt | memh (Rs + #U3:1) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMH__RS____U3_1____RV___MEMW__SP____U5_2____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001200) { - // Instruction: 14: 11100IIIuuuutttt00010010ssssiiii | memh (Ru + #U3:1) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMB__RS____U4_0_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001300) { - // Instruction: 14: 11100IIIuuuutttt00010011ssssiiii | memh (Ru + #U3:1) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMB__RS____U4_0_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001000) { - // Instruction: 14: 11100IIIuuuutttt00010000ssssiiii | memh (Ru + #U3:1) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMW__RS____U4_2_____0; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800ff00) == 0xe0001100) { - // Instruction: 14: 11100IIIuuuutttt00010001ssssiiii | memh (Ru + #U3:1) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RT___MEMW__RS____U4_2_____1; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf800f800) == 0xe0000000) { - // Instruction: 14: 11100IIIuuuuvvvv00000iiisssstttt | memh (Ru + #U3:1) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMH__RU____U3_1____RV___MEMH__RS____U3_1____RT; - hi->op_count = 6; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[5].type = HEX_OP_TYPE_REG; - hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (%s + 0x%x) = %s ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hex_get_sub_reg(hi->ops[3].op.reg), hi->ops[4].op.imm, hex_get_sub_reg(hi->ops[5].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf0001c00) { - // Instruction: 14: 11110000ssssIIII0001110iiiii---- | memw (Rs + #U4:2) = #0 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____0___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf0000a00) { - // Instruction: 14: 11110000ssssIIII0000101iiiiiittt | memw (Rs + #U4:2) = #0 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____0___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf0000800) { - // Instruction: 14: 11110000ssssIIII0000100iiiiitttt | memw (Rs + #U4:2) = #0 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____0___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf1001c00) { - // Instruction: 14: 11110001ssssIIII0001110iiiii---- | memw (Rs + #U4:2) = #1 ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____1___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; allocframe (0x%x)", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf1000a00) { - // Instruction: 14: 11110001ssssIIII0000101iiiiiittt | memw (Rs + #U4:2) = #1 ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____1___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memd (Sp + %d) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00fe00) == 0xf1000800) { - // Instruction: 14: 11110001ssssIIII0000100iiiiitttt | memw (Rs + #U4:2) = #1 ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RS____U4_2_____1___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memw (Sp + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001200) { - // Instruction: 14: 11110000uuuuIIII00010010ssssiiii | memw (Ru + #U4:2) = #0 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001300) { - // Instruction: 14: 11110000uuuuIIII00010011ssssiiii | memw (Ru + #U4:2) = #0 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf0000000) { - // Instruction: 14: 11110000uuuuIIII00000iiisssstttt | memw (Ru + #U4:2) = #0 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001000) { - // Instruction: 14: 11110000uuuuIIII00010000ssssiiii | memw (Ru + #U4:2) = #0 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf0001100) { - // Instruction: 14: 11110000uuuuIIII00010001ssssiiii | memw (Ru + #U4:2) = #0 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____0___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #0 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001200) { - // Instruction: 14: 11110001uuuuIIII00010010ssssiiii | memw (Ru + #U4:2) = #1 ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001300) { - // Instruction: 14: 11110001uuuuIIII00010011ssssiiii | memw (Ru + #U4:2) = #1 ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memb (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00f800) == 0xf1000000) { - // Instruction: 14: 11110001uuuuIIII00000iiisssstttt | memw (Ru + #U4:2) = #1 ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memh (%s + 0x%x) = %s", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001000) { - // Instruction: 14: 11110001uuuuIIII00010000ssssiiii | memw (Ru + #U4:2) = #1 ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #0", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xff00ff00) == 0xf1001100) { - // Instruction: 14: 11110001uuuuIIII00010001ssssiiii | memw (Ru + #U4:2) = #1 ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__RU____U4_2_____1___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (%s + 0x%x) = #1 ; memw (%s + 0x%x) = #1", hex_get_sub_reg(hi->ops[0].op.reg), hi->ops[1].op.imm, hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xe8001c00) { - // Instruction: 14: 1110100IIIIItttt0001110iiiii---- | memw (Sp + #U5:2) = Rt ; allocframe (#u5:3) - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___ALLOCFRAME___U5_3_; - hi->op_count = 3; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; allocframe (0x%x)", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001200) { - // Instruction: 14: 1110100IIIIItttt00010010ssssiiii | memw (Sp + #U5:2) = Rt ; memb (Rs + #u4:0) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMB__RS____U4_0_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memb (%s + 0x%x) = #0", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001300) { - // Instruction: 14: 1110100IIIIItttt00010011ssssiiii | memw (Sp + #U5:2) = Rt ; memb (Rs + #u4:0) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMB__RS____U4_0_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memb (%s + 0x%x) = #1", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001000) { - // Instruction: 14: 1110100IIIIItttt00010000ssssiiii | memw (Sp + #U5:2) = Rt ; memw (Rs + #u4:2) = #0 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMW__RS____U4_2_____0; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memw (%s + 0x%x) = #0", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00ff00) == 0xe8001100) { - // Instruction: 14: 1110100IIIIItttt00010001ssssiiii | memw (Sp + #U5:2) = Rt ; memw (Rs + #u4:2) = #1 - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RT___MEMW__RS____U4_2_____1; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memw (%s + 0x%x) = #1", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xe8000a00) { - // Instruction: 14: 1110100IIIIIvvvv0000101iiiiiittt | memw (Sp + #U5:2) = Rv ; memd (Sp + #s6:3) = Rtt - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RV___MEMD__SP____S6_3____RTT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 8)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memd (Sp + %d) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), (st32)hi->ops[2].op.imm, hex_get_sub_regpair(hi->ops[3].op.reg)); - break; - } - if ((hi_u32 & 0xfe00f800) == 0xe8000000) { - // Instruction: 14: 1110100IIIIIvvvv00000iiisssstttt | memw (Sp + #U5:2) = Rv ; memh (Rs + #u3:1) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RV___MEMH__RS____U3_1____RT; - hi->op_count = 5; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memh (%s + 0x%x) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hex_get_sub_reg(hi->ops[2].op.reg), hi->ops[3].op.imm, hex_get_sub_reg(hi->ops[4].op.reg)); - break; - } - if ((hi_u32 & 0xfe00fe00) == 0xe8000800) { - // Instruction: 14: 1110100IIIIIvvvv0000100iiiiitttt | memw (Sp + #U5:2) = Rv ; memw (Sp + #u5:2) = Rt - hi->instruction = HEX_INS_DUPLEX_MEMW__SP____U5_2____RV___MEMW__SP____U5_2____RT; - hi->op_count = 4; - hi->duplex = true; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rv - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (Sp + 0x%x) = %s ; memw (Sp + 0x%x) = %s", hi->ops[0].op.imm, hex_get_sub_reg(hi->ops[1].op.reg), hi->ops[2].op.imm, hex_get_sub_reg(hi->ops[3].op.reg)); - break; - } - break; - } - } - } else { - switch ((hi_u32 >> 28) & 0xF) { - case 0x0: { - // Handle constant extender - hi->instruction = HEX_INS_IMMEXT; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].attr |= HEX_OP_CONST_EXT; - hi->ops[0].op.imm = ((hi_u32 & 0x3FFF) | (((hi_u32 >> 16) & 0xFFF) << 14)) << 6; - constant_extender = hi->ops[0].op.imm; - sprintf(hi->mnem, "immext(#0x%x)", hi->ops[0].op.imm); - break; - } - case 0x1: { - if ((hi_u32 & 0xfc02300) == 0x1800000) { - // Instruction: 1: 0001000110iissssPP0---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1800100) { - // Instruction: 1: 0001000110iissssPP0---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1800300) { - // Instruction: 1: 0001000110iissssPP0---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1802000) { - // Instruction: 1: 0001000110iissssPP1---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1802100) { - // Instruction: 1: 0001000110iissssPP1---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1802300) { - // Instruction: 1: 0001000110iissssPP1---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c00000) { - // Instruction: 1: 0001000111iissssPP0---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c00100) { - // Instruction: 1: 0001000111iissssPP0---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c00300) { - // Instruction: 1: 0001000111iissssPP0---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c02000) { - // Instruction: 1: 0001000111iissssPP1---00iiiiiii- | p0 = cmp.eq (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, #-1) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c02100) { - // Instruction: 1: 0001000111iissssPP1---01iiiiiii- | p0 = cmp.gt (Rs, #-1) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS____1____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, #-1) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x1c02300) { - // Instruction: 1: 0001000111iissssPP1---11iiiiiii- | p0 = tstbit (Rs, #0) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___TSTBIT__RS___0____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = tstbit (R%d, #0) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x0) { - // Instruction: 1: 0001000000iissssPP0IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000) { - // Instruction: 1: 0001000000iissssPP1IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x400000) { - // Instruction: 1: 0001000001iissssPP0IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x402000) { - // Instruction: 1: 0001000001iissssPP1IIIIIiiiiiii- | p0 = cmp.eq (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, 0x%x) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x800000) { - // Instruction: 1: 0001000010iissssPP0IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x802000) { - // Instruction: 1: 0001000010iissssPP1IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc00000) { - // Instruction: 1: 0001000011iissssPP0IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc02000) { - // Instruction: 1: 0001000011iissssPP1IIIIIiiiiiii- | p0 = cmp.gt (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, 0x%x) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1000000) { - // Instruction: 1: 0001000100iissssPP0IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1002000) { - // Instruction: 1: 0001000100iissssPP1IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1400000) { - // Instruction: 1: 0001000101iissssPP0IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1402000) { - // Instruction: 1: 0001000101iissssPP1IIIIIiiiiiii- | p0 = cmp.gtu (Rs, #U5) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS___U5____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, 0x%x) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3800000) { - // Instruction: 1: 0001001110iissssPP0---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3800100) { - // Instruction: 1: 0001001110iissssPP0---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3800300) { - // Instruction: 1: 0001001110iissssPP0---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3802000) { - // Instruction: 1: 0001001110iissssPP1---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3802100) { - // Instruction: 1: 0001001110iissssPP1---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3802300) { - // Instruction: 1: 0001001110iissssPP1---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c00000) { - // Instruction: 1: 0001001111iissssPP0---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c00100) { - // Instruction: 1: 0001001111iissssPP0---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c00300) { - // Instruction: 1: 0001001111iissssPP0---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c02000) { - // Instruction: 1: 0001001111iissssPP1---00iiiiiii- | p1 = cmp.eq (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, #-1) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c02100) { - // Instruction: 1: 0001001111iissssPP1---01iiiiiii- | p1 = cmp.gt (Rs, #-1) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS____1____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, #-1) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02300) == 0x3c02300) { - // Instruction: 1: 0001001111iissssPP1---11iiiiiii- | p1 = tstbit (Rs, #0) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___TSTBIT__RS___0____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = tstbit (R%d, #0) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000000) { - // Instruction: 1: 0001001000iissssPP0IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2002000) { - // Instruction: 1: 0001001000iissssPP1IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2400000) { - // Instruction: 1: 0001001001iissssPP0IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2402000) { - // Instruction: 1: 0001001001iissssPP1IIIIIiiiiiii- | p1 = cmp.eq (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, 0x%x) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2800000) { - // Instruction: 1: 0001001010iissssPP0IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2802000) { - // Instruction: 1: 0001001010iissssPP1IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2c00000) { - // Instruction: 1: 0001001011iissssPP0IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2c02000) { - // Instruction: 1: 0001001011iissssPP1IIIIIiiiiiii- | p1 = cmp.gt (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, 0x%x) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3000000) { - // Instruction: 1: 0001001100iissssPP0IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3002000) { - // Instruction: 1: 0001001100iissssPP1IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3400000) { - // Instruction: 1: 0001001101iissssPP0IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x3402000) { - // Instruction: 1: 0001001101iissssPP1IIIIIiiiiiii- | p1 = cmp.gtu (Rs, #U5) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS___U5____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, 0x%x) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4000000) { - // Instruction: 1: 0001010000iissssPP00ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4001000) { - // Instruction: 1: 0001010000iissssPP01ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4002000) { - // Instruction: 1: 0001010000iissssPP10ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4003000) { - // Instruction: 1: 0001010000iissssPP11ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4400000) { - // Instruction: 1: 0001010001iissssPP00ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4401000) { - // Instruction: 1: 0001010001iissssPP01ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4402000) { - // Instruction: 1: 0001010001iissssPP10ttttiiiiiii- | p0 = cmp.eq (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_EQ__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.eq (R%d, R%d) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4403000) { - // Instruction: 1: 0001010001iissssPP11ttttiiiiiii- | p1 = cmp.eq (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_EQ__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.eq (R%d, R%d) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4800000) { - // Instruction: 1: 0001010010iissssPP00ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4801000) { - // Instruction: 1: 0001010010iissssPP01ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4802000) { - // Instruction: 1: 0001010010iissssPP10ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4803000) { - // Instruction: 1: 0001010010iissssPP11ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c00000) { - // Instruction: 1: 0001010011iissssPP00ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c01000) { - // Instruction: 1: 0001010011iissssPP01ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c02000) { - // Instruction: 1: 0001010011iissssPP10ttttiiiiiii- | p0 = cmp.gt (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GT__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gt (R%d, R%d) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x4c03000) { - // Instruction: 1: 0001010011iissssPP11ttttiiiiiii- | p1 = cmp.gt (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GT__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gt (R%d, R%d) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5000000) { - // Instruction: 1: 0001010100iissssPP00ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5001000) { - // Instruction: 1: 0001010100iissssPP01ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5002000) { - // Instruction: 1: 0001010100iissssPP10ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF__P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5003000) { - // Instruction: 1: 0001010100iissssPP11ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF__P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5400000) { - // Instruction: 1: 0001010101iissssPP00ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (!p0.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5401000) { - // Instruction: 1: 0001010101iissssPP01ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:nt #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (!p1.new) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5402000) { - // Instruction: 1: 0001010101iissssPP10ttttiiiiiii- | p0 = cmp.gtu (Rs, Rt) ; if (!p0.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P0___CMP_GTU__RS__RT____IF___NOT_P0_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p0 = cmp.gtu (R%d, R%d) ; if (!p0.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc03000) == 0x5403000) { - // Instruction: 1: 0001010101iissssPP11ttttiiiiiii- | p1 = cmp.gtu (Rs, Rt) ; if (!p1.new) jump:t #r9:2 - hi->instruction = HEX_INS_MULT_P1___CMP_GTU__RS__RT____IF___NOT_P1_NEW__JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p1 = cmp.gtu (R%d, R%d) ; if (!p1.new) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x6000000) { - // Instruction: 1: 00010110--iiddddPPIIIIIIiiiiiii- | Rd = #U6 ; jump #r9:2 - hi->instruction = HEX_INS_MULT_RD____U6___JUMP__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = 0x%x ; jump 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x7000000) { - // Instruction: 1: 00010111--iissssPP--ddddiiiiiii- | Rd = Rs ; jump #r9:2 - hi->instruction = HEX_INS_MULT_RD___RS___JUMP__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0xf00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d ; jump 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - break; - } - case 0x2: { - if ((hi_u32 & 0xfc02000) == 0x0) { - // Instruction: 2: 0010000000ii-sssPP0tttttiiiiiii- | if (cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000) { - // Instruction: 2: 0010000000ii-sssPP1tttttiiiiiii- | if (cmp.eq (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x400000) { - // Instruction: 2: 0010000001ii-sssPP0tttttiiiiiii- | if (!cmp.eq (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x402000) { - // Instruction: 2: 0010000001ii-sssPP1tttttiiiiiii- | if (!cmp.eq (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x800000) { - // Instruction: 2: 0010000010ii-sssPP0tttttiiiiiii- | if (cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x802000) { - // Instruction: 2: 0010000010ii-sssPP1tttttiiiiiii- | if (cmp.gt (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc00000) { - // Instruction: 2: 0010000011ii-sssPP0tttttiiiiiii- | if (!cmp.gt (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0xc02000) { - // Instruction: 2: 0010000011ii-sssPP1tttttiiiiiii- | if (!cmp.gt (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1000000) { - // Instruction: 2: 0010000100ii-sssPP0tttttiiiiiii- | if (cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1002000) { - // Instruction: 2: 0010000100ii-sssPP1tttttiiiiiii- | if (cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1400000) { - // Instruction: 2: 0010000101ii-sssPP0tttttiiiiiii- | if (!cmp.gtu (Ns.new, Rt)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1402000) { - // Instruction: 2: 0010000101ii-sssPP1tttttiiiiiii- | if (!cmp.gtu (Ns.new, Rt)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW__RT___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1800000) { - // Instruction: 2: 0010000110ii-sssPP0tttttiiiiiii- | if (cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1802000) { - // Instruction: 2: 0010000110ii-sssPP1tttttiiiiiii- | if (cmp.gt (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1c00000) { - // Instruction: 2: 0010000111ii-sssPP0tttttiiiiiii- | if (!cmp.gt (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x1c02000) { - // Instruction: 2: 0010000111ii-sssPP1tttttiiiiiii- | if (!cmp.gt (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2000000) { - // Instruction: 2: 0010001000ii-sssPP0tttttiiiiiii- | if (cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2002000) { - // Instruction: 2: 0010001000ii-sssPP1tttttiiiiiii- | if (cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2400000) { - // Instruction: 2: 0010001001ii-sssPP0tttttiiiiiii- | if (!cmp.gtu (Rt, Ns.new)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x2402000) { - // Instruction: 2: 0010001001ii-sssPP1tttttiiiiiii- | if (!cmp.gtu (Rt, Ns.new)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__RT__NS_NEW___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, R%d)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.reg, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4000000) { - // Instruction: 2: 0010010000ii-sssPP0IIIIIiiiiiii- | if (cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.eq (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4002000) { - // Instruction: 2: 0010010000ii-sssPP1IIIIIiiiiiii- | if (cmp.eq (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.eq (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4400000) { - // Instruction: 2: 0010010001ii-sssPP0IIIIIiiiiiii- | if (!cmp.eq (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.eq (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4402000) { - // Instruction: 2: 0010010001ii-sssPP1IIIIIiiiiiii- | if (!cmp.eq (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.eq (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4800000) { - // Instruction: 2: 0010010010ii-sssPP0IIIIIiiiiiii- | if (cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.gt (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4802000) { - // Instruction: 2: 0010010010ii-sssPP1IIIIIiiiiiii- | if (cmp.gt (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (cmp.gt (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4c00000) { - // Instruction: 2: 0010010011ii-sssPP0IIIIIiiiiiii- | if (!cmp.gt (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.gt (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x4c02000) { - // Instruction: 2: 0010010011ii-sssPP1IIIIIiiiiiii- | if (!cmp.gt (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (!cmp.gt (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5000000) { - // Instruction: 2: 0010010100ii-sssPP0IIIIIiiiiiii- | if (cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5002000) { - // Instruction: 2: 0010010100ii-sssPP1IIIIIiiiiiii- | if (cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GTU__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gtu (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5400000) { - // Instruction: 2: 0010010101ii-sssPP0IIIIIiiiiiii- | if (!cmp.gtu (Ns.new, #U5)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_NT__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, 0x%x)) jump:nt 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5402000) { - // Instruction: 2: 0010010101ii-sssPP1IIIIIiiiiiii- | if (!cmp.gtu (Ns.new, #U5)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GTU__NS_NEW___U5___JUMP_T__R9_2; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gtu (R%d, 0x%x)) jump:t 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, addr + (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5800000) { - // Instruction: 2: 0010010110ii-sssPP0-----iiiiiii- | if (tstbit (Ns.new, #0)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (tstbit (R%d, #0)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5802000) { - // Instruction: 2: 0010010110ii-sssPP1-----iiiiiii- | if (tstbit (Ns.new, #0)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__TSTBIT__NS_NEW___0___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (tstbit (R%d, #0)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5c00000) { - // Instruction: 2: 0010010111ii-sssPP0-----iiiiiii- | if (!tstbit (Ns.new, #0)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!tstbit (R%d, #0)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x5c02000) { - // Instruction: 2: 0010010111ii-sssPP1-----iiiiiii- | if (!tstbit (Ns.new, #0)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_TSTBIT__NS_NEW___0___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!tstbit (R%d, #0)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6000000) { - // Instruction: 2: 0010011000ii-sssPP0-----iiiiiii- | if (cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6002000) { - // Instruction: 2: 0010011000ii-sssPP1-----iiiiiii- | if (cmp.eq (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_EQ__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.eq (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6400000) { - // Instruction: 2: 0010011001ii-sssPP0-----iiiiiii- | if (!cmp.eq (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6402000) { - // Instruction: 2: 0010011001ii-sssPP1-----iiiiiii- | if (!cmp.eq (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_EQ__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.eq (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6800000) { - // Instruction: 2: 0010011010ii-sssPP0-----iiiiiii- | if (cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6802000) { - // Instruction: 2: 0010011010ii-sssPP1-----iiiiiii- | if (cmp.gt (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF__CMP_GT__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (cmp.gt (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6c00000) { - // Instruction: 2: 0010011011ii-sssPP0-----iiiiiii- | if (!cmp.gt (Ns.new, #-1)) jump:nt #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_NT__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, #-1)) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc02000) == 0x6c02000) { - // Instruction: 2: 0010011011ii-sssPP1-----iiiiiii- | if (!cmp.gt (Ns.new, #-1)) jump:t #r9:2 - hi->instruction = HEX_INS_IF___NOT_CMP_GT__NS_NEW____1___JUMP_T__R9_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns.new - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x300000) >> 13) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (!cmp.gt (R%d, #-1)) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - break; - } - case 0x3: { - if ((hi_u32 & 0xfe00000) == 0xac00000) { - // Instruction: 3: 00111010110sssssPPittttti--ddddd | Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_RDD___MEMD__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc00000) { - // Instruction: 3: 00110000110sssssPPitttttivvddddd | if (Pv) Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1c00000) { - // Instruction: 3: 00110001110sssssPPitttttivvddddd | if !Pv Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2c00000) { - // Instruction: 3: 00110010110sssssPPitttttivvddddd | if (Pv.new) Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3c00000) { - // Instruction: 3: 00110011110sssssPPitttttivvddddd | if !Pv.new Rdd = memd (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RDD___MEMD__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa000000) { - // Instruction: 3: 00111010000sssssPPittttti--ddddd | Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMB__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x0) { - // Instruction: 3: 00110000000sssssPPitttttivvddddd | if (Pv) Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1000000) { - // Instruction: 3: 00110001000sssssPPitttttivvddddd | if !Pv Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2000000) { - // Instruction: 3: 00110010000sssssPPitttttivvddddd | if (Pv.new) Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 3: 00110011000sssssPPitttttivvddddd | if !Pv.new Rd = memb (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memb (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa400000) { - // Instruction: 3: 00111010010sssssPPittttti--ddddd | Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMH__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x400000) { - // Instruction: 3: 00110000010sssssPPitttttivvddddd | if (Pv) Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1400000) { - // Instruction: 3: 00110001010sssssPPitttttivvddddd | if !Pv Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2400000) { - // Instruction: 3: 00110010010sssssPPitttttivvddddd | if (Pv.new) Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3400000) { - // Instruction: 3: 00110011010sssssPPitttttivvddddd | if !Pv.new Rd = memh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa200000) { - // Instruction: 3: 00111010001sssssPPittttti--ddddd | Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMUB__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x200000) { - // Instruction: 3: 00110000001sssssPPitttttivvddddd | if (Pv) Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1200000) { - // Instruction: 3: 00110001001sssssPPitttttivvddddd | if !Pv Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2200000) { - // Instruction: 3: 00110010001sssssPPitttttivvddddd | if (Pv.new) Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3200000) { - // Instruction: 3: 00110011001sssssPPitttttivvddddd | if !Pv.new Rd = memub (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMUB__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memub (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa600000) { - // Instruction: 3: 00111010011sssssPPittttti--ddddd | Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMUH__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x600000) { - // Instruction: 3: 00110000011sssssPPitttttivvddddd | if (Pv) Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1600000) { - // Instruction: 3: 00110001011sssssPPitttttivvddddd | if !Pv Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2600000) { - // Instruction: 3: 00110010011sssssPPitttttivvddddd | if (Pv.new) Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3600000) { - // Instruction: 3: 00110011011sssssPPitttttivvddddd | if !Pv.new Rd = memuh (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMUH__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memuh (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa800000) { - // Instruction: 3: 00111010100sssssPPittttti--ddddd | Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_RD___MEMW__RS___RT_____U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x800000) { - // Instruction: 3: 00110000100sssssPPitttttivvddddd | if (Pv) Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV__RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1800000) { - // Instruction: 3: 00110001100sssssPPitttttivvddddd | if !Pv Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2800000) { - // Instruction: 3: 00110010100sssssPPitttttivvddddd | if (Pv.new) Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__PV_NEW__RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3800000) { - // Instruction: 3: 00110011100sssssPPitttttivvddddd | if !Pv.new Rd = memw (Rs + Rt << #u2) - hi->instruction = HEX_INS_IF__NOT_PV_NEW_RD___MEMW__RS___RT_____U2_; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[4].type = HEX_OP_TYPE_IMM; - hi->ops[4].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new R%d = memw (R%d + R%d << 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg, hi->ops[4].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000000) { - // Instruction: 3: 00111110-00sssssPP0iiiiii00ttttt | memb (Rs + #u6:0) += Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___PLUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) += R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000020) { - // Instruction: 3: 00111110-00sssssPP0iiiiii01ttttt | memb (Rs + #u6:0) -= Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___MINUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) -= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000040) { - // Instruction: 3: 00111110-00sssssPP0iiiiii10ttttt | memb (Rs + #u6:0) &= Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___AND_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) &= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe000060) { - // Instruction: 3: 00111110-00sssssPP0iiiiii11ttttt | memb (Rs + #u6:0) |= Rt - hi->instruction = HEX_INS_MEMB__RS____U6_0___OR_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) |= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000000) { - // Instruction: 3: 00111111-00sssssPP0iiiiii00IIIII | memb (Rs + #u6:0) += #U5 - hi->instruction = HEX_INS_MEMB__RS____U6_0___PLUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) += 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000020) { - // Instruction: 3: 00111111-00sssssPP0iiiiii01IIIII | memb (Rs + #u6:0) -= #U5 - hi->instruction = HEX_INS_MEMB__RS____U6_0___MINUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) -= 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000040) { - // Instruction: 3: 00111111-00sssssPP0iiiiii10IIIII | memb (Rs + #u6:0) = clrbit (#U5) - hi->instruction = HEX_INS_MEMB__RS____U6_0____CLRBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) = clrbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf000060) { - // Instruction: 3: 00111111-00sssssPP0iiiiii11IIIII | memb (Rs + #u6:0) = setbit (#U5) - hi->instruction = HEX_INS_MEMB__RS____U6_0____SETBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + 0x%x) = setbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200000) { - // Instruction: 3: 00111110-01sssssPP0iiiiii00ttttt | memh (Rs + #u6:1) += Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___PLUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) += R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200020) { - // Instruction: 3: 00111110-01sssssPP0iiiiii01ttttt | memh (Rs + #u6:1) -= Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___MINUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) -= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200040) { - // Instruction: 3: 00111110-01sssssPP0iiiiii10ttttt | memh (Rs + #u6:1) &= Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___AND_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) &= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe200060) { - // Instruction: 3: 00111110-01sssssPP0iiiiii11ttttt | memh (Rs + #u6:1) |= Rt - hi->instruction = HEX_INS_MEMH__RS____U6_1___OR_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) |= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200000) { - // Instruction: 3: 00111111-01sssssPP0iiiiii00IIIII | memh (Rs + #u6:1) += #U5 - hi->instruction = HEX_INS_MEMH__RS____U6_1___PLUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) += 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200020) { - // Instruction: 3: 00111111-01sssssPP0iiiiii01IIIII | memh (Rs + #u6:1) -= #U5 - hi->instruction = HEX_INS_MEMH__RS____U6_1___MINUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) -= 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200040) { - // Instruction: 3: 00111111-01sssssPP0iiiiii10IIIII | memh (Rs + #u6:1) = clrbit (#U5) - hi->instruction = HEX_INS_MEMH__RS____U6_1____CLRBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) = clrbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf200060) { - // Instruction: 3: 00111111-01sssssPP0iiiiii11IIIII | memh (Rs + #u6:1) = setbit (#U5) - hi->instruction = HEX_INS_MEMH__RS____U6_1____SETBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + 0x%x) = setbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400000) { - // Instruction: 3: 00111110-10sssssPP0iiiiii00ttttt | memw (Rs + #u6:2) += Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___PLUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) += R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400020) { - // Instruction: 3: 00111110-10sssssPP0iiiiii01ttttt | memw (Rs + #u6:2) -= Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___MINUS_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) -= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400040) { - // Instruction: 3: 00111110-10sssssPP0iiiiii10ttttt | memw (Rs + #u6:2) &= Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___AND_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) &= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xe400060) { - // Instruction: 3: 00111110-10sssssPP0iiiiii11ttttt | memw (Rs + #u6:2) |= Rt - hi->instruction = HEX_INS_MEMW__RS____U6_2___OR_EQ__RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) |= R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400000) { - // Instruction: 3: 00111111-10sssssPP0iiiiii00IIIII | memw (Rs + #u6:2) += #U5 - hi->instruction = HEX_INS_MEMW__RS____U6_2___PLUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) += 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400020) { - // Instruction: 3: 00111111-10sssssPP0iiiiii01IIIII | memw (Rs + #u6:2) -= #U5 - hi->instruction = HEX_INS_MEMW__RS____U6_2___MINUS_EQ___U5; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) -= 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400040) { - // Instruction: 3: 00111111-10sssssPP0iiiiii10IIIII | memw (Rs + #u6:2) = clrbit (#U5) - hi->instruction = HEX_INS_MEMW__RS____U6_2____CLRBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) = clrbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602060) == 0xf400060) { - // Instruction: 3: 00111111-10sssssPP0iiiiii11IIIII | memw (Rs + #u6:2) = setbit (#U5) - hi->instruction = HEX_INS_MEMW__RS____U6_2____SETBIT___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + 0x%x) = setbit (0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xba00000) { - // Instruction: 3: 00111011101sssssPPiuuuuui--00ttt | memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x4a00000) { - // Instruction: 3: 00110100101sssssPPiuuuuuivv00ttt | if (Pv) memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x5a00000) { - // Instruction: 3: 00110101101sssssPPiuuuuuivv00ttt | if !Pv memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x6a00000) { - // Instruction: 3: 00110110101sssssPPiuuuuuivv00ttt | if (Pv.new) memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x7a00000) { - // Instruction: 3: 00110111101sssssPPiuuuuuivv00ttt | if !Pv.new memb (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xba00008) { - // Instruction: 3: 00111011101sssssPPiuuuuui--01ttt | memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x4a00008) { - // Instruction: 3: 00110100101sssssPPiuuuuuivv01ttt | if (Pv) memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x5a00008) { - // Instruction: 3: 00110101101sssssPPiuuuuuivv01ttt | if !Pv memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x6a00008) { - // Instruction: 3: 00110110101sssssPPiuuuuuivv01ttt | if (Pv.new) memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x7a00008) { - // Instruction: 3: 00110111101sssssPPiuuuuuivv01ttt | if !Pv.new memh (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xba00010) { - // Instruction: 3: 00111011101sssssPPiuuuuui--10ttt | memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x4a00010) { - // Instruction: 3: 00110100101sssssPPiuuuuuivv10ttt | if (Pv) memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x5a00010) { - // Instruction: 3: 00110101101sssssPPiuuuuuivv10ttt | if !Pv memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x6a00010) { - // Instruction: 3: 00110110101sssssPPiuuuuuivv10ttt | if (Pv.new) memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0x7a00010) { - // Instruction: 3: 00110111101sssssPPiuuuuuivv10ttt | if !Pv.new memw (Rs + Ru << #u2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS___RU_____U2____NT_NEW; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xbc00000) { - // Instruction: 3: 00111011110sssssPPiuuuuui--ttttt | memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_MEMD__RS___RU_____U2____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4c00000) { - // Instruction: 3: 00110100110sssssPPiuuuuuivvttttt | if (Pv) memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5c00000) { - // Instruction: 3: 00110101110sssssPPiuuuuuivvttttt | if !Pv memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6c00000) { - // Instruction: 3: 00110110110sssssPPiuuuuuivvttttt | if (Pv.new) memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7c00000) { - // Instruction: 3: 00110111110sssssPPiuuuuuivvttttt | if !Pv.new memd (Rs + Ru << #u2) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD__RS___RU_____U2____RTT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].attr |= HEX_OP_REG_PAIR; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memd (R%d + R%d << 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg + 1, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb000000) { - // Instruction: 3: 00111011000sssssPPiuuuuui--ttttt | memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_MEMB__RS___RU_____U2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe600000) == 0xc000000) { - // Instruction: 3: 0011110--00sssssPPIiiiiiiIIIIIII | memb (Rs + #u6:0) = #S8 - hi->instruction = HEX_INS_MEMB__RS____U6_0_____S8; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0x7f) >> 0)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d + 0x%x) = %d", hi->ops[0].op.reg, hi->ops[1].op.imm, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4000000) { - // Instruction: 3: 00110100000sssssPPiuuuuuivvttttt | if (Pv) memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5000000) { - // Instruction: 3: 00110101000sssssPPiuuuuuivvttttt | if !Pv memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 3: 00110110000sssssPPiuuuuuivvttttt | if (Pv.new) memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7000000) { - // Instruction: 3: 00110111000sssssPPiuuuuuivvttttt | if !Pv.new memb (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8000000) { - // Instruction: 3: 00111000000sssssPPIiiiiiivvIIIII | if (Pv) memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__PV__MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8800000) { - // Instruction: 3: 00111000100sssssPPIiiiiiivvIIIII | if !Pv memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9000000) { - // Instruction: 3: 00111001000sssssPPIiiiiiivvIIIII | if (Pv.new) memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9800000) { - // Instruction: 3: 00111001100sssssPPIiiiiiivvIIIII | if !Pv.new memb (Rs + #u6:0) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS____U6_0_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb400000) { - // Instruction: 3: 00111011010sssssPPiuuuuui--ttttt | memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_MEMH__RS___RU_____U2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb600000) { - // Instruction: 3: 00111011011sssssPPiuuuuui--ttttt | memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_MEMH__RS___RU_____U2____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe600000) == 0xc200000) { - // Instruction: 3: 0011110--01sssssPPIiiiiiiIIIIIII | memh (Rs + #u6:1) = #S8 - hi->instruction = HEX_INS_MEMH__RS____U6_1_____S8; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0x7f) >> 0)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 1); - sprintf(hi->mnem, "memh (R%d + 0x%x) = %d", hi->ops[0].op.reg, hi->ops[1].op.imm, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4400000) { - // Instruction: 3: 00110100010sssssPPiuuuuuivvttttt | if (Pv) memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4600000) { - // Instruction: 3: 00110100011sssssPPiuuuuuivvttttt | if (Pv) memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5400000) { - // Instruction: 3: 00110101010sssssPPiuuuuuivvttttt | if !Pv memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5600000) { - // Instruction: 3: 00110101011sssssPPiuuuuuivvttttt | if !Pv memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6400000) { - // Instruction: 3: 00110110010sssssPPiuuuuuivvttttt | if (Pv.new) memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 3: 00110110011sssssPPiuuuuuivvttttt | if (Pv.new) memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7400000) { - // Instruction: 3: 00110111010sssssPPiuuuuuivvttttt | if !Pv.new memh (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7600000) { - // Instruction: 3: 00110111011sssssPPiuuuuuivvttttt | if !Pv.new memh (Rs + Ru << #u2) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS___RU_____U2____RT_H; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + R%d << 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8200000) { - // Instruction: 3: 00111000001sssssPPIiiiiiivvIIIII | if (Pv) memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8a00000) { - // Instruction: 3: 00111000101sssssPPIiiiiiivvIIIII | if !Pv memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9200000) { - // Instruction: 3: 00111001001sssssPPIiiiiiivvIIIII | if (Pv.new) memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9a00000) { - // Instruction: 3: 00111001101sssssPPIiiiiiivvIIIII | if !Pv.new memh (Rs + #u6:1) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xb800000) { - // Instruction: 3: 00111011100sssssPPiuuuuui--ttttt | memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_MEMW__RS___RU_____U2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe600000) == 0xc400000) { - // Instruction: 3: 0011110--10sssssPPIiiiiiiIIIIIII | memw (Rs + #u6:2) = #S8 - hi->instruction = HEX_INS_MEMW__RS____U6_2_____S8; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0x7f) >> 0)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "memw (R%d + 0x%x) = %d", hi->ops[0].op.reg, hi->ops[1].op.imm, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4800000) { - // Instruction: 3: 00110100100sssssPPiuuuuuivvttttt | if (Pv) memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5800000) { - // Instruction: 3: 00110101100sssssPPiuuuuuivvttttt | if !Pv memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6800000) { - // Instruction: 3: 00110110100sssssPPiuuuuuivvttttt | if (Pv.new) memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7800000) { - // Instruction: 3: 00110111100sssssPPiuuuuuivvttttt | if !Pv.new memw (Rs + Ru << #u2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS___RU_____U2____RT; - hi->op_count = 5; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[4].type = HEX_OP_TYPE_REG; - hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + R%d << 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm, hi->ops[4].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8400000) { - // Instruction: 3: 00111000010sssssPPIiiiiiivvIIIII | if (Pv) memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__PV__MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8c00000) { - // Instruction: 3: 00111000110sssssPPIiiiiiivvIIIII | if !Pv memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9400000) { - // Instruction: 3: 00111001010sssssPPIiiiiiivvIIIII | if (Pv.new) memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9c00000) { - // Instruction: 3: 00111001110sssssPPIiiiiiivvIIIII | if !Pv.new memw (Rs + #u6:2) = #S6 - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS____U6_2_____S6; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0x1f) >> 0)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + 0x%x) = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - break; - } - case 0x4: { - if ((hi_u32 & 0x9e00000) == 0x9c00000) { - // Instruction: 4: 01001ii1110iiiiiPPiiiiiiiiiddddd | Rdd = memd (gp + #u16:3) - hi->instruction = HEX_INS_RDD___MEMD__GP____U16_3_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (gp + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1c00000) { - // Instruction: 4: 01000001110sssssPP0ttiiiiiiddddd | if (Pt) Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__PT__RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3c00000) { - // Instruction: 4: 01000011110sssssPP0ttiiiiiiddddd | if (Pt.new) Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__PT_NEW__RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5c00000) { - // Instruction: 4: 01000101110sssssPP0ttiiiiiiddddd | if !Pt Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__NOT_PT_RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7c00000) { - // Instruction: 4: 01000111110sssssPP0ttiiiiiiddddd | if !Pt.new Rdd = memd (Rs + #u6:3) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RDD___MEMD__RS____U6_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 3); - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9000000) { - // Instruction: 4: 01001ii1000iiiiiPPiiiiiiiiiddddd | Rd = memb (gp + #u16:0) - hi->instruction = HEX_INS_RD___MEMB__GP____U16_0_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1000000) { - // Instruction: 4: 01000001000sssssPP0ttiiiiiiddddd | if (Pt) Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d) R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3000000) { - // Instruction: 4: 01000011000sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d.new) R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5000000) { - // Instruction: 4: 01000101000sssssPP0ttiiiiiiddddd | if !Pt Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7000000) { - // Instruction: 4: 01000111000sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memb (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d.new R%d = memb (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9400000) { - // Instruction: 4: 01001ii1010iiiiiPPiiiiiiiiiddddd | Rd = memh (gp + #u16:1) - hi->instruction = HEX_INS_RD___MEMH__GP____U16_1_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1400000) { - // Instruction: 4: 01000001010sssssPP0ttiiiiiiddddd | if (Pt) Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT__RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d) R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3400000) { - // Instruction: 4: 01000011010sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d.new) R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5400000) { - // Instruction: 4: 01000101010sssssPP0ttiiiiiiddddd | if !Pt Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7400000) { - // Instruction: 4: 01000111010sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d.new R%d = memh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9200000) { - // Instruction: 4: 01001ii1001iiiiiPPiiiiiiiiiddddd | Rd = memub (gp + #u16:0) - hi->instruction = HEX_INS_RD___MEMUB__GP____U16_0_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1200000) { - // Instruction: 4: 01000001001sssssPP0ttiiiiiiddddd | if (Pt) Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d) R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3200000) { - // Instruction: 4: 01000011001sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d.new) R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5200000) { - // Instruction: 4: 01000101001sssssPP0ttiiiiiiddddd | if !Pt Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7200000) { - // Instruction: 4: 01000111001sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memub (Rs + #u6:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUB__RS____U6_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d.new R%d = memub (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9600000) { - // Instruction: 4: 01001ii1011iiiiiPPiiiiiiiiiddddd | Rd = memuh (gp + #u16:1) - hi->instruction = HEX_INS_RD___MEMUH__GP____U16_1_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1600000) { - // Instruction: 4: 01000001011sssssPP0ttiiiiiiddddd | if (Pt) Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT__RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d) R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3600000) { - // Instruction: 4: 01000011011sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5600000) { - // Instruction: 4: 01000101011sssssPP0ttiiiiiiddddd | if !Pt Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7600000) { - // Instruction: 4: 01000111011sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memuh (Rs + #u6:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUH__RS____U6_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 1); - sprintf(hi->mnem, "if !P%d.new R%d = memuh (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x9800000) { - // Instruction: 4: 01001ii1100iiiiiPPiiiiiiiiiddddd | Rd = memw (gp + #u16:2) - hi->instruction = HEX_INS_RD___MEMW__GP____U16_2_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "R%d = memw (gp + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x1800000) { - // Instruction: 4: 01000001100sssssPP0ttiiiiiiddddd | if (Pt) Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__PT__RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if (P%d) R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x3800000) { - // Instruction: 4: 01000011100sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if (P%d.new) R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5800000) { - // Instruction: 4: 01000101100sssssPP0ttiiiiiiddddd | if !Pt Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if !P%d R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x7800000) { - // Instruction: 4: 01000111100sssssPP0ttiiiiiiddddd | if !Pt.new Rd = memw (Rs + #u6:2) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMW__RS____U6_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x1800) >> 11); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend_off(&hi->ops[3], 2); - sprintf(hi->mnem, "if !P%d.new R%d = memw (R%d + 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0x9e01800) == 0x8a00000) { - // Instruction: 4: 01001ii0101iiiiiPPi00tttiiiiiiii | memb (gp + #u16:0) = Nt.new - hi->instruction = HEX_INS_MEMB__GP____U16_0____NT_NEW; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[0]); - sprintf(hi->mnem, "memb (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0xa00000) { - // Instruction: 4: 01000000101sssssPPi00tttiiiii0vv | if (Pv) memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x2a00000) { - // Instruction: 4: 01000010101sssssPPi00tttiiiii0vv | if (Pv.new) memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x4a00000) { - // Instruction: 4: 01000100101sssssPPi00tttiiiii0vv | if !Pv memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x6a00000) { - // Instruction: 4: 01000110101sssssPPi00tttiiiii0vv | if !Pv.new memb (Rs + #u6:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS____U6_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x8a00800) { - // Instruction: 4: 01001ii0101iiiiiPPi01tttiiiiiiii | memh (gp + #u16:1) = Nt.new - hi->instruction = HEX_INS_MEMH__GP____U16_1____NT_NEW; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0xa00800) { - // Instruction: 4: 01000000101sssssPPi01tttiiiii0vv | if (Pv) memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x2a00800) { - // Instruction: 4: 01000010101sssssPPi01tttiiiii0vv | if (Pv.new) memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x4a00800) { - // Instruction: 4: 01000100101sssssPPi01tttiiiii0vv | if !Pv memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x6a00800) { - // Instruction: 4: 01000110101sssssPPi01tttiiiii0vv | if !Pv.new memh (Rs + #u6:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x8a01000) { - // Instruction: 4: 01001ii0101iiiiiPPi10tttiiiiiiii | memw (gp + #u16:2) = Nt.new - hi->instruction = HEX_INS_MEMW__GP____U16_2____NT_NEW; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0xa01000) { - // Instruction: 4: 01000000101sssssPPi10tttiiiii0vv | if (Pv) memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x2a01000) { - // Instruction: 4: 01000010101sssssPPi10tttiiiii0vv | if (Pv.new) memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x4a01000) { - // Instruction: 4: 01000100101sssssPPi10tttiiiii0vv | if !Pv memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01804) == 0x6a01000) { - // Instruction: 4: 01000110101sssssPPi10tttiiiii0vv | if !Pv.new memw (Rs + #u6:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS____U6_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8c00000) { - // Instruction: 4: 01001ii0110iiiiiPPitttttiiiiiiii | memd (gp + #u16:3) = Rtt - hi->instruction = HEX_INS_MEMD__GP____U16_3____RTT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 3; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (gp + 0x%x) = R%d:R%d", hi->ops[0].op.imm, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0xc00000) { - // Instruction: 4: 01000000110sssssPPitttttiiiii0vv | if (Pv) memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if (P%d) memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2c00000) { - // Instruction: 4: 01000010110sssssPPitttttiiiii0vv | if (Pv.new) memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if (P%d.new) memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4c00000) { - // Instruction: 4: 01000100110sssssPPitttttiiiii0vv | if !Pv memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if !P%d memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6c00000) { - // Instruction: 4: 01000110110sssssPPitttttiiiii0vv | if !Pv.new memd (Rs + #u6:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD__RS____U6_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 3; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "if !P%d.new memd (R%d + 0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8000000) { - // Instruction: 4: 01001ii0000iiiiiPPitttttiiiiiiii | memb (gp + #u16:0) = Rt - hi->instruction = HEX_INS_MEMB__GP____U16_0____RT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[0]); - sprintf(hi->mnem, "memb (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x0) { - // Instruction: 4: 01000000000sssssPPitttttiiiii0vv | if (Pv) memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2000000) { - // Instruction: 4: 01000010000sssssPPitttttiiiii0vv | if (Pv.new) memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4000000) { - // Instruction: 4: 01000100000sssssPPitttttiiiii0vv | if !Pv memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6000000) { - // Instruction: 4: 01000110000sssssPPitttttiiiii0vv | if !Pv.new memb (Rs + #u6:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RS____U6_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new memb (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8400000) { - // Instruction: 4: 01001ii0010iiiiiPPitttttiiiiiiii | memh (gp + #u16:1) = Rt - hi->instruction = HEX_INS_MEMH__GP____U16_1____RT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8600000) { - // Instruction: 4: 01001ii0011iiiiiPPitttttiiiiiiii | memh (gp + #u16:1) = Rt.H - hi->instruction = HEX_INS_MEMH__GP____U16_1____RT_H; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (gp + 0x%x) = R%d.H", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x400000) { - // Instruction: 4: 01000000010sssssPPitttttiiiii0vv | if (Pv) memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x600000) { - // Instruction: 4: 01000000011sssssPPitttttiiiii0vv | if (Pv) memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2400000) { - // Instruction: 4: 01000010010sssssPPitttttiiiii0vv | if (Pv.new) memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2600000) { - // Instruction: 4: 01000010011sssssPPitttttiiiii0vv | if (Pv.new) memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4400000) { - // Instruction: 4: 01000100010sssssPPitttttiiiii0vv | if !Pv memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4600000) { - // Instruction: 4: 01000100011sssssPPitttttiiiii0vv | if !Pv memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6400000) { - // Instruction: 4: 01000110010sssssPPitttttiiiii0vv | if !Pv.new memh (Rs + #u6:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6600000) { - // Instruction: 4: 01000110011sssssPPitttttiiiii0vv | if !Pv.new memh (Rs + #u6:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RS____U6_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 1; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d + 0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x8800000) { - // Instruction: 4: 01001ii0100iiiiiPPitttttiiiiiiii | memw (gp + #u16:2) = Rt - hi->instruction = HEX_INS_MEMW__GP____U16_2____RT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x6000000) >> 11) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (gp + 0x%x) = R%d", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x800000) { - // Instruction: 4: 01000000100sssssPPitttttiiiii0vv | if (Pv) memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (P%d) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x2800000) { - // Instruction: 4: 01000010100sssssPPitttttiiiii0vv | if (Pv.new) memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if (P%d.new) memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x4800000) { - // Instruction: 4: 01000100100sssssPPitttttiiiii0vv | if !Pv memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if !P%d memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00004) == 0x6800000) { - // Instruction: 4: 01000110100sssssPPitttttiiiii0vv | if !Pv.new memw (Rs + #u6:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RS____U6_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 8) | ((hi_u32 & 0xf8) >> 3)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "if !P%d.new memw (R%d + 0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - break; - } - case 0x5: { - if ((hi_u32 & 0xfe00000) == 0xa00000) { - // Instruction: 5: 01010000101sssssPP-------------- | callr Rs - hi->instruction = HEX_INS_CALLR_RS; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "callr R%d", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1000000) { - // Instruction: 5: 01010001000sssssPP----uu-------- | if (Pu) callr Rs - hi->instruction = HEX_INS_IF__PU__CALLR_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) callr R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1200000) { - // Instruction: 5: 01010001001sssssPP----uu-------- | if !Pu callr Rs - hi->instruction = HEX_INS_IF__NOT_PU_CALLR_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d callr R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2a00000) { - // Instruction: 5: 01010010101sssssPP-------------- | hintjr (Rs) - hi->instruction = HEX_INS_HINTJR__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "hintjr (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2800000) { - // Instruction: 5: 01010010100sssssPP-------------- | jumpr Rs - hi->instruction = HEX_INS_JUMPR_RS; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "jumpr R%d", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3400000) { - // Instruction: 5: 01010011010sssssPP-00-uu-------- | if (Pu) jumpr:nt Rs - hi->instruction = HEX_INS_IF__PU__JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3400800) { - // Instruction: 5: 01010011010sssssPP-01-uu-------- | if (Pu.new) jumpr:nt Rs - hi->instruction = HEX_INS_IF__PU_NEW__JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3401000) { - // Instruction: 5: 01010011010sssssPP-10-uu-------- | if (Pu) jumpr:t Rs - hi->instruction = HEX_INS_IF__PU__JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3401800) { - // Instruction: 5: 01010011010sssssPP-11-uu-------- | if (Pu.new) jumpr:t Rs - hi->instruction = HEX_INS_IF__PU_NEW__JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3600000) { - // Instruction: 5: 01010011011sssssPP-00-uu-------- | if !Pu jumpr:nt Rs - hi->instruction = HEX_INS_IF__NOT_PU_JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3600800) { - // Instruction: 5: 01010011011sssssPP-01-uu-------- | if !Pu.new jumpr:nt Rs - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMPR_NT_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jumpr:nt R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3601000) { - // Instruction: 5: 01010011011sssssPP-10-uu-------- | if !Pu jumpr:t Rs - hi->instruction = HEX_INS_IF__NOT_PU_JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe01800) == 0x3601800) { - // Instruction: 5: 01010011011sssssPP-11-uu-------- | if !Pu.new jumpr:t Rs - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMPR_T_RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jumpr:t R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xe000001) == 0xa000000) { - // Instruction: 5: 0101101iiiiiiiiiPPiiiiiiiiiiiii0 | call #r22:2 - hi->instruction = HEX_INS_CALL__R22_2; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 23)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 23); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "call 0x%x", addr + (st32)hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xf200800) == 0xd000000) { - // Instruction: 5: 01011101ii0iiiiiPPi-0-uuiiiiiii- | if (Pu) call #r15:2 - hi->instruction = HEX_INS_IF__PU__CALL__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "if (P%d) call 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf200800) == 0xd200000) { - // Instruction: 5: 01011101ii1iiiiiPPi-0-uuiiiiiii- | if !Pu call #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_CALL__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "if !P%d call 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xe000000) == 0x8000000) { - // Instruction: 5: 0101100iiiiiiiiiPPiiiiiiiiiiiii- | jump #r22:2 - hi->instruction = HEX_INS_JUMP__R22_2; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 23)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 23); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "jump 0x%x", addr + (st32)hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc000000) { - // Instruction: 5: 01011100ii0iiiiiPPi00-uuiiiiiii- | if (Pu) jump:nt #r15:2 - hi->instruction = HEX_INS_IF__PU__JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc001000) { - // Instruction: 5: 01011100ii0iiiiiPPi10-uuiiiiiii- | if (Pu) jump:t #r15:2 - hi->instruction = HEX_INS_IF__PU__JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) jump:t 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc200000) { - // Instruction: 5: 01011100ii1iiiiiPPi00-uuiiiiiii- | if !Pu jump:nt #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc201000) { - // Instruction: 5: 01011100ii1iiiiiPPi10-uuiiiiiii- | if !Pu jump:t #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d jump:t 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc000800) { - // Instruction: 5: 01011100ii0iiiiiPPi01-uuiiiiiii- | if (Pu.new) jump:nt #r15:2 - hi->instruction = HEX_INS_IF__PU_NEW__JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc001800) { - // Instruction: 5: 01011100ii0iiiiiPPi11-uuiiiiiii- | if (Pu.new) jump:t #r15:2 - hi->instruction = HEX_INS_IF__PU_NEW__JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) jump:t 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc200800) { - // Instruction: 5: 01011100ii1iiiiiPPi01-uuiiiiiii- | if !Pu.new jump:nt #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMP_NT__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jump:nt 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf201800) == 0xc201800) { - // Instruction: 5: 01011100ii1iiiiiPPi11-uuiiiiiii- | if !Pu.new jump:t #r15:2 - hi->instruction = HEX_INS_IF__NOT_PU_NEW_JUMP_T__R15_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 9) | ((hi_u32 & 0x1f0000) >> 8) | ((hi_u32 & 0x2000) >> 6) | ((hi_u32 & 0xfe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 16)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 16); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new jump:t 0x%x", hi->ops[0].op.pred, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5a00000) { - // Instruction: 5: 01010101101sssssPP---------ddddd | Rd = icdatar (Rs) - hi->instruction = HEX_INS_RD___ICDATAR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = icdatar (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5e00000) { - // Instruction: 5: 01010101111sssssPP---------ddddd | Rd = ictagr (Rs) - hi->instruction = HEX_INS_RD___ICTAGR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ictagr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0x6c00800) { - // Instruction: 5: 01010110110sssssPP001----------- | icinvidx (Rs) - hi->instruction = HEX_INS_ICINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "icinvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5c00000) { - // Instruction: 5: 01010101110sssssPP-ttttt-------- | ictagw (Rs, Rt) - hi->instruction = HEX_INS_ICTAGW__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "ictagw (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0x6c01000) { - // Instruction: 5: 01010110110-----PP010----------- | ickill - hi->instruction = HEX_INS_ICKILL; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "ickill"); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x7e00000) { - // Instruction: 5: 01010111111-----PP00----000----- | rte - hi->instruction = HEX_INS_RTE; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "rte"); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x7e01000) { - // Instruction: 5: 01010111111-----PP01----000----- | rteunlock - hi->instruction = HEX_INS_RTEUNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "rteunlock"); - break; - } - if ((hi_u32 & 0xfe03800) == 0x6c00000) { - // Instruction: 5: 01010110110sssssPP000----------- | icinva (Rs) - hi->instruction = HEX_INS_ICINVA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "icinva (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfff23ff) == 0x7c00002) { - // Instruction: 5: 0101011111000000PP0---0000000010 | isync - hi->instruction = HEX_INS_ISYNC; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "isync"); - break; - } - if ((hi_u32 & 0xfc00000) == 0x4400000) { - // Instruction: 5: 0101010001------PP-iiiii---iii-- | pause (#u8) - hi->instruction = HEX_INS_PAUSE___U8_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 5) | ((hi_u32 & 0x1c) >> 2)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "pause (0x%x)", hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x4000000) { - // Instruction: 5: 0101010000------PP-iiiii---iii-- | trap0 (#u8) - hi->instruction = HEX_INS_TRAP0___U8_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 5) | ((hi_u32 & 0x1c) >> 2)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "trap0 (0x%x)", hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x4800000) { - // Instruction: 5: 0101010010------PP-iiiii---iii-- | trap1 (#u8) - hi->instruction = HEX_INS_TRAP1___U8_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 5) | ((hi_u32 & 0x1c) >> 2)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "trap1 (0x%x)", hi->ops[0].op.imm); - break; - } - break; - } - case 0x6: { - if ((hi_u32 & 0xff02090) == 0xb002090) { - // Instruction: 6: 011010110000--ssPP1---tt1--1--dd | Pd = fastcorner9 (Ps, Pt) - hi->instruction = HEX_INS_PD___FASTCORNER9__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = fastcorner9 (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02090) == 0xb102090) { - // Instruction: 6: 011010110001--ssPP1---tt1--1--dd | Pd = !fastcorner9 (Ps, Pt) - hi->instruction = HEX_INS_PD____NOT_FASTCORNER9__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !fastcorner9 (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb800000) { - // Instruction: 6: 011010111000--ssPP0-----------dd | Pd = any8 (Ps) - hi->instruction = HEX_INS_PD___ANY8__PS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = any8 (P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xba00000) { - // Instruction: 6: 011010111010--ssPP0-----------dd | Pd = all8 (Ps) - hi->instruction = HEX_INS_PD___ALL8__PS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = all8 (P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x0) { - // Instruction: 6: 01100000000sssssPP-iiiii---ii--- | loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x200000) { - // Instruction: 6: 01100000001sssssPP-iiiii---ii--- | loop1 (#r7:2, Rs) - hi->instruction = HEX_INS_LOOP1___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop1 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9000000) { - // Instruction: 6: 01101001000IIIIIPP-iiiiiIIIii-II | loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9200000) { - // Instruction: 6: 01101001001IIIIIPP-iiiiiIIIii-II | loop1 (#r7:2, #U10) - hi->instruction = HEX_INS_LOOP1___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[0], 2); - sprintf(hi->mnem, "loop1 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfff0000) == 0xa490000) { - // Instruction: 6: 0110101001001001PP-iiiiii--ddddd | Rd = add (pc, #u6) - hi->instruction = HEX_INS_RD___ADD__PC___U6_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = add (pc, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa00000) { - // Instruction: 6: 01100000101sssssPP-iiiii---ii--- | p3 = sp1loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_P3___SP1LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp1loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc00000) { - // Instruction: 6: 01100000110sssssPP-iiiii---ii--- | p3 = sp2loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_P3___SP2LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp2loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xe00000) { - // Instruction: 6: 01100000111sssssPP-iiiii---ii--- | p3 = sp3loop0 (#r7:2, Rs) - hi->instruction = HEX_INS_P3___SP3LOOP0___R7_2__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp3loop0 (0x%x, R%d)", hi->ops[0].op.imm, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9a00000) { - // Instruction: 6: 01101001101IIIIIPP-iiiiiIIIii-II | p3 = sp1loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_P3___SP1LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp1loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9c00000) { - // Instruction: 6: 01101001110IIIIIPP-iiiiiIIIii-II | p3 = sp2loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_P3___SP2LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp2loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x9e00000) { - // Instruction: 6: 01101001111IIIIIPP-iiiiiIIIii-II | p3 = sp3loop0 (#r7:2, #U10) - hi->instruction = HEX_INS_P3___SP3LOOP0___R7_2___U10_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32 & 0x1f00) >> 6) | ((hi_u32 & 0x18) >> 3)) << 2; // scaled - if (hi->ops[0].op.imm & (1 << 8)) { - hi->ops[0].op.imm |= (0xFFFFFFFF << 8); - } - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 11) | ((hi_u32 & 0xe0) >> 3) | ((hi_u32 & 0x3) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "p3 = sp3loop0 (0x%x, 0x%x)", hi->ops[0].op.imm, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xff02000) == 0xb000000) { - // Instruction: 6: 011010110000--ssPP0---tt------dd | Pd = and (Pt, Ps) - hi->instruction = HEX_INS_PD___AND__PT__PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb100000) { - // Instruction: 6: 011010110001--ssPP0---ttuu----dd | Pd = and (Ps, and (Pt, Pu)) - hi->instruction = HEX_INS_PD___AND__PS__AND__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, and (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb200000) { - // Instruction: 6: 011010110010--ssPP0---tt------dd | Pd = or (Pt, Ps) - hi->instruction = HEX_INS_PD___OR__PT__PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb300000) { - // Instruction: 6: 011010110011--ssPP0---ttuu----dd | Pd = and (Ps, or (Pt, Pu)) - hi->instruction = HEX_INS_PD___AND__PS__OR__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, or (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb400000) { - // Instruction: 6: 011010110100--ssPP0---tt------dd | Pd = xor (Ps, Pt) - hi->instruction = HEX_INS_PD___XOR__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = xor (P%d, P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb500000) { - // Instruction: 6: 011010110101--ssPP0---ttuu----dd | Pd = or (Ps, and (Pt, Pu)) - hi->instruction = HEX_INS_PD___OR__PS__AND__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, and (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb600000) { - // Instruction: 6: 011010110110--ssPP0---tt------dd | Pd = and (Pt, !Ps) - hi->instruction = HEX_INS_PD___AND__PT___NOT_PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, !P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb700000) { - // Instruction: 6: 011010110111--ssPP0---ttuu----dd | Pd = or (Ps, or (Pt, Pu)) - hi->instruction = HEX_INS_PD___OR__PS__OR__PT__PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, or (P%d, P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xb900000) { - // Instruction: 6: 011010111001--ssPP0---ttuu----dd | Pd = and (Ps, and (Pt, !Pu)) - hi->instruction = HEX_INS_PD___AND__PS__AND__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, and (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbb00000) { - // Instruction: 6: 011010111011--ssPP0---ttuu----dd | Pd = and (Ps, or (Pt, !Pu)) - hi->instruction = HEX_INS_PD___AND__PS__OR__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = and (P%d, or (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbc00000) { - // Instruction: 6: 011010111100--ssPP0-----------dd | Pd = not (Ps) - hi->instruction = HEX_INS_PD___NOT__PS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = not (P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbd00000) { - // Instruction: 6: 011010111101--ssPP0---ttuu----dd | Pd = or (Ps, and (Pt, !Pu)) - hi->instruction = HEX_INS_PD___OR__PS__AND__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, and (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbe00000) { - // Instruction: 6: 011010111110--ssPP0---tt------dd | Pd = or (Pt, !Ps) - hi->instruction = HEX_INS_PD___OR__PT___NOT_PS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, !P%d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xff02000) == 0xbf00000) { - // Instruction: 6: 011010111111--ssPP0---ttuu----dd | Pd = or (Ps, or (Pt, !Pu)) - hi->instruction = HEX_INS_PD___OR__PS__OR__PT___NOT_PU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0xc0) >> 6); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = or (P%d, or (P%d, !P%d))", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.pred, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2200000) { - // Instruction: 6: 01100010001sssssPP---------ddddd | Cd = Rs - hi->instruction = HEX_INS_CD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_CONTROL; - hi->ops[0].op.cr = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = R%d", hex_get_cntl_reg(hi->ops[0].op.cr), hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3200000) { - // Instruction: 6: 01100011001sssssPP---------ddddd | Cdd = Rss - hi->instruction = HEX_INS_CDD___RSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_CONTROL; - hi->ops[0].op.cr = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%sd = R%d:R%d", hex_get_cntl_reg(hi->ops[0].op.cr), hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8000000) { - // Instruction: 6: 01101000000sssssPP---------ddddd | Rdd = Css - hi->instruction = HEX_INS_RDD___CSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_CONTROL; - hi->ops[1].op.cr = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = %ss", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hex_get_cntl_reg(hi->ops[1].op.cr)); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa000000) { - // Instruction: 6: 01101010000sssssPP---------ddddd | Rd = Cs - hi->instruction = HEX_INS_RD___CS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_CONTROL; - hi->ops[1].op.cr = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = %s", hi->ops[0].op.reg, hex_get_cntl_reg(hi->ops[1].op.cr)); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1000000) { - // Instruction: 6: 0110000100isssssPPi0iiiiiiiiiii- | if (Rs != #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS__NOT____0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d != #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1001000) { - // Instruction: 6: 0110000100isssssPPi1iiiiiiiiiii- | if (Rs != #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS__NOT____0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d != #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1400000) { - // Instruction: 6: 0110000101isssssPPi0iiiiiiiiiii- | if (Rs> = #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS_GT_EQ___0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d> = #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1401000) { - // Instruction: 6: 0110000101isssssPPi1iiiiiiiiiii- | if (Rs> = #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS_GT_EQ___0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d> = #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1800000) { - // Instruction: 6: 0110000110isssssPPi0iiiiiiiiiii- | if (Rs == #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS__EQ___0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d == #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1801000) { - // Instruction: 6: 0110000110isssssPPi1iiiiiiiiiii- | if (Rs == #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS__EQ___0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d == #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1c00000) { - // Instruction: 6: 0110000111isssssPPi0iiiiiiiiiii- | if (Rs< = #0) jump:nt #r13:2 - hi->instruction = HEX_INS_IF__RS_LT_EQ___0__JUMP_NT__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d< = #0) jump:nt 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc01000) == 0x1c01000) { - // Instruction: 6: 0110000111isssssPPi1iiiiiiiiiii- | if (Rs< = #0) jump:t #r13:2 - hi->instruction = HEX_INS_IF__RS_LT_EQ___0__JUMP_T__R13_2; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 9) | ((hi_u32 & 0x2000) >> 2) | ((hi_u32 & 0xffe) >> 1)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 14)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 14); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (R%d< = #0) jump:t 0x%x", hi->ops[0].op.reg, addr + (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2000000) { - // Instruction: 6: 01100010000sssssPP---------ddddd | Gd = Rs - hi->instruction = HEX_INS_GD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Gd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 6: 01100011000sssssPP---------ddddd | Gdd = Rss - hi->instruction = HEX_INS_GDD___RSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Gd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%dd = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8200000) { - // Instruction: 6: 01101000001sssssPP---------ddddd | Rdd = Gss - hi->instruction = HEX_INS_RDD___GSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Gs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = R%ds", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa200000) { - // Instruction: 6: 01101010001sssssPP---------ddddd | Rd = Gs - hi->instruction = HEX_INS_RD___GS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Gs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000060) { - // Instruction: 6: 01100100000sssssPP------011----- | ciad (Rs) - hi->instruction = HEX_INS_CIAD__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "ciad (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5000000) { - // Instruction: 6: 01100101000xxxxxPP-------------- | crswap (Rx, sgp0) - hi->instruction = HEX_INS_CRSWAP__RX__SGP0_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "crswap (R%d, sgp0)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5200000) { - // Instruction: 6: 01100101001xxxxxPP-------------- | crswap (Rx, sgp1) - hi->instruction = HEX_INS_CRSWAP__RX__SGP1_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "crswap (R%d, sgp1)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfc0001f) == 0xd800000) { - // Instruction: 6: 0110110110-xxxxxPP---------00000 | crswap (Rxx, sgp1:0) - hi->instruction = HEX_INS_CRSWAP__RXX__SGP1_0_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "crswap (R%d:R%d, sgp1:0)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000020) { - // Instruction: 6: 01100100000sssssPP------001----- | cswi (Rs) - hi->instruction = HEX_INS_CSWI__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "cswi (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 6: 01100110000sssssPP---------ddddd | Rd = getimask (Rs) - hi->instruction = HEX_INS_RD___GETIMASK__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = getimask (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200020) { - // Instruction: 6: 01101100001-----PP------001----- | tlblock - hi->instruction = HEX_INS_TLBLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlblock"); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200060) { - // Instruction: 6: 01101100001-----PP------011----- | k0lock - hi->instruction = HEX_INS_K0LOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "k0lock"); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200040) { - // Instruction: 6: 01101100001-----PP------010----- | tlbunlock - hi->instruction = HEX_INS_TLBUNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlbunlock"); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200080) { - // Instruction: 6: 01101100001-----PP------100----- | k0unlock - hi->instruction = HEX_INS_K0UNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "k0unlock"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 6: 01100110011sssssPP---------ddddd | Rd = iassignr (Rs) - hi->instruction = HEX_INS_RD___IASSIGNR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = iassignr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000040) { - // Instruction: 6: 01100100000sssssPP------010----- | iassignw (Rs) - hi->instruction = HEX_INS_IASSIGNW__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "iassignw (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4600040) { - // Instruction: 6: 01100100011sssssPP------010----- | nmi (Rs) - hi->instruction = HEX_INS_NMI__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "nmi (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4400020) { - // Instruction: 6: 01100100010sssssPP------001----- | resume (Rs) - hi->instruction = HEX_INS_RESUME__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "resume (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4800000) { - // Instruction: 6: 01100100100sssssPP----tt000----- | setimask (Pt, Rs) - hi->instruction = HEX_INS_SETIMASK__PT__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "setimask (P%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4800060) { - // Instruction: 6: 01100100100sssssPP------011----- | siad (Rs) - hi->instruction = HEX_INS_SIAD__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "siad (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4600020) { - // Instruction: 6: 01100100011sssssPP------001----- | start (Rs) - hi->instruction = HEX_INS_START__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "start (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4600000) { - // Instruction: 6: 01100100011sssssPP------000----- | stop (Rs) - hi->instruction = HEX_INS_STOP__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "stop (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000000) { - // Instruction: 6: 01100100000sssssPP------000----- | swi (Rs) - hi->instruction = HEX_INS_SWI__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "swi (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xc000000) { - // Instruction: 6: 01101100000sssssPP0ttttt-------- | tlbw (Rss, Rt) - hi->instruction = HEX_INS_TLBW__RSS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlbw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc400000) { - // Instruction: 6: 01101100010sssssPP---------ddddd | Rdd = tlbr (Rs) - hi->instruction = HEX_INS_RDD___TLBR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = tlbr (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xc800000) { - // Instruction: 6: 01101100100sssssPP---------ddddd | Rd = tlbp (Rs) - hi->instruction = HEX_INS_RD___TLBP__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = tlbp (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xca00000) { - // Instruction: 6: 01101100101sssssPP-------------- | tlbinvasid (Rs) - hi->instruction = HEX_INS_TLBINVASID__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "tlbinvasid (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xcc00000) { - // Instruction: 6: 01101100110sssssPP0ttttt---ddddd | Rd = ctlbw (Rss, Rt) - hi->instruction = HEX_INS_RD___CTLBW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ctlbw (R%d:R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xce00000) { - // Instruction: 6: 01101100111sssssPP---------ddddd | Rd = tlboc (Rss) - hi->instruction = HEX_INS_RD___TLBOC__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = tlboc (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7000000) { - // Instruction: 6: 0110011100-sssssPP--------dddddd | Sd = Rs - hi->instruction = HEX_INS_SD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_SYSTEM; - hi->ops[0].op.sys = (((hi_u32)&0x3f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s = R%d", hex_get_sys_reg(hi->ops[0].op.sys), hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0xd000000) { - // Instruction: 6: 0110110100-sssssPP--------dddddd | Sdd = Rss - hi->instruction = HEX_INS_SDD___RSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_SYSTEM; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.sys = (((hi_u32)&0x3f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "%s:%s = R%d:R%d", hex_get_sys_reg(hi->ops[0].op.sys + 1), hex_get_sys_reg(hi->ops[0].op.sys), hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0xe800000) { - // Instruction: 6: 011011101-ssssssPP---------ddddd | Rd = Ss - hi->instruction = HEX_INS_RD___SS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_SYSTEM; - hi->ops[1].op.sys = (((hi_u32)&0x3f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = %s", hi->ops[0].op.reg, hex_get_sys_reg(hi->ops[1].op.sys)); - break; - } - if ((hi_u32 & 0xf800000) == 0xf000000) { - // Instruction: 6: 011011110-ssssssPP---------ddddd | Rdd = Sss - hi->instruction = HEX_INS_RDD___SSS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_SYSTEM; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.sys = (((hi_u32)&0x3f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = %s:%s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hex_get_sys_reg(hi->ops[1].op.sys + 1), hex_get_sys_reg(hi->ops[1].op.sys)); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4400000) { - // Instruction: 6: 01100100010sssssPP------000----- | wait (Rs) - hi->instruction = HEX_INS_WAIT__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "wait (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200000) { - // Instruction: 6: 01101100001-----PP------000----- | brkpt - hi->instruction = HEX_INS_BRKPT; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "brkpt"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2400000) { - // Instruction: 6: 01100010010sssssPP-------------- | trace (Rs) - hi->instruction = HEX_INS_TRACE__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "trace (R%d)", hi->ops[0].op.reg); - break; - } - break; - } - case 0x7: { - if ((hi_u32 & 0xfc00000) == 0x6000000) { - // Instruction: 7: 0111011000isssssPPiiiiiiiiiddddd | Rd = and (Rs, #s10) - hi->instruction = HEX_INS_RD___AND__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = and (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6800000) { - // Instruction: 7: 0111011010isssssPPiiiiiiiiiddddd | Rd = or (Rs, #s10) - hi->instruction = HEX_INS_RD___OR__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = or (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0xf000000) { - // Instruction: 7: 01111111--------PP-------------- | nop - hi->instruction = HEX_INS_NOP; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "nop"); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6400000) { - // Instruction: 7: 0111011001isssssPPiiiiiiiiiddddd | Rd = sub (#s10, Rs) - hi->instruction = HEX_INS_RD___SUB___S10__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[1].op.imm & (1 << 9)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 9); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = sub (%d, R%d)", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xa00000) { - // Instruction: 7: 01110000101sssssPP0--------ddddd | Rd = sxtb (Rs) - hi->instruction = HEX_INS_RD___SXTB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sxtb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xe00000) { - // Instruction: 7: 01110000111sssssPP0--------ddddd | Rd = sxth (Rs) - hi->instruction = HEX_INS_RD___SXTH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sxth (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf200000) == 0x1200000) { - // Instruction: 7: 01110001ii1xxxxxPPiiiiiiiiiiiiii | Rx.L = #u16 - hi->instruction = HEX_INS_RX_L____U16; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 8) | ((hi_u32 & 0x3fff) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d.L = 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf200000) == 0x2200000) { - // Instruction: 7: 01110010ii1xxxxxPPiiiiiiiiiiiiii | Rx.H = #u16 - hi->instruction = HEX_INS_RX_H____U16; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 8) | ((hi_u32 & 0x3fff) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d.H = 0x%x", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x8000000) { - // Instruction: 7: 01111000ii-iiiiiPPiiiiiiiiiddddd | Rd = #s16 - hi->instruction = HEX_INS_RD____S16; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xc00000) >> 8) | ((hi_u32 & 0x1f0000) >> 7) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[1].op.imm & (1 << 15)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 15); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = %d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x600000) { - // Instruction: 7: 01110000011sssssPP0--------ddddd | Rd = Rs - hi->instruction = HEX_INS_RD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xc00000) { - // Instruction: 7: 01110000110sssssPP0--------ddddd | Rd = zxth (Rs) - hi->instruction = HEX_INS_RD___ZXTH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = zxth (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf602000) == 0x3002000) { - // Instruction: 7: 01110011-00sssssPP1iiiiiiiiddddd | Rdd = combine (Rs, #s8) - hi->instruction = HEX_INS_RDD___COMBINE__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d:R%d = combine (R%d, %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602000) == 0x3202000) { - // Instruction: 7: 01110011-01sssssPP1iiiiiiiiddddd | Rdd = combine (#s8, Rs) - hi->instruction = HEX_INS_RDD___COMBINE___S8__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[1].op.imm & (1 << 7)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d:R%d = combine (%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0xc000000) { - // Instruction: 7: 011111000IIIIIIIPPIiiiiiiiiddddd | Rdd = combine (#s8, #S8) - hi->instruction = HEX_INS_RDD___COMBINE___S8___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[1].op.imm & (1 << 7)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x7f0000) >> 15) | ((hi_u32 & 0x2000) >> 13)); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d:R%d = combine (%d, %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0xc800000) { - // Instruction: 7: 011111001--IIIIIPPIiiiiiiiiddddd | Rdd = combine (#s8, #U6) - hi->instruction = HEX_INS_RDD___COMBINE___S8___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[1].op.imm & (1 << 7)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x2000) >> 13)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d:R%d = combine (%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x3000000) { - // Instruction: 7: 011100110uusssssPP0iiiiiiiiddddd | Rd = mux (Pu, Rs, #s8) - hi->instruction = HEX_INS_RD___MUX__PU__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "R%d = mux (P%d, R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x3800000) { - // Instruction: 7: 011100111uusssssPP0iiiiiiiiddddd | Rd = mux (Pu, #s8, Rs) - hi->instruction = HEX_INS_RD___MUX__PU___S8__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = mux (P%d, %d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xe000000) == 0xa000000) { - // Instruction: 7: 0111101uuIIIIIIIPPIiiiiiiiiddddd | Rd = mux (Pu, #s8, #S8) - hi->instruction = HEX_INS_RD___MUX__PU___S8___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x1800000) >> 23); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x7f0000) >> 15) | ((hi_u32 & 0x2000) >> 13)); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = mux (P%d, %d, %d)", hi->ops[0].op.reg, hi->ops[1].op.pred, (st32)hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x0) { - // Instruction: 7: 01110000000sssssPP0--------ddddd | Rd = aslh (Rs) - hi->instruction = HEX_INS_RD___ASLH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = aslh (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x200000) { - // Instruction: 7: 01110000001sssssPP0--------ddddd | Rd = asrh (Rs) - hi->instruction = HEX_INS_RD___ASRH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asrh (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf802000) == 0x4000000) { - // Instruction: 7: 011101000uusssssPP0iiiiiiiiddddd | if (Pu) Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__PU__RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d) R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x4002000) { - // Instruction: 7: 011101000uusssssPP1iiiiiiiiddddd | if (Pu.new) Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if (P%d.new) R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x4800000) { - // Instruction: 7: 011101001uusssssPP0iiiiiiiiddddd | if !Pu Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x4802000) { - // Instruction: 7: 011101001uusssssPP1iiiiiiiiddddd | if !Pu.new Rd = add (Rs, #s8) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS___S8_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[3].op.imm & (1 << 7)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "if !P%d.new R%d = add (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2000) { - // Instruction: 7: 01110000000sssssPP1-00uu---ddddd | if (Pu) Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2400) { - // Instruction: 7: 01110000000sssssPP1-01uu---ddddd | if (Pu.new) Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2800) { - // Instruction: 7: 01110000000sssssPP1-10uu---ddddd | if !Pu Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x2c00) { - // Instruction: 7: 01110000000sssssPP1-11uu---ddddd | if !Pu.new Rd = aslh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ASLH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = aslh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202000) { - // Instruction: 7: 01110000001sssssPP1-00uu---ddddd | if (Pu) Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202400) { - // Instruction: 7: 01110000001sssssPP1-01uu---ddddd | if (Pu.new) Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202800) { - // Instruction: 7: 01110000001sssssPP1-10uu---ddddd | if !Pu Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x202c00) { - // Instruction: 7: 01110000001sssssPP1-11uu---ddddd | if !Pu.new Rd = asrh (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ASRH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = asrh (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02000) { - // Instruction: 7: 01110000101sssssPP1-00uu---ddddd | if (Pu) Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__PU__RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02400) { - // Instruction: 7: 01110000101sssssPP1-01uu---ddddd | if (Pu.new) Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02800) { - // Instruction: 7: 01110000101sssssPP1-10uu---ddddd | if !Pu Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xa02c00) { - // Instruction: 7: 01110000101sssssPP1-11uu---ddddd | if !Pu.new Rd = sxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___SXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = sxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02000) { - // Instruction: 7: 01110000111sssssPP1-00uu---ddddd | if (Pu) Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__PU__RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02400) { - // Instruction: 7: 01110000111sssssPP1-01uu---ddddd | if (Pu.new) Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02800) { - // Instruction: 7: 01110000111sssssPP1-10uu---ddddd | if !Pu Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xe02c00) { - // Instruction: 7: 01110000111sssssPP1-11uu---ddddd | if !Pu.new Rd = sxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___SXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = sxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf902000) == 0xe000000) { - // Instruction: 7: 011111100uu0iiiiPP0iiiiiiiiddddd | if (Pu) Rd = #s12 - hi->instruction = HEX_INS_IF__PU__RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_TRUE; // if (Pu) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf902000) == 0xe002000) { - // Instruction: 7: 011111100uu0iiiiPP1iiiiiiiiddddd | if (Pu.new) Rd = #s12 - hi->instruction = HEX_INS_IF__PU_NEW__RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf902000) == 0xe800000) { - // Instruction: 7: 011111101uu0iiiiPP0iiiiiiiiddddd | if !Pu Rd = #s12 - hi->instruction = HEX_INS_IF__NOT_PU_RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_FALSE; // if !Pu - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf902000) == 0xe802000) { - // Instruction: 7: 011111101uu0iiiiPP1iiiiiiiiddddd | if !Pu.new Rd = #s12 - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD____S12; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600000) >> 21); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf0000) >> 8) | ((hi_u32 & 0x1fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = %d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802000) { - // Instruction: 7: 01110000100sssssPP1-00uu---ddddd | if (Pu) Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802400) { - // Instruction: 7: 01110000100sssssPP1-01uu---ddddd | if (Pu.new) Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802800) { - // Instruction: 7: 01110000100sssssPP1-10uu---ddddd | if !Pu Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0x802c00) { - // Instruction: 7: 01110000100sssssPP1-11uu---ddddd | if !Pu.new Rd = zxtb (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ZXTB__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = zxtb (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02000) { - // Instruction: 7: 01110000110sssssPP1-00uu---ddddd | if (Pu) Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__PU__RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02400) { - // Instruction: 7: 01110000110sssssPP1-01uu---ddddd | if (Pu.new) Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02800) { - // Instruction: 7: 01110000110sssssPP1-10uu---ddddd | if !Pu Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02c00) == 0xc02c00) { - // Instruction: 7: 01110000110sssssPP1-11uu---ddddd | if !Pu.new Rd = zxth (Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ZXTH__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = zxth (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5000000) { - // Instruction: 7: 0111010100isssssPPiiiiiiiii000dd | Pd = cmp.eq (Rs, #s10) - hi->instruction = HEX_INS_PD___CMP_EQ__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmp.eq (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5000010) { - // Instruction: 7: 0111010100isssssPPiiiiiiiii100dd | Pd = !cmp.eq (Rs, #s10) - hi->instruction = HEX_INS_PD____NOT_CMP_EQ__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = !cmp.eq (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5400000) { - // Instruction: 7: 0111010101isssssPPiiiiiiiii000dd | Pd = cmp.gt (Rs, #s10) - hi->instruction = HEX_INS_PD___CMP_GT__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmp.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc0001c) == 0x5400010) { - // Instruction: 7: 0111010101isssssPPiiiiiiiii100dd | Pd = !cmp.gt (Rs, #s10) - hi->instruction = HEX_INS_PD____NOT_CMP_GT__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = !cmp.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe0001c) == 0x5800000) { - // Instruction: 7: 01110101100sssssPPiiiiiiiii000dd | Pd = cmp.gtu (Rs, #u9) - hi->instruction = HEX_INS_PD___CMP_GTU__RS___U9_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3fe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmp.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe0001c) == 0x5800010) { - // Instruction: 7: 01110101100sssssPPiiiiiiiii100dd | Pd = !cmp.gtu (Rs, #u9) - hi->instruction = HEX_INS_PD____NOT_CMP_GTU__RS___U9_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3fe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = !cmp.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602000) == 0x3402000) { - // Instruction: 7: 01110011-10sssssPP1iiiiiiiiddddd | Rd = cmp.eq (Rs, #s8) - hi->instruction = HEX_INS_RD___CMP_EQ__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = cmp.eq (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf602000) == 0x3602000) { - // Instruction: 7: 01110011-11sssssPP1iiiiiiiiddddd | Rd = !cmp.eq (Rs, #s8) - hi->instruction = HEX_INS_RD____NOT_CMP_EQ__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = !cmp.eq (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - break; - } - case 0x8: { - if ((hi_u32 & 0xfe000e0) == 0x8000c0) { - // Instruction: 8: 10000000100sssssPP------110ddddd | Rdd = abs (Rss) - hi->instruction = HEX_INS_RDD___ABS__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = abs (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc800080) { - // Instruction: 8: 10001100100sssssPP------100ddddd | Rd = abs (Rs) - hi->instruction = HEX_INS_RD___ABS__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = abs (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc8000a0) { - // Instruction: 8: 10001100100sssssPP------101ddddd | Rd = abs (Rs) :sat - hi->instruction = HEX_INS_RD___ABS__RS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = abs (R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x800080) { - // Instruction: 8: 10000000100sssssPP------100ddddd | Rdd = not (Rss) - hi->instruction = HEX_INS_RDD___NOT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = not (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000a0) { - // Instruction: 8: 10000000100sssssPP------101ddddd | Rdd = neg (Rss) - hi->instruction = HEX_INS_RDD___NEG__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = neg (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc8000c0) { - // Instruction: 8: 10001100100sssssPP------110ddddd | Rd = neg (Rs) :sat - hi->instruction = HEX_INS_RD___NEG__RS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = neg (R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8c00020) { - // Instruction: 8: 10001000110sssssPP------001ddddd | Rd = round (Rss) :sat - hi->instruction = HEX_INS_RD___ROUND__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = round (R%d:R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020c0) == 0xce00000) { - // Instruction: 8: 10001100111sssssPP0iiiii00-ddddd | Rd = cround (Rs, #u5) - hi->instruction = HEX_INS_RD___CROUND__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cround (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020c0) == 0xce00080) { - // Instruction: 8: 10001100111sssssPP0iiiii10-ddddd | Rd = round (Rs, #u5) - hi->instruction = HEX_INS_RD___ROUND__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = round (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020c0) == 0xce000c0) { - // Instruction: 8: 10001100111sssssPP0iiiii11-ddddd | Rd = round (Rs, #u5) :sat - hi->instruction = HEX_INS_RD___ROUND__RS___U5___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = round (R%d, 0x%x) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4400000) { - // Instruction: 8: 1000010001-sssssPP------00-ddddd | Rdd = sxtw (Rs) - hi->instruction = HEX_INS_RDD___SXTW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = sxtw (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x400080) { - // Instruction: 8: 10000000010sssssPP------100ddddd | Rdd = vabsh (Rss) - hi->instruction = HEX_INS_RDD___VABSH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsh (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000a0) { - // Instruction: 8: 10000000010sssssPP------101ddddd | Rdd = vabsh (Rss) :sat - hi->instruction = HEX_INS_RDD___VABSH__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vabsh (R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000c0) { - // Instruction: 8: 10000000010sssssPP------110ddddd | Rdd = vabsw (Rss) - hi->instruction = HEX_INS_RDD___VABSW__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsw (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x4000e0) { - // Instruction: 8: 10000000010sssssPP------111ddddd | Rdd = vabsw (Rss) :sat - hi->instruction = HEX_INS_RDD___VABSW__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vabsw (R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400000) { - // Instruction: 8: 10001000010sssssPP------000ddddd | Rd = clb (Rss) - hi->instruction = HEX_INS_RD___CLB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400040) { - // Instruction: 8: 10001000010sssssPP------010ddddd | Rd = cl0 (Rss) - hi->instruction = HEX_INS_RD___CL0__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl0 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400080) { - // Instruction: 8: 10001000010sssssPP------100ddddd | Rd = cl1 (Rss) - hi->instruction = HEX_INS_RD___CL1__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl1 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600000) { - // Instruction: 8: 10001000011sssssPP------000ddddd | Rd = normamt (Rss) - hi->instruction = HEX_INS_RD___NORMAMT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = normamt (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600040) { - // Instruction: 8: 10001000011sssssPPiiiiii010ddddd | Rd = add (clb (Rss), #s6) - hi->instruction = HEX_INS_RD___ADD__CLB__RSS____S6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (clb (R%d:R%d), %d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc200000) { - // Instruction: 8: 10001100001sssssPPiiiiii000ddddd | Rd = add (clb (Rs), #s6) - hi->instruction = HEX_INS_RD___ADD__CLB__RS____S6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (clb (R%d), %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000080) { - // Instruction: 8: 10001100000sssssPP------100ddddd | Rd = clb (Rs) - hi->instruction = HEX_INS_RD___CLB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0000a0) { - // Instruction: 8: 10001100000sssssPP------101ddddd | Rd = cl0 (Rs) - hi->instruction = HEX_INS_RD___CL0__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl0 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0000c0) { - // Instruction: 8: 10001100000sssssPP------110ddddd | Rd = cl1 (Rs) - hi->instruction = HEX_INS_RD___CL1__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cl1 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0000e0) { - // Instruction: 8: 10001100000sssssPP------111ddddd | Rd = normamt (Rs) - hi->instruction = HEX_INS_RD___NORMAMT__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = normamt (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600060) { - // Instruction: 8: 10001000011sssssPP------011ddddd | Rd = popcount (Rss) - hi->instruction = HEX_INS_RD___POPCOUNT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = popcount (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8e00040) { - // Instruction: 8: 10001000111sssssPP------010ddddd | Rd = ct0 (Rss) - hi->instruction = HEX_INS_RD___CT0__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct0 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8e00080) { - // Instruction: 8: 10001000111sssssPP------100ddddd | Rd = ct1 (Rss) - hi->instruction = HEX_INS_RD___CT1__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct1 (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc400080) { - // Instruction: 8: 10001100010sssssPP------100ddddd | Rd = ct0 (Rs) - hi->instruction = HEX_INS_RD___CT0__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct0 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc4000a0) { - // Instruction: 8: 10001100010sssssPP------101ddddd | Rd = ct1 (Rs) - hi->instruction = HEX_INS_RD___CT1__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = ct1 (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x1000000) { - // Instruction: 8: 10000001IIIsssssPPiiiiiiIIIddddd | Rdd = extractu (Rss, #u6, #U6) - hi->instruction = HEX_INS_RDD___EXTRACTU__RSS___U6___U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xe00000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extractu (R%d:R%d, 0x%x, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0xa000000) { - // Instruction: 8: 10001010IIIsssssPPiiiiiiIIIddddd | Rdd = extract (Rss, #u6, #U6) - hi->instruction = HEX_INS_RDD___EXTRACT__RSS___U6___U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xe00000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extract (R%d:R%d, 0x%x, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0xd000000) { - // Instruction: 8: 100011010IIsssssPP0iiiiiIIIddddd | Rd = extractu (Rs, #u5, #U5) - hi->instruction = HEX_INS_RD___EXTRACTU__RS___U5___U5_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extractu (R%d, 0x%x, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0xd800000) { - // Instruction: 8: 100011011IIsssssPP0iiiiiIIIddddd | Rd = extract (Rs, #u5, #U5) - hi->instruction = HEX_INS_RD___EXTRACT__RS___U5___U5_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extract (R%d, 0x%x, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x3000000) { - // Instruction: 8: 10000011IIIsssssPPiiiiiiIIIxxxxx | Rxx = insert (Rss, #u6, #U6) - hi->instruction = HEX_INS_RXX___INSERT__RSS___U6___U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xe00000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = insert (R%d:R%d, 0x%x, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0xf000000) { - // Instruction: 8: 100011110IIsssssPP0iiiiiIIIxxxxx | Rx = insert (Rs, #u5, #U5) - hi->instruction = HEX_INS_RX___INSERT__RS___U5___U5_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = insert (R%d, 0x%x, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc00080) { - // Instruction: 8: 10000000110sssssPP------100ddddd | Rdd = deinterleave (Rss) - hi->instruction = HEX_INS_RDD___DEINTERLEAVE__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = deinterleave (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000a0) { - // Instruction: 8: 10000000110sssssPP------101ddddd | Rdd = interleave (Rss) - hi->instruction = HEX_INS_RDD___INTERLEAVE__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = interleave (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000c0) { - // Instruction: 8: 10000000110sssssPP------110ddddd | Rdd = brev (Rss) - hi->instruction = HEX_INS_RDD___BREV__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = brev (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc4000c0) { - // Instruction: 8: 10001100010sssssPP------110ddddd | Rd = brev (Rs) - hi->instruction = HEX_INS_RD___BREV__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = brev (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xcc00000) { - // Instruction: 8: 10001100110sssssPP0iiiii000ddddd | Rd = setbit (Rs, #u5) - hi->instruction = HEX_INS_RD___SETBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = setbit (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xcc00020) { - // Instruction: 8: 10001100110sssssPP0iiiii001ddddd | Rd = clrbit (Rs, #u5) - hi->instruction = HEX_INS_RD___CLRBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clrbit (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xcc00040) { - // Instruction: 8: 10001100110sssssPP0iiiii010ddddd | Rd = togglebit (Rs, #u5) - hi->instruction = HEX_INS_RD___TOGGLEBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = togglebit (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8c00080) { - // Instruction: 8: 10001000110sssssPP0iiiii100ddddd | Rdd = bitsplit (Rs, #u5) - hi->instruction = HEX_INS_RDD___BITSPLIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = bitsplit (R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7000000) { - // Instruction: 8: 1000011100isssssPPIIIIIIiiixxxxx | Rx = tableidxb (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXB__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxb (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7400000) { - // Instruction: 8: 1000011101isssssPPIIIIIIiiixxxxx | Rx = tableidxh (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXH__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxh (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7800000) { - // Instruction: 8: 1000011110isssssPPIIIIIIiiixxxxx | Rx = tableidxw (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXW__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxw (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x7c00000) { - // Instruction: 8: 1000011111isssssPPIIIIIIiiixxxxx | Rx = tableidxd (Rs, #u4, #S6) :raw - hi->instruction = HEX_INS_RX___TABLEIDXD__RS___U4___S6___RAW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 18) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = tableidxd (R%d, 0x%x, %d) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000e0) { - // Instruction: 8: 10000000100sssssPP------111ddddd | Rdd = vconj (Rss) :sat - hi->instruction = HEX_INS_RDD___VCONJ__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vconj (R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5e00000) { - // Instruction: 8: 10000101111sssssPP0iiiii------dd | Pd = sfclass (Rs, #u5) - hi->instruction = HEX_INS_PD___SFCLASS__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = sfclass (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800000) { - // Instruction: 8: 100001001--sssssPP------000ddddd | Rdd = convert_sf2df (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_SF2DF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2df (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000020) { - // Instruction: 8: 10001000000sssssPP------001ddddd | Rd = convert_df2sf (Rss) - hi->instruction = HEX_INS_RD___CONVERT_DF2SF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_df2sf (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00040) { - // Instruction: 8: 10000000111sssssPP0-----010ddddd | Rdd = convert_ud2df (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_UD2DF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_ud2df (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00060) { - // Instruction: 8: 10000000111sssssPP0-----011ddddd | Rdd = convert_d2df (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_D2DF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_d2df (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800020) { - // Instruction: 8: 100001001--sssssPP------001ddddd | Rdd = convert_uw2df (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_UW2DF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_uw2df (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800040) { - // Instruction: 8: 100001001--sssssPP------010ddddd | Rdd = convert_w2df (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_W2DF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_w2df (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8200020) { - // Instruction: 8: 10001000001sssssPP------001ddddd | Rd = convert_ud2sf (Rss) - hi->instruction = HEX_INS_RD___CONVERT_UD2SF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_ud2sf (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8400020) { - // Instruction: 8: 10001000010sssssPP------001ddddd | Rd = convert_d2sf (Rss) - hi->instruction = HEX_INS_RD___CONVERT_D2SF__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_d2sf (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb200000) { - // Instruction: 8: 10001011001sssssPP------000ddddd | Rd = convert_uw2sf (Rs) - hi->instruction = HEX_INS_RD___CONVERT_UW2SF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_uw2sf (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb400000) { - // Instruction: 8: 10001011010sssssPP------000ddddd | Rd = convert_w2sf (Rs) - hi->instruction = HEX_INS_RD___CONVERT_W2SF__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_w2sf (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00000) { - // Instruction: 8: 10000000111sssssPP0-----000ddddd | Rdd = convert_df2d (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_DF2D__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_df2d (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe00020) { - // Instruction: 8: 10000000111sssssPP0-----001ddddd | Rdd = convert_df2ud (Rss) - hi->instruction = HEX_INS_RDD___CONVERT_DF2UD__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_df2ud (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe000c0) { - // Instruction: 8: 10000000111sssssPP0-----110ddddd | Rdd = convert_df2d (Rss) :chop - hi->instruction = HEX_INS_RDD___CONVERT_DF2D__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d:R%d = convert_df2d (R%d:R%d) :chop", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xe000e0) { - // Instruction: 8: 10000000111sssssPP0-----111ddddd | Rdd = convert_df2ud (Rss) :chop - hi->instruction = HEX_INS_RDD___CONVERT_DF2UD__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d:R%d = convert_df2ud (R%d:R%d) :chop", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800060) { - // Instruction: 8: 100001001--sssssPP------011ddddd | Rdd = convert_sf2ud (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_SF2UD__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2ud (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x4800080) { - // Instruction: 8: 100001001--sssssPP------100ddddd | Rdd = convert_sf2d (Rs) - hi->instruction = HEX_INS_RDD___CONVERT_SF2D__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2d (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x48000a0) { - // Instruction: 8: 100001001--sssssPP------101ddddd | Rdd = convert_sf2ud (Rs) :ch - hi->instruction = HEX_INS_RDD___CONVERT_SF2UD__RS___CH; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = convert_sf2ud (R%d) :ch", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf8000e0) == 0x48000c0) { - // Instruction: 8: 100001001--sssssPP------110ddddd | Rdd = convert_sf2d (Rs) :chop - hi->instruction = HEX_INS_RDD___CONVERT_SF2D__RS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d:R%d = convert_sf2d (R%d) :chop", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8600020) { - // Instruction: 8: 10001000011sssssPP------001ddddd | Rd = convert_df2uw (Rss) - hi->instruction = HEX_INS_RD___CONVERT_DF2UW__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_df2uw (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800020) { - // Instruction: 8: 10001000100sssssPP------001ddddd | Rd = convert_df2w (Rss) - hi->instruction = HEX_INS_RD___CONVERT_DF2W__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_df2w (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8a00020) { - // Instruction: 8: 10001000101sssssPP------001ddddd | Rd = convert_df2uw (Rss) :chop - hi->instruction = HEX_INS_RD___CONVERT_DF2UW__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_df2uw (R%d:R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8e00020) { - // Instruction: 8: 10001000111sssssPP------001ddddd | Rd = convert_df2w (Rss) :chop - hi->instruction = HEX_INS_RD___CONVERT_DF2W__RSS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_df2w (R%d:R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb600000) { - // Instruction: 8: 10001011011sssssPP------000ddddd | Rd = convert_sf2uw (Rs) - hi->instruction = HEX_INS_RD___CONVERT_SF2UW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_sf2uw (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb600020) { - // Instruction: 8: 10001011011sssssPP------001ddddd | Rd = convert_sf2uw (Rs) :chop - hi->instruction = HEX_INS_RD___CONVERT_SF2UW__RS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_sf2uw (R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb800000) { - // Instruction: 8: 10001011100sssssPP------000ddddd | Rd = convert_sf2w (Rs) - hi->instruction = HEX_INS_RD___CONVERT_SF2W__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = convert_sf2w (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xb800020) { - // Instruction: 8: 10001011100sssssPP------001ddddd | Rd = convert_sf2w (Rs) :chop - hi->instruction = HEX_INS_RD___CONVERT_SF2W__RS___CHOP; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CHOP; // :chop - sprintf(hi->mnem, "R%d = convert_sf2w (R%d) :chop", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xba00000) { - // Instruction: 8: 10001011101sssssPP------000ddddd | Rd = sffixupr (Rs) - hi->instruction = HEX_INS_RD___SFFIXUPR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sffixupr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xbe00000) { - // Instruction: 8: 10001011111sssssPP------0eeddddd | Rd, Pe = sfinvsqrta (Rs) - hi->instruction = HEX_INS_RD__PE___SFINVSQRTA__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d, P%d = sfinvsqrta (R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8c00000) { - // Instruction: 8: 10001000110sssssPP------000ddddd | Rd = sat (Rss) - hi->instruction = HEX_INS_RD___SAT__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sat (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc00080) { - // Instruction: 8: 10001100110sssssPP------100ddddd | Rd = sath (Rs) - hi->instruction = HEX_INS_RD___SATH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sath (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc000a0) { - // Instruction: 8: 10001100110sssssPP------101ddddd | Rd = satuh (Rs) - hi->instruction = HEX_INS_RD___SATUH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = satuh (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc000c0) { - // Instruction: 8: 10001100110sssssPP------110ddddd | Rd = satub (Rs) - hi->instruction = HEX_INS_RD___SATUB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = satub (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xcc000e0) { - // Instruction: 8: 10001100110sssssPP------111ddddd | Rd = satb (Rs) - hi->instruction = HEX_INS_RD___SATB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = satb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc8000e0) { - // Instruction: 8: 10001100100sssssPP------111ddddd | Rd = swiz (Rs) - hi->instruction = HEX_INS_RD___SWIZ__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = swiz (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800080) { - // Instruction: 8: 10001000100sssssPP------100ddddd | Rd = vrndwh (Rss) - hi->instruction = HEX_INS_RD___VRNDWH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vrndwh (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x88000c0) { - // Instruction: 8: 10001000100sssssPP------110ddddd | Rd = vrndwh (Rss) :sat - hi->instruction = HEX_INS_RD___VRNDWH__RSS___SAT; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vrndwh (R%d:R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000000) { - // Instruction: 8: 10001000000sssssPP------000ddddd | Rd = vsathub (Rss) - hi->instruction = HEX_INS_RD___VSATHUB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathub (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000040) { - // Instruction: 8: 10001000000sssssPP------010ddddd | Rd = vsatwh (Rss) - hi->instruction = HEX_INS_RD___VSATWH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsatwh (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8000080) { - // Instruction: 8: 10001000000sssssPP------100ddddd | Rd = vsatwuh (Rss) - hi->instruction = HEX_INS_RD___VSATWUH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsatwuh (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x80000c0) { - // Instruction: 8: 10001000000sssssPP------110ddddd | Rd = vsathb (Rss) - hi->instruction = HEX_INS_RD___VSATHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800000) { - // Instruction: 8: 1000110010-sssssPP------00-ddddd | Rd = vsathb (Rs) - hi->instruction = HEX_INS_RD___VSATHB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800040) { - // Instruction: 8: 1000110010-sssssPP------01-ddddd | Rd = vsathub (Rs) - hi->instruction = HEX_INS_RD___VSATHUB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsathub (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x80) { - // Instruction: 8: 10000000000sssssPP------100ddddd | Rdd = vsathub (Rss) - hi->instruction = HEX_INS_RDD___VSATHUB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsathub (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xa0) { - // Instruction: 8: 10000000000sssssPP------101ddddd | Rdd = vsatwuh (Rss) - hi->instruction = HEX_INS_RDD___VSATWUH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsatwuh (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc0) { - // Instruction: 8: 10000000000sssssPP------110ddddd | Rdd = vsatwh (Rss) - hi->instruction = HEX_INS_RDD___VSATWH__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsatwh (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xe0) { - // Instruction: 8: 10000000000sssssPP------111ddddd | Rdd = vsathb (Rss) - hi->instruction = HEX_INS_RDD___VSATHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsathb (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4400080) { - // Instruction: 8: 1000010001-sssssPP------10-ddddd | Rdd = vsplatb (Rs) - hi->instruction = HEX_INS_RDD___VSPLATB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsplatb (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc4000e0) { - // Instruction: 8: 10001100010sssssPP------111ddddd | Rd = vsplatb (Rs) - hi->instruction = HEX_INS_RD___VSPLATB__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsplatb (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4400040) { - // Instruction: 8: 1000010001-sssssPP------01-ddddd | Rdd = vsplath (Rs) - hi->instruction = HEX_INS_RDD___VSPLATH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsplath (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4000000) { - // Instruction: 8: 1000010000-sssssPP------00-ddddd | Rdd = vsxtbh (Rs) - hi->instruction = HEX_INS_RDD___VSXTBH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsxtbh (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4000080) { - // Instruction: 8: 1000010000-sssssPP------10-ddddd | Rdd = vsxthw (Rs) - hi->instruction = HEX_INS_RDD___VSXTHW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsxthw (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800000) { - // Instruction: 8: 10001000100sssssPP------000ddddd | Rd = vtrunohb (Rss) - hi->instruction = HEX_INS_RD___VTRUNOHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vtrunohb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x8800040) { - // Instruction: 8: 10001000100sssssPP------010ddddd | Rd = vtrunehb (Rss) - hi->instruction = HEX_INS_RD___VTRUNEHB__RSS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vtrunehb (R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x4000040) { - // Instruction: 8: 1000010000-sssssPP------01-ddddd | Rdd = vzxtbh (Rs) - hi->instruction = HEX_INS_RDD___VZXTBH__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vzxtbh (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x40000c0) { - // Instruction: 8: 1000010000-sssssPP------11-ddddd | Rdd = vzxthw (Rs) - hi->instruction = HEX_INS_RDD___VZXTHW__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vzxthw (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5800000) { - // Instruction: 8: 10000101100sssssPPiiiiii------dd | Pd = bitsclr (Rs, #u6) - hi->instruction = HEX_INS_PD___BITSCLR__RS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = bitsclr (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5a00000) { - // Instruction: 8: 10000101101sssssPPiiiiii------dd | Pd = !bitsclr (Rs, #u6) - hi->instruction = HEX_INS_PD____NOT_BITSCLR__RS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !bitsclr (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x6000000) { - // Instruction: 8: 10000110--------PP----tt---ddddd | Rdd = mask (Pt) - hi->instruction = HEX_INS_RDD___MASK__PT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mask (P%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5400000) { - // Instruction: 8: 10000101010sssssPP------------dd | Pd = Rs - hi->instruction = HEX_INS_PD___RS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xf400000) == 0x9400000) { - // Instruction: 8: 10001001-1----ssPP---------ddddd | Rd = Ps - hi->instruction = HEX_INS_RD___PS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = P%d", hi->ops[0].op.reg, hi->ops[1].op.pred); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5000000) { - // Instruction: 8: 10000101000sssssPP0iiiii------dd | Pd = tstbit (Rs, #u5) - hi->instruction = HEX_INS_PD___TSTBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = tstbit (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe02000) == 0x5200000) { - // Instruction: 8: 10000101001sssssPP0iiiii------dd | Pd = !tstbit (Rs, #u5) - hi->instruction = HEX_INS_PD____NOT_TSTBIT__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !tstbit (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600000) == 0x9000000) { - // Instruction: 8: 10001001-00---ssPP----tt---ddddd | Rd = vitpack (Ps, Pt) - hi->instruction = HEX_INS_RD___VITPACK__PS__PT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x30000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_PREDICATE; - hi->ops[2].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vitpack (P%d, P%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.pred); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x0) { - // Instruction: 8: 10000000000sssssPPiiiiii000ddddd | Rdd = asr (Rss, #u6) - hi->instruction = HEX_INS_RDD___ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x20) { - // Instruction: 8: 10000000000sssssPPiiiiii001ddddd | Rdd = lsr (Rss, #u6) - hi->instruction = HEX_INS_RDD___LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x40) { - // Instruction: 8: 10000000000sssssPPiiiiii010ddddd | Rdd = asl (Rss, #u6) - hi->instruction = HEX_INS_RDD___ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x60) { - // Instruction: 8: 10000000000sssssPPiiiiii011ddddd | Rdd = rol (Rss, #u6) - hi->instruction = HEX_INS_RDD___ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000000) { - // Instruction: 8: 10001100000sssssPP0iiiii000ddddd | Rd = asr (Rs, #u5) - hi->instruction = HEX_INS_RD___ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000020) { - // Instruction: 8: 10001100000sssssPP0iiiii001ddddd | Rd = lsr (Rs, #u5) - hi->instruction = HEX_INS_RD___LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000040) { - // Instruction: 8: 10001100000sssssPP0iiiii010ddddd | Rd = asl (Rs, #u5) - hi->instruction = HEX_INS_RD___ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc000060) { - // Instruction: 8: 10001100000sssssPP0iiiii011ddddd | Rd = rol (Rs, #u5) - hi->instruction = HEX_INS_RD___ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000000) { - // Instruction: 8: 1000001000-sssssPPiiiiii000xxxxx | Rxx -= asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000020) { - // Instruction: 8: 1000001000-sssssPPiiiiii001xxxxx | Rxx -= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000040) { - // Instruction: 8: 1000001000-sssssPPiiiiii010xxxxx | Rxx -= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000060) { - // Instruction: 8: 1000001000-sssssPPiiiiii011xxxxx | Rxx -= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2000080) { - // Instruction: 8: 1000001000-sssssPPiiiiii100xxxxx | Rxx += asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x20000a0) { - // Instruction: 8: 1000001000-sssssPPiiiiii101xxxxx | Rxx += lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x20000c0) { - // Instruction: 8: 1000001000-sssssPPiiiiii110xxxxx | Rxx += asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x20000e0) { - // Instruction: 8: 1000001000-sssssPPiiiiii111xxxxx | Rxx += rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000000) { - // Instruction: 8: 1000111000-sssssPP0iiiii000xxxxx | Rx -= asr (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000020) { - // Instruction: 8: 1000111000-sssssPP0iiiii001xxxxx | Rx -= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000040) { - // Instruction: 8: 1000111000-sssssPP0iiiii010xxxxx | Rx -= asl (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000060) { - // Instruction: 8: 1000111000-sssssPP0iiiii011xxxxx | Rx -= rol (Rs, #u5) - hi->instruction = HEX_INS_RX__MINUS_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe000080) { - // Instruction: 8: 1000111000-sssssPP0iiiii100xxxxx | Rx += asr (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe0000a0) { - // Instruction: 8: 1000111000-sssssPP0iiiii101xxxxx | Rx += lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe0000c0) { - // Instruction: 8: 1000111000-sssssPP0iiiii110xxxxx | Rx += asl (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe0000e0) { - // Instruction: 8: 1000111000-sssssPP0iiiii111xxxxx | Rx += rol (Rs, #u5) - hi->instruction = HEX_INS_RX__PLUS_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400000) { - // Instruction: 8: 1000001001-sssssPPiiiiii000xxxxx | Rxx &= asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400020) { - // Instruction: 8: 1000001001-sssssPPiiiiii001xxxxx | Rxx &= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400040) { - // Instruction: 8: 1000001001-sssssPPiiiiii010xxxxx | Rxx &= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400060) { - // Instruction: 8: 1000001001-sssssPPiiiiii011xxxxx | Rxx &= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__AND_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2400080) { - // Instruction: 8: 1000001001-sssssPPiiiiii100xxxxx | Rxx |= asr (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__ASR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x24000a0) { - // Instruction: 8: 1000001001-sssssPPiiiiii101xxxxx | Rxx |= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x24000c0) { - // Instruction: 8: 1000001001-sssssPPiiiiii110xxxxx | Rxx |= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x24000e0) { - // Instruction: 8: 1000001001-sssssPPiiiiii111xxxxx | Rxx |= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX__OR_EQ__ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2800020) { - // Instruction: 8: 1000001010-sssssPPiiiiii001xxxxx | Rxx ^= lsr (Rss, #u6) - hi->instruction = HEX_INS_RXX____LSR__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= lsr (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2800040) { - // Instruction: 8: 1000001010-sssssPPiiiiii010xxxxx | Rxx ^= asl (Rss, #u6) - hi->instruction = HEX_INS_RXX____ASL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= asl (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x2800060) { - // Instruction: 8: 1000001010-sssssPPiiiiii011xxxxx | Rxx ^= rol (Rss, #u6) - hi->instruction = HEX_INS_RXX____ROL__RSS___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= rol (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400000) { - // Instruction: 8: 1000111001-sssssPP0iiiii000xxxxx | Rx &= asr (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400020) { - // Instruction: 8: 1000111001-sssssPP0iiiii001xxxxx | Rx &= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400040) { - // Instruction: 8: 1000111001-sssssPP0iiiii010xxxxx | Rx &= asl (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400060) { - // Instruction: 8: 1000111001-sssssPP0iiiii011xxxxx | Rx &= rol (Rs, #u5) - hi->instruction = HEX_INS_RX__AND_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe400080) { - // Instruction: 8: 1000111001-sssssPP0iiiii100xxxxx | Rx |= asr (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__ASR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe4000a0) { - // Instruction: 8: 1000111001-sssssPP0iiiii101xxxxx | Rx |= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe4000c0) { - // Instruction: 8: 1000111001-sssssPP0iiiii110xxxxx | Rx |= asl (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe4000e0) { - // Instruction: 8: 1000111001-sssssPP0iiiii111xxxxx | Rx |= rol (Rs, #u5) - hi->instruction = HEX_INS_RX__OR_EQ__ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe800020) { - // Instruction: 8: 1000111010-sssssPP0iiiii001xxxxx | Rx ^= lsr (Rs, #u5) - hi->instruction = HEX_INS_RX____LSR__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= lsr (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe800040) { - // Instruction: 8: 1000111010-sssssPP0iiiii010xxxxx | Rx ^= asl (Rs, #u5) - hi->instruction = HEX_INS_RX____ASL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= asl (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xe800060) { - // Instruction: 8: 1000111010-sssssPP0iiiii011xxxxx | Rx ^= rol (Rs, #u5) - hi->instruction = HEX_INS_RX____ROL__RS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= rol (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0xc000e0) { - // Instruction: 8: 10000000110sssssPPiiiiii111ddddd | Rdd = asr (Rss, #u6) :rnd - hi->instruction = HEX_INS_RDD___ASR__RSS___U6___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = asr (R%d:R%d, 0x%x) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc400000) { - // Instruction: 8: 10001100010sssssPP0iiiii000ddddd | Rd = asr (Rs, #u5) :rnd - hi->instruction = HEX_INS_RD___ASR__RS___U5___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = asr (R%d, 0x%x) :rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xc400040) { - // Instruction: 8: 10001100010sssssPP0iiiii010ddddd | Rd = asl (Rs, #u5) :sat - hi->instruction = HEX_INS_RD___ASL__RS___U5___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = asl (R%d, 0x%x) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x800000) { - // Instruction: 8: 10000000100sssssPP00iiii000ddddd | Rdd = vasrh (Rss, #u4) - hi->instruction = HEX_INS_RDD___VASRH__RSS___U4_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrh (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x800020) { - // Instruction: 8: 10000000100sssssPP00iiii001ddddd | Rdd = vlsrh (Rss, #u4) - hi->instruction = HEX_INS_RDD___VLSRH__RSS___U4_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrh (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x800040) { - // Instruction: 8: 10000000100sssssPP00iiii010ddddd | Rdd = vaslh (Rss, #u4) - hi->instruction = HEX_INS_RDD___VASLH__RSS___U4_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslh (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x200000) { - // Instruction: 8: 10000000001sssssPP00iiii000ddddd | Rdd = vasrh (Rss, #u4) :raw - hi->instruction = HEX_INS_RDD___VASRH__RSS___U4___RAW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d:R%d = vasrh (R%d:R%d, 0x%x) :raw", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x8600080) { - // Instruction: 8: 10001000011sssssPP00iiii100ddddd | Rd = vasrhub (Rss, #u4) :raw - hi->instruction = HEX_INS_RD___VASRHUB__RSS___U4___RAW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d = vasrhub (R%d:R%d, 0x%x) :raw", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe030e0) == 0x86000a0) { - // Instruction: 8: 10001000011sssssPP00iiii101ddddd | Rd = vasrhub (Rss, #u4) :sat - hi->instruction = HEX_INS_RD___VASRHUB__RSS___U4___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vasrhub (R%d:R%d, 0x%x) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x400000) { - // Instruction: 8: 10000000010sssssPP0iiiii000ddddd | Rdd = vasrw (Rss, #u5) - hi->instruction = HEX_INS_RDD___VASRW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrw (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x400020) { - // Instruction: 8: 10000000010sssssPP0iiiii001ddddd | Rdd = vlsrw (Rss, #u5) - hi->instruction = HEX_INS_RDD___VLSRW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrw (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x400040) { - // Instruction: 8: 10000000010sssssPP0iiiii010ddddd | Rdd = vaslw (Rss, #u5) - hi->instruction = HEX_INS_RDD___VASLW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslw (R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8c00040) { - // Instruction: 8: 10001000110sssssPP0iiiii010ddddd | Rd = vasrw (Rss, #u5) - hi->instruction = HEX_INS_RD___VASRW__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vasrw (R%d:R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - break; - } - case 0x9: { - if ((hi_u32 & 0x9e00000) == 0x1c00000) { - // Instruction: 9: 10010ii1110sssssPPiiiiiiiiiddddd | Rdd = memd (Rs + #s11:3) - hi->instruction = HEX_INS_RDD___MEMD__RS____S11_3_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 13)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 13); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 3); - sprintf(hi->mnem, "R%d:R%d = memd (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9c00000) { - // Instruction: 9: 10011001110xxxxxPPu0--0iiiiddddd | Rdd = memd (Rx ++ #s4:3:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMD__RX_____S4_3_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9c00200) { - // Instruction: 9: 10011001110xxxxxPPu0--1-0--ddddd | Rdd = memd (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMD__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xbc01000) { - // Instruction: 9: 10011011110eeeeePP01IIII-IIddddd | Rdd = memd (Re = #U6) - hi->instruction = HEX_INS_RDD___MEMD__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d:R%d = memd (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xbc00000) { - // Instruction: 9: 10011011110xxxxxPP00---iiiiddddd | Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_RDD___MEMD__RX_____S4_3_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xdc01000) { - // Instruction: 9: 10011101110tttttPPi1IIIIiIIddddd | Rdd = memd (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RDD___MEMD__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d:R%d = memd (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xdc00000) { - // Instruction: 9: 10011101110xxxxxPPu0----0--ddddd | Rdd = memd (Rx ++ Mu) - hi->instruction = HEX_INS_RDD___MEMD__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xfc00000) { - // Instruction: 9: 10011111110xxxxxPPu0----0--ddddd | Rdd = memd (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RDD___MEMD__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc02000) { - // Instruction: 9: 10011011110xxxxxPP100ttiiiiddddd | if (Pt) Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__PT__RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc02800) { - // Instruction: 9: 10011011110xxxxxPP101ttiiiiddddd | if !Pt Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__NOT_PT_RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc03000) { - // Instruction: 9: 10011011110xxxxxPP110ttiiiiddddd | if (Pt.new) Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__PT_NEW__RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xbc03800) { - // Instruction: 9: 10011011110xxxxxPP111ttiiiiddddd | if !Pt.new Rdd = memd (Rx ++ #s4:3) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RDD___MEMD__RX_____S4_3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled - if (hi->ops[3].op.imm & (1 << 6)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 6); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc02080) { - // Instruction: 9: 10011111110iiiiiPP100tti1--ddddd | if (Pt) Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__PT__RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc02880) { - // Instruction: 9: 10011111110iiiiiPP101tti1--ddddd | if !Pt Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc03080) { - // Instruction: 9: 10011111110iiiiiPP110tti1--ddddd | if (Pt.new) Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xfc03880) { - // Instruction: 9: 10011111110iiiiiPP111tti1--ddddd | if !Pt.new Rdd = memd (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RDD___MEMD___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d:R%d = memd (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1000000) { - // Instruction: 9: 10010ii1000sssssPPiiiiiiiiiddddd | Rd = memb (Rs + #s11:0) - hi->instruction = HEX_INS_RD___MEMB__RS____S11_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memb (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9000000) { - // Instruction: 9: 10011001000xxxxxPPu0--0iiiiddddd | Rd = memb (Rx ++ #s4:0:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMB__RX_____S4_0_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9000200) { - // Instruction: 9: 10011001000xxxxxPPu0--1-0--ddddd | Rd = memb (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMB__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb001000) { - // Instruction: 9: 10011011000eeeeePP01IIII-IIddddd | Rd = memb (Re = #U6) - hi->instruction = HEX_INS_RD___MEMB__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memb (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb000000) { - // Instruction: 9: 10011011000xxxxxPP00---iiiiddddd | Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_RD___MEMB__RX_____S4_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd001000) { - // Instruction: 9: 10011101000tttttPPi1IIIIiIIddddd | Rd = memb (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMB__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memb (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd000000) { - // Instruction: 9: 10011101000xxxxxPPu0----0--ddddd | Rd = memb (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMB__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf000000) { - // Instruction: 9: 10011111000xxxxxPPu0----0--ddddd | Rd = memb (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMB__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memb (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb002000) { - // Instruction: 9: 10011011000xxxxxPP100ttiiiiddddd | if (Pt) Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb002800) { - // Instruction: 9: 10011011000xxxxxPP101ttiiiiddddd | if !Pt Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb003000) { - // Instruction: 9: 10011011000xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb003800) { - // Instruction: 9: 10011011000xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memb (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memb (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf002080) { - // Instruction: 9: 10011111000iiiiiPP100tti1--ddddd | if (Pt) Rd = memb (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf002880) { - // Instruction: 9: 10011111000iiiiiPP101tti1--ddddd | if !Pt Rd = memb (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf003080) { - // Instruction: 9: 10011111000iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memb (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf003880) { - // Instruction: 9: 10011111000iiiiiPP111tti1--ddddd | if !Pt.new Rd = memb (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memb (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x800000) { - // Instruction: 9: 10010ii0100sssssPPiiiiiiiiiyyyyy | Ryy = memb_fifo (Rs + #s11:0) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RS____S11_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8800000) { - // Instruction: 9: 10011000100xxxxxPPu0--0iiiiyyyyy | Ryy = memb_fifo (Rx ++ #s4:0:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX_____S4_0_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8800200) { - // Instruction: 9: 10011000100xxxxxPPu0--1-0--yyyyy | Ryy = memb_fifo (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa801000) { - // Instruction: 9: 10011010100eeeeePP01IIII-IIyyyyy | Ryy = memb_fifo (Re = #U6) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa800000) { - // Instruction: 9: 10011010100xxxxxPP00---iiiiyyyyy | Ryy = memb_fifo (Rx ++ #s4:0) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX_____S4_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc801000) { - // Instruction: 9: 10011100100tttttPPi1IIIIiIIyyyyy | Ryy = memb_fifo (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc800000) { - // Instruction: 9: 10011100100xxxxxPPu0----0--yyyyy | Ryy = memb_fifo (Rx ++ Mu) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe800000) { - // Instruction: 9: 10011110100xxxxxPPu0----0--yyyyy | Ryy = memb_fifo (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RYY___MEMB_FIFO__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memb_fifo (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x400000) { - // Instruction: 9: 10010ii0010sssssPPiiiiiiiiiyyyyy | Ryy = memh_fifo (Rs + #s11:1) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8400000) { - // Instruction: 9: 10011000010xxxxxPPu0--0iiiiyyyyy | Ryy = memh_fifo (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8400200) { - // Instruction: 9: 10011000010xxxxxPPu0--1-0--yyyyy | Ryy = memh_fifo (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa401000) { - // Instruction: 9: 10011010010eeeeePP01IIII-IIyyyyy | Ryy = memh_fifo (Re = #U6) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa400000) { - // Instruction: 9: 10011010010xxxxxPP00---iiiiyyyyy | Ryy = memh_fifo (Rx ++ #s4:1) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc401000) { - // Instruction: 9: 10011100010tttttPPi1IIIIiIIyyyyy | Ryy = memh_fifo (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc400000) { - // Instruction: 9: 10011100010xxxxxPPu0----0--yyyyy | Ryy = memh_fifo (Rx ++ Mu) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe400000) { - // Instruction: 9: 10011110010xxxxxPPu0----0--yyyyy | Ryy = memh_fifo (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RYY___MEMH_FIFO__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memh_fifo (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1400000) { - // Instruction: 9: 10010ii1010sssssPPiiiiiiiiiddddd | Rd = memh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "R%d = memh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9400000) { - // Instruction: 9: 10011001010xxxxxPPu0--0iiiiddddd | Rd = memh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9400200) { - // Instruction: 9: 10011001010xxxxxPPu0--1-0--ddddd | Rd = memh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb401000) { - // Instruction: 9: 10011011010eeeeePP01IIII-IIddddd | Rd = memh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb400000) { - // Instruction: 9: 10011011010xxxxxPP00---iiiiddddd | Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd401000) { - // Instruction: 9: 10011101010tttttPPi1IIIIiIIddddd | Rd = memh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd400000) { - // Instruction: 9: 10011101010xxxxxPPu0----0--ddddd | Rd = memh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf400000) { - // Instruction: 9: 10011111010xxxxxPPu0----0--ddddd | Rd = memh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb402000) { - // Instruction: 9: 10011011010xxxxxPP100ttiiiiddddd | if (Pt) Pd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT__PD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) P%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.pred, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb402800) { - // Instruction: 9: 10011011010xxxxxPP101ttiiiiddddd | if !Pt Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb403000) { - // Instruction: 9: 10011011010xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb403800) { - // Instruction: 9: 10011011010xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf402080) { - // Instruction: 9: 10011111010iiiiiPP100tti1--ddddd | if (Pt) Rd = memh (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf402880) { - // Instruction: 9: 10011111010iiiiiPP101tti1--ddddd | if !Pt Rd = memh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf403080) { - // Instruction: 9: 10011111010iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memh (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf403880) { - // Instruction: 9: 10011111010iiiiiPP111tti1--ddddd | if !Pt.new Rd = memh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1200000) { - // Instruction: 9: 10010ii1001sssssPPiiiiiiiiiddddd | Rd = memub (Rs + #s11:0) - hi->instruction = HEX_INS_RD___MEMUB__RS____S11_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 10)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 10); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memub (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9200000) { - // Instruction: 9: 10011001001xxxxxPPu0--0iiiiddddd | Rd = memub (Rx ++ #s4:0:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUB__RX_____S4_0_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9200200) { - // Instruction: 9: 10011001001xxxxxPPu0--1-0--ddddd | Rd = memub (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUB__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb201000) { - // Instruction: 9: 10011011001eeeeePP01IIII-IIddddd | Rd = memub (Re = #U6) - hi->instruction = HEX_INS_RD___MEMUB__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memub (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb200000) { - // Instruction: 9: 10011011001xxxxxPP00---iiiiddddd | Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_RD___MEMUB__RX_____S4_0_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd201000) { - // Instruction: 9: 10011101001tttttPPi1IIIIiIIddddd | Rd = memub (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMUB__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memub (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd200000) { - // Instruction: 9: 10011101001xxxxxPPu0----0--ddddd | Rd = memub (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMUB__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf200000) { - // Instruction: 9: 10011111001xxxxxPPu0----0--ddddd | Rd = memub (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMUB__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memub (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb202000) { - // Instruction: 9: 10011011001xxxxxPP100ttiiiiddddd | if (Pt) Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT__RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb202800) { - // Instruction: 9: 10011011001xxxxxPP101ttiiiiddddd | if !Pt Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb203000) { - // Instruction: 9: 10011011001xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb203800) { - // Instruction: 9: 10011011001xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memub (Rx ++ #s4:0) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUB__RX_____S4_0_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); - if (hi->ops[3].op.imm & (1 << 3)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 3); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memub (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf202080) { - // Instruction: 9: 10011111001iiiiiPP100tti1--ddddd | if (Pt) Rd = memub (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf202880) { - // Instruction: 9: 10011111001iiiiiPP101tti1--ddddd | if !Pt Rd = memub (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf203080) { - // Instruction: 9: 10011111001iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memub (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf203880) { - // Instruction: 9: 10011111001iiiiiPP111tti1--ddddd | if !Pt.new Rd = memub (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUB___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memub (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1600000) { - // Instruction: 9: 10010ii1011sssssPPiiiiiiiiiddddd | Rd = memuh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMUH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 1); - sprintf(hi->mnem, "R%d = memuh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9600000) { - // Instruction: 9: 10011001011xxxxxPPu0--0iiiiddddd | Rd = memuh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9600200) { - // Instruction: 9: 10011001011xxxxxPPu0--1-0--ddddd | Rd = memuh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb601000) { - // Instruction: 9: 10011011011eeeeePP01IIII-IIddddd | Rd = memuh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMUH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memuh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb600000) { - // Instruction: 9: 10011011011xxxxxPP00---iiiiddddd | Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMUH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd601000) { - // Instruction: 9: 10011101011tttttPPi1IIIIiIIddddd | Rd = memuh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMUH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memuh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd600000) { - // Instruction: 9: 10011101011xxxxxPPu0----0--ddddd | Rd = memuh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMUH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf600000) { - // Instruction: 9: 10011111011xxxxxPPu0----0--ddddd | Rd = memuh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMUH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memuh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb602000) { - // Instruction: 9: 10011011011xxxxxPP100ttiiiiddddd | if (Pt) Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT__RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb602800) { - // Instruction: 9: 10011011011xxxxxPP101ttiiiiddddd | if !Pt Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb603000) { - // Instruction: 9: 10011011011xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb603800) { - // Instruction: 9: 10011011011xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memuh (Rx ++ #s4:1) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUH__RX_____S4_1_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[3].op.imm & (1 << 4)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memuh (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf602080) { - // Instruction: 9: 10011111011iiiiiPP100tti1--ddddd | if (Pt) Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf602880) { - // Instruction: 9: 10011111011iiiiiPP101tti1--ddddd | if !Pt Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf603080) { - // Instruction: 9: 10011111011iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf603880) { - // Instruction: 9: 10011111011iiiiiPP111tti1--ddddd | if !Pt.new Rd = memuh (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMUH___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memuh (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1800000) { - // Instruction: 9: 10010ii1100sssssPPiiiiiiiiiddddd | Rd = memw (Rs + #s11:2) - hi->instruction = HEX_INS_RD___MEMW__RS____S11_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 12)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 12); - } - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[2], 2); - sprintf(hi->mnem, "R%d = memw (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x9800000) { - // Instruction: 9: 10011001100xxxxxPPu0--0iiiiddddd | Rd = memw (Rx ++ #s4:2:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMW__RX_____S4_2_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x9800200) { - // Instruction: 9: 10011001100xxxxxPPu0--1-0--ddddd | Rd = memw (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMW__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb801000) { - // Instruction: 9: 10011011100eeeeePP01IIII-IIddddd | Rd = memw (Re = #U6) - hi->instruction = HEX_INS_RD___MEMW__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memw (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xb800000) { - // Instruction: 9: 10011011100xxxxxPP00---iiiiddddd | Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_RD___MEMW__RX_____S4_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xd801000) { - // Instruction: 9: 10011101100tttttPPi1IIIIiIIddddd | Rd = memw (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMW__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = memw (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xd800000) { - // Instruction: 9: 10011101100xxxxxPPu0----0--ddddd | Rd = memw (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMW__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xf800000) { - // Instruction: 9: 10011111100xxxxxPPu0----0--ddddd | Rd = memw (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMW__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb802000) { - // Instruction: 9: 10011011100xxxxxPP100ttiiiiddddd | if (Pt) Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__PT__RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE; // if (Pt) - sprintf(hi->mnem, "if (P%d) R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb802800) { - // Instruction: 9: 10011011100xxxxxPP101ttiiiiddddd | if !Pt Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE; // if !Pt - sprintf(hi->mnem, "if !P%d R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb803000) { - // Instruction: 9: 10011011100xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - sprintf(hi->mnem, "if (P%d.new) R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03800) == 0xb803800) { - // Instruction: 9: 10011011100xxxxxPP111ttiiiiddddd | if !Pt.new Rd = memw (Rx ++ #s4:2) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMW__RX_____S4_2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - sprintf(hi->mnem, "if !P%d.new R%d = memw (R%d ++ %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf802080) { - // Instruction: 9: 10011111100iiiiiPP100tti1--ddddd | if (Pt) Rd = memw (#u6) - hi->instruction = HEX_INS_IF__PT__RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE; // if (Pt) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d) R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf802880) { - // Instruction: 9: 10011111100iiiiiPP101tti1--ddddd | if !Pt Rd = memw (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE; // if !Pt - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf803080) { - // Instruction: 9: 10011111100iiiiiPP110tti1--ddddd | if (Pt.new) Rd = memw (#u6) - hi->instruction = HEX_INS_IF__PT_NEW__RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pt.new) - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if (P%d.new) R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03880) == 0xf803880) { - // Instruction: 9: 10011111100iiiiiPP111tti1--ddddd | if !Pt.new Rd = memw (#u6) - hi->instruction = HEX_INS_IF__NOT_PT_NEW_RD___MEMW___U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x600) >> 9); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x100) >> 8)); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pt.new - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "if !P%d.new R%d = memw (0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfff201f) == 0x1e001e) { - // Instruction: 9: 1001000000011110PP0--------11110 | deallocframe - hi->instruction = HEX_INS_DEALLOCFRAME; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "deallocframe"); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e001e) { - // Instruction: 9: 1001011000011110PP0000-----11110 | dealloc_return - hi->instruction = HEX_INS_DEALLOC_RETURN; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dealloc_return"); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e081e) { - // Instruction: 9: 1001011000011110PP0010ss---11110 | if (Ps.new) dealloc_return:nt - hi->instruction = HEX_INS_IF__PS_NEW__DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (P%d.new) dealloc_return:nt", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e101e) { - // Instruction: 9: 1001011000011110PP0100ss---11110 | if (Ps) dealloc_return - hi->instruction = HEX_INS_IF__PS__DEALLOC_RETURN; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (P%d) dealloc_return", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e181e) { - // Instruction: 9: 1001011000011110PP0110ss---11110 | if (Ps.new) dealloc_return:t - hi->instruction = HEX_INS_IF__PS_NEW__DEALLOC_RETURN_T; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if (P%d.new) dealloc_return:t", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e281e) { - // Instruction: 9: 1001011000011110PP1010ss---11110 | if !Ps.new dealloc_return:nt - hi->instruction = HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_NT; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if !P%d.new dealloc_return:nt", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e301e) { - // Instruction: 9: 1001011000011110PP1100ss---11110 | if !Ps dealloc_return - hi->instruction = HEX_INS_IF__NOT_PS_DEALLOC_RETURN; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if !P%d dealloc_return", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0xfff3c1f) == 0x61e381e) { - // Instruction: 9: 1001011000011110PP1110ss---11110 | if !Ps.new dealloc_return:t - hi->instruction = HEX_INS_IF__NOT_PS_NEW_DEALLOC_RETURN_T; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x300) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "if !P%d.new dealloc_return:t", hi->ops[0].op.pred); - break; - } - if ((hi_u32 & 0x9e00000) == 0x200000) { - // Instruction: 9: 10010ii0001sssssPPiiiiiiiiiddddd | Rd = membh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMBH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0x600000) { - // Instruction: 9: 10010ii0011sssssPPiiiiiiiiiddddd | Rd = memubh (Rs + #s11:1) - hi->instruction = HEX_INS_RD___MEMUBH__RS____S11_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 11)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 11); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d + %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0xa00000) { - // Instruction: 9: 10010ii0101sssssPPiiiiiiiiiddddd | Rdd = memubh (Rs + #s11:2) - hi->instruction = HEX_INS_RDD___MEMUBH__RS____S11_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 12)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 12); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0x9e00000) == 0xe00000) { - // Instruction: 9: 10010ii0111sssssPPiiiiiiiiiddddd | Rdd = membh (Rs + #s11:2) - hi->instruction = HEX_INS_RDD___MEMBH__RS____S11_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x3fe0) >> 5)) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 12)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 12); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d + %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8200000) { - // Instruction: 9: 10011000001xxxxxPPu0--0iiiiddddd | Rd = membh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMBH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8200200) { - // Instruction: 9: 10011000001xxxxxPPu0--1-0--ddddd | Rd = membh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8600000) { - // Instruction: 9: 10011000011xxxxxPPu0--0iiiiddddd | Rd = memubh (Rx ++ #s4:1:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUBH__RX_____S4_1_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8600200) { - // Instruction: 9: 10011000011xxxxxPPu0--1-0--ddddd | Rd = memubh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RD___MEMUBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8a00000) { - // Instruction: 9: 10011000101xxxxxPPu0--0iiiiddddd | Rdd = memubh (Rx ++ #s4:2:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMUBH__RX_____S4_2_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8a00200) { - // Instruction: 9: 10011000101xxxxxPPu0--1-0--ddddd | Rdd = memubh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMUBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01200) == 0x8e00000) { - // Instruction: 9: 10011000111xxxxxPPu0--0iiiiddddd | Rdd = membh (Rx ++ #s4:2:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMBH__RX_____S4_2_CIRC__MU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ %d:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01280) == 0x8e00200) { - // Instruction: 9: 10011000111xxxxxPPu0--1-0--ddddd | Rdd = membh (Rx ++ I:circ (Mu)) - hi->instruction = HEX_INS_RDD___MEMBH__RX____I_CIRC__MU__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ I:circ (R%d))", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa201000) { - // Instruction: 9: 10011010001eeeeePP01IIII-IIddddd | Rd = membh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa200000) { - // Instruction: 9: 10011010001xxxxxPP00---iiiiddddd | Rd = membh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMBH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa601000) { - // Instruction: 9: 10011010011eeeeePP01IIII-IIddddd | Rd = memubh (Re = #U6) - hi->instruction = HEX_INS_RD___MEMUBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d = 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xa600000) { - // Instruction: 9: 10011010011xxxxxPP00---iiiiddddd | Rd = memubh (Rx ++ #s4:1) - hi->instruction = HEX_INS_RD___MEMUBH__RX_____S4_1_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xaa01000) { - // Instruction: 9: 10011010101eeeeePP01IIII-IIddddd | Rdd = memubh (Re = #U6) - hi->instruction = HEX_INS_RDD___MEMUBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xaa00000) { - // Instruction: 9: 10011010101xxxxxPP00---iiiiddddd | Rdd = memubh (Rx ++ #s4:2) - hi->instruction = HEX_INS_RDD___MEMUBH__RX_____S4_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xae01000) { - // Instruction: 9: 10011010111eeeeePP01IIII-IIddddd | Rdd = membh (Re = #U6) - hi->instruction = HEX_INS_RDD___MEMBH__RE____U6_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d = 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe03000) == 0xae00000) { - // Instruction: 9: 10011010111xxxxxPP00---iiiiddddd | Rdd = membh (Rx ++ #s4:2) - hi->instruction = HEX_INS_RDD___MEMBH__RX_____S4_2_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ %d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc201000) { - // Instruction: 9: 10011100001tttttPPi1IIIIiIIddddd | Rd = membh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc200000) { - // Instruction: 9: 10011100001xxxxxPPu0----0--ddddd | Rd = membh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01000) == 0xc601000) { - // Instruction: 9: 10011100011tttttPPi1IIIIiIIddddd | Rd = memubh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RD___MEMUBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xc600000) { - // Instruction: 9: 10011100011xxxxxPPu0----0--ddddd | Rd = memubh (Rx ++ Mu) - hi->instruction = HEX_INS_RD___MEMUBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01000) == 0xca01000) { - // Instruction: 9: 10011100101tttttPPi1IIIIiIIddddd | Rdd = memubh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RDD___MEMUBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xca00000) { - // Instruction: 9: 10011100101xxxxxPPu0----0--ddddd | Rdd = memubh (Rx ++ Mu) - hi->instruction = HEX_INS_RDD___MEMUBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01000) == 0xce01000) { - // Instruction: 9: 10011100111tttttPPi1IIIIiIIddddd | Rdd = membh (Rt << #u2 + #U6) - hi->instruction = HEX_INS_RDD___MEMBH__RT_____U2____U6_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x80) >> 7)); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0xf00) >> 6) | ((hi_u32 & 0x60) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d << 0x%x + 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe01080) == 0xce00000) { - // Instruction: 9: 10011100111xxxxxPPu0----0--ddddd | Rdd = membh (Rx ++ Mu) - hi->instruction = HEX_INS_RDD___MEMBH__RX____MU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe200000) { - // Instruction: 9: 10011110001xxxxxPPu0----0--ddddd | Rd = membh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = membh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xe600000) { - // Instruction: 9: 10011110011xxxxxPPu0----0--ddddd | Rd = memubh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RD___MEMUBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memubh (R%d ++ R%d:brev)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xea00000) { - // Instruction: 9: 10011110101xxxxxPPu0----0--ddddd | Rdd = memubh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RDD___MEMUBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memubh (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01080) == 0xee00000) { - // Instruction: 9: 10011110111xxxxxPPu0----0--ddddd | Rdd = membh (Rx ++ Mu:brev) - hi->instruction = HEX_INS_RDD___MEMBH__RX____MU_BREV_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = membh (R%d ++ R%d:brev)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02020) == 0x2002000) { - // Instruction: 9: 10010010000sssssPP1ttttt--0ddddd | Rd = memw_phys (Rs, Rt) - hi->instruction = HEX_INS_RD___MEMW_PHYS__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw_phys (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03020) == 0x2000000) { - // Instruction: 9: 10010010000sssssPP00------0ddddd | Rd = memw_locked (Rs) - hi->instruction = HEX_INS_RD___MEMW_LOCKED__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = memw_locked (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe03020) == 0x2001000) { - // Instruction: 9: 10010010000sssssPP01------0ddddd | Rdd = memd_locked (Rs) - hi->instruction = HEX_INS_RDD___MEMD_LOCKED__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = memd_locked (R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x4000000) { - // Instruction: 9: 10010100000sssssPP0--iiiiiiiiiii | dcfetch (Rs + #u11:3) - hi->instruction = HEX_INS_DCFETCH__RS____U11_3_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x7ff) >> 0) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dcfetch (R%d + 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - break; - } - case 0xa: { - if ((hi_u32 & 0x9e01800) == 0x1a00000) { - // Instruction: 10: 10100ii1101sssssPPi00tttiiiiiiii | memb (Rs + #s11:0) = Nt.new - hi->instruction = HEX_INS_MEMB__RS____S11_0____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d + %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00002) { - // Instruction: 10: 10101001101xxxxxPPu00ttt0-----1- | memb (Rx ++ I:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMB__RX____I_CIRC__MU_____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00000) { - // Instruction: 10: 10101001101xxxxxPPu00ttt0iiii-0- | memb (Rx ++ #s4:0:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMB__RX_____S4_0_CIRC__MU_____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03880) == 0xba00080) { - // Instruction: 10: 10101011101eeeeePP000ttt1-IIIIII | memb (Re = #U6) = Nt.new - hi->instruction = HEX_INS_MEMB__RE____U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03882) == 0xba00000) { - // Instruction: 10: 10101011101xxxxxPP000ttt0iiii-0- | memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00080) { - // Instruction: 10: 10101101101uuuuuPPi00ttt1iIIIIII | memb (Ru << #u2 + #U6) = Nt.new - hi->instruction = HEX_INS_MEMB__RU_____U2____U6____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00000) { - // Instruction: 10: 10101101101xxxxxPPu00ttt0------- | memb (Rx ++ Mu) = Nt.new - hi->instruction = HEX_INS_MEMB__RX____MU____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xfa00000) { - // Instruction: 10: 10101111101xxxxxPPu00ttt0------- | memb (Rx ++ Mu:brev) = Nt.new - hi->instruction = HEX_INS_MEMB__RX____MU_BREV____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02000) { - // Instruction: 10: 10101011101xxxxxPP100ttt0iiii0vv | if (Pv) memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02004) { - // Instruction: 10: 10101011101xxxxxPP100ttt0iiii1vv | if !Pv memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02080) { - // Instruction: 10: 10101011101xxxxxPP100ttt1iiii0vv | if (Pv.new) memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02084) { - // Instruction: 10: 10101011101xxxxxPP100ttt1iiii1vv | if !Pv.new memb (Rx ++ #s4:0) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RX_____S4_0____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00080) { - // Instruction: 10: 10101111101---iiPP000ttt1iiii0vv | if (Pv) memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00084) { - // Instruction: 10: 10101111101---iiPP000ttt1iiii1vv | if !Pv memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02080) { - // Instruction: 10: 10101111101---iiPP100ttt1iiii0vv | if (Pv.new) memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02084) { - // Instruction: 10: 10101111101---iiPP100ttt1iiii1vv | if !Pv.new memb (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x1a00800) { - // Instruction: 10: 10100ii1101sssssPPi01tttiiiiiiii | memh (Rs + #s11:1) = Nt.new - hi->instruction = HEX_INS_MEMH__RS____S11_1____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 11)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 11); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 1); - sprintf(hi->mnem, "memh (R%d + %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00802) { - // Instruction: 10: 10101001101xxxxxPPu01ttt0-----1- | memh (Rx ++ I:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMH__RX____I_CIRC__MU_____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a00800) { - // Instruction: 10: 10101001101xxxxxPPu01ttt0iiii-0- | memh (Rx ++ #s4:1:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMH__RX_____S4_1_CIRC__MU_____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03880) == 0xba00880) { - // Instruction: 10: 10101011101eeeeePP001ttt1-IIIIII | memh (Re = #U6) = Nt.new - hi->instruction = HEX_INS_MEMH__RE____U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03882) == 0xba00800) { - // Instruction: 10: 10101011101xxxxxPP001ttt0iiii-0- | memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00880) { - // Instruction: 10: 10101101101uuuuuPPi01ttt1iIIIIII | memh (Ru << #u2 + #U6) = Nt.new - hi->instruction = HEX_INS_MEMH__RU_____U2____U6____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memh (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda00800) { - // Instruction: 10: 10101101101xxxxxPPu01ttt0------- | memh (Rx ++ Mu) = Nt.new - hi->instruction = HEX_INS_MEMH__RX____MU____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xfa00800) { - // Instruction: 10: 10101111101xxxxxPPu01ttt0------- | memh (Rx ++ Mu:brev) = Nt.new - hi->instruction = HEX_INS_MEMH__RX____MU_BREV____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02800) { - // Instruction: 10: 10101011101xxxxxPP101ttt0iiii0vv | if (Pv) memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02804) { - // Instruction: 10: 10101011101xxxxxPP101ttt0iiii1vv | if !Pv memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02880) { - // Instruction: 10: 10101011101xxxxxPP101ttt1iiii0vv | if (Pv.new) memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba02884) { - // Instruction: 10: 10101011101xxxxxPP101ttt1iiii1vv | if !Pv.new memh (Rx ++ #s4:1) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RX_____S4_1____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00880) { - // Instruction: 10: 10101111101---iiPP001ttt1iiii0vv | if (Pv) memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa00884) { - // Instruction: 10: 10101111101---iiPP001ttt1iiii1vv | if !Pv memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02880) { - // Instruction: 10: 10101111101---iiPP101ttt1iiii0vv | if (Pv.new) memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa02884) { - // Instruction: 10: 10101111101---iiPP101ttt1iiii1vv | if !Pv.new memh (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e01800) == 0x1a01000) { - // Instruction: 10: 10100ii1101sssssPPi10tttiiiiiiii | memw (Rs + #s11:2) = Nt.new - hi->instruction = HEX_INS_MEMW__RS____S11_2____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 12)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 12); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "memw (R%d + %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a01002) { - // Instruction: 10: 10101001101xxxxxPPu10ttt0-----1- | memw (Rx ++ I:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMW__RX____I_CIRC__MU_____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01882) == 0x9a01000) { - // Instruction: 10: 10101001101xxxxxPPu10ttt0iiii-0- | memw (Rx ++ #s4:2:circ (Mu)) = Nt.new - hi->instruction = HEX_INS_MEMW__RX_____S4_2_CIRC__MU_____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03880) == 0xba01080) { - // Instruction: 10: 10101011101eeeeePP010ttt1-IIIIII | memw (Re = #U6) = Nt.new - hi->instruction = HEX_INS_MEMW__RE____U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03882) == 0xba01000) { - // Instruction: 10: 10101011101xxxxxPP010ttt0iiii-0- | memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda01080) { - // Instruction: 10: 10101101101uuuuuPPi10ttt1iIIIIII | memw (Ru << #u2 + #U6) = Nt.new - hi->instruction = HEX_INS_MEMW__RU_____U2____U6____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memw (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xda01000) { - // Instruction: 10: 10101101101xxxxxPPu10ttt0------- | memw (Rx ++ Mu) = Nt.new - hi->instruction = HEX_INS_MEMW__RX____MU____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01880) == 0xfa01000) { - // Instruction: 10: 10101111101xxxxxPPu10ttt0------- | memw (Rx ++ Mu:brev) = Nt.new - hi->instruction = HEX_INS_MEMW__RX____MU_BREV____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03000) { - // Instruction: 10: 10101011101xxxxxPP110ttt0iiii0vv | if (Pv) memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03004) { - // Instruction: 10: 10101011101xxxxxPP110ttt0iiii1vv | if !Pv memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03080) { - // Instruction: 10: 10101011101xxxxxPP110ttt1iiii0vv | if (Pv.new) memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xba03084) { - // Instruction: 10: 10101011101xxxxxPP110ttt1iiii1vv | if !Pv.new memw (Rx ++ #s4:2) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RX_____S4_2____NT_NEW; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa01080) { - // Instruction: 10: 10101111101---iiPP010ttt1iiii0vv | if (Pv) memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV__MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa01084) { - // Instruction: 10: 10101111101---iiPP010ttt1iiii1vv | if !Pv memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa03080) { - // Instruction: 10: 10101111101---iiPP110ttt1iiii0vv | if (Pv.new) memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__PV_NEW__MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d.new) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe03884) == 0xfa03084) { - // Instruction: 10: 10101111101---iiPP110ttt1iiii1vv | if !Pv.new memw (#u6) = Nt.new - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW___U6____NT_NEW; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt.new - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d.new memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1c00000) { - // Instruction: 10: 10100ii1110sssssPPitttttiiiiiiii | memd (Rs + #s11:3) = Rtt - hi->instruction = HEX_INS_MEMD__RS____S11_3____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 13)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 13); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 3); - sprintf(hi->mnem, "memd (R%d + %d) = R%d:R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9c00002) { - // Instruction: 10: 10101001110xxxxxPPuttttt0-----1- | memd (Rx ++ I:circ (Mu)) = Rtt - hi->instruction = HEX_INS_MEMD__RX____I_CIRC__MU_____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ I:circ (R%d)) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9c00000) { - // Instruction: 10: 10101001110xxxxxPPuttttt0iiii-0- | memd (Rx ++ #s4:3:circ (Mu)) = Rtt - hi->instruction = HEX_INS_MEMD__RX_____S4_3_CIRC__MU_____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ %d:circ (R%d)) = R%d:R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xbc00080) { - // Instruction: 10: 10101011110eeeeePP0ttttt1-IIIIII | memd (Re = #U6) = Rtt - hi->instruction = HEX_INS_MEMD__RE____U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memd (R%d = 0x%x) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xbc00000) { - // Instruction: 10: 10101011110xxxxxPP0ttttt0iiii-0- | memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_MEMD__RX_____S4_3____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled - if (hi->ops[1].op.imm & (1 << 6)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xdc00080) { - // Instruction: 10: 10101101110uuuuuPPittttt1iIIIIII | memd (Ru << #u2 + #U6) = Rtt - hi->instruction = HEX_INS_MEMD__RU_____U2____U6____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memd (R%d << 0x%x + 0x%x) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xdc00000) { - // Instruction: 10: 10101101110xxxxxPPuttttt0------- | memd (Rx ++ Mu) = Rtt - hi->instruction = HEX_INS_MEMD__RX____MU____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ R%d) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xfc00000) { - // Instruction: 10: 10101111110xxxxxPPuttttt0------- | memd (Rx ++ Mu:brev) = Rtt - hi->instruction = HEX_INS_MEMD__RX____MU_BREV____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd (R%d ++ R%d:brev) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02000) { - // Instruction: 10: 10101011110xxxxxPP1ttttt0iiii0vv | if (Pv) memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02004) { - // Instruction: 10: 10101011110xxxxxPP1ttttt0iiii1vv | if !Pv memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02080) { - // Instruction: 10: 10101011110xxxxxPP1ttttt1iiii0vv | if (Pv.new) memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xbc02084) { - // Instruction: 10: 10101011110xxxxxPP1ttttt1iiii1vv | if !Pv.new memd (Rx ++ #s4:3) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD__RX_____S4_3____RTT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled - if (hi->ops[2].op.imm & (1 << 6)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 6); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memd (R%d ++ %d) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc00080) { - // Instruction: 10: 10101111110---iiPP0ttttt1iiii0vv | if (Pv) memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__PV__MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc00084) { - // Instruction: 10: 10101111110---iiPP0ttttt1iiii1vv | if !Pv memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc02080) { - // Instruction: 10: 10101111110---iiPP1ttttt1iiii0vv | if (Pv.new) memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__PV_NEW__MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xfc02084) { - // Instruction: 10: 10101111110---iiPP1ttttt1iiii1vv | if !Pv.new memd (#u6) = Rtt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMD___U6____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memd (0x%x) = R%d:R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1000000) { - // Instruction: 10: 10100ii1000sssssPPitttttiiiiiiii | memb (Rs + #s11:0) = Rt - hi->instruction = HEX_INS_MEMB__RS____S11_0____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)); - if (hi->ops[1].op.imm & (1 << 10)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 10); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d + %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9000002) { - // Instruction: 10: 10101001000xxxxxPPuttttt0-----1- | memb (Rx ++ I:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMB__RX____I_CIRC__MU_____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9000000) { - // Instruction: 10: 10101001000xxxxxPPuttttt0iiii-0- | memb (Rx ++ #s4:0:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMB__RX_____S4_0_CIRC__MU_____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb000080) { - // Instruction: 10: 10101011000eeeeePP0ttttt1-IIIIII | memb (Re = #U6) = Rt - hi->instruction = HEX_INS_MEMB__RE____U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb000000) { - // Instruction: 10: 10101011000xxxxxPP0ttttt0iiii-0- | memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_MEMB__RX_____S4_0____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[1].op.imm & (1 << 3)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd000080) { - // Instruction: 10: 10101101000uuuuuPPittttt1iIIIIII | memb (Ru << #u2 + #U6) = Rt - hi->instruction = HEX_INS_MEMB__RU_____U2____U6____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memb (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd000000) { - // Instruction: 10: 10101101000xxxxxPPuttttt0------- | memb (Rx ++ Mu) = Rt - hi->instruction = HEX_INS_MEMB__RX____MU____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf000000) { - // Instruction: 10: 10101111000xxxxxPPuttttt0------- | memb (Rx ++ Mu:brev) = Rt - hi->instruction = HEX_INS_MEMB__RX____MU_BREV____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memb (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002000) { - // Instruction: 10: 10101011000xxxxxPP1ttttt0iiii0vv | if (Pv) memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002004) { - // Instruction: 10: 10101011000xxxxxPP1ttttt0iiii1vv | if !Pv memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002080) { - // Instruction: 10: 10101011000xxxxxPP1ttttt1iiii0vv | if (Pv.new) memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb002084) { - // Instruction: 10: 10101011000xxxxxPP1ttttt1iiii1vv | if !Pv.new memb (Rx ++ #s4:0) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB__RX_____S4_0____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); - if (hi->ops[2].op.imm & (1 << 3)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 3); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf000080) { - // Instruction: 10: 10101111000---iiPP0ttttt1iiii0vv | if (Pv) memb (#u6) = Rt - hi->instruction = HEX_INS_IF__PV__MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf000084) { - // Instruction: 10: 10101111000---iiPP0ttttt1iiii1vv | if !Pv memb (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf002080) { - // Instruction: 10: 10101111000---iiPP1ttttt1iiii0vv | if (Pv.new) memb (#u6) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf002084) { - // Instruction: 10: 10101111000---iiPP1ttttt1iiii1vv | if !Pv.new memb (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMB___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memb (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1400000) { - // Instruction: 10: 10100ii1010sssssPPitttttiiiiiiii | memh (Rs + #s11:1) = Rt - hi->instruction = HEX_INS_MEMH__RS____S11_1____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 11)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 11); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 1); - sprintf(hi->mnem, "memh (R%d + %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1600000) { - // Instruction: 10: 10100ii1011sssssPPitttttiiiiiiii | memh (Rs + #s11:1) = Rt.H - hi->instruction = HEX_INS_MEMH__RS____S11_1____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 11)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 11); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d + %d) = R%d.H", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9400002) { - // Instruction: 10: 10101001010xxxxxPPuttttt0-----1- | memh (Rx ++ I:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMH__RX____I_CIRC__MU_____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9400000) { - // Instruction: 10: 10101001010xxxxxPPuttttt0iiii-0- | memh (Rx ++ #s4:1:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMH__RX_____S4_1_CIRC__MU_____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9600002) { - // Instruction: 10: 10101001011xxxxxPPuttttt0-----1- | memh (Rx ++ I:circ (Mu)) = Rt.H - hi->instruction = HEX_INS_MEMH__RX____I_CIRC__MU_____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ I:circ (R%d)) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9600000) { - // Instruction: 10: 10101001011xxxxxPPuttttt0iiii-0- | memh (Rx ++ #s4:1:circ (Mu)) = Rt.H - hi->instruction = HEX_INS_MEMH__RX_____S4_1_CIRC__MU_____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d:circ (R%d)) = R%d.H", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb400080) { - // Instruction: 10: 10101011010eeeeePP0ttttt1-IIIIII | memh (Re = #U6) = Rt - hi->instruction = HEX_INS_MEMH__RE____U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memh (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb400000) { - // Instruction: 10: 10101011010xxxxxPP0ttttt0iiii-0- | memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_MEMH__RX_____S4_1____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb600080) { - // Instruction: 10: 10101011011eeeeePP0ttttt1-IIIIII | memh (Re = #U6) = Rt.H - hi->instruction = HEX_INS_MEMH__RE____U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d = 0x%x) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb600000) { - // Instruction: 10: 10101011011xxxxxPP0ttttt0iiii-0- | memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_MEMH__RX_____S4_1____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[1].op.imm & (1 << 4)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ %d) = R%d.H", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd400080) { - // Instruction: 10: 10101101010uuuuuPPittttt1iIIIIII | memh (Ru << #u2 + #U6) = Rt - hi->instruction = HEX_INS_MEMH__RU_____U2____U6____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memh (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd400000) { - // Instruction: 10: 10101101010xxxxxPPuttttt0------- | memh (Rx ++ Mu) = Rt - hi->instruction = HEX_INS_MEMH__RX____MU____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd600080) { - // Instruction: 10: 10101101011uuuuuPPittttt1iIIIIII | memh (Ru << #u2 + #U6) = Rt.H - hi->instruction = HEX_INS_MEMH__RU_____U2____U6____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d << 0x%x + 0x%x) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd600000) { - // Instruction: 10: 10101101011xxxxxPPuttttt0------- | memh (Rx ++ Mu) = Rt.H - hi->instruction = HEX_INS_MEMH__RX____MU____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf400000) { - // Instruction: 10: 10101111010xxxxxPPuttttt0------- | memh (Rx ++ Mu:brev) = Rt - hi->instruction = HEX_INS_MEMH__RX____MU_BREV____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf600000) { - // Instruction: 10: 10101111011xxxxxPPuttttt0------- | memh (Rx ++ Mu:brev) = Rt.H - hi->instruction = HEX_INS_MEMH__RX____MU_BREV____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memh (R%d ++ R%d:brev) = R%d.H", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402000) { - // Instruction: 10: 10101011010xxxxxPP1ttttt0iiii0vv | if (Pv) memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402004) { - // Instruction: 10: 10101011010xxxxxPP1ttttt0iiii1vv | if !Pv memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402080) { - // Instruction: 10: 10101011010xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb402084) { - // Instruction: 10: 10101011010xxxxxPP1ttttt1iiii1vv | if !Pv.new memh (Rx ++ #s4:1) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RX_____S4_1____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602000) { - // Instruction: 10: 10101011011xxxxxPP1ttttt0iiii0vv | if (Pv) memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602004) { - // Instruction: 10: 10101011011xxxxxPP1ttttt0iiii1vv | if !Pv memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602080) { - // Instruction: 10: 10101011011xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb602084) { - // Instruction: 10: 10101011011xxxxxPP1ttttt1iiii1vv | if !Pv.new memh (Rx ++ #s4:1) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH__RX_____S4_1____RT_H; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled - if (hi->ops[2].op.imm & (1 << 4)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 4); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (R%d ++ %d) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf400080) { - // Instruction: 10: 10101111010---iiPP0ttttt1iiii0vv | if (Pv) memh (#u6) = Rt - hi->instruction = HEX_INS_IF__PV__MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf400084) { - // Instruction: 10: 10101111010---iiPP0ttttt1iiii1vv | if !Pv memh (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf402080) { - // Instruction: 10: 10101111010---iiPP1ttttt1iiii0vv | if (Pv.new) memh (#u6) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf402084) { - // Instruction: 10: 10101111010---iiPP1ttttt1iiii1vv | if !Pv.new memh (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf600080) { - // Instruction: 10: 10101111011---iiPP0ttttt1iiii0vv | if (Pv) memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__PV__MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf600084) { - // Instruction: 10: 10101111011---iiPP0ttttt1iiii1vv | if !Pv memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf602080) { - // Instruction: 10: 10101111011---iiPP1ttttt1iiii0vv | if (Pv.new) memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__PV_NEW__MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf602084) { - // Instruction: 10: 10101111011---iiPP1ttttt1iiii1vv | if !Pv.new memh (#u6) = Rt.H - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMH___U6____RT_H; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memh (0x%x) = R%d.H", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0x9e00000) == 0x1800000) { - // Instruction: 10: 10100ii1100sssssPPitttttiiiiiiii | memw (Rs + #s11:2) = Rt - hi->instruction = HEX_INS_MEMW__RS____S11_2____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x6000000) >> 16) | ((hi_u32 & 0x2000) >> 5) | ((hi_u32 & 0xff) >> 0)) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 12)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 12); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend_off(&hi->ops[1], 2); - sprintf(hi->mnem, "memw (R%d + %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9800002) { - // Instruction: 10: 10101001100xxxxxPPuttttt0-----1- | memw (Rx ++ I:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMW__RX____I_CIRC__MU_____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ I:circ (R%d)) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00082) == 0x9800000) { - // Instruction: 10: 10101001100xxxxxPPuttttt0iiii-0- | memw (Rx ++ #s4:2:circ (Mu)) = Rt - hi->instruction = HEX_INS_MEMW__RX_____S4_2_CIRC__MU_____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d:circ (R%d)) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xb800080) { - // Instruction: 10: 10101011100eeeeePP0ttttt1-IIIIII | memw (Re = #U6) = Rt - hi->instruction = HEX_INS_MEMW__RE____U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memw (R%d = 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02082) == 0xb800000) { - // Instruction: 10: 10101011100xxxxxPP0ttttt0iiii-0- | memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_MEMW__RX_____S4_2____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ %d) = R%d", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd800080) { - // Instruction: 10: 10101101100uuuuuPPittttt1iIIIIII | memw (Ru << #u2 + #U6) = Rt - hi->instruction = HEX_INS_MEMW__RU_____U2____U6____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x40) >> 6)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "memw (R%d << 0x%x + 0x%x) = R%d", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xd800000) { - // Instruction: 10: 10101101100xxxxxPPuttttt0------- | memw (Rx ++ Mu) = Rt - hi->instruction = HEX_INS_MEMW__RX____MU____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0xf800000) { - // Instruction: 10: 10101111100xxxxxPPuttttt0------- | memw (Rx ++ Mu:brev) = Rt - hi->instruction = HEX_INS_MEMW__RX____MU_BREV____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw (R%d ++ R%d:brev) = R%d", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802000) { - // Instruction: 10: 10101011100xxxxxPP1ttttt0iiii0vv | if (Pv) memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - sprintf(hi->mnem, "if (P%d) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802004) { - // Instruction: 10: 10101011100xxxxxPP1ttttt0iiii1vv | if !Pv memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - sprintf(hi->mnem, "if !P%d memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802080) { - // Instruction: 10: 10101011100xxxxxPP1ttttt1iiii0vv | if (Pv.new) memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - sprintf(hi->mnem, "if (P%d.new) memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xb802084) { - // Instruction: 10: 10101011100xxxxxPP1ttttt1iiii1vv | if !Pv.new memw (Rx ++ #s4:2) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW__RX_____S4_2____RT; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - sprintf(hi->mnem, "if !P%d.new memw (R%d ++ %d) = R%d", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf800080) { - // Instruction: 10: 10101111100---iiPP0ttttt1iiii0vv | if (Pv) memw (#u6) = Rt - hi->instruction = HEX_INS_IF__PV__MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pv) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf800084) { - // Instruction: 10: 10101111100---iiPP0ttttt1iiii1vv | if !Pv memw (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pv - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf802080) { - // Instruction: 10: 10101111100---iiPP1ttttt1iiii0vv | if (Pv.new) memw (#u6) = Rt - hi->instruction = HEX_INS_IF__PV_NEW__MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pv.new) - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if (P%d.new) memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02084) == 0xf802084) { - // Instruction: 10: 10101111100---iiPP1ttttt1iiii1vv | if !Pv.new memw (#u6) = Rt - hi->instruction = HEX_INS_IF__NOT_PV_NEW_MEMW___U6____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x30000) >> 12) | ((hi_u32 & 0x78) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pv.new - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "if !P%d.new memw (0x%x) = R%d", hi->ops[0].op.pred, hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfff3800) == 0x9d0000) { - // Instruction: 10: 1010000010011101PP000iiiiiiiiiii | allocframe (#u11:3) - hi->instruction = HEX_INS_ALLOCFRAME___U11_3_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_IMM; - hi->ops[0].op.imm = (((hi_u32)&0x7ff) >> 0) << 3; // scaled - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "allocframe (0x%x)", hi->ops[0].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2000000) { - // Instruction: 10: 10100010000-----PP-------------- | dckill - hi->instruction = HEX_INS_DCKILL; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dckill"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2200000) { - // Instruction: 10: 10100010001sssssPP-------------- | dccleanidx (Rs) - hi->instruction = HEX_INS_DCCLEANIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleanidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2400000) { - // Instruction: 10: 10100010010sssssPP-------------- | dcinvidx (Rs) - hi->instruction = HEX_INS_DCINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dcinvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2600000) { - // Instruction: 10: 10100010011sssssPP-------------- | dccleaninvidx (Rs) - hi->instruction = HEX_INS_DCCLEANINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleaninvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4000000) { - // Instruction: 10: 10100100000sssssPP-ttttt-------- | dctagw (Rs, Rt) - hi->instruction = HEX_INS_DCTAGW__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dctagw (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4200000) { - // Instruction: 10: 10100100001sssssPP---------ddddd | Rd = dctagr (Rs) - hi->instruction = HEX_INS_RD___DCTAGR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = dctagr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6200000) { - // Instruction: 10: 10100110001sssssPP-------------- | l2cleanidx (Rs) - hi->instruction = HEX_INS_L2CLEANIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2cleanidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6400000) { - // Instruction: 10: 10100110010sssssPP-------------- | l2invidx (Rs) - hi->instruction = HEX_INS_L2INVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2invidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8600000) { - // Instruction: 10: 10101000011sssssPP-------------- | l2cleaninvidx (Rs) - hi->instruction = HEX_INS_L2CLEANINVIDX__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2cleaninvidx (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6a00000) { - // Instruction: 10: 10100110101-----PP-ttttt-------- | l2gclean (Rtt) - hi->instruction = HEX_INS_L2GCLEAN__RTT_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gclean (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6c00000) { - // Instruction: 10: 10100110110-----PP-ttttt-------- | l2gcleaninv (Rtt) - hi->instruction = HEX_INS_L2GCLEANINV__RTT_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gcleaninv (R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8200000) { - // Instruction: 10: 10101000001-----PP-000---------- | l2kill - hi->instruction = HEX_INS_L2KILL; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2kill"); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8200800) { - // Instruction: 10: 10101000001-----PP-010---------- | l2gunlock - hi->instruction = HEX_INS_L2GUNLOCK; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gunlock"); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8201000) { - // Instruction: 10: 10101000001-----PP-100---------- | l2gclean - hi->instruction = HEX_INS_L2GCLEAN; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gclean"); - break; - } - if ((hi_u32 & 0xfe01c00) == 0x8201800) { - // Instruction: 10: 10101000001-----PP-110---------- | l2gcleaninv - hi->instruction = HEX_INS_L2GCLEANINV; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2gcleaninv"); - break; - } - if ((hi_u32 & 0xfe02000) == 0xe02000) { - // Instruction: 10: 10100000111sssssPP1-----------dd | Pd = l2locka (Rs) - hi->instruction = HEX_INS_PD___L2LOCKA__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = l2locka (R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 10: 10100110011sssssPP-------------- | l2unlocka (Rs) - hi->instruction = HEX_INS_L2UNLOCKA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2unlocka (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x4400000) { - // Instruction: 10: 10100100010sssssPP0ttttt-------- | l2tagw (Rs, Rt) - hi->instruction = HEX_INS_L2TAGW__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2tagw (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x4600000) { - // Instruction: 10: 10100100011sssssPP---------ddddd | Rd = l2tagr (Rs) - hi->instruction = HEX_INS_RD___L2TAGR__RS_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = l2tagr (R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0xa00000) { - // Instruction: 10: 10100000101sssssPP-ttttt------dd | memw_locked (Rs, Pd) = Rt - hi->instruction = HEX_INS_MEMW_LOCKED__RS__PD____RT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memw_locked (R%d, P%d) = R%d", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xe00000) { - // Instruction: 10: 10100000111sssssPP0ttttt------dd | memd_locked (Rs, Pd) = Rtt - hi->instruction = HEX_INS_MEMD_LOCKED__RS__PD____RTT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "memd_locked (R%d, P%d) = R%d:R%d", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0xc00000) { - // Instruction: 10: 10100000110sssssPP0------------- | dczeroa (Rs) - hi->instruction = HEX_INS_DCZEROA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dczeroa (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8000000) { - // Instruction: 10: 10101000000-----PP-------------- | barrier - hi->instruction = HEX_INS_BARRIER; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "barrier"); - break; - } - if ((hi_u32 & 0xfe00000) == 0x0) { - // Instruction: 10: 10100000000sssssPP-------------- | dccleana (Rs) - hi->instruction = HEX_INS_DCCLEANA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleana (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x200000) { - // Instruction: 10: 10100000001sssssPP-------------- | dcinva (Rs) - hi->instruction = HEX_INS_DCINVA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dcinva (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x400000) { - // Instruction: 10: 10100000010sssssPP-------------- | dccleaninva (Rs) - hi->instruction = HEX_INS_DCCLEANINVA__RS_; - hi->op_count = 1; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "dccleaninva (R%d)", hi->ops[0].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 10: 10100110000sssssPP-ttttt-------- | l2fetch (Rs, Rt) - hi->instruction = HEX_INS_L2FETCH__RS__RT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2fetch (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6800000) { - // Instruction: 10: 10100110100sssssPP-ttttt-------- | l2fetch (Rs, Rtt) - hi->instruction = HEX_INS_L2FETCH__RS__RTT_; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "l2fetch (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x8400000) { - // Instruction: 10: 10101000010-----PP-------------- | syncht - hi->instruction = HEX_INS_SYNCHT; - hi->op_count = 0; - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "syncht"); - break; - } - break; - } - case 0xb: { - if ((hi_u32 & 0x0) == 0x0) { - // Instruction: 11: 1011iiiiiiisssssPPiiiiiiiiiddddd | Rd = add (Rs, #s16) - hi->instruction = HEX_INS_RD___ADD__RS___S16_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0xfe00000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 15)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 15); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = add (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - break; - } - case 0xc: { - if ((hi_u32 & 0xfe00000) == 0x2c00000) { - // Instruction: 12: 11000010110sssssPP-ttttt-xxddddd | Rdd = add (Rss, Rtt, Px) :carry - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT__PX___CARRY; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d, P%d) :carry", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2e00000) { - // Instruction: 12: 11000010111sssssPP-ttttt-xxddddd | Rdd = sub (Rss, Rtt, Px) :carry - hi->instruction = HEX_INS_RDD___SUB__RSS__RTT__PX___CARRY; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = sub (R%d:R%d, R%d:R%d, P%d) :carry", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfc020e0) == 0xa800000) { - // Instruction: 12: 1100101010-sssssPP0ttttt000xxxxx | Rxx ^= xor (Rss, Rtt) - hi->instruction = HEX_INS_RXX____XOR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= xor (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6c00000) { - // Instruction: 12: 1100011011-sssssPP-ttttt00-ddddd | Rd = cround (Rs, Rt) - hi->instruction = HEX_INS_RD___CROUND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cround (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6c00080) { - // Instruction: 12: 1100011011-sssssPP-ttttt10-ddddd | Rd = round (Rs, Rt) - hi->instruction = HEX_INS_RD___ROUND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = round (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6c000c0) { - // Instruction: 12: 1100011011-sssssPP-ttttt11-ddddd | Rd = round (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ROUND__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = round (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400020) { - // Instruction: 12: 1100000101-sssssPP-ttttt001ddddd | Rd = vaddhub (Rss, Rtt) :sat - hi->instruction = HEX_INS_RD___VADDHUB__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vaddhub (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3c00040) { - // Instruction: 12: 1100001111-sssssPP-ttttt01-ddddd | Rdd = vcnegh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VCNEGH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vcnegh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2020e0) { - // Instruction: 12: 11001011001sssssPP1ttttt111xxxxx | Rxx += vrcnegh (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCNEGH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcnegh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb200020) { - // Instruction: 12: 11001011001sssssPP0xxxxx001uuuuu | Rxx = vrmaxh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb202020) { - // Instruction: 12: 11001011001sssssPP1xxxxx001uuuuu | Rxx = vrmaxuh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXUH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxuh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb200040) { - // Instruction: 12: 11001011001sssssPP0xxxxx010uuuuu | Rxx = vrmaxw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb202040) { - // Instruction: 12: 11001011001sssssPP1xxxxx010uuuuu | Rxx = vrmaxuw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMAXUW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmaxuw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2000a0) { - // Instruction: 12: 11001011001sssssPP0xxxxx101uuuuu | Rxx = vrminh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2020a0) { - // Instruction: 12: 11001011001sssssPP1xxxxx101uuuuu | Rxx = vrminuh (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINUH__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminuh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2000c0) { - // Instruction: 12: 11001011001sssssPP0xxxxx110uuuuu | Rxx = vrminw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb2020c0) { - // Instruction: 12: 11001011001sssssPP1xxxxx110uuuuu | Rxx = vrminuw (Rss, Ru) - hi->instruction = HEX_INS_RXX___VRMINUW__RSS__RU_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrminuw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1000000) { - // Instruction: 12: 1100000100-sssssPP-ttttt00-ddddd | Rdd = extractu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___EXTRACTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extractu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c00080) { - // Instruction: 12: 1100000111-sssssPP-ttttt10-ddddd | Rdd = extract (Rss, Rtt) - hi->instruction = HEX_INS_RDD___EXTRACT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = extract (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x9000000) { - // Instruction: 12: 1100100100-sssssPP-ttttt00-ddddd | Rd = extractu (Rs, Rtt) - hi->instruction = HEX_INS_RD___EXTRACTU__RS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extractu (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x9000040) { - // Instruction: 12: 1100100100-sssssPP-ttttt01-ddddd | Rd = extract (Rs, Rtt) - hi->instruction = HEX_INS_RD___EXTRACT__RS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = extract (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x8000000) { - // Instruction: 12: 11001000---sssssPP-ttttt---xxxxx | Rx = insert (Rs, Rtt) - hi->instruction = HEX_INS_RX___INSERT__RS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = insert (R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf802000) == 0xa000000) { - // Instruction: 12: 110010100--sssssPP0ttttt---xxxxx | Rxx = insert (Rss, Rtt) - hi->instruction = HEX_INS_RXX___INSERT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = insert (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x18000c0) { - // Instruction: 12: 1100000110-sssssPP-ttttt110ddddd | Rdd = lfs (Rss, Rtt) - hi->instruction = HEX_INS_RDD___LFS__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lfs (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6800000) { - // Instruction: 12: 1100011010-sssssPP-ttttt00-ddddd | Rd = setbit (Rs, Rt) - hi->instruction = HEX_INS_RD___SETBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = setbit (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6800040) { - // Instruction: 12: 1100011010-sssssPP-ttttt01-ddddd | Rd = clrbit (Rs, Rt) - hi->instruction = HEX_INS_RD___CLRBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = clrbit (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6800080) { - // Instruction: 12: 1100011010-sssssPP-ttttt10-ddddd | Rd = togglebit (Rs, Rt) - hi->instruction = HEX_INS_RD___TOGGLEBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = togglebit (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400080) { - // Instruction: 12: 1100000101-sssssPP-ttttt100ddddd | Rdd = vxaddsubh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXADDSUBH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxaddsubh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x14000c0) { - // Instruction: 12: 1100000101-sssssPP-ttttt110ddddd | Rdd = vxsubaddh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXSUBADDH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxsubaddh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c00000) { - // Instruction: 12: 1100000111-sssssPP-ttttt00-ddddd | Rdd = vxaddsubh (Rss, Rtt) :rnd:>>1:sat - hi->instruction = HEX_INS_RDD___VXADDSUBH__RSS__RTT___RND___1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RSH1; // :>>1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxaddsubh (R%d:R%d, R%d:R%d) :rnd:>>1:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c00040) { - // Instruction: 12: 1100000111-sssssPP-ttttt01-ddddd | Rdd = vxsubaddh (Rss, Rtt) :rnd:>>1:sat - hi->instruction = HEX_INS_RDD___VXSUBADDH__RSS__RTT___RND___1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RSH1; // :>>1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxsubaddh (R%d:R%d, R%d:R%d) :rnd:>>1:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400000) { - // Instruction: 12: 1100000101-sssssPP-ttttt000ddddd | Rdd = vxaddsubw (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXADDSUBW__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxaddsubw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1400040) { - // Instruction: 12: 1100000101-sssssPP-ttttt010ddddd | Rdd = vxsubaddw (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VXSUBADDW__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vxsubaddw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x5000080) { - // Instruction: 12: 11000101---sssssPP-ttttt100ddddd | Rd = cmpyiwh (Rss, Rt) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYIWH__RSS__RT_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyiwh (R%d:R%d, R%d) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x50000a0) { - // Instruction: 12: 11000101---sssssPP-ttttt101ddddd | Rd = cmpyiwh (Rss, Rt *) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYIWH__RSS__RT_______1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyiwh (R%d:R%d, R%d *) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x50000c0) { - // Instruction: 12: 11000101---sssssPP-ttttt110ddddd | Rd = cmpyrwh (Rss, Rt) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYRWH__RSS__RT_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyrwh (R%d:R%d, R%d) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x50000e0) { - // Instruction: 12: 11000101---sssssPP-ttttt111ddddd | Rd = cmpyrwh (Rss, Rt *) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___CMPYRWH__RSS__RT_______1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpyrwh (R%d:R%d, R%d *) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3c00000) { - // Instruction: 12: 1100001111-sssssPP-ttttt00-ddddd | Rdd = vcrotate (Rss, Rt) - hi->instruction = HEX_INS_RDD___VCROTATE__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vcrotate (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3c000c0) { - // Instruction: 12: 1100001111-sssssPPittttt11iddddd | Rdd = vrcrotate (Rss, Rt, #u2) - hi->instruction = HEX_INS_RDD___VRCROTATE__RSS__RT___U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x20) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcrotate (R%d:R%d, R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0xba00000) { - // Instruction: 12: 11001011101sssssPPittttt--ixxxxx | Rxx += vrcrotate (Rss, Rt, #u2) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCROTATE__RSS__RT___U2_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x2000) >> 12) | ((hi_u32 & 0x20) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcrotate (R%d:R%d, R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00000) { - // Instruction: 12: 11000111111sssssPP-ttttt000---dd | Pd = cmp.ge (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GE__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.ge (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00020) { - // Instruction: 12: 11000111111sssssPP-ttttt001---dd | Pd = cmp.uo (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_UO__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.uo (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00060) { - // Instruction: 12: 11000111111sssssPP-ttttt011---dd | Pd = cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_EQ__RS__RT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7e00080) { - // Instruction: 12: 11000111111sssssPP-ttttt100---dd | Pd = cmp.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GT__RS__RT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1c000c0) { - // Instruction: 12: 1100000111-sssssPP-ttttt11-ddddd | Rdd = decbin (Rss, Rtt) - hi->instruction = HEX_INS_RDD___DECBIN__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = decbin (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x0) { - // Instruction: 12: 110000000--sssssPP-tttttiiiddddd | Rdd = valignb (Rtt, Rss, #u3) - hi->instruction = HEX_INS_RDD___VALIGNB__RTT__RSS___U3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = valignb (R%d:R%d, R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0x2000000) { - // Instruction: 12: 110000100--sssssPP-ttttt-uuddddd | Rdd = valignb (Rtt, Rss, Pu) - hi->instruction = HEX_INS_RDD___VALIGNB__RTT__RSS__PU_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = valignb (R%d:R%d, R%d:R%d, P%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1000040) { - // Instruction: 12: 1100000100-sssssPP-ttttt01-ddddd | Rdd = shuffeb (Rss, Rtt) - hi->instruction = HEX_INS_RDD___SHUFFEB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffeb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x1000080) { - // Instruction: 12: 1100000100-sssssPP-ttttt10-ddddd | Rdd = shuffob (Rtt, Rss) - hi->instruction = HEX_INS_RDD___SHUFFOB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffob (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x10000c0) { - // Instruction: 12: 1100000100-sssssPP-ttttt11-ddddd | Rdd = shuffeh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___SHUFFEH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffeh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800000) { - // Instruction: 12: 1100000110-sssssPP-ttttt000ddddd | Rdd = shuffoh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___SHUFFOH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = shuffoh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x800000) { - // Instruction: 12: 110000001--sssssPP-tttttiiiddddd | Rdd = vspliceb (Rss, Rtt, #u3) - hi->instruction = HEX_INS_RDD___VSPLICEB__RSS__RTT___U3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vspliceb (R%d:R%d, R%d:R%d, 0x%x)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfe00000) == 0x2800000) { - // Instruction: 12: 11000010100sssssPP-ttttt-uuddddd | Rdd = vspliceb (Rss, Rtt, Pu) - hi->instruction = HEX_INS_RDD___VSPLICEB__RSS__RTT__PU_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vspliceb (R%d:R%d, R%d:R%d, P%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800040) { - // Instruction: 12: 1100000110-sssssPP-ttttt010ddddd | Rdd = vtrunewh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNEWH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunewh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800060) { - // Instruction: 12: 1100000110-sssssPP-ttttt011ddddd | Rdd = vtrunehb (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNEHB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunehb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x1800080) { - // Instruction: 12: 1100000110-sssssPP-ttttt100ddddd | Rdd = vtrunowh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNOWH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunowh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000e0) == 0x18000a0) { - // Instruction: 12: 1100000110-sssssPP-ttttt101ddddd | Rdd = vtrunohb (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VTRUNOHB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vtrunohb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c00040) { - // Instruction: 12: 11000111110sssssPP-ttttt010---dd | Pd = cmpb.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPB_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmpb.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c000c0) { - // Instruction: 12: 11000111110sssssPP-ttttt110---dd | Pd = cmpb.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPB_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmpb.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c000e0) { - // Instruction: 12: 11000111110sssssPP-ttttt111---dd | Pd = cmpb.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPB_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmpb.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c00060) { - // Instruction: 12: 11000111110sssssPP-ttttt011---dd | Pd = cmph.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPH_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmph.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c00080) { - // Instruction: 12: 11000111110sssssPP-ttttt100---dd | Pd = cmph.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPH_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmph.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x7c000a0) { - // Instruction: 12: 11000111110sssssPP-ttttt101---dd | Pd = cmph.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD___CMPH_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmph.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7400000) { - // Instruction: 12: 11000111010sssssPP-ttttt------dd | Pd = bitsset (Rs, Rt) - hi->instruction = HEX_INS_PD___BITSSET__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = bitsset (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7600000) { - // Instruction: 12: 11000111011sssssPP-ttttt------dd | Pd = !bitsset (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_BITSSET__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !bitsset (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7800000) { - // Instruction: 12: 11000111100sssssPP-ttttt------dd | Pd = bitsclr (Rs, Rt) - hi->instruction = HEX_INS_PD___BITSCLR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = bitsclr (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7a00000) { - // Instruction: 12: 11000111101sssssPP-ttttt------dd | Pd = !bitsclr (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_BITSCLR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !bitsclr (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7000000) { - // Instruction: 12: 11000111000sssssPP-ttttt------dd | Pd = tstbit (Rs, Rt) - hi->instruction = HEX_INS_PD___TSTBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = tstbit (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x7200000) { - // Instruction: 12: 11000111001sssssPP-ttttt------dd | Pd = !tstbit (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_TSTBIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !tstbit (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02000) == 0x4000000) { - // Instruction: 12: 11000100000sssssPP0tttttiiiddddd | Rd = addasl (Rt, Rs, #u3) - hi->instruction = HEX_INS_RD___ADDASL__RT__RS___U3_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = addasl (R%d, R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3800000) { - // Instruction: 12: 1100001110-sssssPP-ttttt00-ddddd | Rdd = asr (Rss, Rt) - hi->instruction = HEX_INS_RDD___ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3800040) { - // Instruction: 12: 1100001110-sssssPP-ttttt01-ddddd | Rdd = lsr (Rss, Rt) - hi->instruction = HEX_INS_RDD___LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3800080) { - // Instruction: 12: 1100001110-sssssPP-ttttt10-ddddd | Rdd = asl (Rss, Rt) - hi->instruction = HEX_INS_RDD___ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x38000c0) { - // Instruction: 12: 1100001110-sssssPP-ttttt11-ddddd | Rdd = lsl (Rss, Rt) - hi->instruction = HEX_INS_RDD___LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6400000) { - // Instruction: 12: 1100011001-sssssPP-ttttt00-ddddd | Rd = asr (Rs, Rt) - hi->instruction = HEX_INS_RD___ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6400040) { - // Instruction: 12: 1100011001-sssssPP-ttttt01-ddddd | Rd = lsr (Rs, Rt) - hi->instruction = HEX_INS_RD___LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6400080) { - // Instruction: 12: 1100011001-sssssPP-ttttt10-ddddd | Rd = asl (Rs, Rt) - hi->instruction = HEX_INS_RD___ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x64000c0) { - // Instruction: 12: 1100011001-sssssPP-ttttt11-ddddd | Rd = lsl (Rs, Rt) - hi->instruction = HEX_INS_RD___LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x68000c0) { - // Instruction: 12: 1100011010-iiiiiPP-ttttt11iddddd | Rd = lsl (#s6, Rt) - hi->instruction = HEX_INS_RD___LSL___S6__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x1f0000) >> 15) | ((hi_u32 & 0x20) >> 5)); - if (hi->ops[1].op.imm & (1 << 5)) { - hi->ops[1].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = lsl (%d, R%d)", hi->ops[0].op.reg, (st32)hi->ops[1].op.imm, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb800000) { - // Instruction: 12: 11001011100sssssPP-ttttt00-xxxxx | Rxx -= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb800040) { - // Instruction: 12: 11001011100sssssPP-ttttt01-xxxxx | Rxx -= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb800080) { - // Instruction: 12: 11001011100sssssPP-ttttt10-xxxxx | Rxx -= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb8000c0) { - // Instruction: 12: 11001011100sssssPP-ttttt11-xxxxx | Rxx -= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc00000) { - // Instruction: 12: 11001011110sssssPP-ttttt00-xxxxx | Rxx += asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc00040) { - // Instruction: 12: 11001011110sssssPP-ttttt01-xxxxx | Rxx += lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc00080) { - // Instruction: 12: 11001011110sssssPP-ttttt10-xxxxx | Rxx += asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xbc000c0) { - // Instruction: 12: 11001011110sssssPP-ttttt11-xxxxx | Rxx += lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800000) { - // Instruction: 12: 1100110010-sssssPP-ttttt00-xxxxx | Rx -= asr (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800040) { - // Instruction: 12: 1100110010-sssssPP-ttttt01-xxxxx | Rx -= lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc800080) { - // Instruction: 12: 1100110010-sssssPP-ttttt10-xxxxx | Rx -= asl (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc8000c0) { - // Instruction: 12: 1100110010-sssssPP-ttttt11-xxxxx | Rx -= lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc00000) { - // Instruction: 12: 1100110011-sssssPP-ttttt00-xxxxx | Rx += asr (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc00040) { - // Instruction: 12: 1100110011-sssssPP-ttttt01-xxxxx | Rx += lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc00080) { - // Instruction: 12: 1100110011-sssssPP-ttttt10-xxxxx | Rx += asl (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xcc000c0) { - // Instruction: 12: 1100110011-sssssPP-ttttt11-xxxxx | Rx += lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb000000) { - // Instruction: 12: 11001011000sssssPP-ttttt00-xxxxx | Rxx |= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb000040) { - // Instruction: 12: 11001011000sssssPP-ttttt01-xxxxx | Rxx |= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb000080) { - // Instruction: 12: 11001011000sssssPP-ttttt10-xxxxx | Rxx |= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb0000c0) { - // Instruction: 12: 11001011000sssssPP-ttttt11-xxxxx | Rxx |= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__OR_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d |= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb400000) { - // Instruction: 12: 11001011010sssssPP-ttttt00-xxxxx | Rxx &= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb400040) { - // Instruction: 12: 11001011010sssssPP-ttttt01-xxxxx | Rxx &= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb400080) { - // Instruction: 12: 11001011010sssssPP-ttttt10-xxxxx | Rxx &= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb4000c0) { - // Instruction: 12: 11001011010sssssPP-ttttt11-xxxxx | Rxx &= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX__AND_EQ__LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d &= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb600000) { - // Instruction: 12: 11001011011sssssPP-ttttt00-xxxxx | Rxx ^= asr (Rss, Rt) - hi->instruction = HEX_INS_RXX____ASR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= asr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb600040) { - // Instruction: 12: 11001011011sssssPP-ttttt01-xxxxx | Rxx ^= lsr (Rss, Rt) - hi->instruction = HEX_INS_RXX____LSR__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= lsr (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb600080) { - // Instruction: 12: 11001011011sssssPP-ttttt10-xxxxx | Rxx ^= asl (Rss, Rt) - hi->instruction = HEX_INS_RXX____ASL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= asl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0xb6000c0) { - // Instruction: 12: 11001011011sssssPP-ttttt11-xxxxx | Rxx ^= lsl (Rss, Rt) - hi->instruction = HEX_INS_RXX____LSL__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= lsl (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc000000) { - // Instruction: 12: 1100110000-sssssPP-ttttt00-xxxxx | Rx |= asr (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc000040) { - // Instruction: 12: 1100110000-sssssPP-ttttt01-xxxxx | Rx |= lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc000080) { - // Instruction: 12: 1100110000-sssssPP-ttttt10-xxxxx | Rx |= asl (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc0000c0) { - // Instruction: 12: 1100110000-sssssPP-ttttt11-xxxxx | Rx |= lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc400000) { - // Instruction: 12: 1100110001-sssssPP-ttttt00-xxxxx | Rx &= asr (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__ASR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc400040) { - // Instruction: 12: 1100110001-sssssPP-ttttt01-xxxxx | Rx &= lsr (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__LSR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= lsr (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc400080) { - // Instruction: 12: 1100110001-sssssPP-ttttt10-xxxxx | Rx &= asl (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__ASL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= asl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0xc4000c0) { - // Instruction: 12: 1100110001-sssssPP-ttttt11-xxxxx | Rx &= lsl (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__LSL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= lsl (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6000000) { - // Instruction: 12: 1100011000-sssssPP-ttttt00-ddddd | Rd = asr (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ASR__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = asr (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x6000080) { - // Instruction: 12: 1100011000-sssssPP-ttttt10-ddddd | Rd = asl (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ASL__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = asl (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3400000) { - // Instruction: 12: 1100001101-sssssPP-ttttt00-ddddd | Rdd = vasrh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASRH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3400040) { - // Instruction: 12: 1100001101-sssssPP-ttttt01-ddddd | Rdd = vlsrh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSRH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3400080) { - // Instruction: 12: 1100001101-sssssPP-ttttt10-ddddd | Rdd = vaslh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASLH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x34000c0) { - // Instruction: 12: 1100001101-sssssPP-ttttt11-ddddd | Rdd = vlslh (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSLH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlslh (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3000000) { - // Instruction: 12: 1100001100-sssssPP-ttttt00-ddddd | Rdd = vasrw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASRW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vasrw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3000040) { - // Instruction: 12: 1100001100-sssssPP-ttttt01-ddddd | Rdd = vlsrw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSRW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlsrw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x3000080) { - // Instruction: 12: 1100001100-sssssPP-ttttt10-ddddd | Rdd = vaslw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VASLW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaslw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc000c0) == 0x30000c0) { - // Instruction: 12: 1100001100-sssssPP-ttttt11-ddddd | Rdd = vlslw (Rss, Rt) - hi->instruction = HEX_INS_RDD___VLSLW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vlslw (R%d:R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf0000e0) == 0x5000040) { - // Instruction: 12: 11000101---sssssPP-ttttt010ddddd | Rd = vasrw (Rss, Rt) - hi->instruction = HEX_INS_RD___VASRW__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vasrw (R%d:R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - break; - } - case 0xd: { - if ((hi_u32 & 0xf800000) == 0xb000000) { - // Instruction: 13: 110110110iisssssPPidddddiiiuuuuu | Rd = add (Rs, add (Ru, #s6)) - hi->instruction = HEX_INS_RD___ADD__RS__ADD__RU___S6__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - if (hi->ops[3].op.imm & (1 << 5)) { - hi->ops[3].op.imm |= (0xFFFFFFFF << 5); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[3]); - sprintf(hi->mnem, "R%d = add (R%d, add (R%d, %d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, (st32)hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0xb800000) { - // Instruction: 13: 110110111iisssssPPidddddiiiuuuuu | Rd = add (Rs, sub (#s6, Ru)) - hi->instruction = HEX_INS_RD___ADD__RS__SUB___S6__RU__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 5)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 5); - } - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d = add (R%d, sub (%d, R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x30000e0) { - // Instruction: 13: 11010011000sssssPP-ttttt111ddddd | Rdd = add (Rss, Rtt) - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x36000a0) { - // Instruction: 13: 11010011011sssssPP-ttttt101ddddd | Rdd = add (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x36000c0) { - // Instruction: 13: 11010011011sssssPP-ttttt110ddddd | Rdd = add (Rss, Rtt) :raw:lo - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT___RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d) :raw:lo", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x36000e0) { - // Instruction: 13: 11010011011sssssPP-ttttt111ddddd | Rdd = add (Rss, Rtt) :raw:hi - hi->instruction = HEX_INS_RDD___ADD__RSS__RTT___RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "R%d:R%d = add (R%d:R%d, R%d:R%d) :raw:hi", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5800000) { - // Instruction: 13: 11010101100sssssPP-ttttt0--ddddd | Rd = add (Rs, Rt) :sat:deprecated - hi->instruction = HEX_INS_RD___ADD__RS__RT___SAT_DEPRECATED; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_DEPRECATED; // :deprecated - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d, R%d) :sat:deprecated", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5000000) { - // Instruction: 13: 11010101000sssssPP-ttttt00-ddddd | Rd = add (Rt.L, Rs.L) - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5000040) { - // Instruction: 13: 11010101000sssssPP-ttttt01-ddddd | Rd = add (Rt.L, Rs.H) - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5000080) { - // Instruction: 13: 11010101000sssssPP-ttttt10-ddddd | Rd = add (Rt.L, Rs.L) :sat - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x50000c0) { - // Instruction: 13: 11010101000sssssPP-ttttt11-ddddd | Rd = add (Rt.L, Rs.H) :sat - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400000) { - // Instruction: 13: 11010101010sssssPP-ttttt000ddddd | Rd = add (Rt.L, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400020) { - // Instruction: 13: 11010101010sssssPP-ttttt001ddddd | Rd = add (Rt.L, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400040) { - // Instruction: 13: 11010101010sssssPP-ttttt010ddddd | Rd = add (Rt.H, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400060) { - // Instruction: 13: 11010101010sssssPP-ttttt011ddddd | Rd = add (Rt.H, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5400080) { - // Instruction: 13: 11010101010sssssPP-ttttt100ddddd | Rd = add (Rt.L, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x54000a0) { - // Instruction: 13: 11010101010sssssPP-ttttt101ddddd | Rd = add (Rt.L, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_L__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.L, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x54000c0) { - // Instruction: 13: 11010101010sssssPP-ttttt110ddddd | Rd = add (Rt.H, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x54000e0) { - // Instruction: 13: 11010101010sssssPP-ttttt111ddddd | Rd = add (Rt.H, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___ADD__RT_H__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d.H, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00000) { - // Instruction: 13: 11010011111sssssPP-ttttt000ddddd | Rdd = and (Rss, Rtt) - hi->instruction = HEX_INS_RDD___AND__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = and (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00020) { - // Instruction: 13: 11010011111sssssPP-ttttt001ddddd | Rdd = and (Rtt, ~Rss) - hi->instruction = HEX_INS_RDD___AND__RTT___RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = and (R%d:R%d, ~R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00040) { - // Instruction: 13: 11010011111sssssPP-ttttt010ddddd | Rdd = or (Rss, Rtt) - hi->instruction = HEX_INS_RDD___OR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = or (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00060) { - // Instruction: 13: 11010011111sssssPP-ttttt011ddddd | Rdd = or (Rtt, ~Rss) - hi->instruction = HEX_INS_RDD___OR__RTT___RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = or (R%d:R%d, ~R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e00080) { - // Instruction: 13: 11010011111sssssPP-ttttt100ddddd | Rdd = xor (Rss, Rtt) - hi->instruction = HEX_INS_RDD___XOR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = xor (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0xa000000) { - // Instruction: 13: 1101101000isssssPPiiiiiiiiixxxxx | Rx |= and (Rs, #s10) - hi->instruction = HEX_INS_RX__OR_EQ__AND__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= and (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0xa400000) { - // Instruction: 13: 1101101001ixxxxxPPiiiiiiiiiuuuuu | Rx = or (Ru, and (Rx, #s10)) - hi->instruction = HEX_INS_RX___OR__RU__AND__RX___S10__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = or (R%d, and (Rx, %d))", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0xa800000) { - // Instruction: 13: 1101101010isssssPPiiiiiiiiixxxxx | Rx |= or (Rs, #s10) - hi->instruction = HEX_INS_RX__OR_EQ__OR__RS___S10_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - if (hi->ops[2].op.imm & (1 << 9)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 9); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= or (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5c00000) { - // Instruction: 13: 11010101110sssssPP-ttttt0--ddddd | Rd = max (Rs, Rt) - hi->instruction = HEX_INS_RD___MAX__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = max (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5c00080) { - // Instruction: 13: 11010101110sssssPP-ttttt1--ddddd | Rd = maxu (Rs, Rt) - hi->instruction = HEX_INS_RD___MAXU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = maxu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00080) { - // Instruction: 13: 11010011110sssssPP-ttttt100ddddd | Rdd = max (Rss, Rtt) - hi->instruction = HEX_INS_RDD___MAX__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = max (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c000a0) { - // Instruction: 13: 11010011110sssssPP-ttttt101ddddd | Rdd = maxu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___MAXU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = maxu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5a00000) { - // Instruction: 13: 11010101101sssssPP-ttttt0--ddddd | Rd = min (Rt, Rs) - hi->instruction = HEX_INS_RD___MIN__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = min (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5a00080) { - // Instruction: 13: 11010101101sssssPP-ttttt1--ddddd | Rd = minu (Rt, Rs) - hi->instruction = HEX_INS_RD___MINU__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = minu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a000c0) { - // Instruction: 13: 11010011101sssssPP-ttttt110ddddd | Rdd = min (Rtt, Rss) - hi->instruction = HEX_INS_RDD___MIN__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = min (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a000e0) { - // Instruction: 13: 11010011101sssssPP-ttttt111ddddd | Rdd = minu (Rtt, Rss) - hi->instruction = HEX_INS_RDD___MINU__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = minu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3e000e0) { - // Instruction: 13: 11010011111sssssPP-ttttt111ddddd | Rd = modwrap (Rs, Rt) - hi->instruction = HEX_INS_RD___MODWRAP__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = modwrap (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x32000e0) { - // Instruction: 13: 11010011001sssssPP-ttttt111ddddd | Rdd = sub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___SUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = sub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00080) == 0x5800080) { - // Instruction: 13: 11010101100sssssPP-ttttt1--ddddd | Rd = sub (Rt, Rs) :sat:deprecated - hi->instruction = HEX_INS_RD___SUB__RT__RS___SAT_DEPRECATED; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_DEPRECATED; // :deprecated - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d, R%d) :sat:deprecated", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5200000) { - // Instruction: 13: 11010101001sssssPP-ttttt00-ddddd | Rd = sub (Rt.L, Rs.L) - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5200040) { - // Instruction: 13: 11010101001sssssPP-ttttt01-ddddd | Rd = sub (Rt.L, Rs.H) - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x5200080) { - // Instruction: 13: 11010101001sssssPP-ttttt10-ddddd | Rd = sub (Rt.L, Rs.L) :sat - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x52000c0) { - // Instruction: 13: 11010101001sssssPP-ttttt11-ddddd | Rd = sub (Rt.L, Rs.H) :sat - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600000) { - // Instruction: 13: 11010101011sssssPP-ttttt000ddddd | Rd = sub (Rt.L, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600020) { - // Instruction: 13: 11010101011sssssPP-ttttt001ddddd | Rd = sub (Rt.L, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600040) { - // Instruction: 13: 11010101011sssssPP-ttttt010ddddd | Rd = sub (Rt.H, Rs.L) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_L_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.L) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600060) { - // Instruction: 13: 11010101011sssssPP-ttttt011ddddd | Rd = sub (Rt.H, Rs.H) :<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_H_____16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.H) :<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x5600080) { - // Instruction: 13: 11010101011sssssPP-ttttt100ddddd | Rd = sub (Rt.L, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x56000a0) { - // Instruction: 13: 11010101011sssssPP-ttttt101ddddd | Rd = sub (Rt.L, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_L__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.L, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x56000c0) { - // Instruction: 13: 11010101011sssssPP-ttttt110ddddd | Rd = sub (Rt.H, Rs.L) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_L___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.L) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x56000e0) { - // Instruction: 13: 11010101011sssssPP-ttttt111ddddd | Rd = sub (Rt.H, Rs.H) :sat:<<16 - hi->instruction = HEX_INS_RD___SUB__RT_H__RS_H___SAT___16; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LSH16; // :<<16 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d.H, R%d.H) :sat:<<16", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000040) { - // Instruction: 13: 11010011000sssssPP-ttttt010ddddd | Rdd = vaddh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VADDH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaddh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000060) { - // Instruction: 13: 11010011000sssssPP-ttttt011ddddd | Rdd = vaddh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vaddh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000080) { - // Instruction: 13: 11010011000sssssPP-ttttt100ddddd | Rdd = vadduh (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDUH__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vadduh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000000) { - // Instruction: 13: 11010011000sssssPP-ttttt000ddddd | Rdd = vaddub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VADDUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaddub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3000020) { - // Instruction: 13: 11010011000sssssPP-ttttt001ddddd | Rdd = vaddub (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDUB__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vaddub (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x30000a0) { - // Instruction: 13: 11010011000sssssPP-ttttt101ddddd | Rdd = vaddw (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VADDW__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vaddw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x30000c0) { - // Instruction: 13: 11010011000sssssPP-ttttt110ddddd | Rdd = vaddw (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VADDW__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vaddw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400040) { - // Instruction: 13: 11010011010sssssPP-ttttt010ddddd | Rdd = vavgh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavgh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400060) { - // Instruction: 13: 11010011010sssssPP-ttttt011ddddd | Rdd = vavgh (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGH__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavgh (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400080) { - // Instruction: 13: 11010011010sssssPP-ttttt100ddddd | Rdd = vavgh (Rss, Rtt) :crnd - hi->instruction = HEX_INS_RDD___VAVGH__RSS__RTT___CRND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - sprintf(hi->mnem, "R%d:R%d = vavgh (R%d:R%d, R%d:R%d) :crnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x34000a0) { - // Instruction: 13: 11010011010sssssPP-ttttt101ddddd | Rdd = vavguh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGUH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavguh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x34000c0) { - // Instruction: 13: 11010011010sssssPP-ttttt11-ddddd | Rdd = vavguh (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGUH__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavguh (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800000) { - // Instruction: 13: 11010011100sssssPP-ttttt000ddddd | Rdd = vnavgh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VNAVGH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vnavgh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800020) { - // Instruction: 13: 11010011100sssssPP-ttttt001ddddd | Rdd = vnavgh (Rtt, Rss) :rnd:sat - hi->instruction = HEX_INS_RDD___VNAVGH__RTT__RSS___RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgh (R%d:R%d, R%d:R%d) :rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800040) { - // Instruction: 13: 11010011100sssssPP-ttttt010ddddd | Rdd = vnavgh (Rtt, Rss) :crnd:sat - hi->instruction = HEX_INS_RDD___VNAVGH__RTT__RSS___CRND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgh (R%d:R%d, R%d:R%d) :crnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400000) { - // Instruction: 13: 11010011010sssssPP-ttttt000ddddd | Rdd = vavgub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavgub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3400020) { - // Instruction: 13: 11010011010sssssPP-ttttt001ddddd | Rdd = vavgub (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGUB__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavgub (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600000) { - // Instruction: 13: 11010011011sssssPP-ttttt000ddddd | Rdd = vavgw (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGW__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavgw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600020) { - // Instruction: 13: 11010011011sssssPP-ttttt001ddddd | Rdd = vavgw (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGW__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavgw (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600040) { - // Instruction: 13: 11010011011sssssPP-ttttt010ddddd | Rdd = vavgw (Rss, Rtt) :crnd - hi->instruction = HEX_INS_RDD___VAVGW__RSS__RTT___CRND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - sprintf(hi->mnem, "R%d:R%d = vavgw (R%d:R%d, R%d:R%d) :crnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600060) { - // Instruction: 13: 11010011011sssssPP-ttttt011ddddd | Rdd = vavguw (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VAVGUW__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vavguw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3600080) { - // Instruction: 13: 11010011011sssssPP-ttttt100ddddd | Rdd = vavguw (Rss, Rtt) :rnd - hi->instruction = HEX_INS_RDD___VAVGUW__RSS__RTT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = vavguw (R%d:R%d, R%d:R%d) :rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3800060) { - // Instruction: 13: 11010011100sssssPP-ttttt011ddddd | Rdd = vnavgw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VNAVGW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vnavgw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x3800080) { - // Instruction: 13: 11010011100sssssPP-ttttt10-ddddd | Rdd = vnavgw (Rtt, Rss) :rnd:sat - hi->instruction = HEX_INS_RDD___VNAVGW__RTT__RSS___RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgw (R%d:R%d, R%d:R%d) :rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000c0) == 0x38000c0) { - // Instruction: 13: 11010011100sssssPP-ttttt11-ddddd | Rdd = vnavgw (Rtt, Rss) :crnd:sat - hi->instruction = HEX_INS_RDD___VNAVGW__RTT__RSS___CRND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_CRND; // :crnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vnavgw (R%d:R%d, R%d:R%d) :crnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00000) { - // Instruction: 13: 11010011110sssssPP-ttttt000ddddd | Rdd = vmaxub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c000c0) { - // Instruction: 13: 11010011110sssssPP-ttttt110ddddd | Rdd = vmaxb (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00020) { - // Instruction: 13: 11010011110sssssPP-ttttt001ddddd | Rdd = vmaxh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00040) { - // Instruction: 13: 11010011110sssssPP-ttttt010ddddd | Rdd = vmaxuh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXUH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxuh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a000a0) { - // Instruction: 13: 11010011101sssssPP-ttttt101ddddd | Rdd = vmaxuw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXUW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxuw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c00060) { - // Instruction: 13: 11010011110sssssPP-ttttt011ddddd | Rdd = vmaxw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMAXW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmaxw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00000) { - // Instruction: 13: 11010011101sssssPP-ttttt000ddddd | Rdd = vminub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3c000e0) { - // Instruction: 13: 11010011110sssssPP-ttttt111ddddd | Rdd = vminb (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00020) { - // Instruction: 13: 11010011101sssssPP-ttttt001ddddd | Rdd = vminh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00040) { - // Instruction: 13: 11010011101sssssPP-ttttt010ddddd | Rdd = vminuh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINUH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminuh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00060) { - // Instruction: 13: 11010011101sssssPP-ttttt011ddddd | Rdd = vminw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3a00080) { - // Instruction: 13: 11010011101sssssPP-ttttt100ddddd | Rdd = vminuw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VMINUW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vminuw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200040) { - // Instruction: 13: 11010011001sssssPP-ttttt010ddddd | Rdd = vsubh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VSUBH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsubh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200060) { - // Instruction: 13: 11010011001sssssPP-ttttt011ddddd | Rdd = vsubh (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBH__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200080) { - // Instruction: 13: 11010011001sssssPP-ttttt100ddddd | Rdd = vsubuh (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBUH__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubuh (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200000) { - // Instruction: 13: 11010011001sssssPP-ttttt000ddddd | Rdd = vsubub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VSUBUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsubub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x3200020) { - // Instruction: 13: 11010011001sssssPP-ttttt001ddddd | Rdd = vsubub (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBUB__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubub (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x32000a0) { - // Instruction: 13: 11010011001sssssPP-ttttt101ddddd | Rdd = vsubw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VSUBW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vsubw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x32000c0) { - // Instruction: 13: 11010011001sssssPP-ttttt110ddddd | Rdd = vsubw (Rtt, Rss) :sat - hi->instruction = HEX_INS_RDD___VSUBW__RTT__RSS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vsubw (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x0) { - // Instruction: 13: 11010000---sssssPP-ttttt---ddddd | Rd = parity (Rss, Rtt) - hi->instruction = HEX_INS_RD___PARITY__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = parity (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x5e00000) { - // Instruction: 13: 11010101111sssssPP-ttttt---ddddd | Rd = parity (Rs, Rt) - hi->instruction = HEX_INS_RD___PARITY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = parity (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf200000) == 0x4200000) { - // Instruction: 13: 11010100--1sssssPP-ttttt---ddddd | Rdd = bitsplit (Rs, Rt) - hi->instruction = HEX_INS_RDD___BITSPLIT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = bitsplit (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe01c18) == 0xc800010) { - // Instruction: 13: 11011100100sssssPP-000iiiii10-dd | Pd = dfclass (Rss, #u5) - hi->instruction = HEX_INS_PD___DFCLASS__RSS___U5_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x3e0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = dfclass (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00000) { - // Instruction: 13: 11010010111sssssPP-ttttt000---dd | Pd = cmp.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00020) { - // Instruction: 13: 11010010111sssssPP-ttttt001---dd | Pd = cmp.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00040) { - // Instruction: 13: 11010010111sssssPP-ttttt010---dd | Pd = cmp.ge (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GE__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.ge (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2e00060) { - // Instruction: 13: 11010010111sssssPP-ttttt011---dd | Pd = cmp.uo (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_UO__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.uo (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6000000) { - // Instruction: 13: 1101011000i-----PPiiiiiiiiiddddd | Rd = sfmake (#u10) :pos - hi->instruction = HEX_INS_RD___SFMAKE___U10___POS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_POS; // :pos - sprintf(hi->mnem, "R%d = sfmake (0x%x) :pos", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x6400000) { - // Instruction: 13: 1101011001i-----PPiiiiiiiiiddddd | Rd = sfmake (#u10) :neg - hi->instruction = HEX_INS_RD___SFMAKE___U10___NEG; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_NEG; // :neg - sprintf(hi->mnem, "R%d = sfmake (0x%x) :neg", hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x9000000) { - // Instruction: 13: 1101100100i-----PPiiiiiiiiiddddd | Rdd = dfmake (#u10) :pos - hi->instruction = HEX_INS_RDD___DFMAKE___U10___POS; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_POS; // :pos - sprintf(hi->mnem, "R%d:R%d = dfmake (0x%x) :pos", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xfc00000) == 0x9400000) { - // Instruction: 13: 1101100101i-----PPiiiiiiiiiddddd | Rdd = dfmake (#u10) :neg - hi->instruction = HEX_INS_RDD___DFMAKE___U10___NEG; - hi->op_count = 2; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x200000) >> 12) | ((hi_u32 & 0x3fe0) >> 5)); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_NEG; // :neg - sprintf(hi->mnem, "R%d:R%d = dfmake (0x%x) :neg", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0x7000000) { - // Instruction: 13: 110101110iisssssPPitttttiiiddddd | Rd = add (#u6, mpyi (Rs, Rt)) - hi->instruction = HEX_INS_RD___ADD___U6__MPYI__RS__RT__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (0x%x, mpyi (R%d, R%d))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x8000000) { - // Instruction: 13: 11011000IiisssssPPidddddiiiIIIII | Rd = add (#u6, mpyi (Rs, #U6)) - hi->instruction = HEX_INS_RD___ADD___U6__MPYI__RS___U6__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x800000) >> 18) | ((hi_u32 & 0x1f) >> 0)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (0x%x, mpyi (R%d, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf800000) == 0xf000000) { - // Instruction: 13: 110111110iisssssPPidddddiiiuuuuu | Rd = add (Ru, mpyi (#u6:2, Rs)) - hi->instruction = HEX_INS_RD___ADD__RU__MPYI___U6_2__RS__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)) << 2; // scaled - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, mpyi (0x%x, R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0xf800000) { - // Instruction: 13: 110111111iisssssPPidddddiiiuuuuu | Rd = add (Ru, mpyi (Rs, #u6)) - hi->instruction = HEX_INS_RD___ADD__RU__MPYI__RS___U6__; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_IMM; - hi->ops[3].op.imm = (((hi_u32 & 0x600000) >> 17) | ((hi_u32 & 0x2000) >> 10) | ((hi_u32 & 0xe0) >> 5)); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, mpyi (R%d, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.imm); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002080) { - // Instruction: 13: 110100100--sssssPP1ttttt100---dd | Pd = boundscheck (Rss, Rtt) :raw:lo - hi->instruction = HEX_INS_PD___BOUNDSCHECK__RSS__RTT___RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "P%d = boundscheck (R%d:R%d, R%d:R%d) :raw:lo", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20020a0) { - // Instruction: 13: 110100100--sssssPP1ttttt101---dd | Pd = boundscheck (Rss, Rtt) :raw:hi - hi->instruction = HEX_INS_PD___BOUNDSCHECK__RSS__RTT___RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - sprintf(hi->mnem, "P%d = boundscheck (R%d:R%d, R%d:R%d) :raw:hi", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600018) == 0xd000000) { - // Instruction: 13: 11011101-00sssssPP-iiiiiiii00-dd | Pd = cmpb.eq (Rs, #u8) - hi->instruction = HEX_INS_PD___CMPB_EQ__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmpb.eq (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600018) == 0xd200000) { - // Instruction: 13: 11011101-01sssssPP-iiiiiiii00-dd | Pd = cmpb.gt (Rs, #s8) - hi->instruction = HEX_INS_PD___CMPB_GT__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmpb.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf601018) == 0xd400000) { - // Instruction: 13: 11011101-10sssssPP-0iiiiiii00-dd | Pd = cmpb.gtu (Rs, #u7) - hi->instruction = HEX_INS_PD___CMPB_GTU__RS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmpb.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600018) == 0xd000008) { - // Instruction: 13: 11011101-00sssssPP-iiiiiiii01-dd | Pd = cmph.eq (Rs, #s8) - hi->instruction = HEX_INS_PD___CMPH_EQ__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmph.eq (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf600018) == 0xd200008) { - // Instruction: 13: 11011101-01sssssPP-iiiiiiii01-dd | Pd = cmph.gt (Rs, #s8) - hi->instruction = HEX_INS_PD___CMPH_GT__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmph.gt (R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf601018) == 0xd400008) { - // Instruction: 13: 11011101-10sssssPP-0iiiiiii01-dd | Pd = cmph.gtu (Rs, #u7) - hi->instruction = HEX_INS_PD___CMPH_GTU__RS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "P%d = cmph.gtu (R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2800000) { - // Instruction: 13: 11010010100sssssPP-ttttt000---dd | Pd = cmp.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_EQ__RSS__RTT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2800040) { - // Instruction: 13: 11010010100sssssPP-ttttt010---dd | Pd = cmp.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GT__RSS__RTT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe000e0) == 0x2800080) { - // Instruction: 13: 11010010100sssssPP-ttttt100---dd | Pd = cmp.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___CMP_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002060) { - // Instruction: 13: 110100100--sssssPP1ttttt011---dd | Pd = tlbmatch (Rss, Rt) - hi->instruction = HEX_INS_PD___TLBMATCH__RSS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = tlbmatch (R%d:R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000060) { - // Instruction: 13: 110100100--sssssPP0ttttt011---dd | Pd = vcmph.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPH_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000080) { - // Instruction: 13: 110100100--sssssPP0ttttt100---dd | Pd = vcmph.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPH_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20000a0) { - // Instruction: 13: 110100100--sssssPP0ttttt101---dd | Pd = vcmph.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPH_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc000008) { - // Instruction: 13: 11011100000sssssPP-iiiiiiii01-dd | Pd = vcmph.eq (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPH_EQ__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.eq (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc200008) { - // Instruction: 13: 11011100001sssssPP-iiiiiiii01-dd | Pd = vcmph.gt (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPH_GT__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gt (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01018) == 0xc400008) { - // Instruction: 13: 11011100010sssssPP-0iiiiiii01-dd | Pd = vcmph.gtu (Rss, #u7) - hi->instruction = HEX_INS_PD___VCMPH_GTU__RSS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmph.gtu (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002000) { - // Instruction: 13: 110100100--sssssPP1ttttt000---dd | Pd = any8 (vcmpb.eq (Rss, Rtt)) - hi->instruction = HEX_INS_PD___ANY8__VCMPB_EQ__RSS__RTT__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = any8 (vcmpb.eq (R%d:R%d, R%d:R%d))", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20000c0) { - // Instruction: 13: 110100100--sssssPP0ttttt110---dd | Pd = vcmpb.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPB_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x20000e0) { - // Instruction: 13: 110100100--sssssPP0ttttt111---dd | Pd = vcmpb.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPB_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2002040) { - // Instruction: 13: 110100100--sssssPP1ttttt010---dd | Pd = vcmpb.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPB_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc000000) { - // Instruction: 13: 11011100000sssssPP-iiiiiiii00-dd | Pd = vcmpb.eq (Rss, #u8) - hi->instruction = HEX_INS_PD___VCMPB_EQ__RSS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.eq (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc200000) { - // Instruction: 13: 11011100001sssssPP-iiiiiiii00-dd | Pd = vcmpb.gt (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPB_GT__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gt (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01018) == 0xc400000) { - // Instruction: 13: 11011100010sssssPP-0iiiiiii00-dd | Pd = vcmpb.gtu (Rss, #u7) - hi->instruction = HEX_INS_PD___VCMPB_GTU__RSS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpb.gtu (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000000) { - // Instruction: 13: 110100100--sssssPP0ttttt000---dd | Pd = vcmpw.eq (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPW_EQ__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.eq (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000020) { - // Instruction: 13: 110100100--sssssPP0ttttt001---dd | Pd = vcmpw.gt (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPW_GT__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gt (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf8020e0) == 0x2000040) { - // Instruction: 13: 110100100--sssssPP0ttttt010---dd | Pd = vcmpw.gtu (Rss, Rtt) - hi->instruction = HEX_INS_PD___VCMPW_GTU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gtu (R%d:R%d, R%d:R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc000010) { - // Instruction: 13: 11011100000sssssPP-iiiiiiii10-dd | Pd = vcmpw.eq (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPW_EQ__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.eq (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe00018) == 0xc200010) { - // Instruction: 13: 11011100001sssssPP-iiiiiiii10-dd | Pd = vcmpw.gt (Rss, #s8) - hi->instruction = HEX_INS_PD___VCMPW_GT__RSS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gt (R%d:R%d, %d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe01018) == 0xc400010) { - // Instruction: 13: 11011100010sssssPP-0iiiiiii10-dd | Pd = vcmpw.gtu (Rss, #u7) - hi->instruction = HEX_INS_PD___VCMPW_GTU__RSS___U7_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = vcmpw.gtu (R%d:R%d, 0x%x)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000000) == 0x1000000) { - // Instruction: 13: 11010001---sssssPP-ttttt-uuddddd | Rdd = vmux (Pu, Rss, Rtt) - hi->instruction = HEX_INS_RDD___VMUX__PU__RSS__RTT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmux (P%d, R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000004) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i10- | Rx = add (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___ADD___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = add (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000006) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i11- | Rx = sub (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___SUB___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = sub (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000014) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i10- | Rx = add (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___ADD___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = add (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000016) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i11- | Rx = sub (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___SUB___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = sub (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000000) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i00- | Rx = and (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___AND___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = and (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000002) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii0i01- | Rx = or (#u8, asl (Rx, #U5)) - hi->instruction = HEX_INS_RX___OR___U8__ASL__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = or (0x%x, asl (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000010) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i00- | Rx = and (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___AND___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = and (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf000016) == 0xe000012) { - // Instruction: 13: 11011110iiixxxxxPPiIIIIIiii1i01- | Rx = or (#u8, lsr (Rx, #U5)) - hi->instruction = HEX_INS_RX___OR___U8__LSR__RX___U5__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx - hi->ops[1].type = HEX_OP_TYPE_IMM; - hi->ops[1].op.imm = (((hi_u32 & 0xe00000) >> 16) | ((hi_u32 & 0x2000) >> 9) | ((hi_u32 & 0xe0) >> 4) | ((hi_u32 & 0x8) >> 3)); - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[1]); - sprintf(hi->mnem, "R%d = or (0x%x, lsr (Rx, 0x%x))", hi->ops[0].op.reg, hi->ops[1].op.imm, hi->ops[2].op.imm); - break; - } - break; - } - case 0xe: { - if ((hi_u32 & 0xf802000) == 0x2000000) { - // Instruction: 14: 111000100--sssssPP0iiiiiiiixxxxx | Rx += add (Rs, #s8) - hi->instruction = HEX_INS_RX__PLUS_EQ__ADD__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d += add (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x2800000) { - // Instruction: 14: 111000101--sssssPP0iiiiiiiixxxxx | Rx -= add (Rs, #s8) - hi->instruction = HEX_INS_RX__MINUS_EQ__ADD__RS___S8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - if (hi->ops[2].op.imm & (1 << 7)) { - hi->ops[2].op.imm |= (0xFFFFFFFF << 7); - } - hi->predicate = HEX_NOPRED; - hex_op_extend(&hi->ops[2]); - sprintf(hi->mnem, "R%d -= add (R%d, %d)", hi->ops[0].op.reg, hi->ops[1].op.reg, (st32)hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000020) { - // Instruction: 14: 11101111000sssssPP0ttttt001xxxxx | Rx += add (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__ADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += add (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf800020) { - // Instruction: 14: 11101111100sssssPP0ttttt001xxxxx | Rx -= add (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__ADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= add (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf200000) { - // Instruction: 14: 11101111001sssssPP0ttttt000xxxxx | Rx |= and (Rs, ~Rt) - hi->instruction = HEX_INS_RX__OR_EQ__AND__RS___RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf200020) { - // Instruction: 14: 11101111001sssssPP0ttttt001xxxxx | Rx &= and (Rs, ~Rt) - hi->instruction = HEX_INS_RX__AND_EQ__AND__RS___RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf200040) { - // Instruction: 14: 11101111001sssssPP0ttttt010xxxxx | Rx ^= and (Rs, ~Rt) - hi->instruction = HEX_INS_RX____AND__RS___RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400000) { - // Instruction: 14: 11101111010sssssPP0ttttt000xxxxx | Rx &= and (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400020) { - // Instruction: 14: 11101111010sssssPP0ttttt001xxxxx | Rx &= or (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400040) { - // Instruction: 14: 11101111010sssssPP0ttttt010xxxxx | Rx &= xor (Rs, Rt) - hi->instruction = HEX_INS_RX__AND_EQ__XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d &= xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf400060) { - // Instruction: 14: 11101111010sssssPP0ttttt011xxxxx | Rx |= and (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf800060) { - // Instruction: 14: 11101111100sssssPP0ttttt011xxxxx | Rx ^= xor (Rs, Rt) - hi->instruction = HEX_INS_RX____XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00000) { - // Instruction: 14: 11101111110sssssPP0ttttt000xxxxx | Rx |= or (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00020) { - // Instruction: 14: 11101111110sssssPP0ttttt001xxxxx | Rx |= xor (Rs, Rt) - hi->instruction = HEX_INS_RX__OR_EQ__XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d |= xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00040) { - // Instruction: 14: 11101111110sssssPP0ttttt010xxxxx | Rx ^= and (Rs, Rt) - hi->instruction = HEX_INS_RX____AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xfc00060) { - // Instruction: 14: 11101111110sssssPP0ttttt011xxxxx | Rx ^= or (Rs, Rt) - hi->instruction = HEX_INS_RX____OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d ^= or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000060) { - // Instruction: 14: 11101111000sssssPP0ttttt011xxxxx | Rx += sub (Rt, Rs) - hi->instruction = HEX_INS_RX__PLUS_EQ__SUB__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += sub (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8a00000) { - // Instruction: 14: 11101000101sssssPP0ttttt000ddddd | Rdd = vabsdiffub (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFUB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8e00000) { - // Instruction: 14: 11101000111sssssPP0ttttt000ddddd | Rdd = vabsdiffb (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFB__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffb (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8600000) { - // Instruction: 14: 11101000011sssssPP0ttttt000ddddd | Rdd = vabsdiffh (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFH__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8200000) { - // Instruction: 14: 11101000001sssssPP0ttttt000ddddd | Rdd = vabsdiffw (Rtt, Rss) - hi->instruction = HEX_INS_RDD___VABSDIFFW__RTT__RSS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vabsdiffw (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xaa00000) { - // Instruction: 14: 11101010101sssssPP0ttttt0eexxxxx | Rxx, Pe = vacsh (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PE___VACSH__RSS__RTT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d, P%d = vacsh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8400020) { - // Instruction: 14: 11101000010sssssPP0ttttt001ddddd | Rdd = vraddub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRADDUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vraddub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400020) { - // Instruction: 14: 11101010010sssssPP0ttttt001xxxxx | Rxx += vraddub (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRADDUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vraddub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf802060) == 0x9000020) { - // Instruction: 14: 111010010--sssssPP0ttttt-01ddddd | Rd = vradduh (Rss, Rtt) - hi->instruction = HEX_INS_RD___VRADDUH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vradduh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa020e0) == 0x92000e0) { - // Instruction: 14: 111010010-1sssssPP0ttttt111ddddd | Rd = vraddh (Rss, Rtt) - hi->instruction = HEX_INS_RD___VRADDH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vraddh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xae00000) { - // Instruction: 14: 11101010111sssssPP0ttttt0eeddddd | Rdd, Pe = vminub (Rtt, Rss) - hi->instruction = HEX_INS_RDD__PE___VMINUB__RTT__RSS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].attr |= HEX_OP_REG_PAIR; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d, P%d = vminub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, hi->ops[3].op.reg + 1, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8400040) { - // Instruction: 14: 11101000010sssssPP0ttttt010ddddd | Rdd = vrsadub (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRSADUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrsadub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400040) { - // Instruction: 14: 11101010010sssssPP0ttttt010xxxxx | Rxx += vrsadub (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRSADUB__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrsadub (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x50000c0) { - // Instruction: 14: 11100101N00sssssPP0ttttt110ddddd | Rdd = cmpy (Rs, Rt) [:<instruction = HEX_INS_RDD___CMPY__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = cmpy (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x54000c0) { - // Instruction: 14: 11100101N10sssssPP0ttttt110ddddd | Rdd = cmpy (Rs, Rt *) [:<instruction = HEX_INS_RDD___CMPY__RS__RT________N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = cmpy (R%d, R%d *) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x70000c0) { - // Instruction: 14: 11100111N00sssssPP0ttttt110xxxxx | Rxx += cmpy (Rs, Rt) [:<instruction = HEX_INS_RXX__PLUS_EQ__CMPY__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += cmpy (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x70000e0) { - // Instruction: 14: 11100111N00sssssPP0ttttt111xxxxx | Rxx -= cmpy (Rs, Rt) [:<instruction = HEX_INS_RXX__MINUS_EQ__CMPY__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d -= cmpy (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x74000c0) { - // Instruction: 14: 11100111N10sssssPP0ttttt110xxxxx | Rxx += cmpy (Rs, Rt *) [:<instruction = HEX_INS_RXX__PLUS_EQ__CMPY__RS__RT________N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += cmpy (R%d, R%d *) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x74000e0) { - // Instruction: 14: 11100111N10sssssPP0ttttt111xxxxx | Rxx -= cmpy (Rs, Rt *) [:<instruction = HEX_INS_RXX__MINUS_EQ__CMPY__RS__RT________N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d -= cmpy (R%d, R%d *) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5000020) { - // Instruction: 14: 11100101000sssssPP0ttttt001ddddd | Rdd = cmpyi (Rs, Rt) - hi->instruction = HEX_INS_RDD___CMPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = cmpyi (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5000040) { - // Instruction: 14: 11100101000sssssPP0ttttt010ddddd | Rdd = cmpyr (Rs, Rt) - hi->instruction = HEX_INS_RDD___CMPYR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = cmpyr (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7000020) { - // Instruction: 14: 11100111000sssssPP0ttttt001xxxxx | Rxx += cmpyi (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__CMPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += cmpyi (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7000040) { - // Instruction: 14: 11100111000sssssPP0ttttt010xxxxx | Rxx += cmpyr (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__CMPYR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += cmpyr (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xd2000c0) { - // Instruction: 14: 11101101N01sssssPP0ttttt110ddddd | Rd = cmpy (Rs, Rt) [:<instruction = HEX_INS_RD___CMPY__RS__RT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpy (R%d, R%d) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xd6000c0) { - // Instruction: 14: 11101101N11sssssPP0ttttt110ddddd | Rd = cmpy (Rs, Rt *) [:<instruction = HEX_INS_RD___CMPY__RS__RT________N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = cmpy (R%d, R%d *) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x82000c0) { - // Instruction: 14: 11101000N01sssssPP0ttttt110ddddd | Rdd = vcmpyr (Rss, Rtt) [:<instruction = HEX_INS_RDD___VCMPYR__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vcmpyr (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x84000c0) { - // Instruction: 14: 11101000N10sssssPP0ttttt110ddddd | Rdd = vcmpyi (Rss, Rtt) [:<instruction = HEX_INS_RDD___VCMPYI__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vcmpyi (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa200080) { - // Instruction: 14: 11101010001sssssPP0ttttt100xxxxx | Rxx += vcmpyr (Rss, Rtt) :sat - hi->instruction = HEX_INS_RXX__PLUS_EQ__VCMPYR__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vcmpyr (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400080) { - // Instruction: 14: 11101010010sssssPP0ttttt100xxxxx | Rxx += vcmpyi (Rss, Rtt) :sat - hi->instruction = HEX_INS_RXX__PLUS_EQ__VCMPYI__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vcmpyi (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8000000) { - // Instruction: 14: 11101000000sssssPP0ttttt000ddddd | Rdd = vrcmpyi (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRCMPYI__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyi (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8000020) { - // Instruction: 14: 11101000000sssssPP0ttttt001ddddd | Rdd = vrcmpyr (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRCMPYR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyr (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8400000) { - // Instruction: 14: 11101000010sssssPP0ttttt000ddddd | Rdd = vrcmpyi (Rss, Rtt *) - hi->instruction = HEX_INS_RDD___VRCMPYI__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyi (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8600020) { - // Instruction: 14: 11101000011sssssPP0ttttt001ddddd | Rdd = vrcmpyr (Rss, Rtt *) - hi->instruction = HEX_INS_RDD___VRCMPYR__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrcmpyr (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa000000) { - // Instruction: 14: 11101010000sssssPP0ttttt000xxxxx | Rxx += vrcmpyi (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYI__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyi (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa000020) { - // Instruction: 14: 11101010000sssssPP0ttttt001xxxxx | Rxx += vrcmpyr (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYR__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyr (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa400000) { - // Instruction: 14: 11101010010sssssPP0ttttt000xxxxx | Rxx += vrcmpyi (Rss, Rtt *) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYI__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyi (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa600020) { - // Instruction: 14: 11101010011sssssPP0ttttt001xxxxx | Rxx += vrcmpyr (Rss, Rtt *) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYR__RSS__RTT___; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrcmpyr (R%d:R%d, R%d:R%d *)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8a00080) { - // Instruction: 14: 11101000101sssssPP0ttttt100ddddd | Rdd = vrcmpys (Rss, Rtt) :<<1:sat:raw:hi - hi->instruction = HEX_INS_RDD___VRCMPYS__RSS__RTT_____1_SAT_RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:hi", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8e00080) { - // Instruction: 14: 11101000111sssssPP0ttttt100ddddd | Rdd = vrcmpys (Rss, Rtt) :<<1:sat:raw:lo - hi->instruction = HEX_INS_RDD___VRCMPYS__RSS__RTT_____1_SAT_RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:lo", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xaa00080) { - // Instruction: 14: 11101010101sssssPP0ttttt100xxxxx | Rxx += vrcmpys (Rss, Rtt) :<<1:sat:raw:hi - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYS__RSS__RTT_____1_SAT_RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:hi", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xae00080) { - // Instruction: 14: 11101010111sssssPP0ttttt100xxxxx | Rxx += vrcmpys (Rss, Rtt) :<<1:sat:raw:lo - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRCMPYS__RSS__RTT_____1_SAT_RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vrcmpys (R%d:R%d, R%d:R%d) :<<1:sat:raw:lo", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa020e0) == 0x9a000c0) { - // Instruction: 14: 111010011-1sssssPP0ttttt110ddddd | Rd = vrcmpys (Rss, Rtt) :<<1:rnd:sat:raw:hi - hi->instruction = HEX_INS_RD___VRCMPYS__RSS__RTT_____1_RND_SAT_RAW_HI; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_HI; // :hi - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:rnd:sat:raw:hi", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa020e0) == 0x9a000e0) { - // Instruction: 14: 111010011-1sssssPP0ttttt111ddddd | Rd = vrcmpys (Rss, Rtt) :<<1:rnd:sat:raw:lo - hi->instruction = HEX_INS_RD___VRCMPYS__RSS__RTT_____1_RND_SAT_RAW_LO; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_LO; // :lo - hi->pf |= HEX_PF_RAW; // :raw - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vrcmpys (R%d:R%d, R%d:R%d) :<<1:rnd:sat:raw:lo", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb000000) { - // Instruction: 14: 11101011000sssssPP0ttttt000ddddd | Rd = sfadd (Rs, Rt) - hi->instruction = HEX_INS_RD___SFADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfadd (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xbc00000) { - // Instruction: 14: 11101011110sssssPP0ttttt000ddddd | Rd = sffixupn (Rs, Rt) - hi->instruction = HEX_INS_RD___SFFIXUPN__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sffixupn (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xbc00020) { - // Instruction: 14: 11101011110sssssPP0ttttt001ddddd | Rd = sffixupd (Rs, Rt) - hi->instruction = HEX_INS_RD___SFFIXUPD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sffixupd (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000080) { - // Instruction: 14: 11101111000sssssPP0ttttt100xxxxx | Rx += sfmpy (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__SFMPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += sfmpy (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf0000a0) { - // Instruction: 14: 11101111000sssssPP0ttttt101xxxxx | Rx -= sfmpy (Rs, Rt) - hi->instruction = HEX_INS_RX__MINUS_EQ__SFMPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= sfmpy (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xf600080) { - // Instruction: 14: 11101111011sssssPP0ttttt1uuxxxxx | Rx += sfmpy (Rs, Rt, Pu) :scale - hi->instruction = HEX_INS_RX__PLUS_EQ__SFMPY__RS__RT__PU___SCALE; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_PREDICATE; - hi->ops[3].op.pred = (((hi_u32)&0x60) >> 5); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SCALE; // :scale - sprintf(hi->mnem, "R%d += sfmpy (R%d, R%d, P%d) :scale", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.pred); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf0000c0) { - // Instruction: 14: 11101111000sssssPP0ttttt110xxxxx | Rx += sfmpy (Rs, Rt) :lib - hi->instruction = HEX_INS_RX__PLUS_EQ__SFMPY__RS__RT___LIB; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += sfmpy (R%d, R%d) :lib", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf0000e0) { - // Instruction: 14: 11101111000sssssPP0ttttt111xxxxx | Rx -= sfmpy (Rs, Rt) :lib - hi->instruction = HEX_INS_RX__MINUS_EQ__SFMPY__RS__RT___LIB; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= sfmpy (R%d, R%d) :lib", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb800000) { - // Instruction: 14: 11101011100sssssPP0ttttt000ddddd | Rd = sfmax (Rs, Rt) - hi->instruction = HEX_INS_RD___SFMAX__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfmax (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb800020) { - // Instruction: 14: 11101011100sssssPP0ttttt001ddddd | Rd = sfmin (Rs, Rt) - hi->instruction = HEX_INS_RD___SFMIN__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfmin (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb400000) { - // Instruction: 14: 11101011010sssssPP0ttttt000ddddd | Rd = sfmpy (Rs, Rt) - hi->instruction = HEX_INS_RD___SFMPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfmpy (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe02080) == 0xbe00080) { - // Instruction: 14: 11101011111sssssPP0ttttt1eeddddd | Rd, Pe = sfrecipa (Rs, Rt) - hi->instruction = HEX_INS_RD__PE___SFRECIPA__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d, P%d = sfrecipa (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xb000020) { - // Instruction: 14: 11101011000sssssPP0ttttt001ddddd | Rd = sfsub (Rs, Rt) - hi->instruction = HEX_INS_RD___SFSUB__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sfsub (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 14: 11100011000sssssPP-yyyyy---uuuuu | Ry = add (Ru, mpyi (Ry, Rs)) - hi->instruction = HEX_INS_RY___ADD__RU__MPYI__RY__RS__; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Ry - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, mpyi (Ry, R%d))", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf802000) == 0x0) { - // Instruction: 14: 111000000--sssssPP0iiiiiiiiddddd | Rd = + mpyi (Rs, #u8) - hi->instruction = HEX_INS_RD__EQ_PLUS__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = + mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x800000) { - // Instruction: 14: 111000001--sssssPP0iiiiiiiiddddd | Rd = - mpyi (Rs, #u8) - hi->instruction = HEX_INS_RD__EQ_MINUS__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = - mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x1000000) { - // Instruction: 14: 111000010--sssssPP0iiiiiiiixxxxx | Rx += mpyi (Rs, #u8) - hi->instruction = HEX_INS_RX__PLUS_EQ__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xf802000) == 0x1800000) { - // Instruction: 14: 111000011--sssssPP0iiiiiiiixxxxx | Rx -= mpyi (Rs, #u8) - hi->instruction = HEX_INS_RX__MINUS_EQ__MPYI__RS___U8_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_IMM; - hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyi (R%d, 0x%x)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.imm); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd000000) { - // Instruction: 14: 11101101000sssssPP0ttttt000ddddd | Rd = mpyi (Rs, Rt) - hi->instruction = HEX_INS_RD___MPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyi (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf000000) { - // Instruction: 14: 11101111000sssssPP0ttttt000xxxxx | Rx += mpyi (Rs, Rt) - hi->instruction = HEX_INS_RX__PLUS_EQ__MPYI__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyi (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x80000a0) { - // Instruction: 14: 11101000N00sssssPP0ttttt101ddddd | Rdd = vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x80000e0) { - // Instruction: 14: 11101000N00sssssPP0ttttt111ddddd | Rdd = vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywoh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x82000a0) { - // Instruction: 14: 11101000N01sssssPP0ttttt101ddddd | Rdd = vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x82000e0) { - // Instruction: 14: 11101000N01sssssPP0ttttt111ddddd | Rdd = vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywoh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa0000a0) { - // Instruction: 14: 11101010N00sssssPP0ttttt101xxxxx | Rxx += vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa0000e0) { - // Instruction: 14: 11101010N00sssssPP0ttttt111xxxxx | Rxx += vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywoh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa2000a0) { - // Instruction: 14: 11101010N01sssssPP0ttttt101xxxxx | Rxx += vmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa2000e0) { - // Instruction: 14: 11101010N01sssssPP0ttttt111xxxxx | Rxx += vmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywoh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x84000a0) { - // Instruction: 14: 11101000N10sssssPP0ttttt101ddddd | Rdd = vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweuh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x84000e0) { - // Instruction: 14: 11101000N10sssssPP0ttttt111ddddd | Rdd = vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywouh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x86000a0) { - // Instruction: 14: 11101000N11sssssPP0ttttt101ddddd | Rdd = vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWEUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyweuh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x86000e0) { - // Instruction: 14: 11101000N11sssssPP0ttttt111ddddd | Rdd = vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYWOUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpywouh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa4000a0) { - // Instruction: 14: 11101010N10sssssPP0ttttt101xxxxx | Rxx += vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweuh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa4000e0) { - // Instruction: 14: 11101010N10sssssPP0ttttt111xxxxx | Rxx += vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOUH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywouh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa6000a0) { - // Instruction: 14: 11101010N11sssssPP0ttttt101xxxxx | Rxx += vmpyweuh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWEUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyweuh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa6000e0) { - // Instruction: 14: 11101010N11sssssPP0ttttt111xxxxx | Rxx += vmpywouh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYWOUH__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpywouh (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000000) { - // Instruction: 14: 11100100N00sssssPP-ttttt-00ddddd | Rdd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000020) { - // Instruction: 14: 11100100N00sssssPP-ttttt-01ddddd | Rdd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000040) { - // Instruction: 14: 11100100N00sssssPP-ttttt-10ddddd | Rdd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4000060) { - // Instruction: 14: 11100100N00sssssPP-ttttt-11ddddd | Rdd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200000) { - // Instruction: 14: 11100100N01sssssPP-ttttt-00ddddd | Rdd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.L) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200020) { - // Instruction: 14: 11100100N01sssssPP-ttttt-01ddddd | Rdd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_L__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.L, R%d.H) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200040) { - // Instruction: 14: 11100100N01sssssPP-ttttt-10ddddd | Rdd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.L) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4200060) { - // Instruction: 14: 11100100N01sssssPP-ttttt-11ddddd | Rdd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RDD___MPY__RS_H__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d:R%d = mpy (R%d.H, R%d.H) %s:rnd", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000000) { - // Instruction: 14: 11100110N00sssssPP-ttttt000xxxxx | Rxx += mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000020) { - // Instruction: 14: 11100110N00sssssPP-ttttt001xxxxx | Rxx += mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000040) { - // Instruction: 14: 11100110N00sssssPP-ttttt010xxxxx | Rxx += mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6000060) { - // Instruction: 14: 11100110N00sssssPP-ttttt011xxxxx | Rxx += mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200000) { - // Instruction: 14: 11100110N01sssssPP-ttttt000xxxxx | Rxx -= mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200020) { - // Instruction: 14: 11100110N01sssssPP-ttttt001xxxxx | Rxx -= mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200040) { - // Instruction: 14: 11100110N01sssssPP-ttttt010xxxxx | Rxx -= mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6200060) { - // Instruction: 14: 11100110N01sssssPP-ttttt011xxxxx | Rxx -= mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000000) { - // Instruction: 14: 11101100N00sssssPP-ttttt000ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000020) { - // Instruction: 14: 11101100N00sssssPP-ttttt001ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000040) { - // Instruction: 14: 11101100N00sssssPP-ttttt010ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000060) { - // Instruction: 14: 11101100N00sssssPP-ttttt011ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc000080) { - // Instruction: 14: 11101100N00sssssPP-ttttt100ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc0000a0) { - // Instruction: 14: 11101100N00sssssPP-ttttt101ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc0000c0) { - // Instruction: 14: 11101100N00sssssPP-ttttt110ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc0000e0) { - // Instruction: 14: 11101100N00sssssPP-ttttt111ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200000) { - // Instruction: 14: 11101100N01sssssPP-ttttt000ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200020) { - // Instruction: 14: 11101100N01sssssPP-ttttt001ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200040) { - // Instruction: 14: 11101100N01sssssPP-ttttt010ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200060) { - // Instruction: 14: 11101100N01sssssPP-ttttt011ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N__RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s:rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc200080) { - // Instruction: 14: 11101100N01sssssPP-ttttt100ddddd | Rd = mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_L______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.L) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc2000a0) { - // Instruction: 14: 11101100N01sssssPP-ttttt101ddddd | Rd = mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_L__RT_H______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.L, R%d.H) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc2000c0) { - // Instruction: 14: 11101100N01sssssPP-ttttt110ddddd | Rd = mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_L______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.L) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc2000e0) { - // Instruction: 14: 11101100N01sssssPP-ttttt111ddddd | Rd = mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPY__RS_H__RT_H______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d.H, R%d.H) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000000) { - // Instruction: 14: 11101110N00sssssPP-ttttt000xxxxx | Rx += mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000020) { - // Instruction: 14: 11101110N00sssssPP-ttttt001xxxxx | Rx += mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000040) { - // Instruction: 14: 11101110N00sssssPP-ttttt010xxxxx | Rx += mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000060) { - // Instruction: 14: 11101110N00sssssPP-ttttt011xxxxx | Rx += mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe000080) { - // Instruction: 14: 11101110N00sssssPP-ttttt100xxxxx | Rx += mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe0000a0) { - // Instruction: 14: 11101110N00sssssPP-ttttt101xxxxx | Rx += mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_L__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.L, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe0000c0) { - // Instruction: 14: 11101110N00sssssPP-ttttt110xxxxx | Rx += mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe0000e0) { - // Instruction: 14: 11101110N00sssssPP-ttttt111xxxxx | Rx += mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPY__RS_H__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d.H, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200000) { - // Instruction: 14: 11101110N01sssssPP-ttttt000xxxxx | Rx -= mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200020) { - // Instruction: 14: 11101110N01sssssPP-ttttt001xxxxx | Rx -= mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200040) { - // Instruction: 14: 11101110N01sssssPP-ttttt010xxxxx | Rx -= mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200060) { - // Instruction: 14: 11101110N01sssssPP-ttttt011xxxxx | Rx -= mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe200080) { - // Instruction: 14: 11101110N01sssssPP-ttttt100xxxxx | Rx -= mpy (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe2000a0) { - // Instruction: 14: 11101110N01sssssPP-ttttt101xxxxx | Rx -= mpy (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_L__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.L, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe2000c0) { - // Instruction: 14: 11101110N01sssssPP-ttttt110xxxxx | Rx -= mpy (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_L______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.L) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe2000e0) { - // Instruction: 14: 11101110N01sssssPP-ttttt111xxxxx | Rx -= mpy (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPY__RS_H__RT_H______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d.H, R%d.H) %s:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400000) { - // Instruction: 14: 11100100N10sssssPP-ttttt-00ddddd | Rdd = mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RDD___MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400020) { - // Instruction: 14: 11100100N10sssssPP-ttttt-01ddddd | Rdd = mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RDD___MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400040) { - // Instruction: 14: 11100100N10sssssPP-ttttt-10ddddd | Rdd = mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RDD___MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf600060) == 0x4400060) { - // Instruction: 14: 11100100N10sssssPP-ttttt-11ddddd | Rdd = mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RDD___MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400000) { - // Instruction: 14: 11100110N10sssssPP-ttttt000xxxxx | Rxx += mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400020) { - // Instruction: 14: 11100110N10sssssPP-ttttt001xxxxx | Rxx += mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400040) { - // Instruction: 14: 11100110N10sssssPP-ttttt010xxxxx | Rxx += mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6400060) { - // Instruction: 14: 11100110N10sssssPP-ttttt011xxxxx | Rxx += mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600000) { - // Instruction: 14: 11100110N11sssssPP-ttttt000xxxxx | Rxx -= mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600020) { - // Instruction: 14: 11100110N11sssssPP-ttttt001xxxxx | Rxx -= mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600040) { - // Instruction: 14: 11100110N11sssssPP-ttttt010xxxxx | Rxx -= mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0x6600060) { - // Instruction: 14: 11100110N11sssssPP-ttttt011xxxxx | Rxx -= mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400000) { - // Instruction: 14: 11101100N10sssssPP-ttttt000ddddd | Rd = mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RD___MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400020) { - // Instruction: 14: 11101100N10sssssPP-ttttt001ddddd | Rd = mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RD___MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400040) { - // Instruction: 14: 11101100N10sssssPP-ttttt010ddddd | Rd = mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RD___MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xc400060) { - // Instruction: 14: 11101100N10sssssPP-ttttt011ddddd | Rd = mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RD___MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400000) { - // Instruction: 14: 11101110N10sssssPP-ttttt000xxxxx | Rx += mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400020) { - // Instruction: 14: 11101110N10sssssPP-ttttt001xxxxx | Rx += mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400040) { - // Instruction: 14: 11101110N10sssssPP-ttttt010xxxxx | Rx += mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe400060) { - // Instruction: 14: 11101110N10sssssPP-ttttt011xxxxx | Rx += mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__PLUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d += mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600000) { - // Instruction: 14: 11101110N11sssssPP-ttttt000xxxxx | Rx -= mpyu (Rs.L, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_L__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.L, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600020) { - // Instruction: 14: 11101110N11sssssPP-ttttt001xxxxx | Rx -= mpyu (Rs.L, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_L__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.L, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600040) { - // Instruction: 14: 11101110N11sssssPP-ttttt010xxxxx | Rx -= mpyu (Rs.H, Rt.L) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_H__RT_L______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.H, R%d.L) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6000e0) == 0xe600060) { - // Instruction: 14: 11101110N11sssssPP-ttttt011xxxxx | Rx -= mpyu (Rs.H, Rt.H) [:<instruction = HEX_INS_RX__MINUS_EQ__MPYU__RS_H__RT_H______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d -= mpyu (R%d.H, R%d.H) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x54000e0) { - // Instruction: 14: 11100101010sssssPP0ttttt111ddddd | Rdd = pmpyw (Rs, Rt) - hi->instruction = HEX_INS_RDD___PMPYW__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = pmpyw (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x72000e0) { - // Instruction: 14: 11100111001sssssPP0ttttt111xxxxx | Rxx ^= pmpyw (Rs, Rt) - hi->instruction = HEX_INS_RXX____PMPYW__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= pmpyw (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x8200040) { - // Instruction: 14: 11101000N01sssssPP0ttttt010ddddd | Rdd = vrmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VRMPYWOH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpywoh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x8400080) { - // Instruction: 14: 11101000N10sssssPP0ttttt100ddddd | Rdd = vrmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VRMPYWEH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpyweh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa2000c0) { - // Instruction: 14: 11101010N01sssssPP0ttttt110xxxxx | Rxx += vrmpyweh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VRMPYWEH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpyweh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa6000c0) { - // Instruction: 14: 11101010N11sssssPP0ttttt110xxxxx | Rxx += vrmpywoh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VRMPYWOH__RSS__RTT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpywoh (R%d:R%d, R%d:R%d) %s", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd200020) { - // Instruction: 14: 11101101001sssssPP0ttttt001ddddd | Rd = mpy (Rs, Rt) :rnd - hi->instruction = HEX_INS_RD___MPY__RS__RT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = mpy (R%d, R%d) :rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd400020) { - // Instruction: 14: 11101101010sssssPP0ttttt001ddddd | Rd = mpyu (Rs, Rt) - hi->instruction = HEX_INS_RD___MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpyu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xd600020) { - // Instruction: 14: 11101101011sssssPP0ttttt001ddddd | Rd = mpysu (Rs, Rt) - hi->instruction = HEX_INS_RD___MPYSU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpysu (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xda00000) { - // Instruction: 14: 11101101101sssssPP0ttttt000ddddd | Rd = mpy (Rs, Rt.H) :<<1:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_H_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.H) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xda00020) { - // Instruction: 14: 11101101101sssssPP0ttttt001ddddd | Rd = mpy (Rs, Rt.L) :<<1:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_L_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.L) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xda00080) { - // Instruction: 14: 11101101101sssssPP0ttttt100ddddd | Rd = mpy (Rs, Rt.H) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_H_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.H) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xde00000) { - // Instruction: 14: 11101101111sssssPP0ttttt000ddddd | Rd = mpy (Rs, Rt) :<<1:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xde00080) { - // Instruction: 14: 11101101111sssssPP0ttttt100ddddd | Rd = mpy (Rs, Rt.L) :<<1:rnd:sat - hi->instruction = HEX_INS_RD___MPY__RS__RT_L_____1_RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = mpy (R%d, R%d.L) :<<1:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf402080) == 0xd000000) { - // Instruction: 14: 11101101N0NsssssPP0ttttt0NNddddd | Rd = mpy (Rs, Rt) [:<instruction = HEX_INS_RD___MPY__RS__RT______N_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32 & 0x800000) >> 20) | ((hi_u32 & 0x200000) >> 19) | ((hi_u32 & 0x60) >> 5))) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mpy (R%d, R%d) %s", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf600000) { - // Instruction: 14: 11101111011sssssPP0ttttt000xxxxx | Rx += mpy (Rs, Rt) :<<1:sat - hi->instruction = HEX_INS_RX__PLUS_EQ__MPY__RS__RT_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d += mpy (R%d, R%d) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xf600020) { - // Instruction: 14: 11101111011sssssPP0ttttt001xxxxx | Rx -= mpy (Rs, Rt) :<<1:sat - hi->instruction = HEX_INS_RX__MINUS_EQ__MPY__RS__RT_____1_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_LSH1; // :<<1 - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d -= mpy (R%d, R%d) :<<1:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5000000) { - // Instruction: 14: 11100101000sssssPP0ttttt000ddddd | Rdd = mpy (Rs, Rt) - hi->instruction = HEX_INS_RDD___MPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpy (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5400000) { - // Instruction: 14: 11100101010sssssPP0ttttt000ddddd | Rdd = mpyu (Rs, Rt) - hi->instruction = HEX_INS_RDD___MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = mpyu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7000000) { - // Instruction: 14: 11100111000sssssPP0ttttt000xxxxx | Rxx += mpy (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__MPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpy (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7200000) { - // Instruction: 14: 11100111001sssssPP0ttttt000xxxxx | Rxx -= mpy (Rs, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__MPY__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpy (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7400000) { - // Instruction: 14: 11100111010sssssPP0ttttt000xxxxx | Rxx += mpyu (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += mpyu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7600000) { - // Instruction: 14: 11100111011sssssPP0ttttt000xxxxx | Rxx -= mpyu (Rs, Rt) - hi->instruction = HEX_INS_RXX__MINUS_EQ__MPYU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d -= mpyu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x8000080) { - // Instruction: 14: 11101000N00sssssPP0ttttt100ddddd | Rdd = vdmpy (Rss, Rtt) [:<instruction = HEX_INS_RDD___VDMPY__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vdmpy (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa000080) { - // Instruction: 14: 11101010N00sssssPP0ttttt100xxxxx | Rxx += vdmpy (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VDMPY__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vdmpy (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf002060) == 0x9000000) { - // Instruction: 14: 11101001N--sssssPP0ttttt-00ddddd | Rd = vdmpy (Rss, Rtt) [:<instruction = HEX_INS_RD___VDMPY__RSS__RTT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vdmpy (R%d:R%d, R%d:R%d) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8800020) { - // Instruction: 14: 11101000100sssssPP0ttttt001ddddd | Rdd = vrmpybu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRMPYBU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpybu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8c00020) { - // Instruction: 14: 11101000110sssssPP0ttttt001ddddd | Rdd = vrmpybsu (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRMPYBSU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpybsu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa800020) { - // Instruction: 14: 11101010100sssssPP0ttttt001xxxxx | Rxx += vrmpybu (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRMPYBU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpybu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xac00020) { - // Instruction: 14: 11101010110sssssPP0ttttt001xxxxx | Rxx += vrmpybsu (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRMPYBSU__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpybsu (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8a00020) { - // Instruction: 14: 11101000101sssssPP0ttttt001ddddd | Rdd = vdmpybsu (Rss, Rtt) :sat - hi->instruction = HEX_INS_RDD___VDMPYBSU__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vdmpybsu (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa200020) { - // Instruction: 14: 11101010001sssssPP0ttttt001xxxxx | Rxx += vdmpybsu (Rss, Rtt) :sat - hi->instruction = HEX_INS_RXX__PLUS_EQ__VDMPYBSU__RSS__RTT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vdmpybsu (R%d:R%d, R%d:R%d) :sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x80000c0) { - // Instruction: 14: 11101000N00sssssPP0ttttt110ddddd | Rdd = vmpyeh (Rss, Rtt) [:<instruction = HEX_INS_RDD___VMPYEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyeh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa200040) { - // Instruction: 14: 11101010001sssssPP0ttttt010xxxxx | Rxx += vmpyeh (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYEH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpyeh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xa0000c0) { - // Instruction: 14: 11101010N00sssssPP0ttttt110xxxxx | Rxx += vmpyeh (Rss, Rtt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYEH__RSS__RTT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyeh (R%d:R%d, R%d:R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x50000a0) { - // Instruction: 14: 11100101N00sssssPP0ttttt101ddddd | Rdd = vmpyh (Rs, Rt) [:<instruction = HEX_INS_RDD___VMPYH__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyh (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7200020) { - // Instruction: 14: 11100111001sssssPP0ttttt001xxxxx | Rxx += vmpyh (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpyh (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x70000a0) { - // Instruction: 14: 11100111N00sssssPP0ttttt101xxxxx | Rxx += vmpyh (Rs, Rt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYH__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyh (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0xd2000e0) { - // Instruction: 14: 11101101N01sssssPP0ttttt111ddddd | Rd = vmpyh (Rs, Rt) [:<instruction = HEX_INS_RD___VMPYH__RS__RT______N__RND_SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vmpyh (R%d, R%d) %s:rnd:sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x50000e0) { - // Instruction: 14: 11100101N00sssssPP0ttttt111ddddd | Rdd = vmpyhsu (Rs, Rt) [:<instruction = HEX_INS_RDD___VMPYHSU__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d = vmpyhsu (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xf6020e0) == 0x76000a0) { - // Instruction: 14: 11100111N11sssssPP0ttttt101xxxxx | Rxx += vmpyhsu (Rs, Rt) [:<instruction = HEX_INS_RXX__PLUS_EQ__VMPYHSU__RS__RT______N__SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - if ((((hi_u32)&0x800000) >> 23)) { - hi->pf |= HEX_PF_LSH1; // [:<<1] - } - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d:R%d += vmpyhsu (R%d, R%d) %s:sat", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg, ((hi->pf & HEX_PF_LSH1) == HEX_PF_LSH1) ? ":<<1" : ""); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x8000040) { - // Instruction: 14: 11101000000sssssPP0ttttt010ddddd | Rdd = vrmpyh (Rss, Rtt) - hi->instruction = HEX_INS_RDD___VRMPYH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vrmpyh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0xa000040) { - // Instruction: 14: 11101010000sssssPP0ttttt010xxxxx | Rxx += vrmpyh (Rss, Rtt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VRMPYH__RSS__RTT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].attr |= HEX_OP_REG_PAIR; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vrmpyh (R%d:R%d, R%d:R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg + 1, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5400020) { - // Instruction: 14: 11100101010sssssPP0ttttt001ddddd | Rdd = vmpybsu (Rs, Rt) - hi->instruction = HEX_INS_RDD___VMPYBSU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmpybsu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5800020) { - // Instruction: 14: 11100101100sssssPP0ttttt001ddddd | Rdd = vmpybu (Rs, Rt) - hi->instruction = HEX_INS_RDD___VMPYBU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vmpybu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7800020) { - // Instruction: 14: 11100111100sssssPP0ttttt001xxxxx | Rxx += vmpybu (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYBU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpybu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7c00020) { - // Instruction: 14: 11100111110sssssPP0ttttt001xxxxx | Rxx += vmpybsu (Rs, Rt) - hi->instruction = HEX_INS_RXX__PLUS_EQ__VMPYBSU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d += vmpybsu (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x5c000e0) { - // Instruction: 14: 11100101110sssssPP0ttttt111ddddd | Rdd = vpmpyh (Rs, Rt) - hi->instruction = HEX_INS_RDD___VPMPYH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = vpmpyh (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe020e0) == 0x7a000e0) { - // Instruction: 14: 11100111101sssssPP0ttttt111xxxxx | Rxx ^= vpmpyh (Rs, Rt) - hi->instruction = HEX_INS_RXX____VPMPYH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d ^= vpmpyh (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - break; - } - case 0xf: { - if ((hi_u32 & 0xfe00000) == 0x3000000) { - // Instruction: 15: 11110011000sssssPP-ttttt---ddddd | Rd = add (Rs, Rt) - hi->instruction = HEX_INS_RD___ADD__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = add (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6400000) { - // Instruction: 15: 11110110010sssssPP-ttttt---ddddd | Rd = add (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___ADD__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = add (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1000000) { - // Instruction: 15: 11110001000sssssPP-ttttt---ddddd | Rd = and (Rs, Rt) - hi->instruction = HEX_INS_RD___AND__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = and (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1200000) { - // Instruction: 15: 11110001001sssssPP-ttttt---ddddd | Rd = or (Rs, Rt) - hi->instruction = HEX_INS_RD___OR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = or (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1600000) { - // Instruction: 15: 11110001011sssssPP-ttttt---ddddd | Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_RD___XOR__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = xor (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1800000) { - // Instruction: 15: 11110001100sssssPP-ttttt---ddddd | Rd = and (Rt, ~Rs) - hi->instruction = HEX_INS_RD___AND__RT___RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = and (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x1a00000) { - // Instruction: 15: 11110001101sssssPP-ttttt---ddddd | Rd = or (Rt, ~Rs) - hi->instruction = HEX_INS_RD___OR__RT___RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = or (R%d, ~R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3200000) { - // Instruction: 15: 11110011001sssssPP-ttttt---ddddd | Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_RD___SUB__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = sub (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6c00000) { - // Instruction: 15: 11110110110sssssPP-ttttt---ddddd | Rd = sub (Rt, Rs) :sat - hi->instruction = HEX_INS_RD___SUB__RT__RS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = sub (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6000000) { - // Instruction: 15: 11110110000sssssPP-ttttt---ddddd | Rd = vaddh (Rs, Rt) - hi->instruction = HEX_INS_RD___VADDH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vaddh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6200000) { - // Instruction: 15: 11110110001sssssPP-ttttt---ddddd | Rd = vaddh (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___VADDH__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vaddh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6600000) { - // Instruction: 15: 11110110011sssssPP-ttttt---ddddd | Rd = vadduh (Rs, Rt) :sat - hi->instruction = HEX_INS_RD___VADDUH__RS__RT___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vadduh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600000) == 0x7000000) { - // Instruction: 15: 11110111-00sssssPP-ttttt---ddddd | Rd = vavgh (Rs, Rt) - hi->instruction = HEX_INS_RD___VAVGH__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vavgh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600000) == 0x7200000) { - // Instruction: 15: 11110111-01sssssPP-ttttt---ddddd | Rd = vavgh (Rs, Rt) :rnd - hi->instruction = HEX_INS_RD___VAVGH__RS__RT___RND; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_RND; // :rnd - sprintf(hi->mnem, "R%d = vavgh (R%d, R%d) :rnd", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf600000) == 0x7600000) { - // Instruction: 15: 11110111-11sssssPP-ttttt---ddddd | Rd = vnavgh (Rt, Rs) - hi->instruction = HEX_INS_RD___VNAVGH__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vnavgh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6800000) { - // Instruction: 15: 11110110100sssssPP-ttttt---ddddd | Rd = vsubh (Rt, Rs) - hi->instruction = HEX_INS_RD___VSUBH__RT__RS_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = vsubh (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6a00000) { - // Instruction: 15: 11110110101sssssPP-ttttt---ddddd | Rd = vsubh (Rt, Rs) :sat - hi->instruction = HEX_INS_RD___VSUBH__RT__RS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vsubh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x6e00000) { - // Instruction: 15: 11110110111sssssPP-ttttt---ddddd | Rd = vsubuh (Rt, Rs) :sat - hi->instruction = HEX_INS_RD___VSUBUH__RT__RS___SAT; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - hi->pf |= HEX_PF_SAT; // :sat - sprintf(hi->mnem, "R%d = vsubuh (R%d, R%d) :sat", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3800000) { - // Instruction: 15: 11110011100sssssPP-ttttt---ddddd | Rd = combine (Rt.H, Rs.H) - hi->instruction = HEX_INS_RD___COMBINE__RT_H__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.H, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3a00000) { - // Instruction: 15: 11110011101sssssPP-ttttt---ddddd | Rd = combine (Rt.H, Rs.L) - hi->instruction = HEX_INS_RD___COMBINE__RT_H__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.H, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3c00000) { - // Instruction: 15: 11110011110sssssPP-ttttt---ddddd | Rd = combine (Rt.L, Rs.H) - hi->instruction = HEX_INS_RD___COMBINE__RT_L__RS_H_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.L, R%d.H)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfe00000) == 0x3e00000) { - // Instruction: 15: 11110011111sssssPP-ttttt---ddddd | Rd = combine (Rt.L, Rs.L) - hi->instruction = HEX_INS_RD___COMBINE__RT_L__RS_L_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = combine (R%d.L, R%d.L)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x5000000) { - // Instruction: 15: 111101010--sssssPP-ttttt---ddddd | Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_RDD___COMBINE__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xf000000) == 0x4000000) { - // Instruction: 15: 11110100---sssssPP-ttttt-uuddddd | Rd = mux (Pu, Rs, Rt) - hi->instruction = HEX_INS_RD___MUX__PU__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_PREDICATE; - hi->ops[1].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = mux (P%d, R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.pred, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xf800000) == 0x5800000) { - // Instruction: 15: 111101011--sssssPP-ttttt---ddddd | Rdd = packhl (Rs, Rt) - hi->instruction = HEX_INS_RDD___PACKHL__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].attr |= HEX_OP_REG_PAIR; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d:R%d = packhl (R%d, R%d)", hi->ops[0].op.reg + 1, hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb000000) { - // Instruction: 15: 111110110-0sssssPP0ttttt0uuddddd | if (Pu) Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); - break; - } - if ((hi_u32 & 0xfa02080) == 0xb000080) { - // Instruction: 15: 111110110-0sssssPP0ttttt1uuddddd | if !Pu Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); +static inline bool is_last_instr(const ut8 parse_bits) { + // Duplex instr. (parse bits = 0) are always the last. + return ((parse_bits == 0x3) || (parse_bits == 0x0)); +} + +void hexagon_disasm_duplex_0x0(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xf000f000) == 0x0) { + // 0000IIIISSSSDDDDEE00iiiissssdddd | RD = memw(RS+II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0x1000) { + // 0000IIIISSSSDDDDEE01iiiissssdddd | RD = memw(RS+II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0x10001000) { + // 0001IIIISSSSDDDDEE01iiiissssdddd | RD = memub(RS+II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x1(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xf000ffff) == 0x3f00) { + // 0000iiiissssddddEE11111100000000 | Rd = memw(Rs+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f00) { + // 0001iiiissssddddEE11111100000000 | Rd = memub(Rs+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc0) { + // 0000iiiissssddddEE11111111000000 | Rd = memw(Rs+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc0) { + // 0001iiiissssddddEE11111111000000 | Rd = memub(Rs+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc5) { + // 0000iiiissssddddEE11111111000101 | Rd = memw(Rs+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc5) { + // 0001iiiissssddddEE11111111000101 | Rd = memub(Rs+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc7) { + // 0000iiiissssddddEE11111111000111 | Rd = memw(Rs+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc7) { + // 0001iiiissssddddEE11111111000111 | Rd = memub(Rs+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc4) { + // 0000iiiissssddddEE11111111000100 | Rd = memw(Rs+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc4) { + // 0001iiiissssddddEE11111111000100 | Rd = memub(Rs+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3fc6) { + // 0000iiiissssddddEE11111111000110 | Rd = memw(Rs+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003fc6) { + // 0001iiiissssddddEE11111111000110 | Rd = memub(Rs+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0x3000) { + // 0000IIIISSSSDDDDEE110iiissssdddd | RD = memw(RS+II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0x10003000) { + // 0001IIIISSSSDDDDEE110iiissssdddd | RD = memub(RS+II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0x3e00) { + // 0000IIIIssssDDDDEE111110iiiiiddd | RD = memw(Rs+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0x10003e00) { + // 0001IIIIssssDDDDEE111110iiiiiddd | RD = memub(Rs+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0x2000) { + // 0000IIIISSSSDDDDEE100iiissssdddd | RD = memw(RS+II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0x10002000) { + // 0001IIIISSSSDDDDEE100iiissssdddd | RD = memub(RS+II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0x3c00) { + // 0000IIIIssssDDDDEE11110iiiiidddd | RD = memw(Rs+II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0x10003c00) { + // 0001IIIIssssDDDDEE11110iiiiidddd | RD = memub(Rs+II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0x2800) { + // 0000IIIISSSSDDDDEE101iiissssdddd | RD = memw(RS+II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0x10002800) { + // 0001IIIISSSSDDDDEE101iiissssdddd | RD = memub(RS+II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3f40) { + // 0000iiiissssddddEE11111101000000 | Rd = memw(Rs+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f40) { + // 0001iiiissssddddEE11111101000000 | Rd = memub(Rs+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3f45) { + // 0000iiiissssddddEE11111101000101 | Rd = memw(Rs+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f45) { + // 0001iiiissssddddEE11111101000101 | Rd = memub(Rs+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3f47) { + // 0000iiiissssddddEE11111101000111 | Rd = memw(Rs+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f47) { + // 0001iiiissssddddEE11111101000111 | Rd = memub(Rs+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3f44) { + // 0000iiiissssddddEE11111101000100 | Rd = memw(Rs+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f44) { + // 0001iiiissssddddEE11111101000100 | Rd = memub(Rs+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x3f46) { + // 0000iiiissssddddEE11111101000110 | Rd = memw(Rs+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ffff) == 0x10003f46) { + // 0001iiiissssddddEE11111101000110 | Rd = memub(Rs+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x2(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xffffffff) == 0x3f001f00) { + // 0011111100000000EE01111100000000 | deallocframe ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "deallocframe ; deallocframe"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f00) { + // 00110iiissssddddEE01111100000000 | Rd = memb(Rs+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f00) { + // 00111110iiiiidddEE01111100000000 | Rdd = memd(r29+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f00) { + // 00100iiissssddddEE01111100000000 | Rd = memh(Rs+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f00) { + // 0011110iiiiiddddEE01111100000000 | Rd = memw(r29+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f00) { + // 00101iiissssddddEE01111100000000 | Rd = memuh(Rs+Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc0) { + // 0011111100000000EE01111111000000 | deallocframe ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "deallocframe ; jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc0) { + // 00110iiissssddddEE01111111000000 | Rd = memb(Rs+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc0) { + // 00111110iiiiidddEE01111111000000 | Rdd = memd(r29+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc0) { + // 00100iiissssddddEE01111111000000 | Rd = memh(Rs+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc0) { + // 0011110iiiiiddddEE01111111000000 | Rd = memw(r29+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc0) { + // 00101iiissssddddEE01111111000000 | Rd = memuh(Rs+Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc0) { + // 0011111101000000EE01111111000000 | dealloc_return ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "dealloc_return ; jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc0) { + // 0011111101000101EE01111111000000 | if (!p0) dealloc_return ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc0) { + // 0011111101000111EE01111111000000 | if (!p0.new) dealloc_return:nt ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc0) { + // 0011111101000100EE01111111000000 | if (p0) dealloc_return ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc0) { + // 0011111101000110EE01111111000000 | if (p0.new) dealloc_return:nt ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc5) { + // 0011111100000000EE01111111000101 | deallocframe ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (!P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc5) { + // 00110iiissssddddEE01111111000101 | Rd = memb(Rs+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc5) { + // 00111110iiiiidddEE01111111000101 | Rdd = memd(r29+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc5) { + // 00100iiissssddddEE01111111000101 | Rd = memh(Rs+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc5) { + // 0011110iiiiiddddEE01111111000101 | Rd = memw(r29+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc5) { + // 00101iiissssddddEE01111111000101 | Rd = memuh(Rs+Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc5) { + // 0011111101000000EE01111111000101 | dealloc_return ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (!P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc5) { + // 0011111101000101EE01111111000101 | if (!p0) dealloc_return ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (!P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc5) { + // 0011111101000111EE01111111000101 | if (!p0.new) dealloc_return:nt ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; if (!P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc5) { + // 0011111101000100EE01111111000101 | if (p0) dealloc_return ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (!P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc5) { + // 0011111101000110EE01111111000101 | if (p0.new) dealloc_return:nt ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; if (!P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc7) { + // 0011111100000000EE01111111000111 | deallocframe ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (!P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc7) { + // 00110iiissssddddEE01111111000111 | Rd = memb(Rs+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc7) { + // 00111110iiiiidddEE01111111000111 | Rdd = memd(r29+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc7) { + // 00100iiissssddddEE01111111000111 | Rd = memh(Rs+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc7) { + // 0011110iiiiiddddEE01111111000111 | Rd = memw(r29+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc7) { + // 00101iiissssddddEE01111111000111 | Rd = memuh(Rs+Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc7) { + // 0011111101000000EE01111111000111 | dealloc_return ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (!P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc7) { + // 0011111101000101EE01111111000111 | if (!p0) dealloc_return ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (!P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc7) { + // 0011111101000111EE01111111000111 | if (!p0.new) dealloc_return:nt ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; if (!P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc7) { + // 0011111101000100EE01111111000111 | if (p0) dealloc_return ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (!P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc7) { + // 0011111101000110EE01111111000111 | if (p0.new) dealloc_return:nt ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; if (!P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc4) { + // 0011111100000000EE01111111000100 | deallocframe ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc4) { + // 00110iiissssddddEE01111111000100 | Rd = memb(Rs+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc4) { + // 00111110iiiiidddEE01111111000100 | Rdd = memd(r29+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc4) { + // 00100iiissssddddEE01111111000100 | Rd = memh(Rs+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc4) { + // 0011110iiiiiddddEE01111111000100 | Rd = memw(r29+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc4) { + // 00101iiissssddddEE01111111000100 | Rd = memuh(Rs+Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc4) { + // 0011111101000000EE01111111000100 | dealloc_return ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc4) { + // 0011111101000101EE01111111000100 | if (!p0) dealloc_return ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc4) { + // 0011111101000111EE01111111000100 | if (!p0.new) dealloc_return:nt ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; if (P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc4) { + // 0011111101000100EE01111111000100 | if (p0) dealloc_return ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc4) { + // 0011111101000110EE01111111000100 | if (p0.new) dealloc_return:nt ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; if (P0) jumpr R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001fc6) { + // 0011111100000000EE01111111000110 | deallocframe ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001fc6) { + // 00110iiissssddddEE01111111000110 | Rd = memb(Rs+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001fc6) { + // 00111110iiiiidddEE01111111000110 | Rdd = memd(r29+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001fc6) { + // 00100iiissssddddEE01111111000110 | Rd = memh(Rs+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001fc6) { + // 0011110iiiiiddddEE01111111000110 | Rd = memw(r29+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001fc6) { + // 00101iiissssddddEE01111111000110 | Rd = memuh(Rs+Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401fc6) { + // 0011111101000000EE01111111000110 | dealloc_return ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451fc6) { + // 0011111101000101EE01111111000110 | if (!p0) dealloc_return ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f471fc6) { + // 0011111101000111EE01111111000110 | if (!p0.new) dealloc_return:nt ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; if (P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441fc6) { + // 0011111101000100EE01111111000110 | if (p0) dealloc_return ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461fc6) { + // 0011111101000110EE01111111000110 | if (p0.new) dealloc_return:nt ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; if (P0.new) jumpr:nt R31"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x30001000) { + // 00110IIISSSSDDDDEE010iiissssdddd | RD = memb(RS+II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x20001000) { + // 00100IIISSSSDDDDEE010iiissssdddd | RD = memh(RS+II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x28001000) { + // 00101IIISSSSDDDDEE010iiissssdddd | RD = memuh(RS+II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x30001e00) { + // 00110IIIssssDDDDEE011110iiiiiddd | RD = memb(Rs+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x3e001e00) { + // 00111110IIIIIDDDEE011110iiiiiddd | RDD = memd(r29+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20001e00) { + // 00100IIIssssDDDDEE011110iiiiiddd | RD = memh(Rs+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0x3c001e00) { + // 0011110IIIIIDDDDEE011110iiiiiddd | RD = memw(r29+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x28001e00) { + // 00101IIIssssDDDDEE011110iiiiiddd | RD = memuh(Rs+II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x20000000) { + // 00100IIISSSSDDDDEE000iiissssdddd | RD = memh(RS+II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0x30001c00) { + // 00110IIIssssDDDDEE01110iiiiidddd | RD = memb(Rs+II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0x20001c00) { + // 00100IIIssssDDDDEE01110iiiiidddd | RD = memh(Rs+II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe00) == 0x3c001c00) { + // 0011110IIIIIDDDDEE01110iiiiidddd | RD = memw(r29+II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0x28001c00) { + // 00101IIIssssDDDDEE01110iiiiidddd | RD = memuh(Rs+II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x20000800) { + // 00100IIISSSSDDDDEE001iiissssdddd | RD = memh(RS+II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x28000800) { + // 00101IIISSSSDDDDEE001iiissssdddd | RD = memuh(RS+II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f40) { + // 0011111100000000EE01111101000000 | deallocframe ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "deallocframe ; dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f40) { + // 00110iiissssddddEE01111101000000 | Rd = memb(Rs+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f40) { + // 00111110iiiiidddEE01111101000000 | Rdd = memd(r29+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f40) { + // 00100iiissssddddEE01111101000000 | Rd = memh(Rs+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f40) { + // 0011110iiiiiddddEE01111101000000 | Rd = memw(r29+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f40) { + // 00101iiissssddddEE01111101000000 | Rd = memuh(Rs+Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f40) { + // 0011111101000000EE01111101000000 | dealloc_return ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "dealloc_return ; dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f45) { + // 0011111100000000EE01111101000101 | deallocframe ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (!P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f45) { + // 00110iiissssddddEE01111101000101 | Rd = memb(Rs+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f45) { + // 00111110iiiiidddEE01111101000101 | Rdd = memd(r29+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f45) { + // 00100iiissssddddEE01111101000101 | Rd = memh(Rs+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f45) { + // 0011110iiiiiddddEE01111101000101 | Rd = memw(r29+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f45) { + // 00101iiissssddddEE01111101000101 | Rd = memuh(Rs+Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f45) { + // 0011111101000000EE01111101000101 | dealloc_return ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (!P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451f45) { + // 0011111101000101EE01111101000101 | if (!p0) dealloc_return ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (!P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f45) { + // 0011111101000100EE01111101000101 | if (p0) dealloc_return ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (!P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f47) { + // 0011111100000000EE01111101000111 | deallocframe ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (!P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f47) { + // 00110iiissssddddEE01111101000111 | Rd = memb(Rs+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f47) { + // 00111110iiiiidddEE01111101000111 | Rdd = memd(r29+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f47) { + // 00100iiissssddddEE01111101000111 | Rd = memh(Rs+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f47) { + // 0011110iiiiiddddEE01111101000111 | Rd = memw(r29+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f47) { + // 00101iiissssddddEE01111101000111 | Rd = memuh(Rs+Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f47) { + // 0011111101000000EE01111101000111 | dealloc_return ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (!P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451f47) { + // 0011111101000101EE01111101000111 | if (!p0) dealloc_return ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (!P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f471f47) { + // 0011111101000111EE01111101000111 | if (!p0.new) dealloc_return:nt ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; if (!P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f47) { + // 0011111101000100EE01111101000111 | if (p0) dealloc_return ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (!P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461f47) { + // 0011111101000110EE01111101000111 | if (p0.new) dealloc_return:nt ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; if (!P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f44) { + // 0011111100000000EE01111101000100 | deallocframe ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f44) { + // 00110iiissssddddEE01111101000100 | Rd = memb(Rs+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f44) { + // 00111110iiiiidddEE01111101000100 | Rdd = memd(r29+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f44) { + // 00100iiissssddddEE01111101000100 | Rd = memh(Rs+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f44) { + // 0011110iiiiiddddEE01111101000100 | Rd = memw(r29+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f44) { + // 00101iiissssddddEE01111101000100 | Rd = memuh(Rs+Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f44) { + // 0011111101000000EE01111101000100 | dealloc_return ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f44) { + // 0011111101000100EE01111101000100 | if (p0) dealloc_return ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (P0) dealloc_return"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f001f46) { + // 0011111100000000EE01111101000110 | deallocframe ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "deallocframe ; if (P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x30001f46) { + // 00110iiissssddddEE01111101000110 | Rd = memb(Rs+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x3e001f46) { + // 00111110iiiiidddEE01111101000110 | Rdd = memd(r29+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x20001f46) { + // 00100iiissssddddEE01111101000110 | Rd = memh(Rs+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ffff) == 0x3c001f46) { + // 0011110iiiiiddddEE01111101000110 | Rd = memw(r29+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x28001f46) { + // 00101iiissssddddEE01111101000110 | Rd = memuh(Rs+Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f401f46) { + // 0011111101000000EE01111101000110 | dealloc_return ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "dealloc_return ; if (P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f451f46) { + // 0011111101000101EE01111101000110 | if (!p0) dealloc_return ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; if (P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f441f46) { + // 0011111101000100EE01111101000110 | if (p0) dealloc_return ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; if (P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffffff) == 0x3f461f46) { + // 0011111101000110EE01111101000110 | if (p0.new) dealloc_return:nt ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; if (P0.new) dealloc_return:nt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x3(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf800ff00) == 0x20003800) { + // 00100iiiiiiiXXXXEE111000ssssxxxx | RX = add(RXin,Ii) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].attr |= HEX_OP_REG_OUT; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x38003800) { + // 00111000SSSSXXXXEE111000ssssxxxx | RX = add(RXin,RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RX16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].attr |= HEX_OP_REG_OUT; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003800) { + // 001011iiiiiiddddEE111000ssssxxxx | Rd = add(r29,Ii) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003800) { + // 00110010SSSSddddEE111000ssssxxxx | Rd = and(RS,#1) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x33003800) { + // 00110011SSSSddddEE111000ssssxxxx | Rd = add(RS,n1) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[4].attr |= HEX_OP_REG_OUT; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003800) { + // 00110001SSSSddddEE111000ssssxxxx | Rd = add(RS,#1) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003800) { + // 001010iiiiiiddddEE111000ssssxxxx | Rd = Ii ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x35003800) { + // 00110101SSSSddddEE111000ssssxxxx | Rd = sxtb(RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x34003800) { + // 00110100SSSSddddEE111000ssssxxxx | Rd = sxth(RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003800) { + // 00110000SSSSddddEE111000ssssxxxx | Rd = RS ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x37003800) { + // 00110111SSSSddddEE111000ssssxxxx | Rd = and(RS,#255) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x36003800) { + // 00110110SSSSddddEE111000ssssxxxx | Rd = zxth(RS) ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003800) { + // 001010iiiiiiddddEE111000ssssxxxx | Rd = Ii ; Rx = add(Rxin,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ADDRX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rx16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rx16in + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(%sin,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fc00) == 0x20002c00) { + // 00100IIIIIIIxxxxEE1011iiiiiidddd | Rx = add(Rxin,II) ; Rd = add(r29,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDSP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = add(R29,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fc00) == 0x2c002c00) { + // 001011IIIIIIDDDDEE1011iiiiiidddd | RD = add(r29,II) ; Rd = add(r29,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDSP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = add(R29,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fc00) == 0x28002c00) { + // 001010IIIIIIDDDDEE1011iiiiiidddd | RD = II ; Rd = add(r29,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDSP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(R29,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fc00) == 0x28002c00) { + // 001010IIIIIIDDDDEE1011iiiiiidddd | RD = II ; Rd = add(r29,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ADDSP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(R29,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003200) { + // 00100iiiiiiixxxxEE110010ssssdddd | Rx = add(Rxin,Ii) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003200) { + // 001011iiiiiiDDDDEE110010ssssdddd | RD = add(r29,Ii) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003200) { + // 00110010SSSSDDDDEE110010ssssdddd | RD = and(RS,#1) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003200) { + // 00110001SSSSDDDDEE110010ssssdddd | RD = add(RS,#1) ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003200) { + // 001010iiiiiiDDDDEE110010ssssdddd | RD = Ii ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003200) { + // 00110000SSSSDDDDEE110010ssssdddd | RD = RS ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003200) { + // 001010iiiiiiDDDDEE110010ssssdddd | RD = Ii ; Rd = and(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_AND1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = and(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a70) { + // 00100iiiiiiixxxxEE1110100111dddd | Rx = add(Rxin,Ii) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a70) { + // 00111000ssssxxxxEE1110100111dddd | Rx = add(Rxin,Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a70) { + // 001011iiiiiiDDDDEE1110100111dddd | RD = add(r29,Ii) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a70) { + // 00110010ssssDDDDEE1110100111dddd | RD = and(Rs,#1) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a703a70) { + // 001110100111DDDDEE1110100111dddd | if (!p0) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a503a70) { + // 001110100101DDDDEE1110100111dddd | if (!p0.new) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a603a70) { + // 001110100110DDDDEE1110100111dddd | if (p0) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a70) { + // 001110100100DDDDEE1110100111dddd | if (p0.new) RD = #0 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a70) { + // 00111001ssss00iiEE1110100111dddd | p0 = cmp.eq(Rs,Ii) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a70) { + // 00110011ssssDDDDEE1110100111dddd | RD = add(Rs,n1) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a70) { + // 00110001ssssDDDDEE1110100111dddd | RD = add(Rs,#1) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a70) { + // 001010iiiiiiDDDDEE1110100111dddd | RD = Ii ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a70) { + // 001110100000DDDDEE1110100111dddd | RD = n1 ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a70) { + // 00110101ssssDDDDEE1110100111dddd | RD = sxtb(Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a70) { + // 00110100ssssDDDDEE1110100111dddd | RD = sxth(Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a70) { + // 00110000ssssDDDDEE1110100111dddd | RD = Rs ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = %s ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a70) { + // 00110111ssssDDDDEE1110100111dddd | RD = and(Rs,#255) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a70) { + // 00110110ssssDDDDEE1110100111dddd | RD = zxth(Rs) ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a70) { + // 001010iiiiiiDDDDEE1110100111dddd | RD = Ii ; if (!p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a50) { + // 00100iiiiiiixxxxEE1110100101dddd | Rx = add(Rxin,Ii) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a50) { + // 00111000ssssxxxxEE1110100101dddd | Rx = add(Rxin,Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a50) { + // 001011iiiiiiDDDDEE1110100101dddd | RD = add(r29,Ii) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a50) { + // 00110010ssssDDDDEE1110100101dddd | RD = and(Rs,#1) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a503a50) { + // 001110100101DDDDEE1110100101dddd | if (!p0.new) RD = #0 ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a50) { + // 001110100100DDDDEE1110100101dddd | if (p0.new) RD = #0 ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a50) { + // 00111001ssss00iiEE1110100101dddd | p0 = cmp.eq(Rs,Ii) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a50) { + // 00110011ssssDDDDEE1110100101dddd | RD = add(Rs,n1) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a50) { + // 00110001ssssDDDDEE1110100101dddd | RD = add(Rs,#1) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a50) { + // 001010iiiiiiDDDDEE1110100101dddd | RD = Ii ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a50) { + // 001110100000DDDDEE1110100101dddd | RD = n1 ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a50) { + // 00110101ssssDDDDEE1110100101dddd | RD = sxtb(Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a50) { + // 00110100ssssDDDDEE1110100101dddd | RD = sxth(Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a50) { + // 00110000ssssDDDDEE1110100101dddd | RD = Rs ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = %s ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a50) { + // 00110111ssssDDDDEE1110100101dddd | RD = and(Rs,#255) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a50) { + // 00110110ssssDDDDEE1110100101dddd | RD = zxth(Rs) ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a50) { + // 001010iiiiiiDDDDEE1110100101dddd | RD = Ii ; if (!p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a60) { + // 00100iiiiiiixxxxEE1110100110dddd | Rx = add(Rxin,Ii) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a60) { + // 00111000ssssxxxxEE1110100110dddd | Rx = add(Rxin,Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a60) { + // 001011iiiiiiDDDDEE1110100110dddd | RD = add(r29,Ii) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a60) { + // 00110010ssssDDDDEE1110100110dddd | RD = and(Rs,#1) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a503a60) { + // 001110100101DDDDEE1110100110dddd | if (!p0.new) RD = #0 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a603a60) { + // 001110100110DDDDEE1110100110dddd | if (p0) RD = #0 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a60) { + // 001110100100DDDDEE1110100110dddd | if (p0.new) RD = #0 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a60) { + // 00111001ssss00iiEE1110100110dddd | p0 = cmp.eq(Rs,Ii) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a60) { + // 00110011ssssDDDDEE1110100110dddd | RD = add(Rs,n1) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a60) { + // 00110001ssssDDDDEE1110100110dddd | RD = add(Rs,#1) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a60) { + // 001010iiiiiiDDDDEE1110100110dddd | RD = Ii ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a60) { + // 001110100000DDDDEE1110100110dddd | RD = n1 ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a60) { + // 00110101ssssDDDDEE1110100110dddd | RD = sxtb(Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a60) { + // 00110100ssssDDDDEE1110100110dddd | RD = sxth(Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a60) { + // 00110000ssssDDDDEE1110100110dddd | RD = Rs ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = %s ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a60) { + // 00110111ssssDDDDEE1110100110dddd | RD = and(Rs,#255) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a60) { + // 00110110ssssDDDDEE1110100110dddd | RD = zxth(Rs) ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a60) { + // 001010iiiiiiDDDDEE1110100110dddd | RD = Ii ; if (p0) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a40) { + // 00100iiiiiiixxxxEE1110100100dddd | Rx = add(Rxin,Ii) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a40) { + // 00111000ssssxxxxEE1110100100dddd | Rx = add(Rxin,Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a40) { + // 001011iiiiiiDDDDEE1110100100dddd | RD = add(r29,Ii) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a40) { + // 00110010ssssDDDDEE1110100100dddd | RD = and(Rs,#1) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a403a40) { + // 001110100100DDDDEE1110100100dddd | if (p0.new) RD = #0 ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a40) { + // 00111001ssss00iiEE1110100100dddd | p0 = cmp.eq(Rs,Ii) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a40) { + // 00110011ssssDDDDEE1110100100dddd | RD = add(Rs,n1) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a40) { + // 00110001ssssDDDDEE1110100100dddd | RD = add(Rs,#1) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a40) { + // 001010iiiiiiDDDDEE1110100100dddd | RD = Ii ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a40) { + // 001110100000DDDDEE1110100100dddd | RD = n1 ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a40) { + // 00110101ssssDDDDEE1110100100dddd | RD = sxtb(Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a40) { + // 00110100ssssDDDDEE1110100100dddd | RD = sxth(Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a40) { + // 00110000ssssDDDDEE1110100100dddd | RD = Rs ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = %s ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a40) { + // 00110111ssssDDDDEE1110100100dddd | RD = and(Rs,#255) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a40) { + // 00110110ssssDDDDEE1110100100dddd | RD = zxth(Rs) ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a40) { + // 001010iiiiiiDDDDEE1110100100dddd | RD = Ii ; if (p0.new) Rd = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0.new) %s = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff0c) == 0x20003900) { + // 00100IIIIIIIxxxxEE111001ssss00ii | Rx = add(Rxin,II) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x38003900) { + // 00111000SSSSxxxxEE111001ssss00ii | Rx = add(Rxin,RS) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff0c) == 0x2c003900) { + // 001011IIIIIIddddEE111001ssss00ii | Rd = add(r29,II) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x32003900) { + // 00110010SSSSddddEE111001ssss00ii | Rd = and(RS,#1) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff0c) == 0x39003900) { + // 00111001SSSS00IIEE111001ssss00ii | p0 = cmp.eq(RS,II) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x33003900) { + // 00110011SSSSddddEE111001ssss00ii | Rd = add(RS,n1) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x31003900) { + // 00110001SSSSddddEE111001ssss00ii | Rd = add(RS,#1) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff0c) == 0x28003900) { + // 001010IIIIIIddddEE111001ssss00ii | Rd = II ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x35003900) { + // 00110101SSSSddddEE111001ssss00ii | Rd = sxtb(RS) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x34003900) { + // 00110100SSSSddddEE111001ssss00ii | Rd = sxth(RS) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x30003900) { + // 00110000SSSSddddEE111001ssss00ii | Rd = RS ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x37003900) { + // 00110111SSSSddddEE111001ssss00ii | Rd = and(RS,#255) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff0c) == 0x36003900) { + // 00110110SSSSddddEE111001ssss00ii | Rd = zxth(RS) ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff0c) == 0x28003900) { + // 001010IIIIIIddddEE111001ssss00ii | Rd = II ; p0 = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; P0 = cmp.eq(%s,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c00) { + // 00100IIIIIIIxxxxEE1111000ii00ddd | Rx = add(Rxin,II) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c00) { + // 00111000ssssxxxxEE1111000ii00ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c00) { + // 001011IIIIIIDDDDEE1111000ii00ddd | RD = add(r29,II) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c00) { + // 00110010ssssDDDDEE1111000ii00ddd | RD = and(Rs,#1) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c00) { + // 001110100111DDDDEE1111000ii00ddd | if (!p0) RD = #0 ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c00) { + // 001110100101DDDDEE1111000ii00ddd | if (!p0.new) RD = #0 ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c00) { + // 001110100110DDDDEE1111000ii00ddd | if (p0) RD = #0 ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c00) { + // 001110100100DDDDEE1111000ii00ddd | if (p0.new) RD = #0 ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c00) { + // 00111001ssss00IIEE1111000ii00ddd | p0 = cmp.eq(Rs,II) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c00) { + // 001111000II00DDDEE1111000ii00ddd | RDD = combine(#0,II) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = combine(#0,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c00) { + // 00110011ssssDDDDEE1111000ii00ddd | RD = add(Rs,n1) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c00) { + // 00110001ssssDDDDEE1111000ii00ddd | RD = add(Rs,#1) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c00) { + // 001010IIIIIIDDDDEE1111000ii00ddd | RD = II ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c00) { + // 001110100000DDDDEE1111000ii00ddd | RD = n1 ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c00) { + // 00110101ssssDDDDEE1111000ii00ddd | RD = sxtb(Rs) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c00) { + // 00110100ssssDDDDEE1111000ii00ddd | RD = sxth(Rs) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c00) { + // 00110000ssssDDDDEE1111000ii00ddd | RD = Rs ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c00) { + // 00110111ssssDDDDEE1111000ii00ddd | RD = and(Rs,#255) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c00) { + // 00110110ssssDDDDEE1111000ii00ddd | RD = zxth(Rs) ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c00) { + // 001010IIIIIIDDDDEE1111000ii00ddd | RD = II ; Rdd = combine(#0,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#0,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c08) { + // 00100IIIIIIIxxxxEE1111000ii01ddd | Rx = add(Rxin,II) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c08) { + // 00111000ssssxxxxEE1111000ii01ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c08) { + // 001011IIIIIIDDDDEE1111000ii01ddd | RD = add(r29,II) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c08) { + // 00110010ssssDDDDEE1111000ii01ddd | RD = and(Rs,#1) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c08) { + // 001110100111DDDDEE1111000ii01ddd | if (!p0) RD = #0 ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c08) { + // 001110100101DDDDEE1111000ii01ddd | if (!p0.new) RD = #0 ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c08) { + // 001110100110DDDDEE1111000ii01ddd | if (p0) RD = #0 ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c08) { + // 001110100100DDDDEE1111000ii01ddd | if (p0.new) RD = #0 ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c08) { + // 00111001ssss00IIEE1111000ii01ddd | p0 = cmp.eq(Rs,II) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c08) { + // 001111000II00DDDEE1111000ii01ddd | RDD = combine(#0,II) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = combine(#1,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c083c08) { + // 001111000II01DDDEE1111000ii01ddd | RDD = combine(#1,II) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = combine(#1,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c08) { + // 00110011ssssDDDDEE1111000ii01ddd | RD = add(Rs,n1) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c08) { + // 00110001ssssDDDDEE1111000ii01ddd | RD = add(Rs,#1) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c08) { + // 001010IIIIIIDDDDEE1111000ii01ddd | RD = II ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c08) { + // 001110100000DDDDEE1111000ii01ddd | RD = n1 ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c08) { + // 00110101ssssDDDDEE1111000ii01ddd | RD = sxtb(Rs) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c08) { + // 00110100ssssDDDDEE1111000ii01ddd | RD = sxth(Rs) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c08) { + // 00110000ssssDDDDEE1111000ii01ddd | RD = Rs ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c08) { + // 00110111ssssDDDDEE1111000ii01ddd | RD = and(Rs,#255) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c08) { + // 00110110ssssDDDDEE1111000ii01ddd | RD = zxth(Rs) ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c08) { + // 001010IIIIIIDDDDEE1111000ii01ddd | RD = II ; Rdd = combine(#1,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#1,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c10) { + // 00100IIIIIIIxxxxEE1111000ii10ddd | Rx = add(Rxin,II) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c10) { + // 00111000ssssxxxxEE1111000ii10ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c10) { + // 001011IIIIIIDDDDEE1111000ii10ddd | RD = add(r29,II) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c10) { + // 00110010ssssDDDDEE1111000ii10ddd | RD = and(Rs,#1) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c10) { + // 001110100111DDDDEE1111000ii10ddd | if (!p0) RD = #0 ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c10) { + // 001110100101DDDDEE1111000ii10ddd | if (!p0.new) RD = #0 ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c10) { + // 001110100110DDDDEE1111000ii10ddd | if (p0) RD = #0 ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c10) { + // 001110100100DDDDEE1111000ii10ddd | if (p0.new) RD = #0 ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c10) { + // 00111001ssss00IIEE1111000ii10ddd | p0 = cmp.eq(Rs,II) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c10) { + // 001111000II00DDDEE1111000ii10ddd | RDD = combine(#0,II) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = combine(#2,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c083c10) { + // 001111000II01DDDEE1111000ii10ddd | RDD = combine(#1,II) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = combine(#2,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c103c10) { + // 001111000II10DDDEE1111000ii10ddd | RDD = combine(#2,II) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = combine(#2,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c10) { + // 00110011ssssDDDDEE1111000ii10ddd | RD = add(Rs,n1) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c10) { + // 00110001ssssDDDDEE1111000ii10ddd | RD = add(Rs,#1) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c10) { + // 001010IIIIIIDDDDEE1111000ii10ddd | RD = II ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c10) { + // 001110100000DDDDEE1111000ii10ddd | RD = n1 ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c10) { + // 00110101ssssDDDDEE1111000ii10ddd | RD = sxtb(Rs) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c10) { + // 00110100ssssDDDDEE1111000ii10ddd | RD = sxth(Rs) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c10) { + // 00110000ssssDDDDEE1111000ii10ddd | RD = Rs ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c10) { + // 00110111ssssDDDDEE1111000ii10ddd | RD = and(Rs,#255) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c10) { + // 00110110ssssDDDDEE1111000ii10ddd | RD = zxth(Rs) ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c10) { + // 001010IIIIIIDDDDEE1111000ii10ddd | RD = II ; Rdd = combine(#2,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE2I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#2,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff98) == 0x20003c18) { + // 00100IIIIIIIxxxxEE1111000ii11ddd | Rx = add(Rxin,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x38003c18) { + // 00111000ssssxxxxEE1111000ii11ddd | Rx = add(Rxin,Rs) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x2c003c18) { + // 001011IIIIIIDDDDEE1111000ii11ddd | RD = add(r29,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x32003c18) { + // 00110010ssssDDDDEE1111000ii11ddd | RD = and(Rs,#1) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a703c18) { + // 001110100111DDDDEE1111000ii11ddd | if (!p0) RD = #0 ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a503c18) { + // 001110100101DDDDEE1111000ii11ddd | if (!p0.new) RD = #0 ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a603c18) { + // 001110100110DDDDEE1111000ii11ddd | if (p0) RD = #0 ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a403c18) { + // 001110100100DDDDEE1111000ii11ddd | if (p0.new) RD = #0 ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff98) == 0x39003c18) { + // 00111001ssss00IIEE1111000ii11ddd | p0 = cmp.eq(Rs,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c003c18) { + // 001111000II00DDDEE1111000ii11ddd | RDD = combine(#0,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = combine(#3,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c083c18) { + // 001111000II01DDDEE1111000ii11ddd | RDD = combine(#1,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = combine(#3,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c103c18) { + // 001111000II10DDDEE1111000ii11ddd | RDD = combine(#2,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = combine(#3,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff98) == 0x3c183c18) { + // 001111000II11DDDEE1111000ii11ddd | RDD = combine(#3,II) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = combine(#3,%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x33003c18) { + // 00110011ssssDDDDEE1111000ii11ddd | RD = add(Rs,n1) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x31003c18) { + // 00110001ssssDDDDEE1111000ii11ddd | RD = add(Rs,#1) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c18) { + // 001010IIIIIIDDDDEE1111000ii11ddd | RD = II ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff98) == 0x3a003c18) { + // 001110100000DDDDEE1111000ii11ddd | RD = n1 ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x35003c18) { + // 00110101ssssDDDDEE1111000ii11ddd | RD = sxtb(Rs) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x34003c18) { + // 00110100ssssDDDDEE1111000ii11ddd | RD = sxth(Rs) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x30003c18) { + // 00110000ssssDDDDEE1111000ii11ddd | RD = Rs ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x37003c18) { + // 00110111ssssDDDDEE1111000ii11ddd | RD = and(Rs,#255) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff98) == 0x36003c18) { + // 00110110ssssDDDDEE1111000ii11ddd | RD = zxth(Rs) ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff98) == 0x28003c18) { + // 001010IIIIIIDDDDEE1111000ii11ddd | RD = II ; Rdd = combine(#3,Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE3I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#3,%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff08) == 0x20003d08) { + // 00100iiiiiiixxxxEE111101ssss1ddd | Rx = add(Rxin,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x38003d08) { + // 00111000SSSSxxxxEE111101ssss1ddd | Rx = add(Rxin,RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff08) == 0x2c003d08) { + // 001011iiiiiiDDDDEE111101ssss1ddd | RD = add(r29,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x32003d08) { + // 00110010SSSSDDDDEE111101ssss1ddd | RD = and(RS,#1) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a703d08) { + // 001110100111DDDDEE111101ssss1ddd | if (!p0) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a503d08) { + // 001110100101DDDDEE111101ssss1ddd | if (!p0.new) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a603d08) { + // 001110100110DDDDEE111101ssss1ddd | if (p0) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a403d08) { + // 001110100100DDDDEE111101ssss1ddd | if (p0.new) RD = #0 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff08) == 0x39003d08) { + // 00111001SSSS00iiEE111101ssss1ddd | p0 = cmp.eq(RS,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c003d08) { + // 001111000ii00DDDEE111101ssss1ddd | RDD = combine(#0,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = combine(%s,#0)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c083d08) { + // 001111000ii01DDDEE111101ssss1ddd | RDD = combine(#1,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = combine(%s,#0)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c103d08) { + // 001111000ii10DDDEE111101ssss1ddd | RDD = combine(#2,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = combine(%s,#0)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c183d08) { + // 001111000ii11DDDEE111101ssss1ddd | RDD = combine(#3,Ii) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = combine(%s,#0)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff08) == 0x3d083d08) { + // 00111101SSSS1DDDEE111101ssss1ddd | RDD = combine(RS,#0) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = combine(%s,#0)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff08) == 0x3d003d08) { + // 00111101SSSS0DDDEE111101ssss1ddd | RDD = combine(#0,RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = combine(%s,#0)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x33003d08) { + // 00110011SSSSDDDDEE111101ssss1ddd | RD = add(RS,n1) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x31003d08) { + // 00110001SSSSDDDDEE111101ssss1ddd | RD = add(RS,#1) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff08) == 0x28003d08) { + // 001010iiiiiiDDDDEE111101ssss1ddd | RD = Ii ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a003d08) { + // 001110100000DDDDEE111101ssss1ddd | RD = n1 ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x35003d08) { + // 00110101SSSSDDDDEE111101ssss1ddd | RD = sxtb(RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x34003d08) { + // 00110100SSSSDDDDEE111101ssss1ddd | RD = sxth(RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x30003d08) { + // 00110000SSSSDDDDEE111101ssss1ddd | RD = RS ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x37003d08) { + // 00110111SSSSDDDDEE111101ssss1ddd | RD = and(RS,#255) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x36003d08) { + // 00110110SSSSDDDDEE111101ssss1ddd | RD = zxth(RS) ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff08) == 0x28003d08) { + // 001010iiiiiiDDDDEE111101ssss1ddd | RD = Ii ; Rdd = combine(Rs,#0) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINERZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(%s,#0)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff08) == 0x20003d00) { + // 00100iiiiiiixxxxEE111101ssss0ddd | Rx = add(Rxin,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x38003d00) { + // 00111000SSSSxxxxEE111101ssss0ddd | Rx = add(Rxin,RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff08) == 0x2c003d00) { + // 001011iiiiiiDDDDEE111101ssss0ddd | RD = add(r29,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x32003d00) { + // 00110010SSSSDDDDEE111101ssss0ddd | RD = and(RS,#1) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a703d00) { + // 001110100111DDDDEE111101ssss0ddd | if (!p0) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a503d00) { + // 001110100101DDDDEE111101ssss0ddd | if (!p0.new) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a603d00) { + // 001110100110DDDDEE111101ssss0ddd | if (p0) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a403d00) { + // 001110100100DDDDEE111101ssss0ddd | if (p0.new) RD = #0 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff08) == 0x39003d00) { + // 00111001SSSS00iiEE111101ssss0ddd | p0 = cmp.eq(RS,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c003d00) { + // 001111000ii00DDDEE111101ssss0ddd | RDD = combine(#0,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = combine(#0,%s)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c083d00) { + // 001111000ii01DDDEE111101ssss0ddd | RDD = combine(#1,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = combine(#0,%s)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c103d00) { + // 001111000ii10DDDEE111101ssss0ddd | RDD = combine(#2,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = combine(#0,%s)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff08) == 0x3c183d00) { + // 001111000ii11DDDEE111101ssss0ddd | RDD = combine(#3,Ii) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = combine(#0,%s)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff08) == 0x3d003d00) { + // 00111101SSSS0DDDEE111101ssss0ddd | RDD = combine(#0,RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = combine(#0,%s)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x33003d00) { + // 00110011SSSSDDDDEE111101ssss0ddd | RD = add(RS,n1) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x31003d00) { + // 00110001SSSSDDDDEE111101ssss0ddd | RD = add(RS,#1) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff08) == 0x28003d00) { + // 001010iiiiiiDDDDEE111101ssss0ddd | RD = Ii ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff08) == 0x3a003d00) { + // 001110100000DDDDEE111101ssss0ddd | RD = n1 ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x35003d00) { + // 00110101SSSSDDDDEE111101ssss0ddd | RD = sxtb(RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x34003d00) { + // 00110100SSSSDDDDEE111101ssss0ddd | RD = sxth(RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x30003d00) { + // 00110000SSSSDDDDEE111101ssss0ddd | RD = RS ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x37003d00) { + // 00110111SSSSDDDDEE111101ssss0ddd | RD = and(RS,#255) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff08) == 0x36003d00) { + // 00110110SSSSDDDDEE111101ssss0ddd | RD = zxth(RS) ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff08) == 0x28003d00) { + // 001010iiiiiiDDDDEE111101ssss0ddd | RD = Ii ; Rdd = combine(#0,Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINEZR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = combine(#0,%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003300) { + // 00100iiiiiiixxxxEE110011ssssdddd | Rx = add(Rxin,Ii) ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003300) { + // 001011iiiiiiDDDDEE110011ssssdddd | RD = add(r29,Ii) ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003300) { + // 00110010SSSSDDDDEE110011ssssdddd | RD = and(RS,#1) ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x33003300) { + // 00110011SSSSDDDDEE110011ssssdddd | RD = add(RS,N1) ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003300) { + // 00110001SSSSDDDDEE110011ssssdddd | RD = add(RS,#1) ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003300) { + // 001010iiiiiiDDDDEE110011ssssdddd | RD = Ii ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003300) { + // 00110000SSSSDDDDEE110011ssssdddd | RD = RS ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003300) { + // 001010iiiiiiDDDDEE110011ssssdddd | RD = Ii ; Rd = add(Rs,n1) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_DEC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(%s,-1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003100) { + // 00100iiiiiiixxxxEE110001ssssdddd | Rx = add(Rxin,Ii) ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_INC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = add(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003100) { + // 001011iiiiiiDDDDEE110001ssssdddd | RD = add(r29,Ii) ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_INC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = add(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003100) { + // 00110001SSSSDDDDEE110001ssssdddd | RD = add(RS,#1) ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_INC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = add(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003100) { + // 001010iiiiiiDDDDEE110001ssssdddd | RD = Ii ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_INC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003100) { + // 00110000SSSSDDDDEE110001ssssdddd | RD = RS ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_INC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = add(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003100) { + // 001010iiiiiiDDDDEE110001ssssdddd | RD = Ii ; Rd = add(Rs,#1) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_INC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = add(%s,#1)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fff0) == 0x20003a00) { + // 00100iiiiiiixxxxEE1110100000dddd | Rx = add(Rxin,Ii) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x38003a00) { + // 00111000ssssxxxxEE1110100000dddd | Rx = add(Rxin,Rs) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x2c003a00) { + // 001011iiiiiiDDDDEE1110100000dddd | RD = add(r29,Ii) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x32003a00) { + // 00110010ssssDDDDEE1110100000dddd | RD = and(Rs,#1) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfff0) == 0x39003a00) { + // 00111001ssss00iiEE1110100000dddd | p0 = cmp.eq(Rs,Ii) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x33003a00) { + // 00110011ssssDDDDEE1110100000dddd | RD = add(Rs,N1) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x31003a00) { + // 00110001ssssDDDDEE1110100000dddd | RD = add(Rs,#1) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a00) { + // 001010iiiiiiDDDDEE1110100000dddd | RD = Ii ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fff0) == 0x3a003a00) { + // 001110100000DDDDEE1110100000dddd | RD = N1 ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x35003a00) { + // 00110101ssssDDDDEE1110100000dddd | RD = sxtb(Rs) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x34003a00) { + // 00110100ssssDDDDEE1110100000dddd | RD = sxth(Rs) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x30003a00) { + // 00110000ssssDDDDEE1110100000dddd | RD = Rs ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x37003a00) { + // 00110111ssssDDDDEE1110100000dddd | RD = and(Rs,#255) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fff0) == 0x36003a00) { + // 00110110ssssDDDDEE1110100000dddd | RD = zxth(Rs) ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fff0) == 0x28003a00) { + // 001010iiiiiiDDDDEE1110100000dddd | RD = Ii ; Rd = n1 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_SETIN1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = -1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003500) { + // 00100iiiiiiixxxxEE110101ssssdddd | Rx = add(Rxin,Ii) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003500) { + // 001011iiiiiiDDDDEE110101ssssdddd | RD = add(r29,Ii) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003500) { + // 00110010SSSSDDDDEE110101ssssdddd | RD = and(RS,#1) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x33003500) { + // 00110011SSSSDDDDEE110101ssssdddd | RD = add(RS,n1) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003500) { + // 00110001SSSSDDDDEE110101ssssdddd | RD = add(RS,#1) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003500) { + // 001010iiiiiiDDDDEE110101ssssdddd | RD = Ii ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x35003500) { + // 00110101SSSSDDDDEE110101ssssdddd | RD = sxtb(RS) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x34003500) { + // 00110100SSSSDDDDEE110101ssssdddd | RD = sxth(RS) ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003500) { + // 00110000SSSSDDDDEE110101ssssdddd | RD = RS ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003500) { + // 001010iiiiiiDDDDEE110101ssssdddd | RD = Ii ; Rd = sxtb(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = sxtb(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003400) { + // 00100iiiiiiixxxxEE110100ssssdddd | Rx = add(Rxin,Ii) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003400) { + // 001011iiiiiiDDDDEE110100ssssdddd | RD = add(r29,Ii) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003400) { + // 00110010SSSSDDDDEE110100ssssdddd | RD = and(RS,#1) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x33003400) { + // 00110011SSSSDDDDEE110100ssssdddd | RD = add(RS,n1) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003400) { + // 00110001SSSSDDDDEE110100ssssdddd | RD = add(RS,#1) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003400) { + // 001010iiiiiiDDDDEE110100ssssdddd | RD = Ii ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x34003400) { + // 00110100SSSSDDDDEE110100ssssdddd | RD = sxth(RS) ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003400) { + // 00110000SSSSDDDDEE110100ssssdddd | RD = RS ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003400) { + // 001010iiiiiiDDDDEE110100ssssdddd | RD = Ii ; Rd = sxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = sxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003000) { + // 00100iiiiiiixxxxEE110000ssssdddd | Rx = add(Rxin,Ii) ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_TFR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003000) { + // 001011iiiiiiDDDDEE110000ssssdddd | RD = add(r29,Ii) ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_TFR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003000) { + // 001010iiiiiiDDDDEE110000ssssdddd | RD = Ii ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_TFR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003000) { + // 00110000SSSSDDDDEE110000ssssdddd | RD = RS ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_TFR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003000) { + // 001010iiiiiiDDDDEE110000ssssdddd | RD = Ii ; Rd = Rs + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_TFR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003700) { + // 00100iiiiiiixxxxEE110111ssssdddd | Rx = add(Rxin,Ii) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003700) { + // 001011iiiiiiDDDDEE110111ssssdddd | RD = add(r29,Ii) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003700) { + // 00110010SSSSDDDDEE110111ssssdddd | RD = and(RS,#1) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x33003700) { + // 00110011SSSSDDDDEE110111ssssdddd | RD = add(RS,n1) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003700) { + // 00110001SSSSDDDDEE110111ssssdddd | RD = add(RS,#1) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003700) { + // 001010iiiiiiDDDDEE110111ssssdddd | RD = Ii ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x35003700) { + // 00110101SSSSDDDDEE110111ssssdddd | RD = sxtb(RS) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x34003700) { + // 00110100SSSSDDDDEE110111ssssdddd | RD = sxth(RS) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003700) { + // 00110000SSSSDDDDEE110111ssssdddd | RD = RS ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x37003700) { + // 00110111SSSSDDDDEE110111ssssdddd | RD = and(RS,#255) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x36003700) { + // 00110110SSSSDDDDEE110111ssssdddd | RD = zxth(RS) ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003700) { + // 001010iiiiiiDDDDEE110111ssssdddd | RD = Ii ; Rd = and(Rs,#255) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ZXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = and(%s,#255)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x20003600) { + // 00100iiiiiiixxxxEE110110ssssdddd | Rx = add(Rxin,Ii) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x2c003600) { + // 001011iiiiiiDDDDEE110110ssssdddd | RD = add(r29,Ii) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x32003600) { + // 00110010SSSSDDDDEE110110ssssdddd | RD = and(RS,#1) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x33003600) { + // 00110011SSSSDDDDEE110110ssssdddd | RD = add(RS,n1) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x31003600) { + // 00110001SSSSDDDDEE110110ssssdddd | RD = add(RS,#1) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003600) { + // 001010iiiiiiDDDDEE110110ssssdddd | RD = Ii ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x35003600) { + // 00110101SSSSDDDDEE110110ssssdddd | RD = sxtb(RS) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x34003600) { + // 00110100SSSSDDDDEE110110ssssdddd | RD = sxth(RS) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x30003600) { + // 00110000SSSSDDDDEE110110ssssdddd | RD = RS ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x36003600) { + // 00110110SSSSDDDDEE110110ssssdddd | RD = zxth(RS) ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x28003600) { + // 001010iiiiiiDDDDEE110110ssssdddd | RD = Ii ; Rd = zxth(Rs) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = zxth(%s)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fc00) == 0x20002800) { + // 00100IIIIIIIxxxxEE1010iiiiiidddd | Rx = add(Rxin,II) ; Rd = Ii + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_UNDOCUMENTED_SA2_TFRSI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd32 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x3f0) >> 4); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = %s0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fc00) == 0x28002800) { + // 001010IIIIIIDDDDEE1010iiiiiidddd | RD = II ; Rd = Ii + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_UNDOCUMENTED_SA2_TFRSI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = %s0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fc00) == 0x28002800) { + // 001010IIIIIIDDDDEE1010iiiiiidddd | RD = II ; Rd = Ii + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_UNDOCUMENTED_SA2_TFRSI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f0) >> 4); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = %s0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x4(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf800f000) == 0x40000000) { + // 01000IIIIIIIxxxxEE00iiiissssdddd | Rx = add(Rxin,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x58000000) { + // 01011000SSSSxxxxEE00iiiissssdddd | Rx = add(Rxin,RS) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + hex_extend_op(state, &(hi->ops[5]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x4c000000) { + // 010011IIIIIIDDDDEE00iiiissssdddd | RD = add(r29,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x52000000) { + // 01010010SSSSDDDDEE00iiiissssdddd | RD = and(RS,#1) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a700000) { + // 010110100111DDDDEE00iiiissssdddd | if (!p0) RD = #0 ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a500000) { + // 010110100101DDDDEE00iiiissssdddd | if (!p0.new) RD = #0 ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a600000) { + // 010110100110DDDDEE00iiiissssdddd | if (p0) RD = #0 ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a400000) { + // 010110100100DDDDEE00iiiissssdddd | if (p0.new) RD = #0 ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf000) == 0x59000000) { + // 01011001SSSS00IIEE00iiiissssdddd | p0 = cmp.eq(RS,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c000000) { + // 010111000II00DDDEE00iiiissssdddd | RDD = combine(#0,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c080000) { + // 010111000II01DDDEE00iiiissssdddd | RDD = combine(#1,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c100000) { + // 010111000II10DDDEE00iiiissssdddd | RDD = combine(#2,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c180000) { + // 010111000II11DDDEE00iiiissssdddd | RDD = combine(#3,II) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memw(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x5d080000) { + // 01011101SSSS1DDDEE00iiiissssdddd | RDD = combine(RS,#0) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memw(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x5d000000) { + // 01011101SSSS0DDDEE00iiiissssdddd | RDD = combine(#0,RS) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memw(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x53000000) { + // 01010011SSSSDDDDEE00iiiissssdddd | RD = add(RS,n1) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x51000000) { + // 01010001SSSSDDDDEE00iiiissssdddd | RD = add(RS,#1) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x48000000) { + // 010010IIIIIIDDDDEE00iiiissssdddd | RD = II ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a000000) { + // 010110100000DDDDEE00iiiissssdddd | RD = n1 ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x55000000) { + // 01010101SSSSDDDDEE00iiiissssdddd | RD = sxtb(RS) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x54000000) { + // 01010100SSSSDDDDEE00iiiissssdddd | RD = sxth(RS) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x50000000) { + // 01010000SSSSDDDDEE00iiiissssdddd | RD = RS ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x57000000) { + // 01010111SSSSDDDDEE00iiiissssdddd | RD = and(RS,#255) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x56000000) { + // 01010110SSSSDDDDEE00iiiissssdddd | RD = zxth(RS) ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x48000000) { + // 010010IIIIIIDDDDEE00iiiissssdddd | RD = II ; Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL1_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memw(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x40001000) { + // 01000IIIIIIIxxxxEE01iiiissssdddd | Rx = add(Rxin,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x58001000) { + // 01011000SSSSxxxxEE01iiiissssdddd | Rx = add(Rxin,RS) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[5]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x4c001000) { + // 010011IIIIIIDDDDEE01iiiissssdddd | RD = add(r29,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x52001000) { + // 01010010SSSSDDDDEE01iiiissssdddd | RD = and(RS,#1) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a701000) { + // 010110100111DDDDEE01iiiissssdddd | if (!p0) RD = #0 ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a501000) { + // 010110100101DDDDEE01iiiissssdddd | if (!p0.new) RD = #0 ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a601000) { + // 010110100110DDDDEE01iiiissssdddd | if (p0) RD = #0 ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a401000) { + // 010110100100DDDDEE01iiiissssdddd | if (p0.new) RD = #0 ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf000) == 0x59001000) { + // 01011001SSSS00IIEE01iiiissssdddd | p0 = cmp.eq(RS,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c001000) { + // 010111000II00DDDEE01iiiissssdddd | RDD = combine(#0,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c081000) { + // 010111000II01DDDEE01iiiissssdddd | RDD = combine(#1,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c101000) { + // 010111000II10DDDEE01iiiissssdddd | RDD = combine(#2,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x5c181000) { + // 010111000II11DDDEE01iiiissssdddd | RDD = combine(#3,II) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memub(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x5d081000) { + // 01011101SSSS1DDDEE01iiiissssdddd | RDD = combine(RS,#0) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memub(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x5d001000) { + // 01011101SSSS0DDDEE01iiiissssdddd | RDD = combine(#0,RS) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memub(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x53001000) { + // 01010011SSSSDDDDEE01iiiissssdddd | RD = add(RS,n1) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x51001000) { + // 01010001SSSSDDDDEE01iiiissssdddd | RD = add(RS,#1) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x48001000) { + // 010010IIIIIIDDDDEE01iiiissssdddd | RD = II ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x5a001000) { + // 010110100000DDDDEE01iiiissssdddd | RD = n1 ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x55001000) { + // 01010101SSSSDDDDEE01iiiissssdddd | RD = sxtb(RS) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x54001000) { + // 01010100SSSSDDDDEE01iiiissssdddd | RD = sxth(RS) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x50001000) { + // 01010000SSSSDDDDEE01iiiissssdddd | RD = RS ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x57001000) { + // 01010111SSSSDDDDEE01iiiissssdddd | RD = and(RS,#255) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x56001000) { + // 01010110SSSSDDDDEE01iiiissssdddd | RD = zxth(RS) ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x48001000) { + // 010010IIIIIIDDDDEE01iiiissssdddd | RD = II ; Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL1_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memub(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x5(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf800ffff) == 0x40003f00) { + // 01000iiiiiiixxxxEE11111100000000 | Rx = add(Rxin,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f00) { + // 01011000ssssxxxxEE11111100000000 | Rx = add(Rxin,Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f00) { + // 010011iiiiiiddddEE11111100000000 | Rd = add(r29,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f00) { + // 01010010ssssddddEE11111100000000 | Rd = and(Rs,#1) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f00) { + // 010110100111ddddEE11111100000000 | if (!p0) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f00) { + // 010110100101ddddEE11111100000000 | if (!p0.new) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f00) { + // 010110100110ddddEE11111100000000 | if (p0) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f00) { + // 010110100100ddddEE11111100000000 | if (p0.new) Rd = #0 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f00) { + // 01011001ssss00iiEE11111100000000 | p0 = cmp.eq(Rs,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f00) { + // 010111000ii00dddEE11111100000000 | Rdd = combine(#0,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f00) { + // 010111000ii01dddEE11111100000000 | Rdd = combine(#1,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f00) { + // 010111000ii10dddEE11111100000000 | Rdd = combine(#2,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f00) { + // 010111000ii11dddEE11111100000000 | Rdd = combine(#3,Ii) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f00) { + // 01011101ssss1dddEE11111100000000 | Rdd = combine(Rs,#0) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f00) { + // 01011101ssss0dddEE11111100000000 | Rdd = combine(#0,Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; deallocframe", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f00) { + // 01010011ssssddddEE11111100000000 | Rd = add(Rs,n1) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f00) { + // 01010001ssssddddEE11111100000000 | Rd = add(Rs,#1) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f00) { + // 010010iiiiiiddddEE11111100000000 | Rd = Ii ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f00) { + // 010110100000ddddEE11111100000000 | Rd = n1 ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f00) { + // 01010101ssssddddEE11111100000000 | Rd = sxtb(Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f00) { + // 01010100ssssddddEE11111100000000 | Rd = sxth(Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f00) { + // 01010000ssssddddEE11111100000000 | Rd = Rs ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f00) { + // 01010111ssssddddEE11111100000000 | Rd = and(Rs,#255) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f00) { + // 01010110ssssddddEE11111100000000 | Rd = zxth(Rs) ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f00) { + // 010010iiiiiiddddEE11111100000000 | Rd = Ii ; deallocframe + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; deallocframe", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc0) { + // 01000iiiiiiixxxxEE11111111000000 | Rx = add(Rxin,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc0) { + // 01011000ssssxxxxEE11111111000000 | Rx = add(Rxin,Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc0) { + // 010011iiiiiiddddEE11111111000000 | Rd = add(r29,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc0) { + // 01010010ssssddddEE11111111000000 | Rd = and(Rs,#1) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc0) { + // 010110100111ddddEE11111111000000 | if (!p0) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc0) { + // 010110100101ddddEE11111111000000 | if (!p0.new) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc0) { + // 010110100110ddddEE11111111000000 | if (p0) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc0) { + // 010110100100ddddEE11111111000000 | if (p0.new) Rd = #0 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc0) { + // 01011001ssss00iiEE11111111000000 | p0 = cmp.eq(Rs,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc0) { + // 010111000ii00dddEE11111111000000 | Rdd = combine(#0,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc0) { + // 010111000ii01dddEE11111111000000 | Rdd = combine(#1,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc0) { + // 010111000ii10dddEE11111111000000 | Rdd = combine(#2,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc0) { + // 010111000ii11dddEE11111111000000 | Rdd = combine(#3,Ii) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc0) { + // 01011101ssss1dddEE11111111000000 | Rdd = combine(Rs,#0) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc0) { + // 01011101ssss0dddEE11111111000000 | Rdd = combine(#0,Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc0) { + // 01010011ssssddddEE11111111000000 | Rd = add(Rs,n1) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc0) { + // 01010001ssssddddEE11111111000000 | Rd = add(Rs,#1) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc0) { + // 010010iiiiiiddddEE11111111000000 | Rd = Ii ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc0) { + // 010110100000ddddEE11111111000000 | Rd = n1 ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc0) { + // 01010101ssssddddEE11111111000000 | Rd = sxtb(Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc0) { + // 01010100ssssddddEE11111111000000 | Rd = sxth(Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc0) { + // 01010000ssssddddEE11111111000000 | Rd = Rs ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = %s ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc0) { + // 01010111ssssddddEE11111111000000 | Rd = and(Rs,#255) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc0) { + // 01010110ssssddddEE11111111000000 | Rd = zxth(Rs) ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc0) { + // 010010iiiiiiddddEE11111111000000 | Rd = Ii ; jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc5) { + // 01000iiiiiiixxxxEE11111111000101 | Rx = add(Rxin,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc5) { + // 01011000ssssxxxxEE11111111000101 | Rx = add(Rxin,Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc5) { + // 010011iiiiiiddddEE11111111000101 | Rd = add(r29,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc5) { + // 01010010ssssddddEE11111111000101 | Rd = and(Rs,#1) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc5) { + // 010110100111ddddEE11111111000101 | if (!p0) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc5) { + // 010110100101ddddEE11111111000101 | if (!p0.new) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc5) { + // 010110100110ddddEE11111111000101 | if (p0) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc5) { + // 010110100100ddddEE11111111000101 | if (p0.new) Rd = #0 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc5) { + // 01011001ssss00iiEE11111111000101 | p0 = cmp.eq(Rs,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc5) { + // 010111000ii00dddEE11111111000101 | Rdd = combine(#0,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc5) { + // 010111000ii01dddEE11111111000101 | Rdd = combine(#1,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc5) { + // 010111000ii10dddEE11111111000101 | Rdd = combine(#2,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc5) { + // 010111000ii11dddEE11111111000101 | Rdd = combine(#3,Ii) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc5) { + // 01011101ssss1dddEE11111111000101 | Rdd = combine(Rs,#0) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc5) { + // 01011101ssss0dddEE11111111000101 | Rdd = combine(#0,Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (!P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc5) { + // 01010011ssssddddEE11111111000101 | Rd = add(Rs,n1) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc5) { + // 01010001ssssddddEE11111111000101 | Rd = add(Rs,#1) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc5) { + // 010010iiiiiiddddEE11111111000101 | Rd = Ii ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc5) { + // 010110100000ddddEE11111111000101 | Rd = n1 ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc5) { + // 01010101ssssddddEE11111111000101 | Rd = sxtb(Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc5) { + // 01010100ssssddddEE11111111000101 | Rd = sxth(Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc5) { + // 01010000ssssddddEE11111111000101 | Rd = Rs ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc5) { + // 01010111ssssddddEE11111111000101 | Rd = and(Rs,#255) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc5) { + // 01010110ssssddddEE11111111000101 | Rd = zxth(Rs) ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc5) { + // 010010iiiiiiddddEE11111111000101 | Rd = Ii ; if (!p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc7) { + // 01000iiiiiiixxxxEE11111111000111 | Rx = add(Rxin,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc7) { + // 01011000ssssxxxxEE11111111000111 | Rx = add(Rxin,Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc7) { + // 010011iiiiiiddddEE11111111000111 | Rd = add(r29,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc7) { + // 01010010ssssddddEE11111111000111 | Rd = and(Rs,#1) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc7) { + // 010110100111ddddEE11111111000111 | if (!p0) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc7) { + // 010110100101ddddEE11111111000111 | if (!p0.new) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc7) { + // 010110100110ddddEE11111111000111 | if (p0) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc7) { + // 010110100100ddddEE11111111000111 | if (p0.new) Rd = #0 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc7) { + // 01011001ssss00iiEE11111111000111 | p0 = cmp.eq(Rs,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc7) { + // 010111000ii00dddEE11111111000111 | Rdd = combine(#0,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc7) { + // 010111000ii01dddEE11111111000111 | Rdd = combine(#1,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc7) { + // 010111000ii10dddEE11111111000111 | Rdd = combine(#2,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc7) { + // 010111000ii11dddEE11111111000111 | Rdd = combine(#3,Ii) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc7) { + // 01011101ssss1dddEE11111111000111 | Rdd = combine(Rs,#0) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc7) { + // 01011101ssss0dddEE11111111000111 | Rdd = combine(#0,Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (!P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc7) { + // 01010011ssssddddEE11111111000111 | Rd = add(Rs,n1) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc7) { + // 01010001ssssddddEE11111111000111 | Rd = add(Rs,#1) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc7) { + // 010010iiiiiiddddEE11111111000111 | Rd = Ii ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc7) { + // 010110100000ddddEE11111111000111 | Rd = n1 ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc7) { + // 01010101ssssddddEE11111111000111 | Rd = sxtb(Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc7) { + // 01010100ssssddddEE11111111000111 | Rd = sxth(Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc7) { + // 01010000ssssddddEE11111111000111 | Rd = Rs ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc7) { + // 01010111ssssddddEE11111111000111 | Rd = and(Rs,#255) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc7) { + // 01010110ssssddddEE11111111000111 | Rd = zxth(Rs) ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc7) { + // 010010iiiiiiddddEE11111111000111 | Rd = Ii ; if (!p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc4) { + // 01000iiiiiiixxxxEE11111111000100 | Rx = add(Rxin,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc4) { + // 01011000ssssxxxxEE11111111000100 | Rx = add(Rxin,Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc4) { + // 010011iiiiiiddddEE11111111000100 | Rd = add(r29,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc4) { + // 01010010ssssddddEE11111111000100 | Rd = and(Rs,#1) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc4) { + // 010110100111ddddEE11111111000100 | if (!p0) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc4) { + // 010110100101ddddEE11111111000100 | if (!p0.new) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc4) { + // 010110100110ddddEE11111111000100 | if (p0) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc4) { + // 010110100100ddddEE11111111000100 | if (p0.new) Rd = #0 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc4) { + // 01011001ssss00iiEE11111111000100 | p0 = cmp.eq(Rs,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc4) { + // 010111000ii00dddEE11111111000100 | Rdd = combine(#0,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc4) { + // 010111000ii01dddEE11111111000100 | Rdd = combine(#1,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc4) { + // 010111000ii10dddEE11111111000100 | Rdd = combine(#2,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc4) { + // 010111000ii11dddEE11111111000100 | Rdd = combine(#3,Ii) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc4) { + // 01011101ssss1dddEE11111111000100 | Rdd = combine(Rs,#0) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc4) { + // 01011101ssss0dddEE11111111000100 | Rdd = combine(#0,Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (P0) jumpr R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc4) { + // 01010011ssssddddEE11111111000100 | Rd = add(Rs,n1) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc4) { + // 01010001ssssddddEE11111111000100 | Rd = add(Rs,#1) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc4) { + // 010010iiiiiiddddEE11111111000100 | Rd = Ii ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc4) { + // 010110100000ddddEE11111111000100 | Rd = n1 ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc4) { + // 01010101ssssddddEE11111111000100 | Rd = sxtb(Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc4) { + // 01010100ssssddddEE11111111000100 | Rd = sxth(Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc4) { + // 01010000ssssddddEE11111111000100 | Rd = Rs ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc4) { + // 01010111ssssddddEE11111111000100 | Rd = and(Rs,#255) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc4) { + // 01010110ssssddddEE11111111000100 | Rd = zxth(Rs) ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc4) { + // 010010iiiiiiddddEE11111111000100 | Rd = Ii ; if (p0) jumpr r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0) jumpr R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003fc6) { + // 01000iiiiiiixxxxEE11111111000110 | Rx = add(Rxin,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003fc6) { + // 01011000ssssxxxxEE11111111000110 | Rx = add(Rxin,Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003fc6) { + // 010011iiiiiiddddEE11111111000110 | Rd = add(r29,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003fc6) { + // 01010010ssssddddEE11111111000110 | Rd = and(Rs,#1) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703fc6) { + // 010110100111ddddEE11111111000110 | if (!p0) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503fc6) { + // 010110100101ddddEE11111111000110 | if (!p0.new) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603fc6) { + // 010110100110ddddEE11111111000110 | if (p0) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403fc6) { + // 010110100100ddddEE11111111000110 | if (p0.new) Rd = #0 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003fc6) { + // 01011001ssss00iiEE11111111000110 | p0 = cmp.eq(Rs,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003fc6) { + // 010111000ii00dddEE11111111000110 | Rdd = combine(#0,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083fc6) { + // 010111000ii01dddEE11111111000110 | Rdd = combine(#1,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103fc6) { + // 010111000ii10dddEE11111111000110 | Rdd = combine(#2,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183fc6) { + // 010111000ii11dddEE11111111000110 | Rdd = combine(#3,Ii) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083fc6) { + // 01011101ssss1dddEE11111111000110 | Rdd = combine(Rs,#0) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003fc6) { + // 01011101ssss0dddEE11111111000110 | Rdd = combine(#0,Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (P0.new) jumpr:nt R31", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003fc6) { + // 01010011ssssddddEE11111111000110 | Rd = add(Rs,n1) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003fc6) { + // 01010001ssssddddEE11111111000110 | Rd = add(Rs,#1) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc6) { + // 010010iiiiiiddddEE11111111000110 | Rd = Ii ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003fc6) { + // 010110100000ddddEE11111111000110 | Rd = n1 ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003fc6) { + // 01010101ssssddddEE11111111000110 | Rd = sxtb(Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003fc6) { + // 01010100ssssddddEE11111111000110 | Rd = sxth(Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003fc6) { + // 01010000ssssddddEE11111111000110 | Rd = Rs ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003fc6) { + // 01010111ssssddddEE11111111000110 | Rd = and(Rs,#255) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003fc6) { + // 01010110ssssddddEE11111111000110 | Rd = zxth(Rs) ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003fc6) { + // 010010iiiiiiddddEE11111111000110 | Rd = Ii ; if (p0.new) jumpr:nt r31 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0.new) jumpr:nt R31", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x40003000) { + // 01000IIIIIIIxxxxEE110iiissssdddd | Rx = add(Rxin,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x58003000) { + // 01011000SSSSxxxxEE110iiissssdddd | Rx = add(Rxin,RS) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[5]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x4c003000) { + // 010011IIIIIIDDDDEE110iiissssdddd | RD = add(r29,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x52003000) { + // 01010010SSSSDDDDEE110iiissssdddd | RD = and(RS,#1) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a703000) { + // 010110100111DDDDEE110iiissssdddd | if (!p0) RD = #0 ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a503000) { + // 010110100101DDDDEE110iiissssdddd | if (!p0.new) RD = #0 ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a603000) { + // 010110100110DDDDEE110iiissssdddd | if (p0) RD = #0 ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a403000) { + // 010110100100DDDDEE110iiissssdddd | if (p0.new) RD = #0 ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf800) == 0x59003000) { + // 01011001SSSS00IIEE110iiissssdddd | p0 = cmp.eq(RS,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c003000) { + // 010111000II00DDDEE110iiissssdddd | RDD = combine(#0,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c083000) { + // 010111000II01DDDEE110iiissssdddd | RDD = combine(#1,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c103000) { + // 010111000II10DDDEE110iiissssdddd | RDD = combine(#2,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c183000) { + // 010111000II11DDDEE110iiissssdddd | RDD = combine(#3,II) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memb(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x5d083000) { + // 01011101SSSS1DDDEE110iiissssdddd | RDD = combine(RS,#0) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memb(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x5d003000) { + // 01011101SSSS0DDDEE110iiissssdddd | RDD = combine(#0,RS) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memb(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x53003000) { + // 01010011SSSSDDDDEE110iiissssdddd | RD = add(RS,n1) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x51003000) { + // 01010001SSSSDDDDEE110iiissssdddd | RD = add(RS,#1) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x48003000) { + // 010010IIIIIIDDDDEE110iiissssdddd | RD = II ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a003000) { + // 010110100000DDDDEE110iiissssdddd | RD = n1 ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x55003000) { + // 01010101SSSSDDDDEE110iiissssdddd | RD = sxtb(RS) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x54003000) { + // 01010100SSSSDDDDEE110iiissssdddd | RD = sxth(RS) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x50003000) { + // 01010000SSSSDDDDEE110iiissssdddd | RD = RS ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x57003000) { + // 01010111SSSSDDDDEE110iiissssdddd | RD = and(RS,#255) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x56003000) { + // 01010110SSSSDDDDEE110iiissssdddd | RD = zxth(RS) ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x48003000) { + // 010010IIIIIIDDDDEE110iiissssdddd | RD = II ; Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memb(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x40003e00) { + // 01000IIIIIIIxxxxEE111110iiiiiddd | Rx = add(Rxin,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x58003e00) { + // 01011000ssssxxxxEE111110iiiiiddd | Rx = add(Rxin,Rs) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x4c003e00) { + // 010011IIIIIIDDDDEE111110iiiiiddd | RD = add(r29,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x52003e00) { + // 01010010ssssDDDDEE111110iiiiiddd | RD = and(Rs,#1) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a703e00) { + // 010110100111DDDDEE111110iiiiiddd | if (!p0) RD = #0 ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a503e00) { + // 010110100101DDDDEE111110iiiiiddd | if (!p0.new) RD = #0 ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a603e00) { + // 010110100110DDDDEE111110iiiiiddd | if (p0) RD = #0 ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a403e00) { + // 010110100100DDDDEE111110iiiiiddd | if (p0.new) RD = #0 ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff00) == 0x59003e00) { + // 01011001ssss00IIEE111110iiiiiddd | p0 = cmp.eq(Rs,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x5c003e00) { + // 010111000II00DDDEE111110iiiiiddd | RDD = combine(#0,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x5c083e00) { + // 010111000II01DDDEE111110iiiiiddd | RDD = combine(#1,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x5c103e00) { + // 010111000II10DDDEE111110iiiiiddd | RDD = combine(#2,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x5c183e00) { + // 010111000II11DDDEE111110iiiiiddd | RDD = combine(#3,II) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x5d083e00) { + // 01011101ssss1DDDEE111110iiiiiddd | RDD = combine(Rs,#0) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x5d003e00) { + // 01011101ssss0DDDEE111110iiiiiddd | RDD = combine(#0,Rs) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memd(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x53003e00) { + // 01010011ssssDDDDEE111110iiiiiddd | RD = add(Rs,n1) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x51003e00) { + // 01010001ssssDDDDEE111110iiiiiddd | RD = add(Rs,#1) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x48003e00) { + // 010010IIIIIIDDDDEE111110iiiiiddd | RD = II ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x5a003e00) { + // 010110100000DDDDEE111110iiiiiddd | RD = n1 ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x55003e00) { + // 01010101ssssDDDDEE111110iiiiiddd | RD = sxtb(Rs) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x54003e00) { + // 01010100ssssDDDDEE111110iiiiiddd | RD = sxth(Rs) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x50003e00) { + // 01010000ssssDDDDEE111110iiiiiddd | RD = Rs ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x57003e00) { + // 01010111ssssDDDDEE111110iiiiiddd | RD = and(Rs,#255) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x56003e00) { + // 01010110ssssDDDDEE111110iiiiiddd | RD = zxth(Rs) ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x48003e00) { + // 010010IIIIIIDDDDEE111110iiiiiddd | RD = II ; Rdd = memd(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRD_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rdd8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memd(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_double_low8_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x40002000) { + // 01000IIIIIIIxxxxEE100iiissssdddd | Rx = add(Rxin,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x58002000) { + // 01011000SSSSxxxxEE100iiissssdddd | Rx = add(Rxin,RS) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + hex_extend_op(state, &(hi->ops[5]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x4c002000) { + // 010011IIIIIIDDDDEE100iiissssdddd | RD = add(r29,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x52002000) { + // 01010010SSSSDDDDEE100iiissssdddd | RD = and(RS,#1) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a702000) { + // 010110100111DDDDEE100iiissssdddd | if (!p0) RD = #0 ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a502000) { + // 010110100101DDDDEE100iiissssdddd | if (!p0.new) RD = #0 ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a602000) { + // 010110100110DDDDEE100iiissssdddd | if (p0) RD = #0 ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a402000) { + // 010110100100DDDDEE100iiissssdddd | if (p0.new) RD = #0 ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf800) == 0x59002000) { + // 01011001SSSS00IIEE100iiissssdddd | p0 = cmp.eq(RS,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c002000) { + // 010111000II00DDDEE100iiissssdddd | RDD = combine(#0,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c082000) { + // 010111000II01DDDEE100iiissssdddd | RDD = combine(#1,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c102000) { + // 010111000II10DDDEE100iiissssdddd | RDD = combine(#2,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c182000) { + // 010111000II11DDDEE100iiissssdddd | RDD = combine(#3,II) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x5d082000) { + // 01011101SSSS1DDDEE100iiissssdddd | RDD = combine(RS,#0) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x5d002000) { + // 01011101SSSS0DDDEE100iiissssdddd | RDD = combine(#0,RS) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x53002000) { + // 01010011SSSSDDDDEE100iiissssdddd | RD = add(RS,n1) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x51002000) { + // 01010001SSSSDDDDEE100iiissssdddd | RD = add(RS,#1) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x48002000) { + // 010010IIIIIIDDDDEE100iiissssdddd | RD = II ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a002000) { + // 010110100000DDDDEE100iiissssdddd | RD = n1 ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x55002000) { + // 01010101SSSSDDDDEE100iiissssdddd | RD = sxtb(RS) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x54002000) { + // 01010100SSSSDDDDEE100iiissssdddd | RD = sxth(RS) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x50002000) { + // 01010000SSSSDDDDEE100iiissssdddd | RD = RS ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x57002000) { + // 01010111SSSSDDDDEE100iiissssdddd | RD = and(RS,#255) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x56002000) { + // 01010110SSSSDDDDEE100iiissssdddd | RD = zxth(RS) ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x48002000) { + // 010010IIIIIIDDDDEE100iiissssdddd | RD = II ; Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0x40003c00) { + // 01000IIIIIIIxxxxEE11110iiiiidddd | Rx = add(Rxin,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x58003c00) { + // 01011000ssssxxxxEE11110iiiiidddd | Rx = add(Rxin,Rs) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x4c003c00) { + // 010011IIIIIIDDDDEE11110iiiiidddd | RD = add(r29,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x52003c00) { + // 01010010ssssDDDDEE11110iiiiidddd | RD = and(Rs,#1) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a703c00) { + // 010110100111DDDDEE11110iiiiidddd | if (!p0) RD = #0 ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a503c00) { + // 010110100101DDDDEE11110iiiiidddd | if (!p0.new) RD = #0 ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a603c00) { + // 010110100110DDDDEE11110iiiiidddd | if (p0) RD = #0 ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a403c00) { + // 010110100100DDDDEE11110iiiiidddd | if (p0.new) RD = #0 ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfe00) == 0x59003c00) { + // 01011001ssss00IIEE11110iiiiidddd | p0 = cmp.eq(Rs,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x5c003c00) { + // 010111000II00DDDEE11110iiiiidddd | RDD = combine(#0,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x5c083c00) { + // 010111000II01DDDEE11110iiiiidddd | RDD = combine(#1,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x5c103c00) { + // 010111000II10DDDEE11110iiiiidddd | RDD = combine(#2,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x5c183c00) { + // 010111000II11DDDEE11110iiiiidddd | RDD = combine(#3,II) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memw(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe00) == 0x5d083c00) { + // 01011101ssss1DDDEE11110iiiiidddd | RDD = combine(Rs,#0) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memw(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe00) == 0x5d003c00) { + // 01011101ssss0DDDEE11110iiiiidddd | RDD = combine(#0,Rs) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memw(R29+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x53003c00) { + // 01010011ssssDDDDEE11110iiiiidddd | RD = add(Rs,n1) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x51003c00) { + // 01010001ssssDDDDEE11110iiiiidddd | RD = add(Rs,#1) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x48003c00) { + // 010010IIIIIIDDDDEE11110iiiiidddd | RD = II ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x5a003c00) { + // 010110100000DDDDEE11110iiiiidddd | RD = n1 ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x55003c00) { + // 01010101ssssDDDDEE11110iiiiidddd | RD = sxtb(Rs) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x54003c00) { + // 01010100ssssDDDDEE11110iiiiidddd | RD = sxth(Rs) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x50003c00) { + // 01010000ssssDDDDEE11110iiiiidddd | RD = Rs ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x57003c00) { + // 01010111ssssDDDDEE11110iiiiidddd | RD = and(Rs,#255) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x56003c00) { + // 01010110ssssDDDDEE11110iiiiidddd | RD = zxth(Rs) ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x48003c00) { + // 010010IIIIIIDDDDEE11110iiiiidddd | RD = II ; Rd = memw(r29+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRI_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memw(R29+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x40002800) { + // 01000IIIIIIIxxxxEE101iiissssdddd | Rx = add(Rxin,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x58002800) { + // 01011000SSSSxxxxEE101iiissssdddd | Rx = add(Rxin,RS) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + hex_extend_op(state, &(hi->ops[5]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x4c002800) { + // 010011IIIIIIDDDDEE101iiissssdddd | RD = add(r29,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x52002800) { + // 01010010SSSSDDDDEE101iiissssdddd | RD = and(RS,#1) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a702800) { + // 010110100111DDDDEE101iiissssdddd | if (!p0) RD = #0 ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a502800) { + // 010110100101DDDDEE101iiissssdddd | if (!p0.new) RD = #0 ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a602800) { + // 010110100110DDDDEE101iiissssdddd | if (p0) RD = #0 ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a402800) { + // 010110100100DDDDEE101iiissssdddd | if (p0.new) RD = #0 ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf800) == 0x59002800) { + // 01011001SSSS00IIEE101iiissssdddd | p0 = cmp.eq(RS,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c002800) { + // 010111000II00DDDEE101iiissssdddd | RDD = combine(#0,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c082800) { + // 010111000II01DDDEE101iiissssdddd | RDD = combine(#1,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c102800) { + // 010111000II10DDDEE101iiissssdddd | RDD = combine(#2,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x5c182800) { + // 010111000II11DDDEE101iiissssdddd | RDD = combine(#3,II) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; %s = memuh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x5d082800) { + // 01011101SSSS1DDDEE101iiissssdddd | RDD = combine(RS,#0) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; %s = memuh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x5d002800) { + // 01011101SSSS0DDDEE101iiissssdddd | RDD = combine(#0,RS) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // RDD8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; %s = memuh(%s+%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x53002800) { + // 01010011SSSSDDDDEE101iiissssdddd | RD = add(RS,n1) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[3].attr |= HEX_OP_REG_OUT; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[5].type = HEX_OP_TYPE_IMM; + hi->ops[5].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[5].attr = HEX_OP_IMM_SCALED; + hi->ops[5].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[5].imm = hi->ops[5].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), hex_get_general_sub_regs(hi->ops[4].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[5].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x51002800) { + // 01010001SSSSDDDDEE101iiissssdddd | RD = add(RS,#1) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x48002800) { + // 010010IIIIIIDDDDEE101iiissssdddd | RD = II ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x5a002800) { + // 010110100000DDDDEE101iiissssdddd | RD = n1 ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x55002800) { + // 01010101SSSSDDDDEE101iiissssdddd | RD = sxtb(RS) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x54002800) { + // 01010100SSSSDDDDEE101iiissssdddd | RD = sxth(RS) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x50002800) { + // 01010000SSSSDDDDEE101iiissssdddd | RD = RS ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x57002800) { + // 01010111SSSSDDDDEE101iiissssdddd | RD = and(RS,#255) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x56002800) { + // 01010110SSSSDDDDEE101iiissssdddd | RD = zxth(RS) ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x48002800) { + // 010010IIIIIIDDDDEE101iiissssdddd | RD = II ; Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // RD32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rd16 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; %s = memuh(%s+%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f40) { + // 01000iiiiiiixxxxEE11111101000000 | Rx = add(Rxin,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f40) { + // 01011000ssssxxxxEE11111101000000 | Rx = add(Rxin,Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f40) { + // 010011iiiiiiddddEE11111101000000 | Rd = add(r29,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f40) { + // 01010010ssssddddEE11111101000000 | Rd = and(Rs,#1) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f40) { + // 010110100111ddddEE11111101000000 | if (!p0) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f40) { + // 010110100101ddddEE11111101000000 | if (!p0.new) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f40) { + // 010110100110ddddEE11111101000000 | if (p0) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f40) { + // 010110100100ddddEE11111101000000 | if (p0.new) Rd = #0 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f40) { + // 01011001ssss00iiEE11111101000000 | p0 = cmp.eq(Rs,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f40) { + // 010111000ii00dddEE11111101000000 | Rdd = combine(#0,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f40) { + // 010111000ii01dddEE11111101000000 | Rdd = combine(#1,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f40) { + // 010111000ii10dddEE11111101000000 | Rdd = combine(#2,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f40) { + // 010111000ii11dddEE11111101000000 | Rdd = combine(#3,Ii) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f40) { + // 01011101ssss1dddEE11111101000000 | Rdd = combine(Rs,#0) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f40) { + // 01011101ssss0dddEE11111101000000 | Rdd = combine(#0,Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f40) { + // 01010011ssssddddEE11111101000000 | Rd = add(Rs,n1) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f40) { + // 01010001ssssddddEE11111101000000 | Rd = add(Rs,#1) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f40) { + // 010010iiiiiiddddEE11111101000000 | Rd = Ii ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f40) { + // 010110100000ddddEE11111101000000 | Rd = n1 ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f40) { + // 01010101ssssddddEE11111101000000 | Rd = sxtb(Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f40) { + // 01010100ssssddddEE11111101000000 | Rd = sxth(Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f40) { + // 01010000ssssddddEE11111101000000 | Rd = Rs ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = %s ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f40) { + // 01010111ssssddddEE11111101000000 | Rd = and(Rs,#255) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f40) { + // 01010110ssssddddEE11111101000000 | Rd = zxth(Rs) ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f40) { + // 010010iiiiiiddddEE11111101000000 | Rd = Ii ; dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f45) { + // 01000iiiiiiixxxxEE11111101000101 | Rx = add(Rxin,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f45) { + // 01011000ssssxxxxEE11111101000101 | Rx = add(Rxin,Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f45) { + // 010011iiiiiiddddEE11111101000101 | Rd = add(r29,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f45) { + // 01010010ssssddddEE11111101000101 | Rd = and(Rs,#1) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f45) { + // 010110100111ddddEE11111101000101 | if (!p0) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f45) { + // 010110100101ddddEE11111101000101 | if (!p0.new) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f45) { + // 010110100110ddddEE11111101000101 | if (p0) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f45) { + // 010110100100ddddEE11111101000101 | if (p0.new) Rd = #0 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f45) { + // 01011001ssss00iiEE11111101000101 | p0 = cmp.eq(Rs,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f45) { + // 010111000ii00dddEE11111101000101 | Rdd = combine(#0,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f45) { + // 010111000ii01dddEE11111101000101 | Rdd = combine(#1,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f45) { + // 010111000ii10dddEE11111101000101 | Rdd = combine(#2,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f45) { + // 010111000ii11dddEE11111101000101 | Rdd = combine(#3,Ii) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f45) { + // 01011101ssss1dddEE11111101000101 | Rdd = combine(Rs,#0) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f45) { + // 01011101ssss0dddEE11111101000101 | Rdd = combine(#0,Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (!P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f45) { + // 01010011ssssddddEE11111101000101 | Rd = add(Rs,n1) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f45) { + // 01010001ssssddddEE11111101000101 | Rd = add(Rs,#1) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f45) { + // 010010iiiiiiddddEE11111101000101 | Rd = Ii ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f45) { + // 010110100000ddddEE11111101000101 | Rd = n1 ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f45) { + // 01010101ssssddddEE11111101000101 | Rd = sxtb(Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f45) { + // 01010100ssssddddEE11111101000101 | Rd = sxth(Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f45) { + // 01010000ssssddddEE11111101000101 | Rd = Rs ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f45) { + // 01010111ssssddddEE11111101000101 | Rd = and(Rs,#255) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f45) { + // 01010110ssssddddEE11111101000101 | Rd = zxth(Rs) ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f45) { + // 010010iiiiiiddddEE11111101000101 | Rd = Ii ; if (!p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f47) { + // 01000iiiiiiixxxxEE11111101000111 | Rx = add(Rxin,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f47) { + // 01011000ssssxxxxEE11111101000111 | Rx = add(Rxin,Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f47) { + // 010011iiiiiiddddEE11111101000111 | Rd = add(r29,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f47) { + // 01010010ssssddddEE11111101000111 | Rd = and(Rs,#1) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f47) { + // 010110100111ddddEE11111101000111 | if (!p0) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f47) { + // 010110100101ddddEE11111101000111 | if (!p0.new) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f47) { + // 010110100110ddddEE11111101000111 | if (p0) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f47) { + // 010110100100ddddEE11111101000111 | if (p0.new) Rd = #0 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f47) { + // 01011001ssss00iiEE11111101000111 | p0 = cmp.eq(Rs,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f47) { + // 010111000ii00dddEE11111101000111 | Rdd = combine(#0,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f47) { + // 010111000ii01dddEE11111101000111 | Rdd = combine(#1,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f47) { + // 010111000ii10dddEE11111101000111 | Rdd = combine(#2,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f47) { + // 010111000ii11dddEE11111101000111 | Rdd = combine(#3,Ii) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f47) { + // 01011101ssss1dddEE11111101000111 | Rdd = combine(Rs,#0) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f47) { + // 01011101ssss0dddEE11111101000111 | Rdd = combine(#0,Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (!P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f47) { + // 01010011ssssddddEE11111101000111 | Rd = add(Rs,n1) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f47) { + // 01010001ssssddddEE11111101000111 | Rd = add(Rs,#1) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f47) { + // 010010iiiiiiddddEE11111101000111 | Rd = Ii ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f47) { + // 010110100000ddddEE11111101000111 | Rd = n1 ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f47) { + // 01010101ssssddddEE11111101000111 | Rd = sxtb(Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f47) { + // 01010100ssssddddEE11111101000111 | Rd = sxth(Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f47) { + // 01010000ssssddddEE11111101000111 | Rd = Rs ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f47) { + // 01010111ssssddddEE11111101000111 | Rd = and(Rs,#255) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f47) { + // 01010110ssssddddEE11111101000111 | Rd = zxth(Rs) ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f47) { + // 010010iiiiiiddddEE11111101000111 | Rd = Ii ; if (!p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_FNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (!P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f44) { + // 01000iiiiiiixxxxEE11111101000100 | Rx = add(Rxin,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f44) { + // 01011000ssssxxxxEE11111101000100 | Rx = add(Rxin,Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f44) { + // 010011iiiiiiddddEE11111101000100 | Rd = add(r29,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f44) { + // 01010010ssssddddEE11111101000100 | Rd = and(Rs,#1) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f44) { + // 010110100111ddddEE11111101000100 | if (!p0) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f44) { + // 010110100101ddddEE11111101000100 | if (!p0.new) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f44) { + // 010110100110ddddEE11111101000100 | if (p0) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f44) { + // 010110100100ddddEE11111101000100 | if (p0.new) Rd = #0 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f44) { + // 01011001ssss00iiEE11111101000100 | p0 = cmp.eq(Rs,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f44) { + // 010111000ii00dddEE11111101000100 | Rdd = combine(#0,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f44) { + // 010111000ii01dddEE11111101000100 | Rdd = combine(#1,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f44) { + // 010111000ii10dddEE11111101000100 | Rdd = combine(#2,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f44) { + // 010111000ii11dddEE11111101000100 | Rdd = combine(#3,Ii) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f44) { + // 01011101ssss1dddEE11111101000100 | Rdd = combine(Rs,#0) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f44) { + // 01011101ssss0dddEE11111101000100 | Rdd = combine(#0,Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (P0) dealloc_return", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f44) { + // 01010011ssssddddEE11111101000100 | Rd = add(Rs,n1) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f44) { + // 01010001ssssddddEE11111101000100 | Rd = add(Rs,#1) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f44) { + // 010010iiiiiiddddEE11111101000100 | Rd = Ii ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f44) { + // 010110100000ddddEE11111101000100 | Rd = n1 ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f44) { + // 01010101ssssddddEE11111101000100 | Rd = sxtb(Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f44) { + // 01010100ssssddddEE11111101000100 | Rd = sxth(Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f44) { + // 01010000ssssddddEE11111101000100 | Rd = Rs ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f44) { + // 01010111ssssddddEE11111101000100 | Rd = and(Rs,#255) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f44) { + // 01010110ssssddddEE11111101000100 | Rd = zxth(Rs) ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f44) { + // 010010iiiiiiddddEE11111101000100 | Rd = Ii ; if (p0) dealloc_return + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0) dealloc_return", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ffff) == 0x40003f46) { + // 01000iiiiiiixxxxEE11111101000110 | Rx = add(Rxin,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // Ii + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x58003f46) { + // 01011000ssssxxxxEE11111101000110 | Rx = add(Rxin,Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x4c003f46) { + // 010011iiiiiiddddEE11111101000110 | Rd = add(r29,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x52003f46) { + // 01010010ssssddddEE11111101000110 | Rd = and(Rs,#1) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a703f46) { + // 010110100111ddddEE11111101000110 | if (!p0) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a503f46) { + // 010110100101ddddEE11111101000110 | if (!p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a603f46) { + // 010110100110ddddEE11111101000110 | if (p0) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a403f46) { + // 010110100100ddddEE11111101000110 | if (p0.new) Rd = #0 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cffff) == 0x59003f46) { + // 01011001ssss00iiEE11111101000110 | p0 = cmp.eq(Rs,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c003f46) { + // 010111000ii00dddEE11111101000110 | Rdd = combine(#0,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c083f46) { + // 010111000ii01dddEE11111101000110 | Rdd = combine(#1,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c103f46) { + // 010111000ii10dddEE11111101000110 | Rdd = combine(#2,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ffff) == 0x5c183f46) { + // 010111000ii11dddEE11111101000110 | Rdd = combine(#3,Ii) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d083f46) { + // 01011101ssss1dddEE11111101000110 | Rdd = combine(Rs,#0) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ffff) == 0x5d003f46) { + // 01011101ssss0dddEE11111101000110 | Rdd = combine(#0,Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; if (P0.new) dealloc_return:nt", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x53003f46) { + // 01010011ssssddddEE11111101000110 | Rd = add(Rs,n1) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x51003f46) { + // 01010001ssssddddEE11111101000110 | Rd = add(Rs,#1) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f46) { + // 010010iiiiiiddddEE11111101000110 | Rd = Ii ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ffff) == 0x5a003f46) { + // 010110100000ddddEE11111101000110 | Rd = n1 ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x55003f46) { + // 01010101ssssddddEE11111101000110 | Rd = sxtb(Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x54003f46) { + // 01010100ssssddddEE11111101000110 | Rd = sxth(Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x50003f46) { + // 01010000ssssddddEE11111101000110 | Rd = Rs ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = %s ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x57003f46) { + // 01010111ssssddddEE11111101000110 | Rd = and(Rs,#255) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ffff) == 0x56003f46) { + // 01010110ssssddddEE11111101000110 | Rd = zxth(Rs) ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ffff) == 0x48003f46) { + // 010010iiiiiiddddEE11111101000110 | Rd = Ii ; if (p0.new) dealloc_return:nt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_TNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; if (P0.new) dealloc_return:nt", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x6(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf800f000) == 0x60001000) { + // 01100IIIIIIIxxxxEE01iiiisssstttt | Rx = add(Rxin,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x78001000) { + // 01111000SSSSxxxxEE01iiiisssstttt | Rx = add(Rxin,RS) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x6c001000) { + // 011011IIIIIIddddEE01iiiisssstttt | Rd = add(r29,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x72001000) { + // 01110010SSSSddddEE01iiiisssstttt | Rd = and(RS,#1) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a701000) { + // 011110100111ddddEE01iiiisssstttt | if (!p0) Rd = #0 ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a501000) { + // 011110100101ddddEE01iiiisssstttt | if (!p0.new) Rd = #0 ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a601000) { + // 011110100110ddddEE01iiiisssstttt | if (p0) Rd = #0 ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a401000) { + // 011110100100ddddEE01iiiisssstttt | if (p0.new) Rd = #0 ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf000) == 0x79001000) { + // 01111001SSSS00IIEE01iiiisssstttt | p0 = cmp.eq(RS,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c001000) { + // 011111000II00dddEE01iiiisssstttt | Rdd = combine(#0,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c081000) { + // 011111000II01dddEE01iiiisssstttt | Rdd = combine(#1,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c101000) { + // 011111000II10dddEE01iiiisssstttt | Rdd = combine(#2,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c181000) { + // 011111000II11dddEE01iiiisssstttt | Rdd = combine(#3,II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x7d081000) { + // 01111101SSSS1dddEE01iiiisssstttt | Rdd = combine(RS,#0) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x7d001000) { + // 01111101SSSS0dddEE01iiiisssstttt | Rdd = combine(#0,RS) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x73001000) { + // 01110011SSSSddddEE01iiiisssstttt | Rd = add(RS,n1) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x71001000) { + // 01110001SSSSddddEE01iiiisssstttt | Rd = add(RS,#1) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x68001000) { + // 011010IIIIIIddddEE01iiiisssstttt | Rd = II ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a001000) { + // 011110100000ddddEE01iiiisssstttt | Rd = n1 ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x75001000) { + // 01110101SSSSddddEE01iiiisssstttt | Rd = sxtb(RS) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x74001000) { + // 01110100SSSSddddEE01iiiisssstttt | Rd = sxth(RS) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x70001000) { + // 01110000SSSSddddEE01iiiisssstttt | Rd = RS ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x77001000) { + // 01110111SSSSddddEE01iiiisssstttt | Rd = and(RS,#255) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x76001000) { + // 01110110SSSSddddEE01iiiisssstttt | Rd = zxth(RS) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x68001000) { + // 011010IIIIIIddddEE01iiiisssstttt | Rd = II ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x60000000) { + // 01100IIIIIIIxxxxEE00iiiisssstttt | Rx = add(Rxin,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x78000000) { + // 01111000SSSSxxxxEE00iiiisssstttt | Rx = add(Rxin,RS) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x6c000000) { + // 011011IIIIIIddddEE00iiiisssstttt | Rd = add(r29,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x72000000) { + // 01110010SSSSddddEE00iiiisssstttt | Rd = and(RS,#1) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a700000) { + // 011110100111ddddEE00iiiisssstttt | if (!p0) Rd = #0 ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a500000) { + // 011110100101ddddEE00iiiisssstttt | if (!p0.new) Rd = #0 ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a600000) { + // 011110100110ddddEE00iiiisssstttt | if (p0) Rd = #0 ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a400000) { + // 011110100100ddddEE00iiiisssstttt | if (p0.new) Rd = #0 ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf000) == 0x79000000) { + // 01111001SSSS00IIEE00iiiisssstttt | p0 = cmp.eq(RS,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c000000) { + // 011111000II00dddEE00iiiisssstttt | Rdd = combine(#0,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c080000) { + // 011111000II01dddEE00iiiisssstttt | Rdd = combine(#1,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c100000) { + // 011111000II10dddEE00iiiisssstttt | Rdd = combine(#2,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f000) == 0x7c180000) { + // 011111000II11dddEE00iiiisssstttt | Rdd = combine(#3,II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x7d080000) { + // 01111101SSSS1dddEE00iiiisssstttt | Rdd = combine(RS,#0) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f000) == 0x7d000000) { + // 01111101SSSS0dddEE00iiiisssstttt | Rdd = combine(#0,RS) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x73000000) { + // 01110011SSSSddddEE00iiiisssstttt | Rd = add(RS,n1) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x71000000) { + // 01110001SSSSddddEE00iiiisssstttt | Rd = add(RS,#1) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x68000000) { + // 011010IIIIIIddddEE00iiiisssstttt | Rd = II ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f000) == 0x7a000000) { + // 011110100000ddddEE00iiiisssstttt | Rd = n1 ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x75000000) { + // 01110101SSSSddddEE00iiiisssstttt | Rd = sxtb(RS) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x74000000) { + // 01110100SSSSddddEE00iiiisssstttt | Rd = sxth(RS) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x70000000) { + // 01110000SSSSddddEE00iiiisssstttt | Rd = RS ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x77000000) { + // 01110111SSSSddddEE00iiiisssstttt | Rd = and(RS,#255) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x76000000) { + // 01110110SSSSddddEE00iiiisssstttt | Rd = zxth(RS) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f000) == 0x68000000) { + // 011010IIIIIIddddEE00iiiisssstttt | Rd = II ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x7(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf800fe0f) == 0x60003c00) { + // 01100IIIIIIIxxxxEE11110iiiii0000 | Rx = add(Rxin,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x78003c00) { + // 01111000ssssxxxxEE11110iiiii0000 | Rx = add(Rxin,Rs) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe0f) == 0x6c003c00) { + // 011011IIIIIIddddEE11110iiiii0000 | Rd = add(r29,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x72003c00) { + // 01110010ssssddddEE11110iiiii0000 | Rd = and(Rs,#1) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a703c00) { + // 011110100111ddddEE11110iiiii0000 | if (!p0) Rd = #0 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a503c00) { + // 011110100101ddddEE11110iiiii0000 | if (!p0.new) Rd = #0 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a603c00) { + // 011110100110ddddEE11110iiiii0000 | if (p0) Rd = #0 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a403c00) { + // 011110100100ddddEE11110iiiii0000 | if (p0.new) Rd = #0 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfe0f) == 0x79003c00) { + // 01111001ssss00IIEE11110iiiii0000 | p0 = cmp.eq(Rs,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c003c00) { + // 011111000II00dddEE11110iiiii0000 | Rdd = combine(#0,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c083c00) { + // 011111000II01dddEE11110iiiii0000 | Rdd = combine(#1,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c103c00) { + // 011111000II10dddEE11110iiiii0000 | Rdd = combine(#2,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe0f) == 0x7c183c00) { + // 011111000II11dddEE11110iiiii0000 | Rdd = combine(#3,II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe0f) == 0x7d083c00) { + // 01111101ssss1dddEE11110iiiii0000 | Rdd = combine(Rs,#0) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe0f) == 0x7d003c00) { + // 01111101ssss0dddEE11110iiiii0000 | Rdd = combine(#0,Rs) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x73003c00) { + // 01110011ssssddddEE11110iiiii0000 | Rd = add(Rs,n1) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x71003c00) { + // 01110001ssssddddEE11110iiiii0000 | Rd = add(Rs,#1) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe0f) == 0x68003c00) { + // 011010IIIIIIddddEE11110iiiii0000 | Rd = II ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe0f) == 0x7a003c00) { + // 011110100000ddddEE11110iiiii0000 | Rd = n1 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x75003c00) { + // 01110101ssssddddEE11110iiiii0000 | Rd = sxtb(Rs) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x74003c00) { + // 01110100ssssddddEE11110iiiii0000 | Rd = sxth(Rs) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x70003c00) { + // 01110000ssssddddEE11110iiiii0000 | Rd = Rs ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x77003c00) { + // 01110111ssssddddEE11110iiiii0000 | Rd = and(Rs,#255) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0x76003c00) { + // 01110110ssssddddEE11110iiiii0000 | Rd = zxth(Rs) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe0f) == 0x68003c00) { + // 011010IIIIIIddddEE11110iiiii0000 | Rd = II ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x60003200) { + // 01100IIIIIIIxxxxEE110010ssssiiii | Rx = add(Rxin,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x78003200) { + // 01111000SSSSxxxxEE110010ssssiiii | Rx = add(Rxin,RS) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003200) { + // 011011IIIIIIddddEE110010ssssiiii | Rd = add(r29,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x72003200) { + // 01110010SSSSddddEE110010ssssiiii | Rd = and(RS,#1) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703200) { + // 011110100111ddddEE110010ssssiiii | if (!p0) Rd = #0 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503200) { + // 011110100101ddddEE110010ssssiiii | if (!p0.new) Rd = #0 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603200) { + // 011110100110ddddEE110010ssssiiii | if (p0) Rd = #0 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403200) { + // 011110100100ddddEE110010ssssiiii | if (p0.new) Rd = #0 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff00) == 0x79003200) { + // 01111001SSSS00IIEE110010ssssiiii | p0 = cmp.eq(RS,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003200) { + // 011111000II00dddEE110010ssssiiii | Rdd = combine(#0,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083200) { + // 011111000II01dddEE110010ssssiiii | Rdd = combine(#1,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103200) { + // 011111000II10dddEE110010ssssiiii | Rdd = combine(#2,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183200) { + // 011111000II11dddEE110010ssssiiii | Rdd = combine(#3,II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083200) { + // 01111101SSSS1dddEE110010ssssiiii | Rdd = combine(RS,#0) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003200) { + // 01111101SSSS0dddEE110010ssssiiii | Rdd = combine(#0,RS) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x73003200) { + // 01110011SSSSddddEE110010ssssiiii | Rd = add(RS,n1) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x71003200) { + // 01110001SSSSddddEE110010ssssiiii | Rd = add(RS,#1) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003200) { + // 011010IIIIIIddddEE110010ssssiiii | Rd = II ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003200) { + // 011110100000ddddEE110010ssssiiii | Rd = n1 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x75003200) { + // 01110101SSSSddddEE110010ssssiiii | Rd = sxtb(RS) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x74003200) { + // 01110100SSSSddddEE110010ssssiiii | Rd = sxth(RS) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x70003200) { + // 01110000SSSSddddEE110010ssssiiii | Rd = RS ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x77003200) { + // 01110111SSSSddddEE110010ssssiiii | Rd = and(RS,#255) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x76003200) { + // 01110110SSSSddddEE110010ssssiiii | Rd = zxth(RS) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003200) { + // 011010IIIIIIddddEE110010ssssiiii | Rd = II ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x60003300) { + // 01100IIIIIIIxxxxEE110011ssssiiii | Rx = add(Rxin,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x78003300) { + // 01111000SSSSxxxxEE110011ssssiiii | Rx = add(Rxin,RS) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003300) { + // 011011IIIIIIddddEE110011ssssiiii | Rd = add(r29,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x72003300) { + // 01110010SSSSddddEE110011ssssiiii | Rd = and(RS,#1) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703300) { + // 011110100111ddddEE110011ssssiiii | if (!p0) Rd = #0 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503300) { + // 011110100101ddddEE110011ssssiiii | if (!p0.new) Rd = #0 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603300) { + // 011110100110ddddEE110011ssssiiii | if (p0) Rd = #0 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403300) { + // 011110100100ddddEE110011ssssiiii | if (p0.new) Rd = #0 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff00) == 0x79003300) { + // 01111001SSSS00IIEE110011ssssiiii | p0 = cmp.eq(RS,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003300) { + // 011111000II00dddEE110011ssssiiii | Rdd = combine(#0,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083300) { + // 011111000II01dddEE110011ssssiiii | Rdd = combine(#1,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103300) { + // 011111000II10dddEE110011ssssiiii | Rdd = combine(#2,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183300) { + // 011111000II11dddEE110011ssssiiii | Rdd = combine(#3,II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083300) { + // 01111101SSSS1dddEE110011ssssiiii | Rdd = combine(RS,#0) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003300) { + // 01111101SSSS0dddEE110011ssssiiii | Rdd = combine(#0,RS) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x73003300) { + // 01110011SSSSddddEE110011ssssiiii | Rd = add(RS,n1) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x71003300) { + // 01110001SSSSddddEE110011ssssiiii | Rd = add(RS,#1) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003300) { + // 011010IIIIIIddddEE110011ssssiiii | Rd = II ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003300) { + // 011110100000ddddEE110011ssssiiii | Rd = n1 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x75003300) { + // 01110101SSSSddddEE110011ssssiiii | Rd = sxtb(RS) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x74003300) { + // 01110100SSSSddddEE110011ssssiiii | Rd = sxth(RS) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x70003300) { + // 01110000SSSSddddEE110011ssssiiii | Rd = RS ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x77003300) { + // 01110111SSSSddddEE110011ssssiiii | Rd = and(RS,#255) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x76003300) { + // 01110110SSSSddddEE110011ssssiiii | Rd = zxth(RS) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003300) { + // 011010IIIIIIddddEE110011ssssiiii | Rd = II ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0x60002a00) { + // 01100IIIIIIIxxxxEE10101iiiiiittt | Rx = add(Rxin,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x78002a00) { + // 01111000ssssxxxxEE10101iiiiiittt | Rx = add(Rxin,Rs) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x6c002a00) { + // 011011IIIIIIddddEE10101iiiiiittt | Rd = add(r29,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x72002a00) { + // 01110010ssssddddEE10101iiiiiittt | Rd = and(Rs,#1) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a702a00) { + // 011110100111ddddEE10101iiiiiittt | if (!p0) Rd = #0 ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_general_double_low8_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a502a00) { + // 011110100101ddddEE10101iiiiiittt | if (!p0.new) Rd = #0 ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_general_double_low8_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a602a00) { + // 011110100110ddddEE10101iiiiiittt | if (p0) Rd = #0 ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_general_double_low8_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a402a00) { + // 011110100100ddddEE10101iiiiiittt | if (p0.new) Rd = #0 ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 8)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_general_double_low8_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfe00) == 0x79002a00) { + // 01111001ssss00IIEE10101iiiiiittt | p0 = cmp.eq(Rs,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c002a00) { + // 011111000II00dddEE10101iiiiiittt | Rdd = combine(#0,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c082a00) { + // 011111000II01dddEE10101iiiiiittt | Rdd = combine(#1,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c102a00) { + // 011111000II10dddEE10101iiiiiittt | Rdd = combine(#2,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c182a00) { + // 011111000II11dddEE10101iiiiiittt | Rdd = combine(#3,II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe00) == 0x7d082a00) { + // 01111101ssss1dddEE10101iiiiiittt | Rdd = combine(Rs,#0) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe00) == 0x7d002a00) { + // 01111101ssss0dddEE10101iiiiiittt | Rdd = combine(#0,Rs) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x73002a00) { + // 01110011ssssddddEE10101iiiiiittt | Rd = add(Rs,n1) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x71002a00) { + // 01110001ssssddddEE10101iiiiiittt | Rd = add(Rs,#1) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x68002a00) { + // 011010IIIIIIddddEE10101iiiiiittt | Rd = II ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a002a00) { + // 011110100000ddddEE10101iiiiiittt | Rd = n1 ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x75002a00) { + // 01110101ssssddddEE10101iiiiiittt | Rd = sxtb(Rs) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x74002a00) { + // 01110100ssssddddEE10101iiiiiittt | Rd = sxth(Rs) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x70002a00) { + // 01110000ssssddddEE10101iiiiiittt | Rd = Rs ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x77002a00) { + // 01110111ssssddddEE10101iiiiiittt | Rd = and(Rs,#255) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x76002a00) { + // 01110110ssssddddEE10101iiiiiittt | Rd = zxth(Rs) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x68002a00) { + // 011010IIIIIIddddEE10101iiiiiittt | Rd = II ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0x60002000) { + // 01100IIIIIIIxxxxEE100iiisssstttt | Rx = add(Rxin,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x78002000) { + // 01111000SSSSxxxxEE100iiisssstttt | Rx = add(Rxin,RS) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x6c002000) { + // 011011IIIIIIddddEE100iiisssstttt | Rd = add(r29,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x72002000) { + // 01110010SSSSddddEE100iiisssstttt | Rd = and(RS,#1) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x7a702000) { + // 011110100111ddddEE100iiisssstttt | if (!p0) Rd = #0 ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x7a502000) { + // 011110100101ddddEE100iiisssstttt | if (!p0.new) Rd = #0 ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x7a602000) { + // 011110100110ddddEE100iiisssstttt | if (p0) Rd = #0 ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x7a402000) { + // 011110100100ddddEE100iiisssstttt | if (p0.new) Rd = #0 ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cf800) == 0x79002000) { + // 01111001SSSS00IIEE100iiisssstttt | p0 = cmp.eq(RS,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x7c002000) { + // 011111000II00dddEE100iiisssstttt | Rdd = combine(#0,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x7c082000) { + // 011111000II01dddEE100iiisssstttt | Rdd = combine(#1,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x7c102000) { + // 011111000II10dddEE100iiisssstttt | Rdd = combine(#2,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98f800) == 0x7c182000) { + // 011111000II11dddEE100iiisssstttt | Rdd = combine(#3,II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x7d082000) { + // 01111101SSSS1dddEE100iiisssstttt | Rdd = combine(RS,#0) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08f800) == 0x7d002000) { + // 01111101SSSS0dddEE100iiisssstttt | Rdd = combine(#0,RS) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x73002000) { + // 01110011SSSSddddEE100iiisssstttt | Rd = add(RS,n1) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x71002000) { + // 01110001SSSSddddEE100iiisssstttt | Rd = add(RS,#1) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x68002000) { + // 011010IIIIIIddddEE100iiisssstttt | Rd = II ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0f800) == 0x7a002000) { + // 011110100000ddddEE100iiisssstttt | Rd = n1 ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x75002000) { + // 01110101SSSSddddEE100iiisssstttt | Rd = sxtb(RS) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x74002000) { + // 01110100SSSSddddEE100iiisssstttt | Rd = sxth(RS) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x70002000) { + // 01110000SSSSddddEE100iiisssstttt | Rd = RS ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x77002000) { + // 01110111SSSSddddEE100iiisssstttt | Rd = and(RS,#255) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0x76002000) { + // 01110110SSSSddddEE100iiisssstttt | Rd = zxth(RS) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00f800) == 0x68002000) { + // 011010IIIIIIddddEE100iiisssstttt | Rd = II ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0x60002800) { + // 01100IIIIIIIxxxxEE10100iiiiitttt | Rx = add(Rxin,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x78002800) { + // 01111000ssssxxxxEE10100iiiiitttt | Rx = add(Rxin,Rs) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x6c002800) { + // 011011IIIIIIddddEE10100iiiiitttt | Rd = add(r29,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x72002800) { + // 01110010ssssddddEE10100iiiiitttt | Rd = and(Rs,#1) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a702800) { + // 011110100111ddddEE10100iiiiitttt | if (!p0) Rd = #0 ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a502800) { + // 011110100101ddddEE10100iiiiitttt | if (!p0.new) Rd = #0 ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a602800) { + // 011110100110ddddEE10100iiiiitttt | if (p0) Rd = #0 ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a402800) { + // 011110100100ddddEE10100iiiiitttt | if (p0.new) Rd = #0 ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cfe00) == 0x79002800) { + // 01111001ssss00IIEE10100iiiiitttt | p0 = cmp.eq(Rs,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c002800) { + // 011111000II00dddEE10100iiiiitttt | Rdd = combine(#0,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c082800) { + // 011111000II01dddEE10100iiiiitttt | Rdd = combine(#1,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c102800) { + // 011111000II10dddEE10100iiiiitttt | Rdd = combine(#2,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98fe00) == 0x7c182800) { + // 011111000II11dddEE10100iiiiitttt | Rdd = combine(#3,II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe00) == 0x7d082800) { + // 01111101ssss1dddEE10100iiiiitttt | Rdd = combine(Rs,#0) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08fe00) == 0x7d002800) { + // 01111101ssss0dddEE10100iiiiitttt | Rdd = combine(#0,Rs) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x73002800) { + // 01110011ssssddddEE10100iiiiitttt | Rd = add(Rs,n1) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x71002800) { + // 01110001ssssddddEE10100iiiiitttt | Rd = add(Rs,#1) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x68002800) { + // 011010IIIIIIddddEE10100iiiiitttt | Rd = II ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0fe00) == 0x7a002800) { + // 011110100000ddddEE10100iiiiitttt | Rd = n1 ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x75002800) { + // 01110101ssssddddEE10100iiiiitttt | Rd = sxtb(Rs) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x74002800) { + // 01110100ssssddddEE10100iiiiitttt | Rd = sxth(Rs) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x70002800) { + // 01110000ssssddddEE10100iiiiitttt | Rd = Rs ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x77002800) { + // 01110111ssssddddEE10100iiiiitttt | Rd = and(Rs,#255) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0x76002800) { + // 01110110ssssddddEE10100iiiiitttt | Rd = zxth(Rs) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00fe00) == 0x68002800) { + // 011010IIIIIIddddEE10100iiiiitttt | Rd = II ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x60003000) { + // 01100IIIIIIIxxxxEE110000ssssiiii | Rx = add(Rxin,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x78003000) { + // 01111000SSSSxxxxEE110000ssssiiii | Rx = add(Rxin,RS) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003000) { + // 011011IIIIIIddddEE110000ssssiiii | Rd = add(r29,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x72003000) { + // 01110010SSSSddddEE110000ssssiiii | Rd = and(RS,#1) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703000) { + // 011110100111ddddEE110000ssssiiii | if (!p0) Rd = #0 ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503000) { + // 011110100101ddddEE110000ssssiiii | if (!p0.new) Rd = #0 ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603000) { + // 011110100110ddddEE110000ssssiiii | if (p0) Rd = #0 ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403000) { + // 011110100100ddddEE110000ssssiiii | if (p0.new) Rd = #0 ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff00) == 0x79003000) { + // 01111001SSSS00IIEE110000ssssiiii | p0 = cmp.eq(RS,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003000) { + // 011111000II00dddEE110000ssssiiii | Rdd = combine(#0,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083000) { + // 011111000II01dddEE110000ssssiiii | Rdd = combine(#1,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103000) { + // 011111000II10dddEE110000ssssiiii | Rdd = combine(#2,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183000) { + // 011111000II11dddEE110000ssssiiii | Rdd = combine(#3,II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083000) { + // 01111101SSSS1dddEE110000ssssiiii | Rdd = combine(RS,#0) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003000) { + // 01111101SSSS0dddEE110000ssssiiii | Rdd = combine(#0,RS) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x73003000) { + // 01110011SSSSddddEE110000ssssiiii | Rd = add(RS,n1) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x71003000) { + // 01110001SSSSddddEE110000ssssiiii | Rd = add(RS,#1) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003000) { + // 011010IIIIIIddddEE110000ssssiiii | Rd = II ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003000) { + // 011110100000ddddEE110000ssssiiii | Rd = n1 ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x75003000) { + // 01110101SSSSddddEE110000ssssiiii | Rd = sxtb(RS) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x74003000) { + // 01110100SSSSddddEE110000ssssiiii | Rd = sxth(RS) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x70003000) { + // 01110000SSSSddddEE110000ssssiiii | Rd = RS ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x77003000) { + // 01110111SSSSddddEE110000ssssiiii | Rd = and(RS,#255) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x76003000) { + // 01110110SSSSddddEE110000ssssiiii | Rd = zxth(RS) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003000) { + // 011010IIIIIIddddEE110000ssssiiii | Rd = II ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0x60003100) { + // 01100IIIIIIIxxxxEE110001ssssiiii | Rx = add(Rxin,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7f00000) >> 20); // II + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x78003100) { + // 01111000SSSSxxxxEE110001ssssiiii | Rx = add(Rxin,RS) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rx16in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%sin,%s) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x6c003100) { + // 011011IIIIIIddddEE110001ssssiiii | Rd = add(r29,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(R29,%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x72003100) { + // 01110010SSSSddddEE110001ssssiiii | Rd = and(RS,#1) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#1) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a703100) { + // 011110100111ddddEE110001ssssiiii | if (!p0) Rd = #0 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0) %s = #0 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a503100) { + // 011110100101ddddEE110001ssssiiii | if (!p0.new) Rd = #0 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) %s = #0 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a603100) { + // 011110100110ddddEE110001ssssiiii | if (p0) Rd = #0 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0) %s = #0 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a403100) { + // 011110100100ddddEE110001ssssiiii | if (p0.new) Rd = #0 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) %s = #0 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0cff00) == 0x79003100) { + // 01111001SSSS00IIEE110001ssssiiii | p0 = cmp.eq(RS,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x30000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c003100) { + // 011111000II00dddEE110001ssssiiii | Rdd = combine(#0,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c083100) { + // 011111000II01dddEE110001ssssiiii | Rdd = combine(#1,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#1,%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c103100) { + // 011111000II10dddEE110001ssssiiii | Rdd = combine(#2,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#2,%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff98ff00) == 0x7c183100) { + // 011111000II11dddEE110001ssssiiii | Rdd = combine(#3,II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x600000) >> 21); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#3,%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d083100) { + // 01111101SSSS1dddEE110001ssssiiii | Rdd = combine(RS,#0) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,#0) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff08ff00) == 0x7d003100) { + // 01111101SSSS0dddEE110001ssssiiii | Rdd = combine(#0,RS) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = combine(#0,%s) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x73003100) { + // 01110011SSSSddddEE110001ssssiiii | Rd = add(RS,n1) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,-1) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x71003100) { + // 01110001SSSSddddEE110001ssssiiii | Rd = add(RS,#1) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,#1) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003100) { + // 011010IIIIIIddddEE110001ssssiiii | Rd = II ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff0ff00) == 0x7a003100) { + // 011110100000ddddEE110001ssssiiii | Rd = n1 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = -1 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x75003100) { + // 01110101SSSSddddEE110001ssssiiii | Rd = sxtb(RS) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxtb(%s) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x74003100) { + // 01110100SSSSddddEE110001ssssiiii | Rd = sxth(RS) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sxth(%s) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x70003100) { + // 01110000SSSSddddEE110001ssssiiii | Rd = RS ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x77003100) { + // 01110111SSSSddddEE110001ssssiiii | Rd = and(RS,#255) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,#255) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0x76003100) { + // 01110110SSSSddddEE110001ssssiiii | Rd = zxth(RS) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = zxth(%s) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfc00ff00) == 0x68003100) { + // 011010IIIIIIddddEE110001ssssiiii | Rd = II ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00000) >> 20); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = %s0x%x ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x8(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xf000f000) == 0x80001000) { + // 1000IIIISSSSddddEE01iiiisssstttt | Rd = memw(RS+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0x90001000) { + // 1001IIIISSSSddddEE01iiiisssstttt | Rd = memub(RS+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0x80000000) { + // 1000IIIISSSSddddEE00iiiisssstttt | Rd = memw(RS+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0x90000000) { + // 1001IIIISSSSddddEE00iiiisssstttt | Rd = memub(RS+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0x9(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xfffff000) == 0x9f003000) { + // 1001111100000000EE11iiiisssstttt | deallocframe ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x90003000) { + // 10010IIISSSSddddEE11iiiisssstttt | Rd = memb(RS+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x9e003000) { + // 10011110IIIIIdddEE11iiiisssstttt | Rdd = memd(r29+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x80003000) { + // 10000IIISSSSddddEE11iiiisssstttt | Rd = memh(RS+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00f000) == 0x9c003000) { + // 1001110IIIIIddddEE11iiiisssstttt | Rd = memw(r29+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x88003000) { + // 10001IIISSSSddddEE11iiiisssstttt | Rd = memuh(RS+II) ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f403000) { + // 1001111101000000EE11iiiisssstttt | dealloc_return ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f453000) { + // 1001111101000101EE11iiiisssstttt | if (!p0) dealloc_return ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f473000) { + // 1001111101000111EE11iiiisssstttt | if (!p0.new) dealloc_return:nt ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f443000) { + // 1001111101000100EE11iiiisssstttt | if (p0) dealloc_return ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f463000) { + // 1001111101000110EE11iiiisssstttt | if (p0.new) dealloc_return:nt ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f002000) { + // 1001111100000000EE10iiiisssstttt | deallocframe ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x90002000) { + // 10010IIISSSSddddEE10iiiisssstttt | Rd = memb(RS+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f000) == 0x9e002000) { + // 10011110IIIIIdddEE10iiiisssstttt | Rdd = memd(r29+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x80002000) { + // 10000IIISSSSddddEE10iiiisssstttt | Rd = memh(RS+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00f000) == 0x9c002000) { + // 1001110IIIIIddddEE10iiiisssstttt | Rd = memw(r29+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f000) == 0x88002000) { + // 10001IIISSSSddddEE10iiiisssstttt | Rd = memuh(RS+II) ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f402000) { + // 1001111101000000EE10iiiisssstttt | dealloc_return ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f452000) { + // 1001111101000101EE10iiiisssstttt | if (!p0) dealloc_return ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f472000) { + // 1001111101000111EE10iiiisssstttt | if (!p0.new) dealloc_return:nt ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f442000) { + // 1001111101000100EE10iiiisssstttt | if (p0) dealloc_return ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff000) == 0x9f462000) { + // 1001111101000110EE10iiiisssstttt | if (p0.new) dealloc_return:nt ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0xa(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xf000f000) == 0xb0001000) { + // 1011IIIISSSSTTTTEE01iiiisssstttt | memb(RS+II) = RT ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0xa0001000) { + // 1010IIIISSSSTTTTEE01iiiisssstttt | memw(RS+II) = RT ; memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f000) == 0xa0000000) { + // 1010IIIISSSSTTTTEE00iiiisssstttt | memw(RS+II) = RT ; memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf00) >> 8) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0xb(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf000fe0f) == 0xb0003c00) { + // 1011IIIIssssttttEE11110iiiii0000 | memb(Rs+II) = Rt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe0f) == 0xa0003c00) { + // 1010IIIIssssttttEE11110iiiii0000 | memw(Rs+II) = Rt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003200) { + // 1011IIIISSSSttttEE110010ssssiiii | memb(RS+II) = Rt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003200) { + // 1010IIIISSSSttttEE110010ssssiiii | memw(RS+II) = Rt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003300) { + // 1011IIIISSSSttttEE110011ssssiiii | memb(RS+II) = Rt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003300) { + // 1010IIIISSSSttttEE110011ssssiiii | memw(RS+II) = Rt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xb0002a00) { + // 1011IIIIssssTTTTEE10101iiiiiittt | memb(Rs+II) = RT ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xa0002a00) { + // 1010IIIIssssTTTTEE10101iiiiiittt | memw(Rs+II) = RT ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0xb0002000) { + // 1011IIIISSSSTTTTEE100iiisssstttt | memb(RS+II) = RT ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0xa0002000) { + // 1010IIIISSSSTTTTEE100iiisssstttt | memw(RS+II) = RT ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xb0002800) { + // 1011IIIIssssTTTTEE10100iiiiitttt | memb(Rs+II) = RT ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xa0002800) { + // 1010IIIIssssTTTTEE10100iiiiitttt | memw(Rs+II) = RT ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003000) { + // 1011IIIISSSSttttEE110000ssssiiii | memb(RS+II) = Rt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003000) { + // 1010IIIISSSSttttEE110000ssssiiii | memw(RS+II) = Rt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xb0003100) { + // 1011IIIISSSSttttEE110001ssssiiii | memb(RS+II) = Rt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xa0003100) { + // 1010IIIISSSSttttEE110001ssssiiii | memw(RS+II) = Rt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0xc(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf000fe0f) == 0xc0001c00) { + // 1100IIIIssssddddEE01110iiiii0000 | Rd = memw(Rs+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe0f) == 0xd0001c00) { + // 1101IIIIssssddddEE01110iiiii0000 | Rd = memub(Rs+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001200) { + // 1100IIIISSSSddddEE010010ssssiiii | Rd = memw(RS+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001200) { + // 1101IIIISSSSddddEE010010ssssiiii | Rd = memub(RS+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001300) { + // 1100IIIISSSSddddEE010011ssssiiii | Rd = memw(RS+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001300) { + // 1101IIIISSSSddddEE010011ssssiiii | Rd = memub(RS+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xc0000a00) { + // 1100IIIIssssddddEE00101iiiiiittt | Rd = memw(Rs+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xd0000a00) { + // 1101IIIIssssddddEE00101iiiiiittt | Rd = memub(Rs+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0xc0000000) { + // 1100IIIISSSSddddEE000iiisssstttt | Rd = memw(RS+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000f800) == 0xd0000000) { + // 1101IIIISSSSddddEE000iiisssstttt | Rd = memub(RS+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xc0000800) { + // 1100IIIIssssddddEE00100iiiiitttt | Rd = memw(Rs+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000fe00) == 0xd0000800) { + // 1101IIIIssssddddEE00100iiiiitttt | Rd = memub(Rs+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001000) { + // 1100IIIISSSSddddEE010000ssssiiii | Rd = memw(RS+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001000) { + // 1101IIIISSSSddddEE010000ssssiiii | Rd = memub(RS+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xc0001100) { + // 1100IIIISSSSddddEE010001ssssiiii | Rd = memw(RS+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24) << 2; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf000ff00) == 0xd0001100) { + // 1101IIIISSSSddddEE010001ssssiiii | Rd = memub(RS+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0xd(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xfffffe0f) == 0xdf003c00) { + // 1101111100000000EE11110iiiii0000 | deallocframe ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe0f) == 0xd0003c00) { + // 11010IIIssssddddEE11110iiiii0000 | Rd = memb(Rs+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0xde003c00) { + // 11011110IIIIIdddEE11110iiiii0000 | Rdd = memd(r29+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe0f) == 0xc0003c00) { + // 11000IIIssssddddEE11110iiiii0000 | Rd = memh(Rs+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe0f) == 0xdc003c00) { + // 1101110IIIIIddddEE11110iiiii0000 | Rd = memw(r29+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe0f) == 0xc8003c00) { + // 11001IIIssssddddEE11110iiiii0000 | Rd = memuh(Rs+II) ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf403c00) { + // 1101111101000000EE11110iiiii0000 | dealloc_return ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf453c00) { + // 1101111101000101EE11110iiiii0000 | if (!p0) dealloc_return ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf473c00) { + // 1101111101000111EE11110iiiii0000 | if (!p0.new) dealloc_return:nt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf443c00) { + // 1101111101000100EE11110iiiii0000 | if (p0) dealloc_return ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe0f) == 0xdf463c00) { + // 1101111101000110EE11110iiiii0000 | if (p0.new) dealloc_return:nt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf003200) { + // 1101111100000000EE110010ssssiiii | deallocframe ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003200) { + // 11010IIISSSSddddEE110010ssssiiii | Rd = memb(RS+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xde003200) { + // 11011110IIIIIdddEE110010ssssiiii | Rdd = memd(r29+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003200) { + // 11000IIISSSSddddEE110010ssssiiii | Rd = memh(RS+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003200) { + // 1101110IIIIIddddEE110010ssssiiii | Rd = memw(r29+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003200) { + // 11001IIISSSSddddEE110010ssssiiii | Rd = memuh(RS+II) ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf403200) { + // 1101111101000000EE110010ssssiiii | dealloc_return ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf453200) { + // 1101111101000101EE110010ssssiiii | if (!p0) dealloc_return ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf473200) { + // 1101111101000111EE110010ssssiiii | if (!p0.new) dealloc_return:nt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf443200) { + // 1101111101000100EE110010ssssiiii | if (p0) dealloc_return ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf463200) { + // 1101111101000110EE110010ssssiiii | if (p0.new) dealloc_return:nt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf003300) { + // 1101111100000000EE110011ssssiiii | deallocframe ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003300) { + // 11010IIISSSSddddEE110011ssssiiii | Rd = memb(RS+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xde003300) { + // 11011110IIIIIdddEE110011ssssiiii | Rdd = memd(r29+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003300) { + // 11000IIISSSSddddEE110011ssssiiii | Rd = memh(RS+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003300) { + // 1101110IIIIIddddEE110011ssssiiii | Rd = memw(r29+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003300) { + // 11001IIISSSSddddEE110011ssssiiii | Rd = memuh(RS+II) ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf403300) { + // 1101111101000000EE110011ssssiiii | dealloc_return ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf453300) { + // 1101111101000101EE110011ssssiiii | if (!p0) dealloc_return ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf473300) { + // 1101111101000111EE110011ssssiiii | if (!p0.new) dealloc_return:nt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf443300) { + // 1101111101000100EE110011ssssiiii | if (p0) dealloc_return ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf463300) { + // 1101111101000110EE110011ssssiiii | if (p0.new) dealloc_return:nt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf002a00) { + // 1101111100000000EE10101iiiiiittt | deallocframe ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xd0002a00) { + // 11010IIIssssddddEE10101iiiiiittt | Rd = memb(Rs+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0xde002a00) { + // 11011110IIIIIdddEE10101iiiiiittt | Rdd = memd(r29+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xc0002a00) { + // 11000IIIssssddddEE10101iiiiiittt | Rd = memh(Rs+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe00) == 0xdc002a00) { + // 1101110IIIIIddddEE10101iiiiiittt | Rd = memw(r29+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xc8002a00) { + // 11001IIIssssddddEE10101iiiiiittt | Rd = memuh(Rs+II) ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf402a00) { + // 1101111101000000EE10101iiiiiittt | dealloc_return ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf452a00) { + // 1101111101000101EE10101iiiiiittt | if (!p0) dealloc_return ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf472a00) { + // 1101111101000111EE10101iiiiiittt | if (!p0.new) dealloc_return:nt ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf442a00) { + // 1101111101000100EE10101iiiiiittt | if (p0) dealloc_return ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf462a00) { + // 1101111101000110EE10101iiiiiittt | if (p0.new) dealloc_return:nt ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff800) == 0xdf002000) { + // 1101111100000000EE100iiisssstttt | deallocframe ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0xd0002000) { + // 11010IIISSSSddddEE100iiisssstttt | Rd = memb(RS+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00f800) == 0xde002000) { + // 11011110IIIIIdddEE100iiisssstttt | Rdd = memd(r29+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0xc0002000) { + // 11000IIISSSSddddEE100iiisssstttt | Rd = memh(RS+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00f800) == 0xdc002000) { + // 1101110IIIIIddddEE100iiisssstttt | Rd = memw(r29+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0xc8002000) { + // 11001IIISSSSddddEE100iiisssstttt | Rd = memuh(RS+II) ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff800) == 0xdf402000) { + // 1101111101000000EE100iiisssstttt | dealloc_return ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff800) == 0xdf452000) { + // 1101111101000101EE100iiisssstttt | if (!p0) dealloc_return ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff800) == 0xdf472000) { + // 1101111101000111EE100iiisssstttt | if (!p0.new) dealloc_return:nt ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff800) == 0xdf442000) { + // 1101111101000100EE100iiisssstttt | if (p0) dealloc_return ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffff800) == 0xdf462000) { + // 1101111101000110EE100iiisssstttt | if (p0.new) dealloc_return:nt ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf002800) { + // 1101111100000000EE10100iiiiitttt | deallocframe ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xd0002800) { + // 11010IIIssssddddEE10100iiiiitttt | Rd = memb(Rs+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe00) == 0xde002800) { + // 11011110IIIIIdddEE10100iiiiitttt | Rdd = memd(r29+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xc0002800) { + // 11000IIIssssddddEE10100iiiiitttt | Rd = memh(Rs+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe00) == 0xdc002800) { + // 1101110IIIIIddddEE10100iiiiitttt | Rd = memw(r29+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xc8002800) { + // 11001IIIssssddddEE10100iiiiitttt | Rd = memuh(Rs+II) ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf402800) { + // 1101111101000000EE10100iiiiitttt | dealloc_return ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf452800) { + // 1101111101000101EE10100iiiiitttt | if (!p0) dealloc_return ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf472800) { + // 1101111101000111EE10100iiiiitttt | if (!p0.new) dealloc_return:nt ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf442800) { + // 1101111101000100EE10100iiiiitttt | if (p0) dealloc_return ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffffe00) == 0xdf462800) { + // 1101111101000110EE10100iiiiitttt | if (p0.new) dealloc_return:nt ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf003000) { + // 1101111100000000EE110000ssssiiii | deallocframe ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003000) { + // 11010IIISSSSddddEE110000ssssiiii | Rd = memb(RS+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xde003000) { + // 11011110IIIIIdddEE110000ssssiiii | Rdd = memd(r29+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003000) { + // 11000IIISSSSddddEE110000ssssiiii | Rd = memh(RS+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003000) { + // 1101110IIIIIddddEE110000ssssiiii | Rd = memw(r29+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003000) { + // 11001IIISSSSddddEE110000ssssiiii | Rd = memuh(RS+II) ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf403000) { + // 1101111101000000EE110000ssssiiii | dealloc_return ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf453000) { + // 1101111101000101EE110000ssssiiii | if (!p0) dealloc_return ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf473000) { + // 1101111101000111EE110000ssssiiii | if (!p0.new) dealloc_return:nt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf443000) { + // 1101111101000100EE110000ssssiiii | if (p0) dealloc_return ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf463000) { + // 1101111101000110EE110000ssssiiii | if (p0.new) dealloc_return:nt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf003100) { + // 1101111100000000EE110001ssssiiii | deallocframe ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "deallocframe ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xd0003100) { + // 11010IIISSSSddddEE110001ssssiiii | Rd = memb(RS+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24); // II + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xde003100) { + // 11011110IIIIIdddEE110001ssssiiii | Rdd = memd(r29+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Rdd8 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf80000) >> 19) << 3; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(R29+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_double_low8_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc0003100) { + // 11000IIISSSSddddEE110001ssssiiii | Rd = memh(RS+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xdc003100) { + // 1101110IIIIIddddEE110001ssssiiii | Rd = memw(r29+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(R29+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xc8003100) { + // 11001IIISSSSddddEE110001ssssiiii | Rd = memuh(RS+II) ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s0x%x) ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf403100) { + // 1101111101000000EE110001ssssiiii | dealloc_return ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dealloc_return ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf453100) { + // 1101111101000101EE110001ssssiiii | if (!p0) dealloc_return ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0) dealloc_return ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf473100) { + // 1101111101000111EE110001ssssiiii | if (!p0.new) dealloc_return:nt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!P0.new) dealloc_return:nt ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf443100) { + // 1101111101000100EE110001ssssiiii | if (p0) dealloc_return ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0) dealloc_return ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffffff00) == 0xdf463100) { + // 1101111101000110EE110001ssssiiii | if (p0.new) dealloc_return:nt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->duplex = true; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (P0.new) dealloc_return:nt ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_duplex_0xe(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xff00fe0f) == 0xf2001c00) { + // 11110010ssssIIIIEE01110iiiii0000 | memb(Rs+II) = #0 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = #0 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0xf3001c00) { + // 11110011ssssIIIIEE01110iiiii0000 | memb(Rs+II) = #1 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = #1 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe0f) == 0xea001c00) { + // 1110101IIIIIItttEE01110iiiii0000 | memd(r29+II) = Rtt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memd(R29+%s) = %s ; allocframe(%s0x%x)", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe0f) == 0xe0001c00) { + // 11100IIIssssttttEE01110iiiii0000 | memh(Rs+II) = Rt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe0f) == 0xe8001c00) { + // 1110100IIIIIttttEE01110iiiii0000 | memw(r29+II) = Rt ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; allocframe(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0xf0001c00) { + // 11110000ssssIIIIEE01110iiiii0000 | memw(Rs+II) = #0 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #0 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00fe0f) == 0xf1001c00) { + // 11110001ssssIIIIEE01110iiiii0000 | memw(Rs+II) = #1 ; allocframe(Ii) + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #1 ; allocframe(%s0x%x)", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf2001200) { + // 11110010SSSSIIIIEE010010ssssiiii | memb(RS+II) = #0 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = #0 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001200) { + // 1110101IIIIIItttEE010010ssssiiii | memd(r29+II) = Rtt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memd(R29+%s) = %s ; memb(%s+%s0x%x) = #0", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001200) { + // 11100IIISSSSttttEE010010ssssiiii | memh(RS+II) = Rt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001200) { + // 1110100IIIIIttttEE010010ssssiiii | memw(r29+II) = Rt ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; memb(%s+%s0x%x) = #0", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001200) { + // 11110000SSSSIIIIEE010010ssssiiii | memw(RS+II) = #0 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #0 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf1001200) { + // 11110001SSSSIIIIEE010010ssssiiii | memw(RS+II) = #1 ; memb(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #1 ; memb(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf2001300) { + // 11110010SSSSIIIIEE010011ssssiiii | memb(RS+II) = #0 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = #0 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf3001300) { + // 11110011SSSSIIIIEE010011ssssiiii | memb(RS+II) = #1 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16); // II + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = #1 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001300) { + // 1110101IIIIIItttEE010011ssssiiii | memd(r29+II) = Rtt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memd(R29+%s) = %s ; memb(%s+%s0x%x) = #1", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001300) { + // 11100IIISSSSttttEE010011ssssiiii | memh(RS+II) = Rt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001300) { + // 1110100IIIIIttttEE010011ssssiiii | memw(r29+II) = Rt ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; memb(%s+%s0x%x) = #1", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001300) { + // 11110000SSSSIIIIEE010011ssssiiii | memw(RS+II) = #0 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #0 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf1001300) { + // 11110001SSSSIIIIEE010011ssssiiii | memw(RS+II) = #1 ; memb(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0); // Ii + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #1 ; memb(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe00) == 0xea000a00) { + // 1110101IIIIIITTTEE00101iiiiiittt | memd(r29+II) = RTT ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // RTT8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memd(R29+%s) = %s ; memd(R29+%s) = %s", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xe0000a00) { + // 11100IIIssssTTTTEE00101iiiiiittt | memh(Rs+II) = RT ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 8)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memd(R29+%s) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), signed_imm[3], hex_get_general_double_low8_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe00) == 0xe8000a00) { + // 1110100IIIIITTTTEE00101iiiiiittt | memw(r29+II) = RT ; memd(r29+Ii) = Rtt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STORED_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f8) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 8)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Rtt8 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; memd(R29+%s) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_general_double_low8_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800f800) == 0xe0000000) { + // 11100IIISSSSTTTTEE000iiisssstttt | memh(RS+II) = RT ; memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 6; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0x700) >> 8) << 1; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 1; + hi->ops[5].type = HEX_OP_TYPE_REG; + hi->ops[5].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memh(%s+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm, hex_get_general_sub_regs(hi->ops[5].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800fe00) == 0xe0000800) { + // 11100IIIssssTTTTEE00100iiiiitttt | memh(Rs+II) = RT ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memw(R29+%s0x%x) = %s", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_general_sub_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00fe00) == 0xe8000800) { + // 1110100IIIIITTTTEE00100iiiiitttt | memw(r29+II) = RT ; memw(r29+Ii) = Rt + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREW_SP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // RT16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f0) >> 4) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf) >> 0); // Rt16 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; memw(R29+%s0x%x) = %s", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_general_sub_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001000) { + // 1110101IIIIIItttEE010000ssssiiii | memd(r29+II) = Rtt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memd(R29+%s) = %s ; memw(%s+%s0x%x) = #0", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001000) { + // 11100IIISSSSttttEE010000ssssiiii | memh(RS+II) = Rt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001000) { + // 1110100IIIIIttttEE010000ssssiiii | memw(r29+II) = Rt ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; memw(%s+%s0x%x) = #0", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001000) { + // 11110000SSSSIIIIEE010000ssssiiii | memw(RS+II) = #0 ; memw(Rs+Ii) = #0 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #0 ; memw(%s+%s0x%x) = #0", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xea001100) { + // 1110101IIIIIItttEE010001ssssiiii | memd(r29+II) = Rtt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f80000) >> 19) << 3; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + if (rz_asm->immsign && ((st32)hi->ops[0].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[0].op.imm, tmp, 28); + sprintf(signed_imm[0], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[0], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[0].op.imm); + } + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Rtt8 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memd(R29+%s) = %s ; memw(%s+%s0x%x) = #1", signed_imm[0], hex_get_general_double_low8_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf800ff00) == 0xe0001100) { + // 11100IIISSSSttttEE010001ssssiiii | memh(RS+II) = Rt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7000000) >> 24) << 1; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[4].attr = HEX_OP_IMM_SCALED; + hi->ops[4].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), hex_get_general_sub_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe00ff00) == 0xe8001100) { + // 1110100IIIIIttttEE010001ssssiiii | memw(r29+II) = Rt ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x1f00000) >> 20) << 2; // scaled II + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(R29+%s0x%x) = %s ; memw(%s+%s0x%x) = #1", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm, hex_get_general_sub_regs(hi->ops[1].op.reg), hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf0001100) { + // 11110000SSSSIIIIEE010001ssssiiii | memw(RS+II) = #0 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #0 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff00ff00) == 0xf1001100) { + // 11110001SSSSIIIIEE010001ssssiiii | memw(RS+II) = #1 ; memw(Rs+Ii) = #1 + hi->instruction = HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREWI1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->duplex = true; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00000) >> 20); // RS16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0xf0000) >> 16) << 2; // scaled II + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf0) >> 4); // Rs16 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xf) >> 0) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = #1 ; memw(%s+%s0x%x) = #1", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, hex_get_general_sub_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x0(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xf0000000) == 0x0) { + // 0000iiiiiiiiiiiiPPiiiiiiiiiiiiii | immext(Ii) + hi->instruction = HEX_INS_A4_EXT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0xfff0000) >> 2) | (((hi_u32)&0x3fff) >> 0)) << 6; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 6; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "immext(%s0x%x)", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + hex_extend_op(state, &(hi->ops[0]), true, addr); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x0) { + // 0000000000000000PP00000000000000 | + hi->instruction = HEX_INS_INVALID_DECODE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_ILL; + sprintf(hi->mnem_infix, ""); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x1(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xffc03001) == 0x14400000) { + // 0001010001iissssPP00ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14402000) { + // 0001010001iissssPP10ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14401000) { + // 0001010001iissssPP01ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14403000) { + // 0001010001iissssPP11ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14000000) { + // 0001010000iissssPP00ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14002000) { + // 0001010000iissssPP10ttttiiiiiii0 | p0 = cmp.eq(Rs,Rt); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14001000) { + // 0001010000iissssPP01ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14003000) { + // 0001010000iissssPP11ttttiiiiiii0 | p1 = cmp.eq(Rs,Rt); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10400000) { + // 0001000001iissssPP0IIIIIiiiiiii0 | p0 = cmp.eq(Rs,II); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10402000) { + // 0001000001iissssPP1IIIIIiiiiiii0 | p0 = cmp.eq(Rs,II); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12400000) { + // 0001001001iissssPP0IIIIIiiiiiii0 | p1 = cmp.eq(Rs,II); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s0x%x); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12402000) { + // 0001001001iissssPP1IIIIIiiiiiii0 | p1 = cmp.eq(Rs,II); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s0x%x); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10000000) { + // 0001000000iissssPP0IIIIIiiiiiii0 | p0 = cmp.eq(Rs,II); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10002000) { + // 0001000000iissssPP1IIIIIiiiiiii0 | p0 = cmp.eq(Rs,II); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,%s0x%x); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12000000) { + // 0001001000iissssPP0IIIIIiiiiiii0 | p1 = cmp.eq(Rs,II); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s0x%x); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12002000) { + // 0001001000iissssPP1IIIIIiiiiiii0 | p1 = cmp.eq(Rs,II); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,%s0x%x); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11c00000) { + // 0001000111iissssPP000000iiiiiii0 | p0 = cmp.eq(Rs,n1); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,-1); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11c02000) { + // 0001000111iissssPP100000iiiiiii0 | p0 = cmp.eq(Rs,n1); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,-1); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13c00000) { + // 0001001111iissssPP000000iiiiiii0 | p1 = cmp.eq(Rs,n1); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,-1); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13c02000) { + // 0001001111iissssPP100000iiiiiii0 | p1 = cmp.eq(Rs,n1); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,-1); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11800000) { + // 0001000110iissssPP000000iiiiiii0 | p0 = cmp.eq(Rs,n1); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,-1); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11802000) { + // 0001000110iissssPP100000iiiiiii0 | p0 = cmp.eq(Rs,n1); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.eq(%s,-1); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13800000) { + // 0001001110iissssPP000000iiiiiii0 | p1 = cmp.eq(Rs,n1); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,-1); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13802000) { + // 0001001110iissssPP100000iiiiiii0 | p1 = cmp.eq(Rs,n1); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.eq(%s,-1); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14c00000) { + // 0001010011iissssPP00ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14c02000) { + // 0001010011iissssPP10ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14c01000) { + // 0001010011iissssPP01ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14c03000) { + // 0001010011iissssPP11ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14800000) { + // 0001010010iissssPP00ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14802000) { + // 0001010010iissssPP10ttttiiiiiii0 | p0 = cmp.gt(Rs,Rt); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14801000) { + // 0001010010iissssPP01ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x14803000) { + // 0001010010iissssPP11ttttiiiiiii0 | p1 = cmp.gt(Rs,Rt); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10c00000) { + // 0001000011iissssPP0IIIIIiiiiiii0 | p0 = cmp.gt(Rs,II); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s0x%x); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10c02000) { + // 0001000011iissssPP1IIIIIiiiiiii0 | p0 = cmp.gt(Rs,II); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s0x%x); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12c00000) { + // 0001001011iissssPP0IIIIIiiiiiii0 | p1 = cmp.gt(Rs,II); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s0x%x); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12c02000) { + // 0001001011iissssPP1IIIIIiiiiiii0 | p1 = cmp.gt(Rs,II); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s0x%x); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10800000) { + // 0001000010iissssPP0IIIIIiiiiiii0 | p0 = cmp.gt(Rs,II); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s0x%x); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x10802000) { + // 0001000010iissssPP1IIIIIiiiiiii0 | p0 = cmp.gt(Rs,II); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,%s0x%x); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12800000) { + // 0001001010iissssPP0IIIIIiiiiiii0 | p1 = cmp.gt(Rs,II); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s0x%x); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x12802000) { + // 0001001010iissssPP1IIIIIiiiiiii0 | p1 = cmp.gt(Rs,II); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,%s0x%x); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11c00100) { + // 0001000111iissssPP000001iiiiiii0 | p0 = cmp.gt(Rs,n1); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,-1); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11c02100) { + // 0001000111iissssPP100001iiiiiii0 | p0 = cmp.gt(Rs,n1); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,-1); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13c00100) { + // 0001001111iissssPP000001iiiiiii0 | p1 = cmp.gt(Rs,n1); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,-1); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13c02100) { + // 0001001111iissssPP100001iiiiiii0 | p1 = cmp.gt(Rs,n1); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,-1); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11800100) { + // 0001000110iissssPP000001iiiiiii0 | p0 = cmp.gt(Rs,n1); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,-1); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11802100) { + // 0001000110iissssPP100001iiiiiii0 | p0 = cmp.gt(Rs,n1); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gt(%s,-1); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13800100) { + // 0001001110iissssPP000001iiiiiii0 | p1 = cmp.gt(Rs,n1); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,-1); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13802100) { + // 0001001110iissssPP100001iiiiiii0 | p1 = cmp.gt(Rs,n1); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gt(%s,-1); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15400000) { + // 0001010101iissssPP00ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15402000) { + // 0001010101iissssPP10ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15401000) { + // 0001010101iissssPP01ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15403000) { + // 0001010101iissssPP11ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15000000) { + // 0001010100iissssPP00ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15002000) { + // 0001010100iissssPP10ttttiiiiiii0 | p0 = cmp.gtu(Rs,Rt); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15001000) { + // 0001010100iissssPP01ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x15003000) { + // 0001010100iissssPP11ttttiiiiiii0 | p1 = cmp.gtu(Rs,Rt); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf00) >> 8); // Rt16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x11400000) { + // 0001000101iissssPP0IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,II); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s0x%x); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x11402000) { + // 0001000101iissssPP1IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,II); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s0x%x); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x13400000) { + // 0001001101iissssPP0IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,II); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s0x%x); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x13402000) { + // 0001001101iissssPP1IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,II); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s0x%x); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x11000000) { + // 0001000100iissssPP0IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,II); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s0x%x); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x11002000) { + // 0001000100iissssPP1IIIIIiiiiiii0 | p0 = cmp.gtu(Rs,II); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = cmp.gtu(%s,%s0x%x); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x13000000) { + // 0001001100iissssPP0IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,II); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s0x%x); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc02001) == 0x13002000) { + // 0001001100iissssPP1IIIIIiiiiiii0 | p1 = cmp.gtu(Rs,II); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = cmp.gtu(%s,%s0x%x); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00001) == 0x16000000) { + // 0001011000iiddddPPIIIIIIiiiiiii0 | Rd = II ; jump Ii + hi->instruction = HEX_INS_J4_JUMPSETI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "%s = %s0x%x ; jump 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03001) == 0x17000000) { + // 0001011100iissssPP00ddddiiiiiii0 | Rd = Rs ; jump Ii + hi->instruction = HEX_INS_J4_JUMPSETR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf00) >> 8); // Rd16 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "%s = %s ; jump 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), hex_get_general_sub_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11c00300) { + // 0001000111iissssPP000011iiiiiii0 | p0 = tstbit(Rs,#0); if (!p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = tstbit(%s,#0); if (!P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11c02300) { + // 0001000111iissssPP100011iiiiiii0 | p0 = tstbit(Rs,#0); if (!p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = tstbit(%s,#0); if (!P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13c00300) { + // 0001001111iissssPP000011iiiiiii0 | p1 = tstbit(Rs,#0); if (!p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = tstbit(%s,#0); if (!P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13c02300) { + // 0001001111iissssPP100011iiiiiii0 | p1 = tstbit(Rs,#0); if (!p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_FP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = tstbit(%s,#0); if (!P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11800300) { + // 0001000110iissssPP000011iiiiiii0 | p0 = tstbit(Rs,#0); if (p0.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP0_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = tstbit(%s,#0); if (P0.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x11802300) { + // 0001000110iissssPP100011iiiiiii0 | p0 = tstbit(Rs,#0); if (p0.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP0_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P0 = tstbit(%s,#0); if (P0.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13800300) { + // 0001001110iissssPP000011iiiiiii0 | p1 = tstbit(Rs,#0); if (p1.new) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP1_JUMP_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = tstbit(%s,#0); if (P1.new) jump:nt 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc03f01) == 0x13802300) { + // 0001001110iissssPP100011iiiiiii0 | p1 = tstbit(Rs,#0); if (p1.new) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_TP1_JUMP_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xf0000) >> 16); // Rs16 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P1 = tstbit(%s,#0); if (P1.new) jump:t 0x%x", hex_get_general_sub_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x19c00040) { + // 00011001110tttttPP000000010ddddd | Vd.b = vsplat(Rt) + hi->instruction = HEX_INS_V6_LVSPLATB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vsplat(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x19c00020) { + // 00011001110tttttPP000000001ddddd | Vd.h = vsplat(Rt) + hi->instruction = HEX_INS_V6_LVSPLATH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsplat(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x19a00020) { + // 00011001101tttttPP000000001ddddd | Vd = vsplat(Rt) + hi->instruction = HEX_INS_V6_LVSPLATW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsplat(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030000) { + // 00011110tt000011PP0000ss000000dd | Qd = and(Qs,Qt) + hi->instruction = HEX_INS_V6_PRED_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030014) { + // 00011110tt000011PP0000ss000101dd | Qd = and(Qs,!Qt) + hi->instruction = HEX_INS_V6_PRED_AND_N; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,!%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3cfc) == 0x1e030008) { + // 0001111000000011PP0000ss000010dd | Qd = not(Qs) + hi->instruction = HEX_INS_V6_PRED_NOT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = not(%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030004) { + // 00011110tt000011PP0000ss000001dd | Qd = or(Qs,Qt) + hi->instruction = HEX_INS_V6_PRED_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030010) { + // 00011110tt000011PP0000ss000100dd | Qd = or(Qs,!Qt) + hi->instruction = HEX_INS_V6_PRED_OR_N; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,!%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ffc) == 0x19a00044) { + // 00011001101tttttPP000000010001dd | Qd = vsetq(Rt) + hi->instruction = HEX_INS_V6_PRED_SCALAR2; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsetq(%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ffc) == 0x19a0004c) { + // 00011001101tttttPP000000010011dd | Qd = vsetq2(Rt) + hi->instruction = HEX_INS_V6_PRED_SCALAR2V2; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsetq2(%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e03000c) { + // 00011110tt000011PP0000ss000011dd | Qd = xor(Qs,Qt) + hi->instruction = HEX_INS_V6_PRED_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = xor(%s,%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e030018) { + // 00011110tt000011PP0000ss000110dd | Qd.b = vshuffe(Qs.h,Qt.h) + hi->instruction = HEX_INS_V6_SHUFFEQH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vshuffe(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3cfc) == 0x1e03001c) { + // 00011110tt000011PP0000ss000111dd | Qd.h = vshuffe(Qs.w,Qt.w) + hi->instruction = HEX_INS_V6_SHUFFEQW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qs4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xc00000) >> 22); // Qt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vshuffe(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_qr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1f402080) { + // 00011111010vvvvvPP1uuuuu1iiddddd | Vdd.w = v6mpy(Vuu.ub,Vvv.b,Ii):h + hi->instruction = HEX_INS_V6_V6MPYHUBS10; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.w = V6mpy(%s.ub,%s.b,%s0x%x):h", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1f202080) { + // 00011111001vvvvvPP1uuuuu1iixxxxx | Vxx.w += v6mpy(Vuu.ub,Vvv.b,Ii):h + hi->instruction = HEX_INS_V6_V6MPYHUBS10_VXX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.w += V6mpy(%s.ub,%s.b,%s0x%x):h", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1f402000) { + // 00011111010vvvvvPP1uuuuu0iiddddd | Vdd.w = v6mpy(Vuu.ub,Vvv.b,Ii):v + hi->instruction = HEX_INS_V6_V6MPYVUBS10; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.w = V6mpy(%s.ub,%s.b,%s0x%x):v", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1f202000) { + // 00011111001vvvvvPP1uuuuu0iixxxxx | Vxx.w += v6mpy(Vuu.ub,Vvv.b,Ii):v + hi->instruction = HEX_INS_V6_V6MPYVUBS10_VXX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x60) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.w += V6mpy(%s.ub,%s.b,%s0x%x):v", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010080) { + // 0001111000000001PP0uuuuu100ddddd | Vd.b = vabs(Vu.b) + hi->instruction = HEX_INS_V6_VABSB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vabs(%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0100a0) { + // 0001111000000001PP0uuuuu101ddddd | Vd.b = vabs(Vu.b):sat + hi->instruction = HEX_INS_V6_VABSB_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vabs(%s.b):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00020) { + // 00011100110vvvvvPP0uuuuu001ddddd | Vd.uh = vabsdiff(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VABSDIFFH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vabsdiff(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00000) { + // 00011100110vvvvvPP0uuuuu000ddddd | Vd.ub = vabsdiff(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VABSDIFFUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vabsdiff(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00040) { + // 00011100110vvvvvPP0uuuuu010ddddd | Vd.uh = vabsdiff(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VABSDIFFUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vabsdiff(%s.uh,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00060) { + // 00011100110vvvvvPP0uuuuu011ddddd | Vd.uw = vabsdiff(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VABSDIFFW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vabsdiff(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000000) { + // 0001111000000000PP0uuuuu000ddddd | Vd.h = vabs(Vu.h) + hi->instruction = HEX_INS_V6_VABSH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vabs(%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000020) { + // 0001111000000000PP0uuuuu001ddddd | Vd.h = vabs(Vu.h):sat + hi->instruction = HEX_INS_V6_VABSH_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vabs(%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000040) { + // 0001111000000000PP0uuuuu010ddddd | Vd.w = vabs(Vu.w) + hi->instruction = HEX_INS_V6_VABSW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vabs(%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000060) { + // 0001111000000000PP0uuuuu011ddddd | Vd.w = vabs(Vu.w):sat + hi->instruction = HEX_INS_V6_VABSW_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vabs(%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa000c0) { + // 00011111101vvvvvPP0uuuuu110ddddd | Vd.b = vadd(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VADDB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vadd(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600080) { + // 00011100011vvvvvPP0uuuuu100ddddd | Vdd.b = vadd(Vuu.b,Vvv.b) + hi->instruction = HEX_INS_V6_VADDB_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vadd(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012060) { + // 00011110vv000001PP1uuuuu011xxxxx | if (!Qv) Vx.b += Vu.b + hi->instruction = HEX_INS_V6_VADDBNQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) %s.b += %s.b", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012000) { + // 00011110vv000001PP1uuuuu000xxxxx | if (Qv) Vx.b += Vu.b + hi->instruction = HEX_INS_V6_VADDBQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) %s.b += %s.b", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000000) { + // 00011111000vvvvvPP0uuuuu000ddddd | Vd.b = vadd(Vu.b,Vv.b):sat + hi->instruction = HEX_INS_V6_VADDBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vadd(%s.b,%s.b):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00000) { + // 00011110101vvvvvPP0uuuuu000ddddd | Vdd.b = vadd(Vuu.b,Vvv.b):sat + hi->instruction = HEX_INS_V6_VADDBSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vadd(%s.b,%s.b):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1ca02000) { + // 00011100101vvvvvPP1uuuuu0xxddddd | Vd.w = vadd(Vu.w,Vv.w,Qx):carry + hi->instruction = HEX_INS_V6_VADDCARRY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Qx4 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.w,%s.w,%s):carry", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_qr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1da02000) { + // 00011101101vvvvvPP1uuuuu0eeddddd | Vd.w,Qe = vadd(Vu.w,Vv.w):carry + hi->instruction = HEX_INS_V6_VADDCARRYO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qe4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w,%s = vadd(%s.w,%s.w):carry", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1d802000) { + // 00011101100vvvvvPP1uuuuu0ssddddd | Vd.w = vadd(Vu.w,Vv.w,Qs):carry:sat + hi->instruction = HEX_INS_V6_VADDCARRYSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.w,%s.w,%s):carry:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_qr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002000) { + // 00011111000vvvvvPP1uuuuu000ddddd | Vd.h = vadd(vclb(Vu.h),Vv.h) + hi->instruction = HEX_INS_V6_VADDCLBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vadd(vclb(%s.h),%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002020) { + // 00011111000vvvvvPP1uuuuu001ddddd | Vd.w = vadd(vclb(Vu.w),Vv.w) + hi->instruction = HEX_INS_V6_VADDCLBW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(vclb(%s.w),%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa000e0) { + // 00011111101vvvvvPP0uuuuu111ddddd | Vd.h = vadd(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VADDH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vadd(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c6000a0) { + // 00011100011vvvvvPP0uuuuu101ddddd | Vdd.h = vadd(Vuu.h,Vvv.h) + hi->instruction = HEX_INS_V6_VADDH_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vadd(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012080) { + // 00011110vv000001PP1uuuuu100xxxxx | if (!Qv) Vx.h += Vu.h + hi->instruction = HEX_INS_V6_VADDHNQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) %s.h += %s.h", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012020) { + // 00011110vv000001PP1uuuuu001xxxxx | if (Qv) Vx.h += Vu.h + hi->instruction = HEX_INS_V6_VADDHQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) %s.h += %s.h", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400060) { + // 00011100010vvvvvPP0uuuuu011ddddd | Vd.h = vadd(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VADDHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vadd(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800020) { + // 00011100100vvvvvPP0uuuuu001ddddd | Vdd.h = vadd(Vuu.h,Vvv.h):sat + hi->instruction = HEX_INS_V6_VADDHSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vadd(%s.h,%s.h):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00080) { + // 00011100101vvvvvPP0uuuuu100ddddd | Vdd.w = vadd(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VADDHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202040) { + // 00011100001vvvvvPP1uuuuu010xxxxx | Vxx.w += vadd(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VADDHW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vadd(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00040) { + // 00011100101vvvvvPP0uuuuu010ddddd | Vdd.h = vadd(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VADDUBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vadd(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4020a0) { + // 00011100010vvvvvPP1uuuuu101xxxxx | Vxx.h += vadd(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VADDUBH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vadd(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400020) { + // 00011100010vvvvvPP0uuuuu001ddddd | Vd.ub = vadd(Vu.ub,Vv.ub):sat + hi->instruction = HEX_INS_V6_VADDUBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vadd(%s.ub,%s.ub):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c6000e0) { + // 00011100011vvvvvPP0uuuuu111ddddd | Vdd.ub = vadd(Vuu.ub,Vvv.ub):sat + hi->instruction = HEX_INS_V6_VADDUBSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vadd(%s.ub,%s.ub):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00080) { + // 00011110101vvvvvPP0uuuuu100ddddd | Vd.ub = vadd(Vu.ub,Vv.b):sat + hi->instruction = HEX_INS_V6_VADDUBUBB_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vadd(%s.ub,%s.b):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400040) { + // 00011100010vvvvvPP0uuuuu010ddddd | Vd.uh = vadd(Vu.uh,Vv.uh):sat + hi->instruction = HEX_INS_V6_VADDUHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vadd(%s.uh,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800000) { + // 00011100100vvvvvPP0uuuuu000ddddd | Vdd.uh = vadd(Vuu.uh,Vvv.uh):sat + hi->instruction = HEX_INS_V6_VADDUHSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vadd(%s.uh,%s.uh):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00060) { + // 00011100101vvvvvPP0uuuuu011ddddd | Vdd.w = vadd(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VADDUHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c402080) { + // 00011100010vvvvvPP1uuuuu100xxxxx | Vxx.w += vadd(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VADDUHW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vadd(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600020) { + // 00011111011vvvvvPP0uuuuu001ddddd | Vd.uw = vadd(Vu.uw,Vv.uw):sat + hi->instruction = HEX_INS_V6_VADDUWSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vadd(%s.uw,%s.uw):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00040) { + // 00011110101vvvvvPP0uuuuu010ddddd | Vdd.uw = vadd(Vuu.uw,Vvv.uw):sat + hi->instruction = HEX_INS_V6_VADDUWSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vadd(%s.uw,%s.uw):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400000) { + // 00011100010vvvvvPP0uuuuu000ddddd | Vd.w = vadd(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VADDW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c6000c0) { + // 00011100011vvvvvPP0uuuuu110ddddd | Vdd.w = vadd(Vuu.w,Vvv.w) + hi->instruction = HEX_INS_V6_VADDW_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.w,%s.w)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e0120a0) { + // 00011110vv000001PP1uuuuu101xxxxx | if (!Qv) Vx.w += Vu.w + hi->instruction = HEX_INS_V6_VADDWNQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) %s.w += %s.w", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e012040) { + // 00011110vv000001PP1uuuuu010xxxxx | if (Qv) Vx.w += Vu.w + hi->instruction = HEX_INS_V6_VADDWQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) %s.w += %s.w", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c400080) { + // 00011100010vvvvvPP0uuuuu100ddddd | Vd.w = vadd(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VADDWSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.w,%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800040) { + // 00011100100vvvvvPP0uuuuu010ddddd | Vdd.w = vadd(Vuu.w,Vvv.w):sat + hi->instruction = HEX_INS_V6_VADDWSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vadd(%s.w,%s.w):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000000) { + // 00011011vvvvvtttPP0uuuuu000ddddd | Vd = valign(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VALIGNB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = valign(%s,%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x1e202000) { + // 00011110001vvvvvPP1uuuuuiiiddddd | Vd = valign(Vu,Vv,Ii) + hi->instruction = HEX_INS_V6_VALIGNBI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = valign(%s,%s,%s0x%x)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2000a0) { + // 00011100001vvvvvPP0uuuuu101ddddd | Vd = vand(Vu,Vv) + hi->instruction = HEX_INS_V6_VAND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vand(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x19a004a0) { + // 00011001101tttttPP0001uu101ddddd | Vd = vand(!Qu,Rt) + hi->instruction = HEX_INS_V6_VANDNQRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vand(!%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x19602460) { + // 00011001011tttttPP1001uu011xxxxx | Vx |= vand(!Qu,Rt) + hi->instruction = HEX_INS_V6_VANDNQRT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vand(!%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x19a000a0) { + // 00011001101tttttPP0000uu101ddddd | Vd = vand(Qu,Rt) + hi->instruction = HEX_INS_V6_VANDQRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vand(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x19602060) { + // 00011001011tttttPP1000uu011xxxxx | Vx |= vand(Qu,Rt) + hi->instruction = HEX_INS_V6_VANDQRT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Qu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vand(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e032020) { + // 00011110vv000011PP1uuuuu001ddddd | Vd = vand(!Qv,Vu) + hi->instruction = HEX_INS_V6_VANDVNQV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vand(!%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e032000) { + // 00011110vv000011PP1uuuuu000ddddd | Vd = vand(Qv,Vu) + hi->instruction = HEX_INS_V6_VANDVQV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vand(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x19a00048) { + // 00011001101tttttPP0uuuuu010010dd | Qd = vand(Vu,Rt) + hi->instruction = HEX_INS_V6_VANDVRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vand(%s,%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x19602080) { + // 00011001011tttttPP1uuuuu100000xx | Qx |= vand(Vu,Rt) + hi->instruction = HEX_INS_V6_VANDVRT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vand(%s,%s)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19800000) { + // 00011001100tttttPP0uuuuu000ddddd | Vd.h = vasl(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASLH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasl(%s.h,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a020a0) { + // 00011001101tttttPP1uuuuu101xxxxx | Vx.h += vasl(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASLH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vasl(%s.h,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa000a0) { + // 00011111101vvvvvPP0uuuuu101ddddd | Vd.h = vasl(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VASLHV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasl(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x196000e0) { + // 00011001011tttttPP0uuuuu111ddddd | Vd.w = vasl(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASLW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vasl(%s.w,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19602040) { + // 00011001011tttttPP1uuuuu010xxxxx | Vx.w += vasl(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASLW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vasl(%s.w,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00080) { + // 00011111101vvvvvPP0uuuuu100ddddd | Vd.w = vasl(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VASLWV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vasl(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1aa020e0) { + // 00011010101vvvvvPP1uuuuu111xxxxx | Vxx.w = vasrinto(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VASR_INTO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vasrinto(%s.w,%s.w)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x196000c0) { + // 00011001011tttttPP0uuuuu110ddddd | Vd.h = vasr(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASRH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasr(%s.h,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x198020e0) { + // 00011001100tttttPP1uuuuu111xxxxx | Vx.h += vasr(Vu.h,Rt) + hi->instruction = HEX_INS_V6_VASRH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vasr(%s.h,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002000) { + // 00011011vvvvvtttPP1uuuuu000ddddd | Vd.b = vasr(Vu.h,Vv.h,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRHBRNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vasr(%s.h,%s.h,%s):rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x18000000) { + // 00011000vvvvvtttPP0uuuuu000ddddd | Vd.b = vasr(Vu.h,Vv.h,Rt):sat + hi->instruction = HEX_INS_V6_VASRHBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vasr(%s.h,%s.h,%s):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0000e0) { + // 00011011vvvvvtttPP0uuuuu111ddddd | Vd.ub = vasr(Vu.h,Vv.h,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRHUBRNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vasr(%s.h,%s.h,%s):rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0000c0) { + // 00011011vvvvvtttPP0uuuuu110ddddd | Vd.ub = vasr(Vu.h,Vv.h,Rt):sat + hi->instruction = HEX_INS_V6_VASRHUBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vasr(%s.h,%s.h,%s):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00060) { + // 00011111101vvvvvPP0uuuuu011ddddd | Vd.h = vasr(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VASRHV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasr(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x180000e0) { + // 00011000vvvvvtttPP0uuuuu111ddddd | Vd.ub = vasr(Vu.uh,Vv.uh,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRUHUBRNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vasr(%s.uh,%s.uh,%s):rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x180020a0) { + // 00011000vvvvvtttPP1uuuuu101ddddd | Vd.ub = vasr(Vu.uh,Vv.uh,Rt):sat + hi->instruction = HEX_INS_V6_VASRUHUBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vasr(%s.uh,%s.uh,%s):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x18000020) { + // 00011000vvvvvtttPP0uuuuu001ddddd | Vd.uh = vasr(Vu.uw,Vv.uw,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRUWUHRNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vasr(%s.uw,%s.uw,%s):rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x18002080) { + // 00011000vvvvvtttPP1uuuuu100ddddd | Vd.uh = vasr(Vu.uw,Vv.uw,Rt):sat + hi->instruction = HEX_INS_V6_VASRUWUHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vasr(%s.uw,%s.uw,%s):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x196000a0) { + // 00011001011tttttPP0uuuuu101ddddd | Vd.w = vasr(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASRW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vasr(%s.w,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x196020a0) { + // 00011001011tttttPP1uuuuu101xxxxx | Vx.w += vasr(Vu.w,Rt) + hi->instruction = HEX_INS_V6_VASRW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vasr(%s.w,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000040) { + // 00011011vvvvvtttPP0uuuuu010ddddd | Vd.h = vasr(Vu.w,Vv.w,Rt) + hi->instruction = HEX_INS_V6_VASRWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasr(%s.w,%s.w,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000080) { + // 00011011vvvvvtttPP0uuuuu100ddddd | Vd.h = vasr(Vu.w,Vv.w,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRWHRNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasr(%s.w,%s.w,%s):rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000060) { + // 00011011vvvvvtttPP0uuuuu011ddddd | Vd.h = vasr(Vu.w,Vv.w,Rt):sat + hi->instruction = HEX_INS_V6_VASRWHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vasr(%s.w,%s.w,%s):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x18000040) { + // 00011000vvvvvtttPP0uuuuu010ddddd | Vd.uh = vasr(Vu.w,Vv.w,Rt):rnd:sat + hi->instruction = HEX_INS_V6_VASRWUHRNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vasr(%s.w,%s.w,%s):rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0000a0) { + // 00011011vvvvvtttPP0uuuuu101ddddd | Vd.uh = vasr(Vu.w,Vv.w,Rt):sat + hi->instruction = HEX_INS_V6_VASRWUHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vasr(%s.w,%s.w,%s):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00000) { + // 00011111101vvvvvPP0uuuuu000ddddd | Vd.w = vasr(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VASRWV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vasr(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0320e0) { + // 0001111000000011PP1uuuuu111ddddd | Vd = Vu + hi->instruction = HEX_INS_V6_VASSIGN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002080) { + // 00011111000vvvvvPP1uuuuu100ddddd | Vd.b = vavg(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VAVGB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vavg(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0020a0) { + // 00011111000vvvvvPP1uuuuu101ddddd | Vd.b = vavg(Vu.b,Vv.b):rnd + hi->instruction = HEX_INS_V6_VAVGBRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vavg(%s.b,%s.b):rnd", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc000c0) { + // 00011100110vvvvvPP0uuuuu110ddddd | Vd.h = vavg(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VAVGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vavg(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce000a0) { + // 00011100111vvvvvPP0uuuuu101ddddd | Vd.h = vavg(Vu.h,Vv.h):rnd + hi->instruction = HEX_INS_V6_VAVGHRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vavg(%s.h,%s.h):rnd", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc00080) { + // 00011100110vvvvvPP0uuuuu100ddddd | Vd.ub = vavg(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VAVGUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vavg(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00060) { + // 00011100111vvvvvPP0uuuuu011ddddd | Vd.ub = vavg(Vu.ub,Vv.ub):rnd + hi->instruction = HEX_INS_V6_VAVGUBRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vavg(%s.ub,%s.ub):rnd", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc000a0) { + // 00011100110vvvvvPP0uuuuu101ddddd | Vd.uh = vavg(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VAVGUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vavg(%s.uh,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00080) { + // 00011100111vvvvvPP0uuuuu100ddddd | Vd.uh = vavg(Vu.uh,Vv.uh):rnd + hi->instruction = HEX_INS_V6_VAVGUHRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vavg(%s.uh,%s.uh):rnd", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002040) { + // 00011111000vvvvvPP1uuuuu010ddddd | Vd.uw = vavg(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VAVGUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vavg(%s.uw,%s.uw)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f002060) { + // 00011111000vvvvvPP1uuuuu011ddddd | Vd.uw = vavg(Vu.uw,Vv.uw):rnd + hi->instruction = HEX_INS_V6_VAVGUWRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vavg(%s.uw,%s.uw):rnd", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1cc000e0) { + // 00011100110vvvvvPP0uuuuu111ddddd | Vd.w = vavg(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VAVGW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vavg(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce000c0) { + // 00011100111vvvvvPP0uuuuu110ddddd | Vd.w = vavg(Vu.w,Vv.w):rnd + hi->instruction = HEX_INS_V6_VAVGWRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vavg(%s.w,%s.w):rnd", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1a600000) { + // 00011010011vvvvvPP0uuuuu0ssddddd | if (Ps) Vdd = vcombine(Vu,Vv) + hi->instruction = HEX_INS_V6_VCCOMBINE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = vcombine(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0200e0) { + // 0001111000000010PP0uuuuu111ddddd | Vd.uh = vcl0(Vu.uh) + hi->instruction = HEX_INS_V6_VCL0H; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vcl0(%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0200a0) { + // 0001111000000010PP0uuuuu101ddddd | Vd.uw = vcl0(Vu.uw) + hi->instruction = HEX_INS_V6_VCL0W; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vcl0(%s.uw)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff2080) == 0x1a000000) { + // 0001101000000000PP0uuuuu0ssddddd | if (Ps) Vd = Vu + hi->instruction = HEX_INS_V6_VCMOV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f4000e0) { + // 00011111010vvvvvPP0uuuuu111ddddd | Vdd = vcombine(Vu,Vv) + hi->instruction = HEX_INS_V6_VCOMBINE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcombine(%s,%s)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19e02040) { + // 00011001111tttttPP1yyyyy010xxxxx | vdeal(Vy,Vx,Rt) + hi->instruction = HEX_INS_V6_VDEAL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Vy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vdeal(%s,%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0000e0) { + // 0001111000000000PP0uuuuu111ddddd | Vd.b = vdeal(Vu.b) + hi->instruction = HEX_INS_V6_VDEALB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vdeal(%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f2000e0) { + // 00011111001vvvvvPP0uuuuu111ddddd | Vd.b = vdeale(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VDEALB4W; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vdeale(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0000c0) { + // 0001111000000000PP0uuuuu110ddddd | Vd.h = vdeal(Vu.h) + hi->instruction = HEX_INS_V6_VDEALH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vdeal(%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002080) { + // 00011011vvvvvtttPP1uuuuu100ddddd | Vdd = vdeal(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VDEALVDD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdeal(%s,%s,%s)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200020) { + // 00011111001vvvvvPP0uuuuu001ddddd | Vd = vdelta(Vu,Vv) + hi->instruction = HEX_INS_V6_VDELTA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdelta(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x190000c0) { + // 00011001000tttttPP0uuuuu110ddddd | Vd.h = vdmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vdmpy(%s.ub,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x190020c0) { + // 00011001000tttttPP1uuuuu110xxxxx | Vx.h += vdmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vdmpy(%s.ub,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x190000e0) { + // 00011001000tttttPP0uuuuu111ddddd | Vdd.h = vdmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vdmpy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x190020e0) { + // 00011001000tttttPP1uuuuu111xxxxx | Vxx.h += vdmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYBUS_DV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vdmpy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19000040) { + // 00011001000tttttPP0uuuuu010ddddd | Vd.w = vdmpy(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19002060) { + // 00011001000tttttPP1uuuuu011xxxxx | Vx.w += vdmpy(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19200080) { + // 00011001001tttttPP0uuuuu100ddddd | Vdd.w = vdmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19202080) { + // 00011001001tttttPP1uuuuu100xxxxx | Vxx.w += vdmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VDMPYHB_DV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19200060) { + // 00011001001tttttPP0uuuuu011ddddd | Vd.w = vdmpy(Vuu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHISAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19202040) { + // 00011001001tttttPP1uuuuu010xxxxx | Vx.w += vdmpy(Vuu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHISAT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19200040) { + // 00011001001tttttPP0uuuuu010ddddd | Vd.w = vdmpy(Vu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19202060) { + // 00011001001tttttPP1uuuuu011xxxxx | Vx.w += vdmpy(Vu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VDMPYHSAT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19200020) { + // 00011001001tttttPP0uuuuu001ddddd | Vd.w = vdmpy(Vuu.h,Rt.uh,#1):sat + hi->instruction = HEX_INS_V6_VDMPYHSUISAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.uh,#1):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19202020) { + // 00011001001tttttPP1uuuuu001xxxxx | Vx.w += vdmpy(Vuu.h,Rt.uh,#1):sat + hi->instruction = HEX_INS_V6_VDMPYHSUISAT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.uh,#1):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19200000) { + // 00011001001tttttPP0uuuuu000ddddd | Vd.w = vdmpy(Vu.h,Rt.uh):sat + hi->instruction = HEX_INS_V6_VDMPYHSUSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19202000) { + // 00011001001tttttPP1uuuuu000xxxxx | Vx.w += vdmpy(Vu.h,Rt.uh):sat + hi->instruction = HEX_INS_V6_VDMPYHSUSAT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000060) { + // 00011100000vvvvvPP0uuuuu011ddddd | Vd.w = vdmpy(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VDMPYHVSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vdmpy(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002060) { + // 00011100000vvvvvPP1uuuuu011xxxxx | Vx.w += vdmpy(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VDMPYHVSAT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vdmpy(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x190000a0) { + // 00011001000tttttPP0uuuuu101ddddd | Vdd.uw = vdsad(Vuu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VDSADUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vdsad(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19602000) { + // 00011001011tttttPP1uuuuu000xxxxx | Vxx.uw += vdsad(Vuu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VDSADUH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vdsad(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800000) { + // 00011111100vvvvvPP0uuuuu000000dd | Qd = vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.eq(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802000) { + // 00011100100vvvvvPP1uuuuu000000xx | Qx &= vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.eq(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802040) { + // 00011100100vvvvvPP1uuuuu010000xx | Qx |= vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.eq(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802080) { + // 00011100100vvvvvPP1uuuuu100000xx | Qx ^= vcmp.eq(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VEQB_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.eq(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800004) { + // 00011111100vvvvvPP0uuuuu000001dd | Qd = vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.eq(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802004) { + // 00011100100vvvvvPP1uuuuu000001xx | Qx &= vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.eq(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802044) { + // 00011100100vvvvvPP1uuuuu010001xx | Qx |= vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.eq(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802084) { + // 00011100100vvvvvPP1uuuuu100001xx | Qx ^= vcmp.eq(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VEQH_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.eq(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800008) { + // 00011111100vvvvvPP0uuuuu000010dd | Qd = vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.eq(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802008) { + // 00011100100vvvvvPP1uuuuu000010xx | Qx &= vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.eq(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802048) { + // 00011100100vvvvvPP1uuuuu010010xx | Qx |= vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.eq(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802088) { + // 00011100100vvvvvPP1uuuuu100010xx | Qx ^= vcmp.eq(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VEQW_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.eq(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800010) { + // 00011111100vvvvvPP0uuuuu000100dd | Qd = vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.gt(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802010) { + // 00011100100vvvvvPP1uuuuu000100xx | Qx &= vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.gt(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802050) { + // 00011100100vvvvvPP1uuuuu010100xx | Qx |= vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.gt(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802090) { + // 00011100100vvvvvPP1uuuuu100100xx | Qx ^= vcmp.gt(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VGTB_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.gt(%s.b,%s.b)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800014) { + // 00011111100vvvvvPP0uuuuu000101dd | Qd = vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.gt(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802014) { + // 00011100100vvvvvPP1uuuuu000101xx | Qx &= vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.gt(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802054) { + // 00011100100vvvvvPP1uuuuu010101xx | Qx |= vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.gt(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802094) { + // 00011100100vvvvvPP1uuuuu100101xx | Qx ^= vcmp.gt(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VGTH_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.gt(%s.h,%s.h)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800020) { + // 00011111100vvvvvPP0uuuuu001000dd | Qd = vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.gt(%s.ub,%s.ub)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802020) { + // 00011100100vvvvvPP1uuuuu001000xx | Qx &= vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.gt(%s.ub,%s.ub)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802060) { + // 00011100100vvvvvPP1uuuuu011000xx | Qx |= vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.gt(%s.ub,%s.ub)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c8020a0) { + // 00011100100vvvvvPP1uuuuu101000xx | Qx ^= vcmp.gt(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VGTUB_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.gt(%s.ub,%s.ub)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800024) { + // 00011111100vvvvvPP0uuuuu001001dd | Qd = vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.gt(%s.uh,%s.uh)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802024) { + // 00011100100vvvvvPP1uuuuu001001xx | Qx &= vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.gt(%s.uh,%s.uh)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802064) { + // 00011100100vvvvvPP1uuuuu011001xx | Qx |= vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.gt(%s.uh,%s.uh)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c8020a4) { + // 00011100100vvvvvPP1uuuuu101001xx | Qx ^= vcmp.gt(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VGTUH_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.gt(%s.uh,%s.uh)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800028) { + // 00011111100vvvvvPP0uuuuu001010dd | Qd = vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.gt(%s.uw,%s.uw)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802028) { + // 00011100100vvvvvPP1uuuuu001010xx | Qx &= vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.gt(%s.uw,%s.uw)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802068) { + // 00011100100vvvvvPP1uuuuu011010xx | Qx |= vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.gt(%s.uw,%s.uw)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c8020a8) { + // 00011100100vvvvvPP1uuuuu101010xx | Qx ^= vcmp.gt(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VGTUW_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.gt(%s.uw,%s.uw)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1f800018) { + // 00011111100vvvvvPP0uuuuu000110dd | Qd = vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmp.gt(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802018) { + // 00011100100vvvvvPP1uuuuu000110xx | Qx &= vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= vcmp.gt(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802058) { + // 00011100100vvvvvPP1uuuuu010110xx | Qx |= vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= vcmp.gt(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x1c802098) { + // 00011100100vvvvvPP1uuuuu100110xx | Qx ^= vcmp.gt(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VGTW_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Qx4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vcmp.gt(%s.w,%s.w)", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002080) { + // 0001111000000000PP10000010000000 | vhist + hi->instruction = HEX_INS_V6_VHIST; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vhist"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022080) { + // 00011110vv000010PP10000010000000 | vhist(Qv) + hi->instruction = HEX_INS_V6_VHISTQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vhist(%s)", hex_get_hvx_qr(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x19a02020) { + // 00011001101tttttPP100000001xxxxx | Vx.w = vinsert(Rt) + hi->instruction = HEX_INS_V6_VINSERTWR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vinsert(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b000020) { + // 00011011vvvvvtttPP0uuuuu001ddddd | Vd = vlalign(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VLALIGNB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vlalign(%s,%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x1e602000) { + // 00011110011vvvvvPP1uuuuuiiiddddd | Vd = vlalign(Vu,Vv,Ii) + hi->instruction = HEX_INS_V6_VLALIGNBI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = vlalign(%s,%s,%s0x%x)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19800060) { + // 00011001100tttttPP0uuuuu011ddddd | Vd.ub = vlsr(Vu.ub,Rt) + hi->instruction = HEX_INS_V6_VLSRB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vlsr(%s.ub,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19800040) { + // 00011001100tttttPP0uuuuu010ddddd | Vd.uh = vlsr(Vu.uh,Rt) + hi->instruction = HEX_INS_V6_VLSRH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vlsr(%s.uh,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00040) { + // 00011111101vvvvvPP0uuuuu010ddddd | Vd.h = vlsr(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VLSRHV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vlsr(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19800020) { + // 00011001100tttttPP0uuuuu001ddddd | Vd.uw = vlsr(Vu.uw,Rt) + hi->instruction = HEX_INS_V6_VLSRW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vlsr(%s.uw,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fa00020) { + // 00011111101vvvvvPP0uuuuu001ddddd | Vd.w = vlsr(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VLSRWV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vlsr(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19600080) { + // 00011001011tttttPP0uuuuu100ddddd | Vd.h = vlut4(Vu.uh,Rtt.h) + hi->instruction = HEX_INS_V6_VLUT4; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vlut4(%s.uh,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002020) { + // 00011011vvvvvtttPP1uuuuu001ddddd | Vd.b = vlut32(Vu.b,Vv.b,Rt) + hi->instruction = HEX_INS_V6_VLUTVVB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vlut32(%s.b,%s.b,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x18000060) { + // 00011000vvvvvtttPP0uuuuu011ddddd | Vd.b = vlut32(Vu.b,Vv.b,Rt):nomatch + hi->instruction = HEX_INS_V6_VLUTVVB_NM; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vlut32(%s.b,%s.b,%s):nomatch", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0020a0) { + // 00011011vvvvvtttPP1uuuuu101xxxxx | Vx.b |= vlut32(Vu.b,Vv.b,Rt) + hi->instruction = HEX_INS_V6_VLUTVVB_ORACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b |= vlut32(%s.b,%s.b,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x1cc02000) { + // 00011100110vvvvvPP1uuuuuiiixxxxx | Vx.b |= vlut32(Vu.b,Vv.b,Ii) + hi->instruction = HEX_INS_V6_VLUTVVB_ORACCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.b |= vlut32(%s.b,%s.b,%s0x%x)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x1e200000) { + // 00011110001vvvvvPP0uuuuuiiiddddd | Vd.b = vlut32(Vu.b,Vv.b,Ii) + hi->instruction = HEX_INS_V6_VLUTVVBI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.b = vlut32(%s.b,%s.b,%s0x%x)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0020c0) { + // 00011011vvvvvtttPP1uuuuu110ddddd | Vdd.h = vlut16(Vu.b,Vv.h,Rt) + hi->instruction = HEX_INS_V6_VLUTVWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vlut16(%s.b,%s.h,%s)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x18000080) { + // 00011000vvvvvtttPP0uuuuu100ddddd | Vdd.h = vlut16(Vu.b,Vv.h,Rt):nomatch + hi->instruction = HEX_INS_V6_VLUTVWH_NM; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vlut16(%s.b,%s.h,%s):nomatch", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b0020e0) { + // 00011011vvvvvtttPP1uuuuu111xxxxx | Vxx.h |= vlut16(Vu.b,Vv.h,Rt) + hi->instruction = HEX_INS_V6_VLUTVWH_ORACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h |= vlut16(%s.b,%s.h,%s)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x1ce02000) { + // 00011100111vvvvvPP1uuuuuiiixxxxx | Vxx.h |= vlut16(Vu.b,Vv.h,Ii) + hi->instruction = HEX_INS_V6_VLUTVWH_ORACCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.h |= vlut16(%s.b,%s.h,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x1e600000) { + // 00011110011vvvvvPP0uuuuuiiiddddd | Vdd.h = vlut16(Vu.b,Vv.h,Ii) + hi->instruction = HEX_INS_V6_VLUTVWHI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.h = vlut16(%s.b,%s.h,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f2000a0) { + // 00011111001vvvvvPP0uuuuu101ddddd | Vd.b = vmax(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMAXB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vmax(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0000e0) { + // 00011111000vvvvvPP0uuuuu111ddddd | Vd.h = vmax(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMAXH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmax(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0000a0) { + // 00011111000vvvvvPP0uuuuu101ddddd | Vd.ub = vmax(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMAXUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vmax(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0000c0) { + // 00011111000vvvvvPP0uuuuu110ddddd | Vd.uh = vmax(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMAXUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vmax(%s.uh,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200000) { + // 00011111001vvvvvPP0uuuuu000ddddd | Vd.w = vmax(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VMAXW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmax(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200080) { + // 00011111001vvvvvPP0uuuuu100ddddd | Vd.b = vmin(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMINB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vmin(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000060) { + // 00011111000vvvvvPP0uuuuu011ddddd | Vd.h = vmin(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMINH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmin(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000020) { + // 00011111000vvvvvPP0uuuuu001ddddd | Vd.ub = vmin(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMINUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vmin(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000040) { + // 00011111000vvvvvPP0uuuuu010ddddd | Vd.uh = vmin(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMINUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vmin(%s.uh,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f000080) { + // 00011111000vvvvvPP0uuuuu100ddddd | Vd.w = vmin(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VMINW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmin(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x192000c0) { + // 00011001001tttttPP0uuuuu110ddddd | Vdd.h = vmpa(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPABUS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpa(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x192020c0) { + // 00011001001tttttPP1uuuuu110xxxxx | Vxx.h += vmpa(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPABUS_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpa(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200060) { + // 00011100001vvvvvPP0uuuuu011ddddd | Vdd.h = vmpa(Vuu.ub,Vvv.b) + hi->instruction = HEX_INS_V6_VMPABUSV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpa(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19600060) { + // 00011001011tttttPP0uuuuu011ddddd | Vdd.h = vmpa(Vuu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPABUU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpa(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a02080) { + // 00011001101tttttPP1uuuuu100xxxxx | Vxx.h += vmpa(Vuu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPABUU_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpa(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce000e0) { + // 00011100111vvvvvPP0uuuuu111ddddd | Vdd.h = vmpa(Vuu.ub,Vvv.ub) + hi->instruction = HEX_INS_V6_VMPABUUV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpa(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x192000e0) { + // 00011001001tttttPP0uuuuu111ddddd | Vdd.w = vmpa(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPAHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpa(%s.h,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x192020e0) { + // 00011001001tttttPP1uuuuu111xxxxx | Vxx.w += vmpa(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPAHB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpa(%s.h,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19802080) { + // 00011001100tttttPP1uuuuu100xxxxx | Vx.h = vmpa(Vxin.h,Vu.h,Rtt.h):sat + hi->instruction = HEX_INS_V6_VMPAHHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpa(%sin.h,%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x198000a0) { + // 00011001100tttttPP0uuuuu101ddddd | Vdd.w = vmpa(Vuu.uh,Rt.b) + hi->instruction = HEX_INS_V6_VMPAUHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpa(%s.uh,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19802040) { + // 00011001100tttttPP1uuuuu010xxxxx | Vxx.w += vmpa(Vuu.uh,Rt.b) + hi->instruction = HEX_INS_V6_VMPAUHB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpa(%s.uh,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x198020a0) { + // 00011001100tttttPP1uuuuu101xxxxx | Vx.h = vmpa(Vxin.h,Vu.uh,Rtt.uh):sat + hi->instruction = HEX_INS_V6_VMPAUHUHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpa(%sin.h,%s.uh,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x198020c0) { + // 00011001100tttttPP1uuuuu110xxxxx | Vx.h = vmps(Vxin.h,Vu.uh,Rtt.uh):sat + hi->instruction = HEX_INS_V6_VMPSUHUHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32in + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmps(%sin.h,%s.uh,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x192000a0) { + // 00011001001tttttPP0uuuuu101ddddd | Vdd.h = vmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPYBUS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x192020a0) { + // 00011001001tttttPP1uuuuu101xxxxx | Vxx.h += vmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VMPYBUS_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0000c0) { + // 00011100000vvvvvPP0uuuuu110ddddd | Vdd.h = vmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBUSV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0020c0) { + // 00011100000vvvvvPP1uuuuu110xxxxx | Vxx.h += vmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBUSV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000080) { + // 00011100000vvvvvPP0uuuuu100ddddd | Vdd.h = vmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpy(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002080) { + // 00011100000vvvvvPP1uuuuu100xxxxx | Vxx.h += vmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VMPYBV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpy(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe000a0) { + // 00011111111vvvvvPP0uuuuu101ddddd | Vd.w = vmpye(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYEWUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpye(%s.w,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea000c0) { + // 00011110101vvvvvPP0uuuuu110ddddd | Vdd = vmpye(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYEWUH_64; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpye(%s.w,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19400000) { + // 00011001010tttttPP0uuuuu000ddddd | Vdd.w = vmpy(Vu.h,Rt.h) + hi->instruction = HEX_INS_V6_VMPYH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpy(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a020c0) { + // 00011001101tttttPP1uuuuu110xxxxx | Vxx.w += vmpy(Vu.h,Rt.h) + hi->instruction = HEX_INS_V6_VMPYH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpy(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19402000) { + // 00011001010tttttPP1uuuuu000xxxxx | Vxx.w += vmpy(Vu.h,Rt.h):sat + hi->instruction = HEX_INS_V6_VMPYHSAT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpy(%s.h,%s.h):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19400040) { + // 00011001010tttttPP0uuuuu010ddddd | Vd.h = vmpy(Vu.h,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_V6_VMPYHSRS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpy(%s.h,%s.h):<<1:rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19400020) { + // 00011001010tttttPP0uuuuu001ddddd | Vd.h = vmpy(Vu.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_V6_VMPYHSS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpy(%s.h,%s.h):<<1:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200040) { + // 00011100001vvvvvPP0uuuuu010ddddd | Vdd.w = vmpy(Vu.h,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYHUS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpy(%s.h,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202020) { + // 00011100001vvvvvPP1uuuuu001xxxxx | Vxx.w += vmpy(Vu.h,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYHUS_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpy(%s.h,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0000e0) { + // 00011100000vvvvvPP0uuuuu111ddddd | Vdd.w = vmpy(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYHV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpy(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0020e0) { + // 00011100000vvvvvPP1uuuuu111xxxxx | Vxx.w += vmpy(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYHV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpy(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200020) { + // 00011100001vvvvvPP0uuuuu001ddddd | Vd.h = vmpy(Vu.h,Vv.h):<<1:rnd:sat + hi->instruction = HEX_INS_V6_VMPYHVSRS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpy(%s.h,%s.h):<<1:rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600000) { + // 00011111011vvvvvPP0uuuuu000ddddd | Vd.w = vmpyieo(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIEOH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyieo(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c402000) { + // 00011100010vvvvvPP1uuuuu000xxxxx | Vx.w += vmpyie(Vu.w,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIEWH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyie(%s.w,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00000) { + // 00011111110vvvvvPP0uuuuu000ddddd | Vd.w = vmpyie(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYIEWUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyie(%s.w,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2020a0) { + // 00011100001vvvvvPP1uuuuu101xxxxx | Vx.w += vmpyie(Vu.w,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYIEWUH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyie(%s.w,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200080) { + // 00011100001vvvvvPP0uuuuu100ddddd | Vd.h = vmpyi(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpyi(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202080) { + // 00011100001vvvvvPP1uuuuu100xxxxx | Vx.h += vmpyi(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpyi(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19600000) { + // 00011001011tttttPP0uuuuu000ddddd | Vd.h = vmpyi(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vmpyi(%s.h,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19602020) { + // 00011001011tttttPP1uuuuu001xxxxx | Vx.h += vmpyi(Vu.h,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIHB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += vmpyi(%s.h,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00020) { + // 00011111110vvvvvPP0uuuuu001ddddd | Vd.w = vmpyio(Vu.w,Vv.h) + hi->instruction = HEX_INS_V6_VMPYIOWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyio(%s.w,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a00000) { + // 00011001101tttttPP0uuuuu000ddddd | Vd.w = vmpyi(Vu.w,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIWB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyi(%s.w,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19402040) { + // 00011001010tttttPP1uuuuu010xxxxx | Vx.w += vmpyi(Vu.w,Rt.b) + hi->instruction = HEX_INS_V6_VMPYIWB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyi(%s.w,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x198000e0) { + // 00011001100tttttPP0uuuuu111ddddd | Vd.w = vmpyi(Vu.w,Rt.h) + hi->instruction = HEX_INS_V6_VMPYIWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyi(%s.w,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19402060) { + // 00011001010tttttPP1uuuuu011xxxxx | Vx.w += vmpyi(Vu.w,Rt.h) + hi->instruction = HEX_INS_V6_VMPYIWH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyi(%s.w,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x198000c0) { + // 00011001100tttttPP0uuuuu110ddddd | Vd.w = vmpyi(Vu.w,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYIWUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyi(%s.w,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19802020) { + // 00011001100tttttPP1uuuuu001xxxxx | Vx.w += vmpyi(Vu.w,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYIWUB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyi(%s.w,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe000e0) { + // 00011111111vvvvvPP0uuuuu111ddddd | Vd.w = vmpyo(Vu.w,Vv.h):<<1:sat + hi->instruction = HEX_INS_V6_VMPYOWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyo(%s.w,%s.h):<<1:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202060) { + // 00011100001vvvvvPP1uuuuu011xxxxx | Vxx += vmpyo(Vu.w,Vv.h) + hi->instruction = HEX_INS_V6_VMPYOWH_64_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyo(%s.w,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400000) { + // 00011111010vvvvvPP0uuuuu000ddddd | Vd.w = vmpyo(Vu.w,Vv.h):<<1:rnd:sat + hi->instruction = HEX_INS_V6_VMPYOWH_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vmpyo(%s.w,%s.h):<<1:rnd:sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2020e0) { + // 00011100001vvvvvPP1uuuuu111xxxxx | Vx.w += vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift + hi->instruction = HEX_INS_V6_VMPYOWH_RND_SACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyo(%s.w,%s.h):<<1:rnd:sat:shift", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2020c0) { + // 00011100001vvvvvPP1uuuuu110xxxxx | Vx.w += vmpyo(Vu.w,Vv.h):<<1:sat:shift + hi->instruction = HEX_INS_V6_VMPYOWH_SACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vmpyo(%s.w,%s.h):<<1:sat:shift", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19c00000) { + // 00011001110tttttPP0uuuuu000ddddd | Vdd.uh = vmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vmpy(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19802000) { + // 00011001100tttttPP1uuuuu000xxxxx | Vxx.uh += vmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VMPYUB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh += vmpy(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0000a0) { + // 00011100000vvvvvPP0uuuuu101ddddd | Vdd.uh = vmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMPYUBV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vmpy(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c0020a0) { + // 00011100000vvvvvPP1uuuuu101xxxxx | Vxx.uh += vmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VMPYUBV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh += vmpy(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19400060) { + // 00011001010tttttPP0uuuuu011ddddd | Vdd.uw = vmpy(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vmpy(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19402020) { + // 00011001010tttttPP1uuuuu001xxxxx | Vxx.uw += vmpy(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vmpy(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19600040) { + // 00011001011tttttPP0uuuuu010ddddd | Vd.uw = vmpye(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUHE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vmpye(%s.uh,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19802060) { + // 00011001100tttttPP1uuuuu011xxxxx | Vx.uw += vmpye(Vu.uh,Rt.uh) + hi->instruction = HEX_INS_V6_VMPYUHE_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vmpye(%s.uh,%s.uh)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c200000) { + // 00011100001vvvvvPP0uuuuu000ddddd | Vdd.uw = vmpy(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYUHV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vmpy(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c202000) { + // 00011100001vvvvvPP1uuuuu000xxxxx | Vxx.uw += vmpy(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VMPYUHV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vmpy(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1ee02000) { + // 00011110111vvvvvPP1uuuuu0ttddddd | Vd = vmux(Qt,Vu,Vv) + hi->instruction = HEX_INS_V6_VMUX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmux(%s,%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f0020c0) { + // 00011111000vvvvvPP1uuuuu110ddddd | Vd.b = vnavg(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VNAVGB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vnavg(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00020) { + // 00011100111vvvvvPP0uuuuu001ddddd | Vd.h = vnavg(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VNAVGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vnavg(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00000) { + // 00011100111vvvvvPP0uuuuu000ddddd | Vd.b = vnavg(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VNAVGUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vnavg(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ce00040) { + // 00011100111vvvvvPP0uuuuu010ddddd | Vd.w = vnavg(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VNAVGW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vnavg(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1a400000) { + // 00011010010vvvvvPP0uuuuu0ssddddd | if (!Ps) Vdd = vcombine(Vu,Vv) + hi->instruction = HEX_INS_V6_VNCCOMBINE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = vcombine(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff2080) == 0x1a200000) { + // 0001101000100000PP0uuuuu0ssddddd | if (!Ps) Vd = Vu + hi->instruction = HEX_INS_V6_VNCMOV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Ps4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0300a0) { + // 0001111000000011PP0uuuuu101ddddd | Vd.h = vnormamt(Vu.h) + hi->instruction = HEX_INS_V6_VNORMAMTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vnormamt(%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e030080) { + // 0001111000000011PP0uuuuu100ddddd | Vd.w = vnormamt(Vu.w) + hi->instruction = HEX_INS_V6_VNORMAMTW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vnormamt(%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e000080) { + // 0001111000000000PP0uuuuu100ddddd | Vd = vnot(Vu) + hi->instruction = HEX_INS_V6_VNOT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnot(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2000c0) { + // 00011100001vvvvvPP0uuuuu110ddddd | Vd = vor(Vu,Vv) + hi->instruction = HEX_INS_V6_VOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vor(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00040) { + // 00011111110vvvvvPP0uuuuu010ddddd | Vd.b = vpacke(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VPACKEB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vpacke(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00060) { + // 00011111110vvvvvPP0uuuuu011ddddd | Vd.h = vpacke(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VPACKEH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vpacke(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc000c0) { + // 00011111110vvvvvPP0uuuuu110ddddd | Vd.b = vpack(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VPACKHB_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vpack(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc000a0) { + // 00011111110vvvvvPP0uuuuu101ddddd | Vd.ub = vpack(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VPACKHUB_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vpack(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00020) { + // 00011111111vvvvvPP0uuuuu001ddddd | Vd.b = vpacko(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VPACKOB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vpacko(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00040) { + // 00011111111vvvvvPP0uuuuu010ddddd | Vd.h = vpacko(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VPACKOH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vpacko(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00000) { + // 00011111111vvvvvPP0uuuuu000ddddd | Vd.h = vpack(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VPACKWH_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vpack(%s.w,%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc000e0) { + // 00011111110vvvvvPP0uuuuu111ddddd | Vd.uh = vpack(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VPACKWUH_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vpack(%s.w,%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0200c0) { + // 0001111000000010PP0uuuuu110ddddd | Vd.h = vpopcount(Vu.h) + hi->instruction = HEX_INS_V6_VPOPCOUNTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vpopcount(%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fe0) == 0x1e032040) { + // 00011110vv000011PP100000010ddddd | Vd.b = prefixsum(Qv) + hi->instruction = HEX_INS_V6_VPREFIXQB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = prefixsum(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fe0) == 0x1e032140) { + // 00011110vv000011PP100001010ddddd | Vd.h = prefixsum(Qv) + hi->instruction = HEX_INS_V6_VPREFIXQH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = prefixsum(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fe0) == 0x1e032240) { + // 00011110vv000011PP100010010ddddd | Vd.w = prefixsum(Qv) + hi->instruction = HEX_INS_V6_VPREFIXQW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = prefixsum(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200060) { + // 00011111001vvvvvPP0uuuuu011ddddd | Vd = vrdelta(Vu,Vv) + hi->instruction = HEX_INS_V6_VRDELTA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrdelta(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19c000a0) { + // 00011001110tttttPP0uuuuu101ddddd | Vdd.w = vrmpy(Vu.b,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYBUB_RTT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpy(%s.b,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a02000) { + // 00011001101tttttPP1uuuuu000xxxxx | Vxx.w += vrmpy(Vu.b,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYBUB_RTT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpy(%s.b,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19000080) { + // 00011001000tttttPP0uuuuu100ddddd | Vd.w = vrmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYBUS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpy(%s.ub,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x190020a0) { + // 00011001000tttttPP1uuuuu101xxxxx | Vx.w += vrmpy(Vu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYBUS_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpy(%s.ub,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0x19400080) { + // 00011001010tttttPP0uuuuu10iddddd | Vdd.w = vrmpy(Vuu.ub,Rt.b,Ii) + hi->instruction = HEX_INS_V6_VRMPYBUSI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.w = vrmpy(%s.ub,%s.b,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0x19402080) { + // 00011001010tttttPP1uuuuu10ixxxxx | Vxx.w += vrmpy(Vuu.ub,Rt.b,Ii) + hi->instruction = HEX_INS_V6_VRMPYBUSI_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.w += vrmpy(%s.ub,%s.b,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000040) { + // 00011100000vvvvvPP0uuuuu010ddddd | Vd.w = vrmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBUSV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpy(%s.ub,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002040) { + // 00011100000vvvvvPP1uuuuu010xxxxx | Vx.w += vrmpy(Vu.ub,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBUSV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpy(%s.ub,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000020) { + // 00011100000vvvvvPP0uuuuu001ddddd | Vd.w = vrmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpy(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002020) { + // 00011100000vvvvvPP1uuuuu001xxxxx | Vx.w += vrmpy(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VRMPYBV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpy(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19000060) { + // 00011001000tttttPP0uuuuu011ddddd | Vd.uw = vrmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vrmpy(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19002080) { + // 00011001000tttttPP1uuuuu100xxxxx | Vx.uw += vrmpy(Vu.ub,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vrmpy(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19c00080) { + // 00011001110tttttPP0uuuuu100ddddd | Vdd.uw = vrmpy(Vu.ub,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB_RTT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vrmpy(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a020e0) { + // 00011001101tttttPP1uuuuu111xxxxx | Vxx.uw += vrmpy(Vu.ub,Rtt.ub) + hi->instruction = HEX_INS_V6_VRMPYUB_RTT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vrmpy(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0x19a000c0) { + // 00011001101tttttPP0uuuuu11iddddd | Vdd.uw = vrmpy(Vuu.ub,Rt.ub,Ii) + hi->instruction = HEX_INS_V6_VRMPYUBI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.uw = vrmpy(%s.ub,%s.ub,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0x196020c0) { + // 00011001011tttttPP1uuuuu11ixxxxx | Vxx.uw += vrmpy(Vuu.ub,Rt.ub,Ii) + hi->instruction = HEX_INS_V6_VRMPYUBI_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.uw += vrmpy(%s.ub,%s.ub,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c000000) { + // 00011100000vvvvvPP0uuuuu000ddddd | Vd.uw = vrmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VRMPYUBV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vrmpy(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c002000) { + // 00011100000vvvvvPP1uuuuu000xxxxx | Vx.uw += vrmpy(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VRMPYUBV_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw += vrmpy(%s.ub,%s.ub)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19e80000) { + // 0001100111101tttPP0uuuuu000ddddd | Vdddd.w = vrmpyz(Vu.b,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZBB_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpyz(%s.b,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19c02040) { + // 0001100111000tttPP1uuuuu010yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZBB_RT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpyz(%s.b,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19e00000) { + // 0001100111100xxxPP0uuuuu000ddddd | Vdddd.w = vrmpyz(Vu.b,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZBB_RX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpyz(%s.b,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19c82040) { + // 0001100111001xxxPP1uuuuu010yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZBB_RX_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpyz(%s.b,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19f80040) { + // 0001100111111tttPP0uuuuu010ddddd | Vdddd.w = vrmpyz(Vu.b,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpyz(%s.b,%s.ub)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19d02020) { + // 0001100111010tttPP1uuuuu001yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rt.ub) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpyz(%s.b,%s.ub)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19f00040) { + // 0001100111110xxxPP0uuuuu010ddddd | Vdddd.w = vrmpyz(Vu.b,Rx.ub++) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vrmpyz(%s.b,%s.ub++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19d82020) { + // 0001100111011xxxPP1uuuuu001yyyyy | Vyyyy.w += vrmpyz(Vu.b,Rx.ub++) + hi->instruction = HEX_INS_V6_VRMPYZBUB_RX_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vrmpyz(%s.b,%s.ub++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19e80020) { + // 0001100111101tttPP0uuuuu001ddddd | Vdddd.w = vr16mpyz(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCB_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vr16mpyz(%s.c,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19c02060) { + // 0001100111000tttPP1uuuuu011yyyyy | Vyyyy.w += vr16mpyz(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCB_RT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vr16mpyz(%s.c,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19e00020) { + // 0001100111100xxxPP0uuuuu001ddddd | Vdddd.w = vr16mpyz(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCB_RX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vr16mpyz(%s.c,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19c82060) { + // 0001100111001xxxPP1uuuuu011yyyyy | Vyyyy.w += vr16mpyz(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCB_RX_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vr16mpyz(%s.c,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19e80040) { + // 0001100111101tttPP0uuuuu010ddddd | Vdddd.w = vr16mpyzs(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vr16mpyzs(%s.c,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19c02020) { + // 0001100111000tttPP1uuuuu001yyyyy | Vyyyy.w += vr16mpyzs(Vu.c,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vr16mpyzs(%s.c,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19e00040) { + // 0001100111100xxxPP0uuuuu010ddddd | Vdddd.w = vr16mpyzs(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vr16mpyzs(%s.c,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19c82020) { + // 0001100111001xxxPP1uuuuu001yyyyy | Vyyyy.w += vr16mpyzs(Vu.c,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZCBS_RX_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vr16mpyzs(%s.c,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19f80000) { + // 0001100111111tttPP0uuuuu000ddddd | Vdddd.w = vr8mpyz(Vu.n,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZNB_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vr8mpyz(%s.n,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19d02040) { + // 0001100111010tttPP1uuuuu010yyyyy | Vyyyy.w += vr8mpyz(Vu.n,Rt.b) + hi->instruction = HEX_INS_V6_VRMPYZNB_RT_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vr8mpyz(%s.n,%s.b)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19f00000) { + // 0001100111110xxxPP0uuuuu000ddddd | Vdddd.w = vr8mpyz(Vu.n,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZNB_RX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdddd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vr8mpyz(%s.n,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfff820e0) == 0x19d82040) { + // 0001100111011xxxPP1uuuuu010yyyyy | Vyyyy.w += vr8mpyz(Vu.n,Rx.b++) + hi->instruction = HEX_INS_V6_VRMPYZNB_RX_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vyyyy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_QUADRUPLE; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x70000) >> 16); // Rx8 + hi->ops[2].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += vr8mpyz(%s.n,%s.b++)", hex_get_hvx_vqr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs_low8(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19600020) { + // 00011001011tttttPP0uuuuu001ddddd | Vd = vror(Vu,Rt) + hi->instruction = HEX_INS_V6_VROR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vror(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1a8020e0) { + // 00011010100vvvvvPP1uuuuu111ddddd | Vd.uw = vrotr(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VROTR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vrotr(%s.uw,%s.uw)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f6000c0) { + // 00011111011vvvvvPP0uuuuu110ddddd | Vd.b = vround(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VROUNDHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vround(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f6000e0) { + // 00011111011vvvvvPP0uuuuu111ddddd | Vd.ub = vround(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VROUNDHUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vround(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00060) { + // 00011111111vvvvvPP0uuuuu011ddddd | Vd.ub = vround(Vu.uh,Vv.uh):sat + hi->instruction = HEX_INS_V6_VROUNDUHUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vround(%s.uh,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fe00080) { + // 00011111111vvvvvPP0uuuuu100ddddd | Vd.uh = vround(Vu.uw,Vv.uw):sat + hi->instruction = HEX_INS_V6_VROUNDUWUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vround(%s.uw,%s.uw):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600080) { + // 00011111011vvvvvPP0uuuuu100ddddd | Vd.h = vround(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VROUNDWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vround(%s.w,%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f6000a0) { + // 00011111011vvvvvPP0uuuuu101ddddd | Vd.uh = vround(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VROUNDWUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vround(%s.w,%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0x194000c0) { + // 00011001010tttttPP0uuuuu11iddddd | Vdd.uw = vrsad(Vuu.ub,Rt.ub,Ii) + hi->instruction = HEX_INS_V6_VRSADUBI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.uw = vrsad(%s.ub,%s.ub,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0x194020c0) { + // 00011001010tttttPP1uuuuu11ixxxxx | Vxx.uw += vrsad(Vuu.ub,Rt.ub,Ii) + hi->instruction = HEX_INS_V6_VRSADUBI_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x20) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s.uw += vrsad(%s.ub,%s.ub,%s0x%x)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1d8020e0) { + // 00011101100vvvvvPP1uuuuu111ddddd | Vd.w = vsatdw(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VSATDW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsatdw(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600040) { + // 00011111011vvvvvPP0uuuuu010ddddd | Vd.ub = vsat(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSATHUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vsat(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f2000c0) { + // 00011111001vvvvvPP0uuuuu110ddddd | Vd.uh = vsat(Vu.uw,Vv.uw) + hi->instruction = HEX_INS_V6_VSATUWUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vsat(%s.uw,%s.uw)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f600060) { + // 00011111011vvvvvPP0uuuuu011ddddd | Vd.h = vsat(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VSATWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsat(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020060) { + // 0001111000000010PP0uuuuu011ddddd | Vdd.h = vsxt(Vu.b) + hi->instruction = HEX_INS_V6_VSB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsxt(%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020080) { + // 0001111000000010PP0uuuuu100ddddd | Vdd.w = vsxt(Vu.h) + hi->instruction = HEX_INS_V6_VSH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsxt(%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400060) { + // 00011111010vvvvvPP0uuuuu011ddddd | Vd.h = vshuffe(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSHUFEH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vshuffe(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19e02020) { + // 00011001111tttttPP1yyyyy001xxxxx | vshuff(Vy,Vx,Rt) + hi->instruction = HEX_INS_V6_VSHUFF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Vy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vshuff(%s,%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020000) { + // 0001111000000010PP0uuuuu000ddddd | Vd.b = vshuff(Vu.b) + hi->instruction = HEX_INS_V6_VSHUFFB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vshuff(%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400020) { + // 00011111010vvvvvPP0uuuuu001ddddd | Vd.b = vshuffe(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSHUFFEB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vshuffe(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e0100e0) { + // 0001111000000001PP0uuuuu111ddddd | Vd.h = vshuff(Vu.h) + hi->instruction = HEX_INS_V6_VSHUFFH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vshuff(%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400040) { + // 00011111010vvvvvPP0uuuuu010ddddd | Vd.b = vshuffo(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSHUFFOB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vshuffo(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff0020e0) == 0x1b002060) { + // 00011011vvvvvtttPP1uuuuu011ddddd | Vdd = vshuff(Vu,Vv,Rt) + hi->instruction = HEX_INS_V6_VSHUFFVDD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0xf80000) >> 19); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x70000) >> 16); // Rt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vshuff(%s,%s,%s)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_int_regs_low8(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f4000c0) { + // 00011111010vvvvvPP0uuuuu110ddddd | Vdd.b = vshuffoe(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSHUFOEB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vshuffoe(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f4000a0) { + // 00011111010vvvvvPP0uuuuu101ddddd | Vdd.h = vshuffoe(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSHUFOEH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vshuffoe(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f400080) { + // 00011111010vvvvvPP0uuuuu100ddddd | Vd.h = vshuffo(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSHUFOH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vshuffo(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4000a0) { + // 00011100010vvvvvPP0uuuuu101ddddd | Vd.b = vsub(Vu.b,Vv.b) + hi->instruction = HEX_INS_V6_VSUBB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vsub(%s.b,%s.b)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800060) { + // 00011100100vvvvvPP0uuuuu011ddddd | Vdd.b = vsub(Vuu.b,Vvv.b) + hi->instruction = HEX_INS_V6_VSUBB_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vsub(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022020) { + // 00011110vv000010PP1uuuuu001xxxxx | if (!Qv) Vx.b -= Vu.b + hi->instruction = HEX_INS_V6_VSUBBNQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) %s.b -= %s.b", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e0120c0) { + // 00011110vv000001PP1uuuuu110xxxxx | if (Qv) Vx.b -= Vu.b + hi->instruction = HEX_INS_V6_VSUBBQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) %s.b -= %s.b", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1f200040) { + // 00011111001vvvvvPP0uuuuu010ddddd | Vd.b = vsub(Vu.b,Vv.b):sat + hi->instruction = HEX_INS_V6_VSUBBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vsub(%s.b,%s.b):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00020) { + // 00011110101vvvvvPP0uuuuu001ddddd | Vdd.b = vsub(Vuu.b,Vvv.b):sat + hi->instruction = HEX_INS_V6_VSUBBSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.b = vsub(%s.b,%s.b):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1ca02080) { + // 00011100101vvvvvPP1uuuuu1xxddddd | Vd.w = vsub(Vu.w,Vv.w,Qx):carry + hi->instruction = HEX_INS_V6_VSUBCARRY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Qx4 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.w,%s.w,%s):carry", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_qr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1da02080) { + // 00011101101vvvvvPP1uuuuu1eeddddd | Vd.w,Qe = vsub(Vu.w,Vv.w):carry + hi->instruction = HEX_INS_V6_VSUBCARRYO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qe4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w,%s = vsub(%s.w,%s.w):carry", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4000c0) { + // 00011100010vvvvvPP0uuuuu110ddddd | Vd.h = vsub(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSUBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsub(%s.h,%s.h)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c800080) { + // 00011100100vvvvvPP0uuuuu100ddddd | Vdd.h = vsub(Vuu.h,Vvv.h) + hi->instruction = HEX_INS_V6_VSUBH_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsub(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022040) { + // 00011110vv000010PP1uuuuu010xxxxx | if (!Qv) Vx.h -= Vu.h + hi->instruction = HEX_INS_V6_VSUBHNQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) %s.h -= %s.h", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e0120e0) { + // 00011110vv000001PP1uuuuu111xxxxx | if (Qv) Vx.h -= Vu.h + hi->instruction = HEX_INS_V6_VSUBHQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) %s.h -= %s.h", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600040) { + // 00011100011vvvvvPP0uuuuu010ddddd | Vd.h = vsub(Vu.h,Vv.h):sat + hi->instruction = HEX_INS_V6_VSUBHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsub(%s.h,%s.h):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00000) { + // 00011100101vvvvvPP0uuuuu000ddddd | Vdd.h = vsub(Vuu.h,Vvv.h):sat + hi->instruction = HEX_INS_V6_VSUBHSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsub(%s.h,%s.h):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca000e0) { + // 00011100101vvvvvPP0uuuuu111ddddd | Vdd.w = vsub(Vu.h,Vv.h) + hi->instruction = HEX_INS_V6_VSUBHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.h,%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca000a0) { + // 00011100101vvvvvPP0uuuuu101ddddd | Vdd.h = vsub(Vu.ub,Vv.ub) + hi->instruction = HEX_INS_V6_VSUBUBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vsub(%s.ub,%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600000) { + // 00011100011vvvvvPP0uuuuu000ddddd | Vd.ub = vsub(Vu.ub,Vv.ub):sat + hi->instruction = HEX_INS_V6_VSUBUBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vsub(%s.ub,%s.ub):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c8000c0) { + // 00011100100vvvvvPP0uuuuu110ddddd | Vdd.ub = vsub(Vuu.ub,Vvv.ub):sat + hi->instruction = HEX_INS_V6_VSUBUBSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vsub(%s.ub,%s.ub):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea000a0) { + // 00011110101vvvvvPP0uuuuu101ddddd | Vd.ub = vsub(Vu.ub,Vv.b):sat + hi->instruction = HEX_INS_V6_VSUBUBUBB_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.ub = vsub(%s.ub,%s.b):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600020) { + // 00011100011vvvvvPP0uuuuu001ddddd | Vd.uh = vsub(Vu.uh,Vv.uh):sat + hi->instruction = HEX_INS_V6_VSUBUHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vsub(%s.uh,%s.uh):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c8000e0) { + // 00011100100vvvvvPP0uuuuu111ddddd | Vdd.uh = vsub(Vuu.uh,Vvv.uh):sat + hi->instruction = HEX_INS_V6_VSUBUHSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vsub(%s.uh,%s.uh):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca000c0) { + // 00011100101vvvvvPP0uuuuu110ddddd | Vdd.w = vsub(Vu.uh,Vv.uh) + hi->instruction = HEX_INS_V6_VSUBUHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.uh,%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1fc00080) { + // 00011111110vvvvvPP0uuuuu100ddddd | Vd.uw = vsub(Vu.uw,Vv.uw):sat + hi->instruction = HEX_INS_V6_VSUBUWSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vsub(%s.uw,%s.uw):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ea00060) { + // 00011110101vvvvvPP0uuuuu011ddddd | Vdd.uw = vsub(Vuu.uw,Vvv.uw):sat + hi->instruction = HEX_INS_V6_VSUBUWSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vsub(%s.uw,%s.uw):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c4000e0) { + // 00011100010vvvvvPP0uuuuu111ddddd | Vd.w = vsub(Vu.w,Vv.w) + hi->instruction = HEX_INS_V6_VSUBW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.w,%s.w)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c8000a0) { + // 00011100100vvvvvPP0uuuuu101ddddd | Vdd.w = vsub(Vuu.w,Vvv.w) + hi->instruction = HEX_INS_V6_VSUBW_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.w,%s.w)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022060) { + // 00011110vv000010PP1uuuuu011xxxxx | if (!Qv) Vx.w -= Vu.w + hi->instruction = HEX_INS_V6_VSUBWNQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) %s.w -= %s.w", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f20e0) == 0x1e022000) { + // 00011110vv000010PP1uuuuu000xxxxx | if (Qv) Vx.w -= Vu.w + hi->instruction = HEX_INS_V6_VSUBWQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) %s.w -= %s.w", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c600060) { + // 00011100011vvvvvPP0uuuuu011ddddd | Vd.w = vsub(Vu.w,Vv.w):sat + hi->instruction = HEX_INS_V6_VSUBWSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.w,%s.w):sat", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1ca00020) { + // 00011100101vvvvvPP0uuuuu001ddddd | Vdd.w = vsub(Vuu.w,Vvv.w):sat + hi->instruction = HEX_INS_V6_VSUBWSAT_DV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vsub(%s.w,%s.w):sat", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0x1ea02000) { + // 00011110101vvvvvPP1uuuuu0ttddddd | Vdd = vswap(Qt,Vu,Vv) + hi->instruction = HEX_INS_V6_VSWAP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Qt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vswap(%s,%s,%s)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_qr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19000000) { + // 00011001000tttttPP0uuuuu000ddddd | Vdd.h = vtmpy(Vuu.b,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = VTMPy(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19002000) { + // 00011001000tttttPP1uuuuu000xxxxx | Vxx.h += vtmpy(Vuu.b,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += VTMPy(%s.b,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19000020) { + // 00011001000tttttPP0uuuuu001ddddd | Vdd.h = vtmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYBUS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = VTMPy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19002020) { + // 00011001000tttttPP1uuuuu001xxxxx | Vxx.h += vtmpy(Vuu.ub,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYBUS_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h += VTMPy(%s.ub,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19a00080) { + // 00011001101tttttPP0uuuuu100ddddd | Vdd.w = vtmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = VTMPy(%s.h,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x19002040) { + // 00011001000tttttPP1uuuuu010xxxxx | Vxx.w += vtmpy(Vuu.h,Rt.b) + hi->instruction = HEX_INS_V6_VTMPYHB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vuu32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w += VTMPy(%s.h,%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_wr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010040) { + // 0001111000000001PP0uuuuu010ddddd | Vdd.h = vunpack(Vu.b) + hi->instruction = HEX_INS_V6_VUNPACKB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h = vunpack(%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010060) { + // 0001111000000001PP0uuuuu011ddddd | Vdd.w = vunpack(Vu.h) + hi->instruction = HEX_INS_V6_VUNPACKH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w = vunpack(%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e002000) { + // 0001111000000000PP1uuuuu000xxxxx | Vxx.h |= vunpacko(Vu.b) + hi->instruction = HEX_INS_V6_VUNPACKOB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.h |= vunpacko(%s.b)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e002020) { + // 0001111000000000PP1uuuuu001xxxxx | Vxx.w |= vunpacko(Vu.h) + hi->instruction = HEX_INS_V6_VUNPACKOH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.w |= vunpacko(%s.h)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010000) { + // 0001111000000001PP0uuuuu000ddddd | Vdd.uh = vunpack(Vu.ub) + hi->instruction = HEX_INS_V6_VUNPACKUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vunpack(%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e010020) { + // 0001111000000001PP0uuuuu001ddddd | Vdd.uw = vunpack(Vu.uh) + hi->instruction = HEX_INS_V6_VUNPACKUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vunpack(%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002480) { + // 0001111000000000PP10010010000000 | vwhist128 + hi->instruction = HEX_INS_V6_VWHIST128; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vwhist128"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3eff) == 0x1e002680) { + // 0001111000000000PP10011i10000000 | vwhist128(Ii) + hi->instruction = HEX_INS_V6_VWHIST128M; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = (((hi_u32)&0x100) >> 8); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "vwhist128(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022480) { + // 00011110vv000010PP10010010000000 | vwhist128(Qv) + hi->instruction = HEX_INS_V6_VWHIST128Q; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vwhist128(%s)", hex_get_hvx_qr(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3eff) == 0x1e022680) { + // 00011110vv000010PP10011i10000000 | vwhist128(Qv,Ii) + hi->instruction = HEX_INS_V6_VWHIST128QM; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x100) >> 8); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vwhist128(%s,%s0x%x)", hex_get_hvx_qr(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002280) { + // 0001111000000000PP10001010000000 | vwhist256 + hi->instruction = HEX_INS_V6_VWHIST256; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vwhist256"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x1e002380) { + // 0001111000000000PP10001110000000 | vwhist256:sat + hi->instruction = HEX_INS_V6_VWHIST256_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vwhist256:sat"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022280) { + // 00011110vv000010PP10001010000000 | vwhist256(Qv) + hi->instruction = HEX_INS_V6_VWHIST256Q; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vwhist256(%s)", hex_get_hvx_qr(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff3f3fff) == 0x1e022380) { + // 00011110vv000010PP10001110000000 | vwhist256(Qv):sat + hi->instruction = HEX_INS_V6_VWHIST256Q_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0xc00000) >> 22); // Qv4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vwhist256(%s):sat", hex_get_hvx_qr(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x1c2000e0) { + // 00011100001vvvvvPP0uuuuu111ddddd | Vd = vxor(Vu,Vv) + hi->instruction = HEX_INS_V6_VXOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxor(%s,%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020020) { + // 0001111000000010PP0uuuuu001ddddd | Vdd.uh = vzxt(Vu.ub) + hi->instruction = HEX_INS_V6_VZB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uh = vzxt(%s.ub)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e0) == 0x1e020040) { + // 0001111000000010PP0uuuuu010ddddd | Vdd.uw = vzxt(Vu.uh) + hi->instruction = HEX_INS_V6_VZH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.uw = vzxt(%s.uh)", hex_get_hvx_wr(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x19a00120) { + // 00011001101tttttPP000001001ddddd | Vd = zextract(Rt) + hi->instruction = HEX_INS_V6_ZEXTRACT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zextract(%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x2(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffc82001) == 0x20400000) { + // 0010000001ii0sssPP0tttttiiiiiii0 | if (!cmp.eq(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.eq(%s.new,%s)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20402000) { + // 0010000001ii0sssPP1tttttiiiiiii0 | if (!cmp.eq(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.eq(%s.new,%s)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20000000) { + // 0010000000ii0sssPP0tttttiiiiiii0 | if (cmp.eq(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQ_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.eq(%s.new,%s)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20002000) { + // 0010000000ii0sssPP1tttttiiiiiii0 | if (cmp.eq(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQ_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.eq(%s.new,%s)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24400000) { + // 0010010001ii0sssPP0IIIIIiiiiiii0 | if (!cmp.eq(Ns.new,II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.eq(%s.new,%s0x%x)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24402000) { + // 0010010001ii0sssPP1IIIIIiiiiiii0 | if (!cmp.eq(Ns.new,II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.eq(%s.new,%s0x%x)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24000000) { + // 0010010000ii0sssPP0IIIIIiiiiiii0 | if (cmp.eq(Ns.new,II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQI_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.eq(%s.new,%s0x%x)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24002000) { + // 0010010000ii0sssPP1IIIIIiiiiiii0 | if (cmp.eq(Ns.new,II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQI_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.eq(%s.new,%s0x%x)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26400000) { + // 0010011001ii0sssPP000000iiiiiii0 | if (!cmp.eq(Ns.new,n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.eq(%s.new,-1)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26402000) { + // 0010011001ii0sssPP100000iiiiiii0 | if (!cmp.eq(Ns.new,n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.eq(%s.new,-1)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26000000) { + // 0010011000ii0sssPP000000iiiiiii0 | if (cmp.eq(Ns.new,n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPEQN1_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.eq(%s.new,-1)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26002000) { + // 0010011000ii0sssPP100000iiiiiii0 | if (cmp.eq(Ns.new,n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPEQN1_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.eq(%s.new,-1)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20c00000) { + // 0010000011ii0sssPP0tttttiiiiiii0 | if (!cmp.gt(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s.new,%s)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20c02000) { + // 0010000011ii0sssPP1tttttiiiiiii0 | if (!cmp.gt(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s.new,%s)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20800000) { + // 0010000010ii0sssPP0tttttiiiiiii0 | if (cmp.gt(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGT_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s.new,%s)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x20802000) { + // 0010000010ii0sssPP1tttttiiiiiii0 | if (cmp.gt(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGT_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s.new,%s)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24c00000) { + // 0010010011ii0sssPP0IIIIIiiiiiii0 | if (!cmp.gt(Ns.new,II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s.new,%s0x%x)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24c02000) { + // 0010010011ii0sssPP1IIIIIiiiiiii0 | if (!cmp.gt(Ns.new,II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s.new,%s0x%x)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24800000) { + // 0010010010ii0sssPP0IIIIIiiiiiii0 | if (cmp.gt(Ns.new,II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTI_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s.new,%s0x%x)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x24802000) { + // 0010010010ii0sssPP1IIIIIiiiiiii0 | if (cmp.gt(Ns.new,II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTI_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s.new,%s0x%x)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26c00000) { + // 0010011011ii0sssPP000000iiiiiii0 | if (!cmp.gt(Ns.new,n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s.new,-1)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26c02000) { + // 0010011011ii0sssPP100000iiiiiii0 | if (!cmp.gt(Ns.new,n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s.new,-1)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26800000) { + // 0010011010ii0sssPP000000iiiiiii0 | if (cmp.gt(Ns.new,n1)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTN1_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s.new,-1)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x26802000) { + // 0010011010ii0sssPP100000iiiiiii0 | if (cmp.gt(Ns.new,n1)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTN1_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s.new,-1)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21400000) { + // 0010000101ii0sssPP0tttttiiiiiii0 | if (!cmp.gtu(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gtu(%s.new,%s)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21402000) { + // 0010000101ii0sssPP1tttttiiiiiii0 | if (!cmp.gtu(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gtu(%s.new,%s)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21000000) { + // 0010000100ii0sssPP0tttttiiiiiii0 | if (cmp.gtu(Ns.new,Rt)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTU_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gtu(%s.new,%s)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21002000) { + // 0010000100ii0sssPP1tttttiiiiiii0 | if (cmp.gtu(Ns.new,Rt)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTU_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gtu(%s.new,%s)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), hex_get_int_regs(hi->ops[1].op.reg), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x25400000) { + // 0010010101ii0sssPP0IIIIIiiiiiii0 | if (!cmp.gtu(Ns.new,II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gtu(%s.new,%s0x%x)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x25402000) { + // 0010010101ii0sssPP1IIIIIiiiiiii0 | if (!cmp.gtu(Ns.new,II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gtu(%s.new,%s0x%x)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x25000000) { + // 0010010100ii0sssPP0IIIIIiiiiiii0 | if (cmp.gtu(Ns.new,II)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPGTUI_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gtu(%s.new,%s0x%x)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x25002000) { + // 0010010100ii0sssPP1IIIIIiiiiiii0 | if (cmp.gtu(Ns.new,II)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPGTUI_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // II + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gtu(%s.new,%s0x%x)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21c00000) { + // 0010000111ii0sssPP0tttttiiiiiii0 | if (!cmp.gt(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLT_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s,%s.new)) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21c02000) { + // 0010000111ii0sssPP1tttttiiiiiii0 | if (!cmp.gt(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLT_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gt(%s,%s.new)) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21800000) { + // 0010000110ii0sssPP0tttttiiiiiii0 | if (cmp.gt(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLT_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s,%s.new)) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x21802000) { + // 0010000110ii0sssPP1tttttiiiiiii0 | if (cmp.gt(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLT_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gt(%s,%s.new)) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x22400000) { + // 0010001001ii0sssPP0tttttiiiiiii0 | if (!cmp.gtu(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLTU_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gtu(%s,%s.new)) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x22402000) { + // 0010001001ii0sssPP1tttttiiiiiii0 | if (!cmp.gtu(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLTU_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!cmp.gtu(%s,%s.new)) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x22000000) { + // 0010001000ii0sssPP0tttttiiiiiii0 | if (cmp.gtu(Rt,Ns.new)) jump:nt Ii + hi->instruction = HEX_INS_J4_CMPLTU_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gtu(%s,%s.new)) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc82001) == 0x22002000) { + // 0010001000ii0sssPP1tttttiiiiiii0 | if (cmp.gtu(Rt,Ns.new)) jump:t Ii + hi->instruction = HEX_INS_J4_CMPLTU_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[2].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[2].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (cmp.gtu(%s,%s.new)) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x25c00000) { + // 0010010111ii0sssPP000000iiiiiii0 | if (!tstbit(Ns.new,#0)) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_F_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!tstbit(%s.new,#0)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x25c02000) { + // 0010010111ii0sssPP100000iiiiiii0 | if (!tstbit(Ns.new,#0)) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_F_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!tstbit(%s.new,#0)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x25800000) { + // 0010010110ii0sssPP000000iiiiiii0 | if (tstbit(Ns.new,#0)) jump:nt Ii + hi->instruction = HEX_INS_J4_TSTBIT0_T_JUMPNV_NT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (tstbit(%s.new,#0)) jump:nt 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc83f01) == 0x25802000) { + // 0010010110ii0sssPP100000iiiiiii0 | if (tstbit(Ns.new,#0)) jump:t Ii + hi->instruction = HEX_INS_J4_TSTBIT0_T_JUMPNV_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x70000) >> 16); // Ns8 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x300000) >> 13) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (tstbit(%s.new,#0)) jump:t 0x%x", hex_get_int_regs(resolve_n_register(hi->ops[0].op.reg, hi->addr, pkt)), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x280000e0) { + // 00101000000tttttPPi00iii111ddddd | Vd = vmemu(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32UB_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vmemu(%s+%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x290000e0) { + // 00101001000xxxxxPP000iii111ddddd | Vd = vmemu(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32UB_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vmemu(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b0000e0) { + // 00101011000xxxxxPPu00000111ddddd | Vd = vmemu(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32UB_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmemu(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28000000) { + // 00101000000tttttPPi00iii000ddddd | Vd = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vmem(%s+%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28000020) { + // 00101000000tttttPPi00iii001ddddd | Vd.cur = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.cur = vmem(%s+%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x288000a0) { + // 00101000100tttttPPivviii101ddddd | if (!Pv) Vd.cur = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.cur = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x298000a0) { + // 00101001100xxxxxPP0vviii101ddddd | if (!Pv) Vd.cur = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.cur = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b8000a0) { + // 00101011100xxxxxPPuvv000101ddddd | if (!Pv) Vd.cur = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_CUR_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s.cur = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29000020) { + // 00101001000xxxxxPP000iii001ddddd | Vd.cur = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.cur = vmem(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b000020) { + // 00101011000xxxxxPPu00000001ddddd | Vd.cur = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_CUR_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.cur = vmem(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28800080) { + // 00101000100tttttPPivviii100ddddd | if (Pv) Vd.cur = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.cur = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29800080) { + // 00101001100xxxxxPP0vviii100ddddd | if (Pv) Vd.cur = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_CUR_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.cur = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800080) { + // 00101011100xxxxxPPuvv000100ddddd | if (Pv) Vd.cur = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_CUR_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s.cur = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28800060) { + // 00101000100tttttPPivviii011ddddd | if (!Pv) Vd = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29800060) { + // 00101001100xxxxxPP0vviii011ddddd | if (!Pv) Vd = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800060) { + // 00101011100xxxxxPPuvv000011ddddd | if (!Pv) Vd = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28400000) { + // 00101000010tttttPPi00iii000ddddd | Vd = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vmem(%s+%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28400020) { + // 00101000010tttttPPi00iii001ddddd | Vd.cur = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.cur = vmem(%s+%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c000a0) { + // 00101000110tttttPPivviii101ddddd | if (!Pv) Vd.cur = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.cur = vmem(%s+%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c000a0) { + // 00101001110xxxxxPP0vviii101ddddd | if (!Pv) Vd.cur = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.cur = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc000a0) { + // 00101011110xxxxxPPuvv000101ddddd | if (!Pv) Vd.cur = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s.cur = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29400020) { + // 00101001010xxxxxPP000iii001ddddd | Vd.cur = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.cur = vmem(%s++%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b400020) { + // 00101011010xxxxxPPu00000001ddddd | Vd.cur = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.cur = vmem(%s++%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00080) { + // 00101000110tttttPPivviii100ddddd | if (Pv) Vd.cur = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.cur = vmem(%s+%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00080) { + // 00101001110xxxxxPP0vviii100ddddd | if (Pv) Vd.cur = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.cur = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00080) { + // 00101011110xxxxxPPuvv000100ddddd | if (Pv) Vd.cur = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_CUR_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s.cur = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00060) { + // 00101000110tttttPPivviii011ddddd | if (!Pv) Vd = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = vmem(%s+%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00060) { + // 00101001110xxxxxPP0vviii011ddddd | if (!Pv) Vd = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00060) { + // 00101011110xxxxxPPuvv000011ddddd | if (!Pv) Vd = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29400000) { + // 00101001010xxxxxPP000iii000ddddd | Vd = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vmem(%s++%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b400000) { + // 00101011010xxxxxPPu00000000ddddd | Vd = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmem(%s++%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00040) { + // 00101000110tttttPPivviii010ddddd | if (Pv) Vd = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = vmem(%s+%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00040) { + // 00101001110xxxxxPP0vviii010ddddd | if (Pv) Vd = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00040) { + // 00101011110xxxxxPPuvv000010ddddd | if (Pv) Vd = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28400040) { + // 00101000010tttttPPi00iii010ddddd | Vd.tmp = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.tmp = vmem(%s+%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c000e0) { + // 00101000110tttttPPivviii111ddddd | if (!Pv) Vd.tmp = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.tmp = vmem(%s+%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c000e0) { + // 00101001110xxxxxPP0vviii111ddddd | if (!Pv) Vd.tmp = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.tmp = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc000e0) { + // 00101011110xxxxxPPuvv000111ddddd | if (!Pv) Vd.tmp = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s.tmp = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29400040) { + // 00101001010xxxxxPP000iii010ddddd | Vd.tmp = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.tmp = vmem(%s++%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b400040) { + // 00101011010xxxxxPPu00000010ddddd | Vd.tmp = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.tmp = vmem(%s++%s):nt", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c000c0) { + // 00101000110tttttPPivviii110ddddd | if (Pv) Vd.tmp = vmem(Rt+Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.tmp = vmem(%s+%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c000c0) { + // 00101001110xxxxxPP0vviii110ddddd | if (Pv) Vd.tmp = vmem(Rx++Ii):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.tmp = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc000c0) { + // 00101011110xxxxxPPuvv000110ddddd | if (Pv) Vd.tmp = vmem(Rx++Mu):nt + hi->instruction = HEX_INS_V6_VL32B_NT_TMP_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s.tmp = vmem(%s++%s):nt", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29000000) { + // 00101001000xxxxxPP000iii000ddddd | Vd = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vmem(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b000000) { + // 00101011000xxxxxPPu00000000ddddd | Vd = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmem(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28800040) { + // 00101000100tttttPPivviii010ddddd | if (Pv) Vd = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29800040) { + // 00101001100xxxxxPP0vviii010ddddd | if (Pv) Vd = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800040) { + // 00101011100xxxxxPPuvv000010ddddd | if (Pv) Vd = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28000040) { + // 00101000000tttttPPi00iii010ddddd | Vd.tmp = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.tmp = vmem(%s+%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x288000e0) { + // 00101000100tttttPPivviii111ddddd | if (!Pv) Vd.tmp = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.tmp = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x298000e0) { + // 00101001100xxxxxPP0vviii111ddddd | if (!Pv) Vd.tmp = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s.tmp = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b8000e0) { + // 00101011100xxxxxPPuvv000111ddddd | if (!Pv) Vd.tmp = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_TMP_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s.tmp = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29000040) { + // 00101001000xxxxxPP000iii010ddddd | Vd.tmp = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s.tmp = vmem(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b000040) { + // 00101011000xxxxxPPu00000010ddddd | Vd.tmp = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_TMP_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s.tmp = vmem(%s++%s)", hex_get_hvx_vr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x288000c0) { + // 00101000100tttttPPivviii110ddddd | if (Pv) Vd.tmp = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.tmp = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x298000c0) { + // 00101001100xxxxxPP0vviii110ddddd | if (Pv) Vd.tmp = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_VL32B_TMP_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[3].op.imm & (1 << 2)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s.tmp = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b8000c0) { + // 00101011100xxxxxPPuvv000110ddddd | if (Pv) Vd.tmp = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_VL32B_TMP_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Vd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s.tmp = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x282000e0) { + // 00101000001tttttPPi00iii111sssss | vmemu(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmemu(%s+%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28a000e0) { + // 00101000101tttttPPivviii111sssss | if (!Pv) vmemu(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmemu(%s+%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29a000e0) { + // 00101001101xxxxxPP0vviii111sssss | if (!Pv) vmemu(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmemu(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba000e0) { + // 00101011101xxxxxPPuvv000111sssss | if (!Pv) vmemu(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32UB_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) vmemu(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x292000e0) { + // 00101001001xxxxxPP000iii111sssss | vmemu(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmemu(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b2000e0) { + // 00101011001xxxxxPPu00000111sssss | vmemu(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vmemu(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28a000c0) { + // 00101000101tttttPPivviii110sssss | if (Pv) vmemu(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmemu(%s+%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29a000c0) { + // 00101001101xxxxxPP0vviii110sssss | if (Pv) vmemu(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmemu(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba000c0) { + // 00101011101xxxxxPPuvv000110sssss | if (Pv) vmemu(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32UB_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) vmemu(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28200000) { + // 00101000001tttttPPi00iii000sssss | vmem(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s+%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018f8) == 0x28200020) { + // 00101000001tttttPPi00iii00100sss | vmem(Rt+Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s+%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000f8) == 0x28a00068) { + // 00101000101tttttPPivviii01101sss | if (!Pv) vmem(Rt+Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s+%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020f8) == 0x29a00068) { + // 00101001101xxxxxPP0vviii01101sss | if (!Pv) vmem(Rx++Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007f8) == 0x2ba00068) { + // 00101011101xxxxxPPuvv00001101sss | if (!Pv) vmem(Rx++Mu) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038f8) == 0x29200020) { + // 00101001001xxxxxPP000iii00100sss | vmem(Rx++Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01ff8) == 0x2b200020) { + // 00101011001xxxxxPPu0000000100sss | vmem(Rx++Mu) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vmem(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000f8) == 0x28a00040) { + // 00101000101tttttPPivviii01000sss | if (Pv) vmem(Rt+Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s+%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020f8) == 0x29a00040) { + // 00101001101xxxxxPP0vviii01000sss | if (Pv) vmem(Rx++Ii) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007f8) == 0x2ba00040) { + // 00101011101xxxxxPPuvv00001000sss | if (Pv) vmem(Rx++Mu) = Os.new + hi->instruction = HEX_INS_V6_VS32B_NEW_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28a00020) { + // 00101000101tttttPPivviii001sssss | if (!Pv) vmem(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s+%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29a00020) { + // 00101001101xxxxxPP0vviii001sssss | if (!Pv) vmem(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba00020) { + // 00101011101xxxxxPPuvv000001sssss | if (!Pv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28800020) { + // 00101000100tttttPPivviii001sssss | if (!Qv) vmem(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NQPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s+%s) = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29800020) { + // 00101001100xxxxxPP0vviii001sssss | if (!Qv) vmem(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_NQPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s) = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800020) { + // 00101011100xxxxxPPuvv000001sssss | if (!Qv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_NQPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s) = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018e0) == 0x28600000) { + // 00101000011tttttPPi00iii000sssss | vmem(Rt+Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s+%s):nt = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018f8) == 0x28600020) { + // 00101000011tttttPPi00iii00100sss | vmem(Rt+Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s+%s):nt = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000f8) == 0x28e00078) { + // 00101000111tttttPPivviii01111sss | if (!Pv) vmem(Rt+Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s+%s):nt = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020f8) == 0x29e00078) { + // 00101001111xxxxxPP0vviii01111sss | if (!Pv) vmem(Rx++Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s):nt = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007f8) == 0x2be00078) { + // 00101011111xxxxxPPuvv00001111sss | if (!Pv) vmem(Rx++Mu):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s):nt = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038f8) == 0x29600020) { + // 00101001011xxxxxPP000iii00100sss | vmem(Rx++Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s++%s):nt = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01ff8) == 0x2b600020) { + // 00101011011xxxxxPPu0000000100sss | vmem(Rx++Mu):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vmem(%s++%s):nt = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000f8) == 0x28e00050) { + // 00101000111tttttPPivviii01010sss | if (Pv) vmem(Rt+Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s+%s):nt = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020f8) == 0x29e00050) { + // 00101001111xxxxxPP0vviii01010sss | if (Pv) vmem(Rx++Ii):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s):nt = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007f8) == 0x2be00050) { + // 00101011111xxxxxPPuvv00001010sss | if (Pv) vmem(Rx++Mu):nt = Os.new + hi->instruction = HEX_INS_V6_VS32B_NT_NEW_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Os8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s):nt = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28e00020) { + // 00101000111tttttPPivviii001sssss | if (!Pv) vmem(Rt+Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s+%s):nt = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29e00020) { + // 00101001111xxxxxPP0vviii001sssss | if (!Pv) vmem(Rx++Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s):nt = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2be00020) { + // 00101011111xxxxxPPuvv000001sssss | if (!Pv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s):nt = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00020) { + // 00101000110tttttPPivviii001sssss | if (!Qv) vmem(Rt+Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NQPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s+%s):nt = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00020) { + // 00101001110xxxxxPP0vviii001sssss | if (!Qv) vmem(Rx++Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NQPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s):nt = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00020) { + // 00101011110xxxxxPPuvv000001sssss | if (!Qv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_NQPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (!%s) vmem(%s++%s):nt = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29600000) { + // 00101001011xxxxxPP000iii000sssss | vmem(Rx++Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s++%s):nt = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b600000) { + // 00101011011xxxxxPPu00000000sssss | vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vmem(%s++%s):nt = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28e00000) { + // 00101000111tttttPPivviii000sssss | if (Pv) vmem(Rt+Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s+%s):nt = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29e00000) { + // 00101001111xxxxxPP0vviii000sssss | if (Pv) vmem(Rx++Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s):nt = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2be00000) { + // 00101011111xxxxxPPuvv000000sssss | if (Pv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s):nt = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28c00000) { + // 00101000110tttttPPivviii000sssss | if (Qv) vmem(Rt+Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_QPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s+%s):nt = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29c00000) { + // 00101001110xxxxxPP0vviii000sssss | if (Qv) vmem(Rx++Ii):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_QPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s):nt = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2bc00000) { + // 00101011110xxxxxPPuvv000000sssss | if (Qv) vmem(Rx++Mu):nt = Vs + hi->instruction = HEX_INS_V6_VS32B_NT_QPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s):nt = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x29200000) { + // 00101001001xxxxxPP000iii000sssss | vmem(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2b200000) { + // 00101011001xxxxxPPu00000000sssss | vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vmem(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28a00000) { + // 00101000101tttttPPivviii000sssss | if (Pv) vmem(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s+%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29a00000) { + // 00101001101xxxxxPP0vviii000sssss | if (Pv) vmem(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2ba00000) { + // 00101011101xxxxxPPuvv000000sssss | if (Pv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x28800000) { + // 00101000100tttttPPivviii000sssss | if (Qv) vmem(Rt+Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_QPRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s+%s) = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x29800000) { + // 00101001100xxxxxPP0vviii000sssss | if (Qv) vmem(Rx++Ii) = Vs + hi->instruction = HEX_INS_V6_VS32B_QPRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s) = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007e0) == 0x2b800000) { + // 00101011100xxxxxPPuvv000000sssss | if (Qv) vmem(Rx++Mu) = Vs + hi->instruction = HEX_INS_V6_VS32B_QPRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Qv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) vmem(%s++%s) = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0x28200028) { + // 00101000001tttttPPi00iii00101000 | vmem(Rt+Ii):scatter_release + hi->instruction = HEX_INS_V6_VS32B_SRLS_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s+%s):scatter_release", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038ff) == 0x29200028) { + // 00101001001xxxxxPP000iii00101000 | vmem(Rx++Ii):scatter_release + hi->instruction = HEX_INS_V6_VS32B_SRLS_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "vmem(%s++%s):scatter_release", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fff) == 0x2b200028) { + // 00101011001xxxxxPPu0000000101000 | vmem(Rx++Mu):scatter_release + hi->instruction = HEX_INS_V6_VS32B_SRLS_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vmem(%s++%s):scatter_release", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2f000100) { + // 00101111000tttttPPu00001000vvvvv | vtmp.h = vgather(Rt,Mu,Vv.h).h + hi->instruction = HEX_INS_V6_VGATHERMH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "VTMP.h = vgather(%s,%s,%s.h).h", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01f80) == 0x2f000500) { + // 00101111000tttttPPu001010ssvvvvv | if (Qs) vtmp.h = vgather(Rt,Mu,Vv.h).h + hi->instruction = HEX_INS_V6_VGATHERMHQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) VTMP.h = vgather(%s,%s,%s.h).h", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2f000200) { + // 00101111000tttttPPu00010000vvvvv | vtmp.h = vgather(Rt,Mu,Vvv.w).h + hi->instruction = HEX_INS_V6_VGATHERMHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "VTMP.h = vgather(%s,%s,%s.w).h", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01f80) == 0x2f000600) { + // 00101111000tttttPPu001100ssvvvvv | if (Qs) vtmp.h = vgather(Rt,Mu,Vvv.w).h + hi->instruction = HEX_INS_V6_VGATHERMHWQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vvv32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) VTMP.h = vgather(%s,%s,%s.w).h", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_wr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x2f000000) { + // 00101111000tttttPPu00000000vvvvv | vtmp.w = vgather(Rt,Mu,Vv.w).w + hi->instruction = HEX_INS_V6_VGATHERMW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "VTMP.w = vgather(%s,%s,%s.w).w", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01f80) == 0x2f000400) { + // 00101111000tttttPPu001000ssvvvvv | if (Qs) vtmp.w = vgather(Rt,Mu,Vv.w).w + hi->instruction = HEX_INS_V6_VGATHERMWQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vv32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) VTMP.w = vgather(%s,%s,%s.w).w", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200020) { + // 00101111001tttttPPuvvvvv001wwwww | vscatter(Rt,Mu,Vv.h).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vscatter(%s,%s,%s.h).h = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x2f2000a0) { + // 00101111001tttttPPuvvvvv101wwwww | vscatter(Rt,Mu,Vv.h).h += Vw + hi->instruction = HEX_INS_V6_VSCATTERMH_ADD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vscatter(%s,%s,%s.h).h += %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0x2f800080) { + // 00101111100tttttPPuvvvvv1sswwwww | if (Qs) vscatter(Rt,Mu,Vv.h).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMHQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) vscatter(%s,%s,%s.h).h = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200040) { + // 00101111001tttttPPuvvvvv010wwwww | vscatter(Rt,Mu,Vvv.w).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vscatter(%s,%s,%s.w).h = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x2f2000c0) { + // 00101111001tttttPPuvvvvv110wwwww | vscatter(Rt,Mu,Vvv.w).h += Vw + hi->instruction = HEX_INS_V6_VSCATTERMHW_ADD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vvv32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vscatter(%s,%s,%s.w).h += %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_wr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0x2fa00000) { + // 00101111101tttttPPuvvvvv0sswwwww | if (Qs) vscatter(Rt,Mu,Vvv.w).h = Vw + hi->instruction = HEX_INS_V6_VSCATTERMHWQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Vvv32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) vscatter(%s,%s,%s.w).h = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_wr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200000) { + // 00101111001tttttPPuvvvvv000wwwww | vscatter(Rt,Mu,Vv.w).w = Vw + hi->instruction = HEX_INS_V6_VSCATTERMW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vscatter(%s,%s,%s.w).w = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x2f200080) { + // 00101111001tttttPPuvvvvv100wwwww | vscatter(Rt,Mu,Vv.w).w += Vw + hi->instruction = HEX_INS_V6_VSCATTERMW_ADD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "vscatter(%s,%s,%s.w).w += %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_hvx_vr(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0x2f800000) { + // 00101111100tttttPPuvvvvv0sswwwww | if (Qs) vscatter(Rt,Mu,Vv.w).w = Vw + hi->instruction = HEX_INS_V6_VSCATTERMWQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Qs4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Vv32 + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Vw32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "if (%s) vscatter(%s,%s,%s.w).w = %s", hex_get_hvx_qr(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg), hex_get_hvx_vr(hi->ops[3].op.reg), hex_get_hvx_vr(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0x2c000000) { + // 00101100000tttttPPi00iii00000000 | z = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_ZLD_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "z = vmem(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038ff) == 0x2d000000) { + // 00101101000xxxxxPP000iii00000000 | z = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_ZLD_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[1].op.imm & (1 << 2)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "z = vmem(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fff) == 0x2d000001) { + // 00101101000xxxxxPPu0000000000001 | z = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_ZLD_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "z = vmem(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0x2c800000) { + // 00101100100tttttPPivviii00000000 | if (Pv) z = vmem(Rt+Ii) + hi->instruction = HEX_INS_V6_ZLD_PRED_AI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 10) | (((hi_u32)&0x700) >> 8)); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) z = vmem(%s+%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x2d800000) { + // 00101101100xxxxxPP0vviii00000000 | if (Pv) z = vmem(Rx++Ii) + hi->instruction = HEX_INS_V6_ZLD_PRED_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x700) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 2)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 2); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) z = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe007ff) == 0x2d800001) { + // 00101101100xxxxxPPuvv00000000001 | if (Pv) z = vmem(Rx++Mu) + hi->instruction = HEX_INS_V6_ZLD_PRED_PPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) z = vmem(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x3(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe02060) == 0x3e000000) { + // 00111110000sssssPP0iiiiii00ttttt | memb(Rs+Ii) += Rt + hi->instruction = HEX_INS_L4_ADD_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) += %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e200000) { + // 00111110001sssssPP0iiiiii00ttttt | memh(Rs+Ii) += Rt + hi->instruction = HEX_INS_L4_ADD_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) += %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e400000) { + // 00111110010sssssPP0iiiiii00ttttt | memw(Rs+Ii) += Rt + hi->instruction = HEX_INS_L4_ADD_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) += %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e000040) { + // 00111110000sssssPP0iiiiii10ttttt | memb(Rs+Ii) &= Rt + hi->instruction = HEX_INS_L4_AND_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) &= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e200040) { + // 00111110001sssssPP0iiiiii10ttttt | memh(Rs+Ii) &= Rt + hi->instruction = HEX_INS_L4_AND_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) &= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e400040) { + // 00111110010sssssPP0iiiiii10ttttt | memw(Rs+Ii) &= Rt + hi->instruction = HEX_INS_L4_AND_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) &= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f000000) { + // 00111111000sssssPP0iiiiii00IIIII | memb(Rs+Ii) += II + hi->instruction = HEX_INS_L4_IADD_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) += %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f200000) { + // 00111111001sssssPP0iiiiii00IIIII | memh(Rs+Ii) += II + hi->instruction = HEX_INS_L4_IADD_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) += %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f400000) { + // 00111111010sssssPP0iiiiii00IIIII | memw(Rs+Ii) += II + hi->instruction = HEX_INS_L4_IADD_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) += %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f000040) { + // 00111111000sssssPP0iiiiii10IIIII | memb(Rs+Ii) = clrbit(II) + hi->instruction = HEX_INS_L4_IAND_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = clrbit(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f200040) { + // 00111111001sssssPP0iiiiii10IIIII | memh(Rs+Ii) = clrbit(II) + hi->instruction = HEX_INS_L4_IAND_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = clrbit(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f400040) { + // 00111111010sssssPP0iiiiii10IIIII | memw(Rs+Ii) = clrbit(II) + hi->instruction = HEX_INS_L4_IAND_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = clrbit(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f000060) { + // 00111111000sssssPP0iiiiii11IIIII | memb(Rs+Ii) = setbit(II) + hi->instruction = HEX_INS_L4_IOR_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = setbit(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f200060) { + // 00111111001sssssPP0iiiiii11IIIII | memh(Rs+Ii) = setbit(II) + hi->instruction = HEX_INS_L4_IOR_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = setbit(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f400060) { + // 00111111010sssssPP0iiiiii11IIIII | memw(Rs+Ii) = setbit(II) + hi->instruction = HEX_INS_L4_IOR_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = setbit(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f000020) { + // 00111111000sssssPP0iiiiii01IIIII | memb(Rs+Ii) -= II + hi->instruction = HEX_INS_L4_ISUB_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) -= %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f200020) { + // 00111111001sssssPP0iiiiii01IIIII | memh(Rs+Ii) -= II + hi->instruction = HEX_INS_L4_ISUB_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) -= %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3f400020) { + // 00111111010sssssPP0iiiiii01IIIII | memw(Rs+Ii) -= II + hi->instruction = HEX_INS_L4_ISUB_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f) >> 0); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) -= %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3a000000) { + // 00111010000sssssPPittttti00ddddd | Rd = memb(Rs+Rt<instruction = HEX_INS_L4_LOADRB_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s<<%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3ac00000) { + // 00111010110sssssPPittttti00ddddd | Rdd = memd(Rs+Rt<instruction = HEX_INS_L4_LOADRD_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s+%s<<%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3a400000) { + // 00111010010sssssPPittttti00ddddd | Rd = memh(Rs+Rt<instruction = HEX_INS_L4_LOADRH_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s<<%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3a800000) { + // 00111010100sssssPPittttti00ddddd | Rd = memw(Rs+Rt<instruction = HEX_INS_L4_LOADRI_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s<<%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3a200000) { + // 00111010001sssssPPittttti00ddddd | Rd = memub(Rs+Rt<instruction = HEX_INS_L4_LOADRUB_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s<<%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3a600000) { + // 00111010011sssssPPittttti00ddddd | Rd = memuh(Rs+Rt<instruction = HEX_INS_L4_LOADRUH_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s<<%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e000060) { + // 00111110000sssssPP0iiiiii11ttttt | memb(Rs+Ii) |= Rt + hi->instruction = HEX_INS_L4_OR_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) |= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e200060) { + // 00111110001sssssPP0iiiiii11ttttt | memh(Rs+Ii) |= Rt + hi->instruction = HEX_INS_L4_OR_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) |= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e400060) { + // 00111110010sssssPP0iiiiii11ttttt | memw(Rs+Ii) |= Rt + hi->instruction = HEX_INS_L4_OR_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) |= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x31000000) { + // 00110001000sssssPPitttttivvddddd | if (!Pv) Rd = memb(Rs+Rt<instruction = HEX_INS_L4_PLOADRBF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memb(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x33000000) { + // 00110011000sssssPPitttttivvddddd | if (!Pv.new) Rd = memb(Rs+Rt<instruction = HEX_INS_L4_PLOADRBFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memb(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x30000000) { + // 00110000000sssssPPitttttivvddddd | if (Pv) Rd = memb(Rs+Rt<instruction = HEX_INS_L4_PLOADRBT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memb(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x32000000) { + // 00110010000sssssPPitttttivvddddd | if (Pv.new) Rd = memb(Rs+Rt<instruction = HEX_INS_L4_PLOADRBTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memb(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x31c00000) { + // 00110001110sssssPPitttttivvddddd | if (!Pv) Rdd = memd(Rs+Rt<instruction = HEX_INS_L4_PLOADRDF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memd(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x33c00000) { + // 00110011110sssssPPitttttivvddddd | if (!Pv.new) Rdd = memd(Rs+Rt<instruction = HEX_INS_L4_PLOADRDFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memd(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x30c00000) { + // 00110000110sssssPPitttttivvddddd | if (Pv) Rdd = memd(Rs+Rt<instruction = HEX_INS_L4_PLOADRDT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memd(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x32c00000) { + // 00110010110sssssPPitttttivvddddd | if (Pv.new) Rdd = memd(Rs+Rt<instruction = HEX_INS_L4_PLOADRDTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memd(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x31400000) { + // 00110001010sssssPPitttttivvddddd | if (!Pv) Rd = memh(Rs+Rt<instruction = HEX_INS_L4_PLOADRHF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x33400000) { + // 00110011010sssssPPitttttivvddddd | if (!Pv.new) Rd = memh(Rs+Rt<instruction = HEX_INS_L4_PLOADRHFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x30400000) { + // 00110000010sssssPPitttttivvddddd | if (Pv) Rd = memh(Rs+Rt<instruction = HEX_INS_L4_PLOADRHT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x32400000) { + // 00110010010sssssPPitttttivvddddd | if (Pv.new) Rd = memh(Rs+Rt<instruction = HEX_INS_L4_PLOADRHTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x31800000) { + // 00110001100sssssPPitttttivvddddd | if (!Pv) Rd = memw(Rs+Rt<instruction = HEX_INS_L4_PLOADRIF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memw(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x33800000) { + // 00110011100sssssPPitttttivvddddd | if (!Pv.new) Rd = memw(Rs+Rt<instruction = HEX_INS_L4_PLOADRIFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memw(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x30800000) { + // 00110000100sssssPPitttttivvddddd | if (Pv) Rd = memw(Rs+Rt<instruction = HEX_INS_L4_PLOADRIT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memw(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x32800000) { + // 00110010100sssssPPitttttivvddddd | if (Pv.new) Rd = memw(Rs+Rt<instruction = HEX_INS_L4_PLOADRITNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memw(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x31200000) { + // 00110001001sssssPPitttttivvddddd | if (!Pv) Rd = memub(Rs+Rt<instruction = HEX_INS_L4_PLOADRUBF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memub(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x33200000) { + // 00110011001sssssPPitttttivvddddd | if (!Pv.new) Rd = memub(Rs+Rt<instruction = HEX_INS_L4_PLOADRUBFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memub(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x30200000) { + // 00110000001sssssPPitttttivvddddd | if (Pv) Rd = memub(Rs+Rt<instruction = HEX_INS_L4_PLOADRUBT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memub(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x32200000) { + // 00110010001sssssPPitttttivvddddd | if (Pv.new) Rd = memub(Rs+Rt<instruction = HEX_INS_L4_PLOADRUBTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memub(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x31600000) { + // 00110001011sssssPPitttttivvddddd | if (!Pv) Rd = memuh(Rs+Rt<instruction = HEX_INS_L4_PLOADRUHF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memuh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x33600000) { + // 00110011011sssssPPitttttivvddddd | if (!Pv.new) Rd = memuh(Rs+Rt<instruction = HEX_INS_L4_PLOADRUHFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memuh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x30600000) { + // 00110000011sssssPPitttttivvddddd | if (Pv) Rd = memuh(Rs+Rt<instruction = HEX_INS_L4_PLOADRUHT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memuh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x32600000) { + // 00110010011sssssPPitttttivvddddd | if (Pv.new) Rd = memuh(Rs+Rt<instruction = HEX_INS_L4_PLOADRUHTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[4].type = HEX_OP_TYPE_IMM; + hi->ops[4].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[4]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[4].imm = hi->ops[4].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memuh(%s+%s<<%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[4].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e000020) { + // 00111110000sssssPP0iiiiii01ttttt | memb(Rs+Ii) -= Rt + hi->instruction = HEX_INS_L4_SUB_MEMOPB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) -= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e200020) { + // 00111110001sssssPP0iiiiii01ttttt | memh(Rs+Ii) -= Rt + hi->instruction = HEX_INS_L4_SUB_MEMOPH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) -= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02060) == 0x3e400020) { + // 00111110010sssssPP0iiiiii01ttttt | memw(Rs+Ii) -= Rt + hi->instruction = HEX_INS_L4_SUB_MEMOPW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) -= %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x35000000) { + // 00110101000sssssPPiuuuuuivvttttt | if (!Pv) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x37000000) { + // 00110111000sssssPPiuuuuuivvttttt | if (!Pv.new) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x35a00000) { + // 00110101101sssssPPiuuuuuivv00ttt | if (!Pv) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBNEWF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x37a00000) { + // 00110111101sssssPPiuuuuuivv00ttt | if (!Pv.new) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBNEWFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x34a00000) { + // 00110100101sssssPPiuuuuuivv00ttt | if (Pv) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBNEWT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x36a00000) { + // 00110110101sssssPPiuuuuuivv00ttt | if (Pv.new) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBNEWTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x34000000) { + // 00110100000sssssPPiuuuuuivvttttt | if (Pv) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x36000000) { + // 00110110000sssssPPiuuuuuivvttttt | if (Pv.new) memb(Rs+Ru<instruction = HEX_INS_S4_PSTORERBTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x35c00000) { + // 00110101110sssssPPiuuuuuivvttttt | if (!Pv) memd(Rs+Ru<instruction = HEX_INS_S4_PSTORERDF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memd(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x37c00000) { + // 00110111110sssssPPiuuuuuivvttttt | if (!Pv.new) memd(Rs+Ru<instruction = HEX_INS_S4_PSTORERDFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memd(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x34c00000) { + // 00110100110sssssPPiuuuuuivvttttt | if (Pv) memd(Rs+Ru<instruction = HEX_INS_S4_PSTORERDT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memd(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x36c00000) { + // 00110110110sssssPPiuuuuuivvttttt | if (Pv.new) memd(Rs+Ru<instruction = HEX_INS_S4_PSTORERDTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + hi->ops[4].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memd(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_double_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x35600000) { + // 00110101011sssssPPiuuuuuivvttttt | if (!Pv) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERFF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s<<%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x37600000) { + // 00110111011sssssPPiuuuuuivvttttt | if (!Pv.new) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERFFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s<<%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x34600000) { + // 00110100011sssssPPiuuuuuivvttttt | if (Pv) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERFT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s<<%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x36600000) { + // 00110110011sssssPPiuuuuuivvttttt | if (Pv.new) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERFTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s<<%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x35400000) { + // 00110101010sssssPPiuuuuuivvttttt | if (!Pv) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x37400000) { + // 00110111010sssssPPiuuuuuivvttttt | if (!Pv.new) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x35a00008) { + // 00110101101sssssPPiuuuuuivv01ttt | if (!Pv) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHNEWF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x37a00008) { + // 00110111101sssssPPiuuuuuivv01ttt | if (!Pv.new) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHNEWFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x34a00008) { + // 00110100101sssssPPiuuuuuivv01ttt | if (Pv) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHNEWT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x36a00008) { + // 00110110101sssssPPiuuuuuivv01ttt | if (Pv.new) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHNEWTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x34400000) { + // 00110100010sssssPPiuuuuuivvttttt | if (Pv) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x36400000) { + // 00110110010sssssPPiuuuuuivvttttt | if (Pv.new) memh(Rs+Ru<instruction = HEX_INS_S4_PSTORERHTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x35800000) { + // 00110101100sssssPPiuuuuuivvttttt | if (!Pv) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERIF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x37800000) { + // 00110111100sssssPPiuuuuuivvttttt | if (!Pv.new) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERIFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x35a00010) { + // 00110101101sssssPPiuuuuuivv10ttt | if (!Pv) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERINEWF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x37a00010) { + // 00110111101sssssPPiuuuuuivv10ttt | if (!Pv.new) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERINEWFNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x34a00010) { + // 00110100101sssssPPiuuuuuivv10ttt | if (Pv) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERINEWT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00018) == 0x36a00010) { + // 00110110101sssssPPiuuuuuivv10ttt | if (Pv.new) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERINEWTNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s+%s<<%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[4].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x34800000) { + // 00110100100sssssPPiuuuuuivvttttt | if (Pv) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERIT_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x36800000) { + // 00110110100sssssPPiuuuuuivvttttt | if (Pv.new) memw(Rs+Ru<instruction = HEX_INS_S4_PSTORERITNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 5; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + hi->ops[4].type = HEX_OP_TYPE_REG; + hi->ops[4].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s+%s<<%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm, hex_get_int_regs(hi->ops[4].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x3c000000) { + // 00111100000sssssPPIiiiiiiIIIIIII | memb(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 6) | (((hi_u32)&0x7f) >> 0)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x38800000) { + // 00111000100sssssPPIiiiiiivvIIIII | if (!Pv) memb(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRBF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x39800000) { + // 00111001100sssssPPIiiiiiivvIIIII | if (!Pv.new) memb(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRBFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x38000000) { + // 00111000000sssssPPIiiiiiivvIIIII | if (Pv) memb(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRBT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x39000000) { + // 00111001000sssssPPIiiiiiivvIIIII | if (Pv.new) memb(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRBTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x3c200000) { + // 00111100001sssssPPIiiiiiiIIIIIII | memh(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 6) | (((hi_u32)&0x7f) >> 0)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x38a00000) { + // 00111000101sssssPPIiiiiiivvIIIII | if (!Pv) memh(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRHF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x39a00000) { + // 00111001101sssssPPIiiiiiivvIIIII | if (!Pv.new) memh(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRHFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x38200000) { + // 00111000001sssssPPIiiiiiivvIIIII | if (Pv) memh(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRHT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x39200000) { + // 00111001001sssssPPIiiiiiivvIIIII | if (Pv.new) memh(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRHTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x3c400000) { + // 00111100010sssssPPIiiiiiiIIIIIII | memw(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 6) | (((hi_u32)&0x7f) >> 0)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x38c00000) { + // 00111000110sssssPPIiiiiiivvIIIII | if (!Pv) memw(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRIF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x39c00000) { + // 00111001110sssssPPIiiiiiivvIIIII | if (!Pv.new) memw(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRIFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x38400000) { + // 00111000010sssssPPIiiiiiivvIIIII | if (Pv) memw(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRIT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x39400000) { + // 00111001010sssssPPIiiiiiivvIIIII | if (Pv.new) memw(Rs+Ii) = II + hi->instruction = HEX_INS_S4_STOREIRITNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f80) >> 7) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0x1f) >> 0)); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3b000000) { + // 00111011000sssssPPiuuuuui00ttttt | memb(Rs+Ru<instruction = HEX_INS_S4_STORERB_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s<<%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00078) == 0x3ba00000) { + // 00111011101sssssPPiuuuuui0000ttt | memb(Rs+Ru<instruction = HEX_INS_S4_STORERBNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s<<%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3bc00000) { + // 00111011110sssssPPiuuuuui00ttttt | memd(Rs+Ru<instruction = HEX_INS_S4_STORERD_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memd(%s+%s<<%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3b600000) { + // 00111011011sssssPPiuuuuui00ttttt | memh(Rs+Ru<instruction = HEX_INS_S4_STORERF_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s<<%s0x%x) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3b400000) { + // 00111011010sssssPPiuuuuui00ttttt | memh(Rs+Ru<instruction = HEX_INS_S4_STORERH_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s<<%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00078) == 0x3ba00008) { + // 00111011101sssssPPiuuuuui0001ttt | memh(Rs+Ru<instruction = HEX_INS_S4_STORERHNEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s<<%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00060) == 0x3b800000) { + // 00111011100sssssPPiuuuuui00ttttt | memw(Rs+Ru<instruction = HEX_INS_S4_STORERI_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s<<%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00078) == 0x3ba00010) { + // 00111011101sssssPPiuuuuui0010ttt | memw(Rs+Ru<instruction = HEX_INS_S4_STORERINEW_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x7) >> 0); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s<<%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x4(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xf9e00000) == 0x49000000) { + // 01001ii1000iiiiiPPiiiiiiiiiddddd | Rd = memb(gp+Ii) + hi->instruction = HEX_INS_L2_LOADRBGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memb(GP+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49c00000) { + // 01001ii1110iiiiiPPiiiiiiiiiddddd | Rdd = memd(gp+Ii) + hi->instruction = HEX_INS_L2_LOADRDGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(GP+%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49400000) { + // 01001ii1010iiiiiPPiiiiiiiiiddddd | Rd = memh(gp+Ii) + hi->instruction = HEX_INS_L2_LOADRHGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memh(GP+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49800000) { + // 01001ii1100iiiiiPPiiiiiiiiiddddd | Rd = memw(gp+Ii) + hi->instruction = HEX_INS_L2_LOADRIGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(GP+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49200000) { + // 01001ii1001iiiiiPPiiiiiiiiiddddd | Rd = memub(gp+Ii) + hi->instruction = HEX_INS_L2_LOADRUBGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memub(GP+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49600000) { + // 01001ii1011iiiiiPPiiiiiiiiiddddd | Rd = memuh(gp+Ii) + hi->instruction = HEX_INS_L2_LOADRUHGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(GP+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x45000000) { + // 01000101000sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRBF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memb(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x47000000) { + // 01000111000sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRBFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memb(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x41000000) { + // 01000001000sssssPP0ttiiiiiiddddd | if (Pt) Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRBT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memb(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x43000000) { + // 01000011000sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRBTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memb(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x45c00000) { + // 01000101110sssssPP0ttiiiiiiddddd | if (!Pt) Rdd = memd(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRDF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memd(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x47c00000) { + // 01000111110sssssPP0ttiiiiiiddddd | if (!Pt.new) Rdd = memd(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRDFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memd(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x41c00000) { + // 01000001110sssssPP0ttiiiiiiddddd | if (Pt) Rdd = memd(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRDT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memd(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x43c00000) { + // 01000011110sssssPP0ttiiiiiiddddd | if (Pt.new) Rdd = memd(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRDTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memd(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x45400000) { + // 01000101010sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRHF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x47400000) { + // 01000111010sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRHFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x41400000) { + // 01000001010sssssPP0ttiiiiiiddddd | if (Pt) Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRHT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x43400000) { + // 01000011010sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRHTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x45800000) { + // 01000101100sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRIF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memw(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x47800000) { + // 01000111100sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRIFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memw(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x41800000) { + // 01000001100sssssPP0ttiiiiiiddddd | if (Pt) Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRIT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memw(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x43800000) { + // 01000011100sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRITNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memw(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x45200000) { + // 01000101001sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUBF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memub(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x47200000) { + // 01000111001sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUBFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memub(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x41200000) { + // 01000001001sssssPP0ttiiiiiiddddd | if (Pt) Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUBT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memub(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x43200000) { + // 01000011001sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUBTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memub(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x45600000) { + // 01000101011sssssPP0ttiiiiiiddddd | if (!Pt) Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUHF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memuh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x47600000) { + // 01000111011sssssPP0ttiiiiiiddddd | if (!Pt.new) Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUHFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memuh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x41600000) { + // 01000001011sssssPP0ttiiiiiiddddd | if (Pt) Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUHT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memuh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x43600000) { + // 01000011011sssssPP0ttiiiiiiddddd | if (Pt.new) Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_L2_PLOADRUHTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1800) >> 11); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x7e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memuh(%s+%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49000000) { + // 01001ii1000iiiiiPPiiiiiiiiiddddd | Rd = memb(Ii) + hi->instruction = HEX_INS_PS_LOADRBABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49c00000) { + // 01001ii1110iiiiiPPiiiiiiiiiddddd | Rdd = memd(Ii) + hi->instruction = HEX_INS_PS_LOADRDABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49400000) { + // 01001ii1010iiiiiPPiiiiiiiiiddddd | Rd = memh(Ii) + hi->instruction = HEX_INS_PS_LOADRHABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49800000) { + // 01001ii1100iiiiiPPiiiiiiiiiddddd | Rd = memw(Ii) + hi->instruction = HEX_INS_PS_LOADRIABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49200000) { + // 01001ii1001iiiiiPPiiiiiiiiiddddd | Rd = memub(Ii) + hi->instruction = HEX_INS_PS_LOADRUBABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x49600000) { + // 01001ii1011iiiiiPPiiiiiiiiiddddd | Rd = memuh(Ii) + hi->instruction = HEX_INS_PS_LOADRUHABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48000000) { + // 01001ii0000iiiiiPPitttttiiiiiiii | memb(Ii) = Rt + hi->instruction = HEX_INS_PS_STORERBABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memb(%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00000) { + // 01001ii0101iiiiiPPi00tttiiiiiiii | memb(Ii) = Nt.new + hi->instruction = HEX_INS_PS_STORERBNEWABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memb(%s0x%x) = %s.new", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48c00000) { + // 01001ii0110iiiiiPPitttttiiiiiiii | memd(Ii) = Rtt + hi->instruction = HEX_INS_PS_STORERDABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memd(%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48600000) { + // 01001ii0011iiiiiPPitttttiiiiiiii | memh(Ii) = Rt.h + hi->instruction = HEX_INS_PS_STORERFABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memh(%s0x%x) = %s.h", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48400000) { + // 01001ii0010iiiiiPPitttttiiiiiiii | memh(Ii) = Rt + hi->instruction = HEX_INS_PS_STORERHABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memh(%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00800) { + // 01001ii0101iiiiiPPi01tttiiiiiiii | memh(Ii) = Nt.new + hi->instruction = HEX_INS_PS_STORERHNEWABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memh(%s0x%x) = %s.new", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48800000) { + // 01001ii0100iiiiiPPitttttiiiiiiii | memw(Ii) = Rt + hi->instruction = HEX_INS_PS_STORERIABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memw(%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0x48a01000) { + // 01001ii0101iiiiiPPi10tttiiiiiiii | memw(Ii) = Nt.new + hi->instruction = HEX_INS_PS_STORERINEWABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memw(%s0x%x) = %s.new", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x44000000) { + // 01000100000sssssPPitttttiiiii0vv | if (!Pv) memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x44a00000) { + // 01000100101sssssPPi00tttiiiii0vv | if (!Pv) memb(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x40a00000) { + // 01000000101sssssPPi00tttiiiii0vv | if (Pv) memb(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x40000000) { + // 01000000000sssssPPitttttiiiii0vv | if (Pv) memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x44c00000) { + // 01000100110sssssPPitttttiiiii0vv | if (!Pv) memd(Rs+Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memd(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x40c00000) { + // 01000000110sssssPPitttttiiiii0vv | if (Pv) memd(Rs+Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memd(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x44600000) { + // 01000100011sssssPPitttttiiiii0vv | if (!Pv) memh(Rs+Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x40600000) { + // 01000000011sssssPPitttttiiiii0vv | if (Pv) memh(Rs+Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x44400000) { + // 01000100010sssssPPitttttiiiii0vv | if (!Pv) memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x44a00800) { + // 01000100101sssssPPi01tttiiiii0vv | if (!Pv) memh(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x40a00800) { + // 01000000101sssssPPi01tttiiiii0vv | if (Pv) memh(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x40400000) { + // 01000000010sssssPPitttttiiiii0vv | if (Pv) memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x44800000) { + // 01000100100sssssPPitttttiiiii0vv | if (!Pv) memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x44a01000) { + // 01000100101sssssPPi10tttiiiii0vv | if (!Pv) memw(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x40a01000) { + // 01000000101sssssPPi10tttiiiii0vv | if (Pv) memw(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x40800000) { + // 01000000100sssssPPitttttiiiii0vv | if (Pv) memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIT_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48000000) { + // 01001ii0000iiiiiPPitttttiiiiiiii | memb(gp+Ii) = Rt + hi->instruction = HEX_INS_S2_STORERBGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memb(GP+%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00000) { + // 01001ii0101iiiiiPPi00tttiiiiiiii | memb(gp+Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEWGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memb(GP+%s0x%x) = %s.new", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48c00000) { + // 01001ii0110iiiiiPPitttttiiiiiiii | memd(gp+Ii) = Rtt + hi->instruction = HEX_INS_S2_STORERDGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 3; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 3; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memd(GP+%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48600000) { + // 01001ii0011iiiiiPPitttttiiiiiiii | memh(gp+Ii) = Rt.h + hi->instruction = HEX_INS_S2_STORERFGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memh(GP+%s0x%x) = %s.h", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48400000) { + // 01001ii0010iiiiiPPitttttiiiiiiii | memh(gp+Ii) = Rt + hi->instruction = HEX_INS_S2_STORERHGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memh(GP+%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0x48a00800) { + // 01001ii0101iiiiiPPi01tttiiiiiiii | memh(gp+Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEWGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 1; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memh(GP+%s0x%x) = %s.new", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x48800000) { + // 01001ii0100iiiiiPPitttttiiiiiiii | memw(gp+Ii) = Rt + hi->instruction = HEX_INS_S2_STORERIGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memw(GP+%s0x%x) = %s", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0x48a01000) { + // 01001ii0101iiiiiPPi10tttiiiiiiii | memw(gp+Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEWGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x6000000) >> 11) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "memw(GP+%s0x%x) = %s.new", !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[0].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[1].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x46000000) { + // 01000110000sssssPPitttttiiiii0vv | if (!Pv.new) memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x46a00000) { + // 01000110101sssssPPi00tttiiiii0vv | if (!Pv.new) memb(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x42a00000) { + // 01000010101sssssPPi00tttiiiii0vv | if (Pv.new) memb(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x42000000) { + // 01000010000sssssPPitttttiiiii0vv | if (Pv.new) memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x46c00000) { + // 01000110110sssssPPitttttiiiii0vv | if (!Pv.new) memd(Rs+Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memd(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x42c00000) { + // 01000010110sssssPPitttttiiiii0vv | if (Pv.new) memd(Rs+Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memd(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x46600000) { + // 01000110011sssssPPitttttiiiii0vv | if (!Pv.new) memh(Rs+Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x42600000) { + // 01000010011sssssPPitttttiiiii0vv | if (Pv.new) memh(Rs+Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x46400000) { + // 01000110010sssssPPitttttiiiii0vv | if (!Pv.new) memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x46a00800) { + // 01000110101sssssPPi01tttiiiii0vv | if (!Pv.new) memh(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x42a00800) { + // 01000010101sssssPPi01tttiiiii0vv | if (Pv.new) memh(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x42400000) { + // 01000010010sssssPPitttttiiiii0vv | if (Pv.new) memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x46800000) { + // 01000110100sssssPPitttttiiiii0vv | if (!Pv.new) memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x46a01000) { + // 01000110101sssssPPi10tttiiiii0vv | if (!Pv.new) memw(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWFNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01804) == 0x42a01000) { + // 01000010101sssssPPi10tttiiiii0vv | if (Pv.new) memw(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWTNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s+%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00004) == 0x42800000) { + // 01000010100sssssPPitttttiiiii0vv | if (Pv.new) memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERITNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 8) | (((hi_u32)&0xf8) >> 3)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s+%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x5(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xfe000001) == 0x5a000000) { + // 0101101iiiiiiiiiPPiiiiiiiiiiiii0 | call Ii + hi->instruction = HEX_INS_J2_CALL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1ff0000) >> 3) | (((hi_u32)&0x3ffe) >> 1)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 23)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 23); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CALL; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "call 0x%x", pkt->pkt_addr + (st32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5d200000) { + // 01011101ii1iiiiiPPi000uuiiiiiii0 | if (!Pu) call Ii + hi->instruction = HEX_INS_J2_CALLF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CCALL; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!%s) call 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x50a00000) { + // 01010000101sssssPP00000000000000 | callr Rs + hi->instruction = HEX_INS_J2_CALLR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCALL; + sprintf(hi->mnem_infix, "callr %s", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x51200000) { + // 01010001001sssssPP0000uu00000000 | if (!Pu) callr Rs + hi->instruction = HEX_INS_J2_CALLRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_UCCALL; + sprintf(hi->mnem_infix, "if (!%s) callr %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x51000000) { + // 01010001000sssssPP0000uu00000000 | if (Pu) callr Rs + hi->instruction = HEX_INS_J2_CALLRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_UCCALL; + sprintf(hi->mnem_infix, "if (%s) callr %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5d000000) { + // 01011101ii0iiiiiPPi000uuiiiiiii0 | if (Pu) call Ii + hi->instruction = HEX_INS_J2_CALLT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CCALL; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s) call 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe000001) == 0x58000000) { + // 0101100iiiiiiiiiPPiiiiiiiiiiiii0 | jump Ii + hi->instruction = HEX_INS_J2_JUMP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1ff0000) >> 3) | (((hi_u32)&0x3ffe) >> 1)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 23)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 23); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "jump 0x%x", pkt->pkt_addr + (st32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c200000) { + // 01011100ii1iiiiiPPi000uuiiiiiii0 | if (!Pu) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!%s) jump:nt 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c200800) { + // 01011100ii1iiiiiPPi010uuiiiiiii0 | if (!Pu.new) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!%s.new) jump:nt 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c201800) { + // 01011100ii1iiiiiPPi110uuiiiiiii0 | if (!Pu.new) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPFNEWPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!%s.new) jump:t 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c201000) { + // 01011100ii1iiiiiPPi100uuiiiiiii0 | if (!Pu) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPFPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (!%s) jump:t 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x52800000) { + // 01010010100sssssPP00000000000000 | jumpr Rs + hi->instruction = HEX_INS_J2_JUMPR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RJMP; + sprintf(hi->mnem_infix, "jumpr %s", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53600000) { + // 01010011011sssssPP0000uu00000000 | if (!Pu) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (!%s) jumpr:nt %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53600800) { + // 01010011011sssssPP0010uu00000000 | if (!Pu.new) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (!%s.new) jumpr:nt %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53601800) { + // 01010011011sssssPP0110uu00000000 | if (!Pu.new) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRFNEWPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (!%s.new) jumpr:t %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53601000) { + // 01010011011sssssPP0100uu00000000 | if (!Pu) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRFPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (!%s) jumpr:t %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53400000) { + // 01010011010sssssPP0000uu00000000 | if (Pu) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (%s) jumpr:nt %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53400800) { + // 01010011010sssssPP0010uu00000000 | if (Pu.new) jumpr:nt Rs + hi->instruction = HEX_INS_J2_JUMPRTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (%s.new) jumpr:nt %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53401800) { + // 01010011010sssssPP0110uu00000000 | if (Pu.new) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRTNEWPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (%s.new) jumpr:t %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x53401000) { + // 01010011010sssssPP0100uu00000000 | if (Pu) jumpr:t Rs + hi->instruction = HEX_INS_J2_JUMPRTPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RCJMP; + sprintf(hi->mnem_infix, "if (%s) jumpr:t %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c000000) { + // 01011100ii0iiiiiPPi000uuiiiiiii0 | if (Pu) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s) jump:nt 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c000800) { + // 01011100ii0iiiiiPPi010uuiiiiiii0 | if (Pu.new) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s.new) jump:nt 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c001800) { + // 01011100ii0iiiiiPPi110uuiiiiiii0 | if (Pu.new) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPTNEWPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s.new) jump:t 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff201c01) == 0x5c001000) { + // 01011100ii0iiiiiPPi100uuiiiiiii0 | if (Pu) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPTPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 9) | (((hi_u32)&0x1f0000) >> 8) | (((hi_u32)&0x2000) >> 6) | (((hi_u32)&0xfe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 16)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 16); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s) jump:t 0x%x", hex_get_pred_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e3) == 0x54400000) { + // 0101010001000000PP0iiiii000iii00 | pause(Ii) + hi->instruction = HEX_INS_J2_PAUSE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "pause(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e3) == 0x54000000) { + // 0101010000000000PP0iiiii000iii00 | trap0(Ii) + hi->instruction = HEX_INS_J2_TRAP0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_TRAP; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "trap0(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e3) == 0x54800000) { + // 01010100100xxxxxPP0iiiii000iii00 | trap1(Rx,Ii) + hi->instruction = HEX_INS_J2_TRAP1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_TRAP; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "trap1(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x52a00000) { + // 01010010101sssssPP00000000000000 | hintjr(Rs) + hi->instruction = HEX_INS_J4_HINTJUMPR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RJMP; + sprintf(hi->mnem_infix, "hintjr(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20e3) == 0x54800000) { + // 0101010010000000PP0iiiii000iii00 | trap1(Ii) + hi->instruction = HEX_INS_PS_TRAP1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 5) | (((hi_u32)&0x1c) >> 2)); // Ii + hex_extend_op(state, &(hi->ops[0]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_TRAP; + hi->ana_op.analysis_vals[0].imm = hi->ops[0].op.imm; + sprintf(hi->mnem_infix, "trap1(%s0x%x)", !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[0].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x56c00000) { + // 01010110110sssssPP00000000000000 | icinva(Rs) + hi->instruction = HEX_INS_Y2_ICINVA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "icinva(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x57c00002) { + // 0101011111000000PP00000000000010 | isync + hi->instruction = HEX_INS_Y2_ISYNC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "isync"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x56c01000) { + // 0101011011000000PP01000000000000 | ickill + hi->instruction = HEX_INS_IMPORTED_ICKILL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "ickill"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x56c00800) { + // 01010110110sssssPP00100000000000 | icinvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_ICINVIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "icinvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x55c02000) { + // 01010101110sssssPP1ttttt00000000 | icdataw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_ICDATAW_RS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "icdataw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x57e00000) { + // 0101011111100000PP00000000000000 | rte + hi->instruction = HEX_INS_IMPORTED_RTE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "rte"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x55c00000) { + // 01010101110sssssPP0ttttt00000000 | ictagw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_ICTAGW_RS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "ictagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x55a00000) { + // 01010101101sssssPP000000000ddddd | Rd = icdatar(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_ICDATAR_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = icdatar(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x55e00000) { + // 01010101111sssssPP000000000ddddd | Rd = ictagr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_ICTAGR_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = ictagr(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x6(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xffe03fe0) == 0x6a000000) { + // 01101010000sssssPP000000000ddddd | Rd = Cs + hi->instruction = HEX_INS_A2_TFRCRR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Cs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_ctr_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x62200000) { + // 01100010001sssssPP000000000ddddd | Cd = Rs + hi->instruction = HEX_INS_A2_TFRRCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Cd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_ctr_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x68000000) { + // 01101000000sssssPP000000000ddddd | Rdd = Css + hi->instruction = HEX_INS_A4_TFRCPP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Css32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_double_regs(hi->ops[0].op.reg), hex_get_ctr_regs64(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x63200000) { + // 01100011001sssssPP000000000ddddd | Cdd = Rss + hi->instruction = HEX_INS_A4_TFRPCP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Cdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_ctr_regs64(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3ffc) == 0x6ba00000) { + // 01101011101000ssPP000000000000dd | Pd = all8(Ps) + hi->instruction = HEX_INS_C2_ALL8; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = all8(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b000000) { + // 01101011000000ssPP0000tt000000dd | Pd = and(Pt,Ps) + hi->instruction = HEX_INS_C2_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b600000) { + // 01101011011000ssPP0000tt000000dd | Pd = and(Pt,!Ps) + hi->instruction = HEX_INS_C2_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,!%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3ffc) == 0x6b800000) { + // 01101011100000ssPP000000000000dd | Pd = any8(Ps) + hi->instruction = HEX_INS_C2_ANY8; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = any8(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3ffc) == 0x6bc00000) { + // 01101011110000ssPP000000000000dd | Pd = not(Ps) + hi->instruction = HEX_INS_C2_NOT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = not(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b200000) { + // 01101011001000ssPP0000tt000000dd | Pd = or(Pt,Ps) + hi->instruction = HEX_INS_C2_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6be00000) { + // 01101011111000ssPP0000tt000000dd | Pd = or(Pt,!Ps) + hi->instruction = HEX_INS_C2_ORN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,!%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b400000) { + // 01101011010000ssPP0000tt000000dd | Pd = xor(Ps,Pt) + hi->instruction = HEX_INS_C2_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = xor(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff2060) == 0x6a490000) { + // 0110101001001001PP0iiiiii00ddddd | Rd = add(pc,Ii) + hi->instruction = HEX_INS_C4_ADDIPC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f80) >> 7); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(PC,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b100000) { + // 01101011000100ssPP0000ttuu0000dd | Pd = and(Ps,and(Pt,Pu)) + hi->instruction = HEX_INS_C4_AND_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,and(%s,%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b900000) { + // 01101011100100ssPP0000ttuu0000dd | Pd = and(Ps,and(Pt,!Pu)) + hi->instruction = HEX_INS_C4_AND_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,and(%s,!%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b300000) { + // 01101011001100ssPP0000ttuu0000dd | Pd = and(Ps,or(Pt,Pu)) + hi->instruction = HEX_INS_C4_AND_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,or(%s,%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6bb00000) { + // 01101011101100ssPP0000ttuu0000dd | Pd = and(Ps,or(Pt,!Pu)) + hi->instruction = HEX_INS_C4_AND_ORN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,or(%s,!%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b002090) { + // 01101011000000ssPP1000tt100100dd | Pd = fastcorner9(Ps,Pt) + hi->instruction = HEX_INS_C4_FASTCORNER9; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = fastcorner9(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3cfc) == 0x6b102090) { + // 01101011000100ssPP1000tt100100dd | Pd = !fastcorner9(Ps,Pt) + hi->instruction = HEX_INS_C4_FASTCORNER9_NOT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !fastcorner9(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b500000) { + // 01101011010100ssPP0000ttuu0000dd | Pd = or(Ps,and(Pt,Pu)) + hi->instruction = HEX_INS_C4_OR_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,and(%s,%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6bd00000) { + // 01101011110100ssPP0000ttuu0000dd | Pd = or(Ps,and(Pt,!Pu)) + hi->instruction = HEX_INS_C4_OR_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,and(%s,!%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6b700000) { + // 01101011011100ssPP0000ttuu0000dd | Pd = or(Ps,or(Pt,Pu)) + hi->instruction = HEX_INS_C4_OR_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,or(%s,%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3c3c) == 0x6bf00000) { + // 01101011111100ssPP0000ttuu0000dd | Pd = or(Ps,or(Pt,!Pu)) + hi->instruction = HEX_INS_C4_OR_ORN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0xc0) >> 6); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,or(%s,!%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x68200000) { + // 01101000001sssssPP000000000ddddd | Rdd = Gss + hi->instruction = HEX_INS_G4_TFRGCPP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Gss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_double_regs(hi->ops[0].op.reg), hex_get_guest_regs64(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x6a200000) { + // 01101010001sssssPP000000000ddddd | Rd = Gs + hi->instruction = HEX_INS_G4_TFRGCRR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Gs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_guest_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x63000000) { + // 01100011000sssssPP000000000ddddd | Gdd = Rss + hi->instruction = HEX_INS_G4_TFRGPCP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Gdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_guest_regs64(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x62000000) { + // 01100010000sssssPP000000000ddddd | Gd = Rs + hi->instruction = HEX_INS_G4_TFRGRCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Gd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_guest_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61400000) { + // 0110000101isssssPPi0iiiiiiiiiii0 | if (Rs>=#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRGTEZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s>=#0) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61401000) { + // 0110000101isssssPPi1iiiiiiiiiii0 | if (Rs>=#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRGTEZPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s>=#0) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61c00000) { + // 0110000111isssssPPi0iiiiiiiiiii0 | if (Rs<=#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRLTEZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s<=#0) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61c01000) { + // 0110000111isssssPPi1iiiiiiiiiii0 | if (Rs<=#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRLTEZPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s<=#0) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61800000) { + // 0110000110isssssPPi0iiiiiiiiiii0 | if (Rs==#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRNZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s==#0) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61801000) { + // 0110000110isssssPPi1iiiiiiiiiii0 | if (Rs==#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRNZPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s==#0) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61000000) { + // 0110000100isssssPPi0iiiiiiiiiii0 | if (Rs!=#0) jump:nt Ii + hi->instruction = HEX_INS_J2_JUMPRZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s!=#0) jump:nt 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc01001) == 0x61001000) { + // 0110000100isssssPPi1iiiiiiiiiii0 | if (Rs!=#0) jump:t Ii + hi->instruction = HEX_INS_J2_JUMPRZPT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 9) | (((hi_u32)&0x2000) >> 2) | (((hi_u32)&0xffe) >> 1)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 14)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 14); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[1].op.imm; + hi->ana_op.fail = hi->ana_op.addr + 4; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "if (%s!=#0) jump:t 0x%x", hex_get_int_regs(hi->ops[0].op.reg), pkt->pkt_addr + (st32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02004) == 0x69000000) { + // 01101001000IIIIIPP0iiiiiIIIii0II | loop0(Ii,II) + hi->instruction = HEX_INS_J2_LOOP0I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "loop0(0x%x,%s0x%x)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e7) == 0x60000000) { + // 01100000000sssssPP0iiiii000ii000 | loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_LOOP0R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "loop0(0x%x,%s)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02004) == 0x69200000) { + // 01101001001IIIIIPP0iiiiiIIIii0II | loop1(Ii,II) + hi->instruction = HEX_INS_J2_LOOP1I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop1_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "loop1(0x%x,%s0x%x)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e7) == 0x60200000) { + // 01100000001sssssPP0iiiii000ii000 | loop1(Ii,Rs) + hi->instruction = HEX_INS_J2_LOOP1R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop1_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "loop1(0x%x,%s)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02004) == 0x69a00000) { + // 01101001101IIIIIPP0iiiiiIIIii0II | p3 = sp1loop0(Ii,II) + hi->instruction = HEX_INS_J2_PLOOP1SI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P3 = sp1loop0(0x%x,%s0x%x)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e7) == 0x60a00000) { + // 01100000101sssssPP0iiiii000ii000 | p3 = sp1loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_PLOOP1SR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P3 = sp1loop0(0x%x,%s)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02004) == 0x69c00000) { + // 01101001110IIIIIPP0iiiiiIIIii0II | p3 = sp2loop0(Ii,II) + hi->instruction = HEX_INS_J2_PLOOP2SI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P3 = sp2loop0(0x%x,%s0x%x)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e7) == 0x60c00000) { + // 01100000110sssssPP0iiiii000ii000 | p3 = sp2loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_PLOOP2SR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P3 = sp2loop0(0x%x,%s)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02004) == 0x69e00000) { + // 01101001111IIIIIPP0iiiiiIIIii0II | p3 = sp3loop0(Ii,II) + hi->instruction = HEX_INS_J2_PLOOP3SI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 11) | (((hi_u32)&0xe0) >> 3) | (((hi_u32)&0x3) >> 0)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[1].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P3 = sP3loop0(0x%x,%s0x%x)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e7) == 0x60e00000) { + // 01100000111sssssPP0iiiii000ii000 | p3 = sp3loop0(Ii,Rs) + hi->instruction = HEX_INS_J2_PLOOP3SR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_IMM; + hi->ops[0].op.imm = ((((hi_u32)&0x1f00) >> 6) | (((hi_u32)&0x18) >> 3)) << 2; // scaled Ii + hi->ops[0].attr = HEX_OP_IMM_SCALED; + hi->ops[0].shift = 2; + if (hi->ops[0].op.imm & (1 << 8)) { // signed + hi->ops[0].op.imm |= (0xffffffffffffffff << 8); + } + hex_extend_op(state, &(hi->ops[0]), false, addr); // Extension possible + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_JMP; + pkt->is_eob = true; + hi->ana_op.jump = pkt->pkt_addr + (st32)hi->ops[0].op.imm; + pkt->hw_loop0_addr = hi->ana_op.jump; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = hi->ana_op.jump; + sprintf(hi->mnem_infix, "P3 = sP3loop0(0x%x,%s)", pkt->pkt_addr + (st32)hi->ops[0].op.imm, hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200000) { + // 0110110000100000PP00000000000000 | brkpt + hi->instruction = HEX_INS_Y2_BREAK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "brkpt"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64400000) { + // 01100100010sssssPP00000000000000 | wait(Rs) + hi->instruction = HEX_INS_Y2_WAIT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "wait(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x62400000) { + // 01100010010sssssPP00000000000000 | trace(Rs) + hi->instruction = HEX_INS_Y4_TRACE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "trace(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x62400020) { + // 01100010010sssssPP00000000100000 | diag(Rs) + hi->instruction = HEX_INS_Y6_DIAG; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "DIAG(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x62400040) { + // 01100010010sssssPP0ttttt01000000 | diag0(Rss,Rtt) + hi->instruction = HEX_INS_Y6_DIAG0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "DIAG0(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x62400060) { + // 01100010010sssssPP0ttttt01100000 | diag1(Rss,Rtt) + hi->instruction = HEX_INS_Y6_DIAG1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "DIAG1(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64400020) { + // 01100100010sssssPP00000000100000 | resume(Rs) + hi->instruction = HEX_INS_IMPORTED_RESUME_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "resume(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200080) { + // 0110110000100000PP00000010000000 | k0unlock + hi->instruction = HEX_INS_IMPORTED_K0UNLOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "k0unlock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64600000) { + // 01100100011sssssPP00000000000000 | stop(Rs) + hi->instruction = HEX_INS_IMPORTED_STOP_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "stop(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64000060) { + // 01100100000sssssPP00000001100000 | ciad(Rs) + hi->instruction = HEX_INS_IMPORTED_CIAD_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "ciad(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x66000000) { + // 01100110000sssssPP000000000ddddd | Rd = getimask(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_GETIMASK_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = getimask(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64000000) { + // 01100100000sssssPP00000000000000 | swi(Rs) + hi->instruction = HEX_INS_IMPORTED_SWI_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "swi(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0x6c000000) { + // 01101100000sssssPP0ttttt00000000 | tlbw(Rss,Rt) + hi->instruction = HEX_INS_IMPORTED_TLBW_RSS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlbw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x6cc00000) { + // 01101100110sssssPP0ttttt000ddddd | Rd = ctlbw(Rss,Rt) + hi->instruction = HEX_INS_IMPORTED_RD_CTLBW_RSS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = ctlbw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200060) { + // 0110110000100000PP00000001100000 | k0lock + hi->instruction = HEX_INS_IMPORTED_K0LOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "k0lock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x66600000) { + // 01100110011sssssPP000000000ddddd | Rd = iassignr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_IASSIGNR_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = iassignr(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff803fe0) == 0x6f000000) { + // 011011110sssssssPP000000000ddddd | Rdd = Sss + hi->instruction = HEX_INS_IMPORTED_RDD_SSS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7f0000) >> 16); // Sss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_double_regs(hi->ops[0].op.reg), hex_get_sys_regs64(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff803fe0) == 0x6e800000) { + // 011011101sssssssPP000000000ddddd | Rd = Ss + hi->instruction = HEX_INS_IMPORTED_RD_SS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x7f0000) >> 16); // Ss32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_sys_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x6c800000) { + // 01101100100sssssPP000000000ddddd | Rd = tlbp(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_TLBP_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = tlbp(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64000040) { + // 01100100000sssssPP00000001000000 | iassignw(Rs) + hi->instruction = HEX_INS_IMPORTED_IASSIGNW_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "iassignw(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64600040) { + // 01100100011sssssPP00000001000000 | nmi(Rs) + hi->instruction = HEX_INS_IMPORTED_NMI_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "nmi(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x6ca00000) { + // 01101100101sssssPP00000000000000 | tlbinvasid(Rs) + hi->instruction = HEX_INS_IMPORTED_TLBINVASID_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlbinvasid(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x6d000000) { + // 0110110100-sssssPP-------ddddddd | Sdd = Rss + hi->instruction = HEX_INS_IMPORTED_SDD_RSS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x7f) >> 0); // Sdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_sys_regs64(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x64800000) { + // 01100100100sssssPP0000tt00000000 | setimask(Pt,Rs) + hi->instruction = HEX_INS_IMPORTED_SETIMASK_PT_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "setimask(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x65000000) { + // 01100101000xxxxxPP00000000000000 | crswap(Rx,sgp0) + hi->instruction = HEX_INS_IMPORTED_CRSWAP_RX_SGP0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "crswap(%s,SGP0)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200020) { + // 0110110000100000PP00000000100000 | tlblock + hi->instruction = HEX_INS_IMPORTED_TLBLOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlblock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x65200000) { + // 01100101001xxxxxPP00000000000000 | crswap(Rx,sgp1) + hi->instruction = HEX_INS_IMPORTED_CRSWAP_RX_SGP1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "crswap(%s,SGP1)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x6c400000) { + // 01101100010sssssPP000000000ddddd | Rdd = tlbr(Rs) + hi->instruction = HEX_INS_IMPORTED_RDD_TLBR_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = tlbr(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03f80) == 0x67000000) { + // 01100111000sssssPP0000000ddddddd | Sd = Rs + hi->instruction = HEX_INS_IMPORTED_SD_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x7f) >> 0); // Sd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_sys_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x6c200040) { + // 0110110000100000PP00000001000000 | tlbunlock + hi->instruction = HEX_INS_IMPORTED_TLBUNLOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "tlbunlock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x6ce00000) { + // 01101100111sssssPP000000000ddddd | Rd = tlboc(Rss) + hi->instruction = HEX_INS_IMPORTED_RD_TLBOC_RSS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = tlboc(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x6d800000) { + // 01101101100xxxxxPP00000000000000 | crswap(Rxx,sgp1:0) + hi->instruction = HEX_INS_IMPORTED_CRSWAP_RXX_SGP1_0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "crswap(%s,SGP1:0)", hex_get_double_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03cff) == 0x64800020) { + // 01100100100sssssPP0000tt00100000 | setprio(Pt,Rs) + hi->instruction = HEX_INS_IMPORTED_SETPRIO_PT_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "setprio(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64000020) { + // 01100100000sssssPP00000000100000 | cswi(Rs) + hi->instruction = HEX_INS_IMPORTED_CSWI_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "CSwi(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64800060) { + // 01100100100sssssPP00000001100000 | siad(Rs) + hi->instruction = HEX_INS_IMPORTED_SIAD_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "siad(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0x64600020) { + // 01100100011sssssPP00000000100000 | start(Rs) + hi->instruction = HEX_INS_IMPORTED_START_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "start(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x7(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffc00000) == 0x76000000) { + // 0111011000isssssPPiiiiiiiiiddddd | Rd = and(Rs,Ii) + hi->instruction = HEX_INS_A2_ANDIR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x70000000) { + // 01110000000sssssPP000000000ddddd | Rd = aslh(Rs) + hi->instruction = HEX_INS_A2_ASLH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = aslh(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x70200000) { + // 01110000001sssssPP000000000ddddd | Rd = asrh(Rs) + hi->instruction = HEX_INS_A2_ASRH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asrh(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff800000) == 0x7c000000) { + // 011111000IIIIIIIPPIiiiiiiiiddddd | Rdd = combine(Ii,II) + hi->instruction = HEX_INS_A2_COMBINEII; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[1].op.imm & (1 << 7)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x7f0000) >> 15) | (((hi_u32)&0x2000) >> 13)); // II + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), signed_imm[1], signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0x7f000000) { + // 0111111100000000PP00000000000000 | nop + hi->instruction = HEX_INS_A2_NOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NOP; + sprintf(hi->mnem_infix, "nop"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x76800000) { + // 0111011010isssssPPiiiiiiiiiddddd | Rd = or(Rs,Ii) + hi->instruction = HEX_INS_A2_ORIR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = or(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x74800000) { + // 011101001uusssssPP0iiiiiiiiddddd | if (!Pu) Rd = add(Rs,Ii) + hi->instruction = HEX_INS_A2_PADDIF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x74802000) { + // 011101001uusssssPP1iiiiiiiiddddd | if (!Pu.new) Rd = add(Rs,Ii) + hi->instruction = HEX_INS_A2_PADDIFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x74000000) { + // 011101000uusssssPP0iiiiiiiiddddd | if (Pu) Rd = add(Rs,Ii) + hi->instruction = HEX_INS_A2_PADDIT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x74002000) { + // 011101000uusssssPP1iiiiiiiiddddd | if (Pu.new) Rd = add(Rs,Ii) + hi->instruction = HEX_INS_A2_PADDITNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x76400000) { + // 0111011001isssssPPiiiiiiiiiddddd | Rd = sub(Ii,Rs) + hi->instruction = HEX_INS_A2_SUBRI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[1].op.imm & (1 << 9)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = sub(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x70a00000) { + // 01110000101sssssPP000000000ddddd | Rd = sxtb(Rs) + hi->instruction = HEX_INS_A2_SXTB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x70e00000) { + // 01110000111sssssPP000000000ddddd | Rd = sxth(Rs) + hi->instruction = HEX_INS_A2_SXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxth(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x70600000) { + // 01110000011sssssPP000000000ddddd | Rd = Rs + hi->instruction = HEX_INS_A2_TFR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff200000) == 0x72200000) { + // 01110010ii1xxxxxPPiiiiiiiiiiiiii | Rx.h = Ii + hi->instruction = HEX_INS_A2_TFRIH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 8) | (((hi_u32)&0x3fff) >> 0)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s.h = %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff200000) == 0x71200000) { + // 01110001ii1xxxxxPPiiiiiiiiiiiiii | Rx.l = Ii + hi->instruction = HEX_INS_A2_TFRIL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 8) | (((hi_u32)&0x3fff) >> 0)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s.l = %s0x%x", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff200000) == 0x78000000) { + // 01111000ii0iiiiiPPiiiiiiiiiddddd | Rd = Ii + hi->instruction = HEX_INS_A2_TFRSI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xc00000) >> 8) | (((hi_u32)&0x1f0000) >> 7) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[1].op.imm & (1 << 15)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 15); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x70c00000) { + // 01110000110sssssPP000000000ddddd | Rd = zxth(Rs) + hi->instruction = HEX_INS_A2_ZXTH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = zxth(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00000) == 0x7c800000) { + // 01111100100IIIIIPPIiiiiiiiiddddd | Rdd = combine(Ii,II) + hi->instruction = HEX_INS_A4_COMBINEII; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[1].op.imm & (1 << 7)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 7); + } + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x2000) >> 13)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), signed_imm[1], !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x73202000) { + // 01110011001sssssPP1iiiiiiiiddddd | Rdd = combine(Ii,Rs) + hi->instruction = HEX_INS_A4_COMBINEIR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[1].op.imm & (1 << 7)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x73002000) { + // 01110011000sssssPP1iiiiiiiiddddd | Rdd = combine(Rs,Ii) + hi->instruction = HEX_INS_A4_COMBINERI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = combine(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002800) { + // 01110000000sssssPP1010uu000ddddd | if (!Pu) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = aslh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002c00) { + // 01110000000sssssPP1011uu000ddddd | if (!Pu.new) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = aslh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002000) { + // 01110000000sssssPP1000uu000ddddd | if (Pu) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = aslh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70002400) { + // 01110000000sssssPP1001uu000ddddd | if (Pu.new) Rd = aslh(Rs) + hi->instruction = HEX_INS_A4_PASLHTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = aslh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202800) { + // 01110000001sssssPP1010uu000ddddd | if (!Pu) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = asrh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202c00) { + // 01110000001sssssPP1011uu000ddddd | if (!Pu.new) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = asrh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202000) { + // 01110000001sssssPP1000uu000ddddd | if (Pu) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = asrh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70202400) { + // 01110000001sssssPP1001uu000ddddd | if (Pu.new) Rd = asrh(Rs) + hi->instruction = HEX_INS_A4_PASRHTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = asrh(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02800) { + // 01110000101sssssPP1010uu000ddddd | if (!Pu) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = sxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02c00) { + // 01110000101sssssPP1011uu000ddddd | if (!Pu.new) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = sxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02000) { + // 01110000101sssssPP1000uu000ddddd | if (Pu) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = sxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70a02400) { + // 01110000101sssssPP1001uu000ddddd | if (Pu.new) Rd = sxtb(Rs) + hi->instruction = HEX_INS_A4_PSXTBTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = sxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02800) { + // 01110000111sssssPP1010uu000ddddd | if (!Pu) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = sxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02c00) { + // 01110000111sssssPP1011uu000ddddd | if (!Pu.new) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = sxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02000) { + // 01110000111sssssPP1000uu000ddddd | if (Pu) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = sxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70e02400) { + // 01110000111sssssPP1001uu000ddddd | if (Pu.new) Rd = sxth(Rs) + hi->instruction = HEX_INS_A4_PSXTHTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = sxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802800) { + // 01110000100sssssPP1010uu000ddddd | if (!Pu) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = zxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802c00) { + // 01110000100sssssPP1011uu000ddddd | if (!Pu.new) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = zxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802000) { + // 01110000100sssssPP1000uu000ddddd | if (Pu) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = zxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70802400) { + // 01110000100sssssPP1001uu000ddddd | if (Pu.new) Rd = zxtb(Rs) + hi->instruction = HEX_INS_A4_PZXTBTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = zxtb(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02800) { + // 01110000110sssssPP1010uu000ddddd | if (!Pu) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = zxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02c00) { + // 01110000110sssssPP1011uu000ddddd | if (!Pu.new) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = zxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02000) { + // 01110000110sssssPP1000uu000ddddd | if (Pu) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = zxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x70c02400) { + // 01110000110sssssPP1001uu000ddddd | if (Pu.new) Rd = zxth(Rs) + hi->instruction = HEX_INS_A4_PZXTHTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = zxth(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x73402000) { + // 01110011010sssssPP1iiiiiiiiddddd | Rd = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_A4_RCMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmp.eq(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0x73602000) { + // 01110011011sssssPP1iiiiiiiiddddd | Rd = !cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_A4_RCMPNEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = !cmp.eq(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff902000) == 0x7e800000) { + // 011111101uu0iiiiPP0iiiiiiiiddddd | if (!Pu) Rd = Ii + hi->instruction = HEX_INS_C2_CMOVEIF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff902000) == 0x7e000000) { + // 011111100uu0iiiiPP0iiiiiiiiddddd | if (Pu) Rd = Ii + hi->instruction = HEX_INS_C2_CMOVEIT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff902000) == 0x7e802000) { + // 011111101uu0iiiiPP1iiiiiiiiddddd | if (!Pu.new) Rd = Ii + hi->instruction = HEX_INS_C2_CMOVENEWIF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff902000) == 0x7e002000) { + // 011111100uu0iiiiPP1iiiiiiiiddddd | if (Pu.new) Rd = Ii + hi->instruction = HEX_INS_C2_CMOVENEWIT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf0000) >> 8) | (((hi_u32)&0x1fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc0001c) == 0x75000000) { + // 0111010100isssssPPiiiiiiiii000dd | Pd = cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_C2_CMPEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc0001c) == 0x75400000) { + // 0111010101isssssPPiiiiiiiii000dd | Pd = cmp.gt(Rs,Ii) + hi->instruction = HEX_INS_C2_CMPGTI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0001c) == 0x75800000) { + // 01110101100sssssPPiiiiiiiii000dd | Pd = cmp.gtu(Rs,Ii) + hi->instruction = HEX_INS_C2_CMPGTUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmp.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfe000000) == 0x7a000000) { + // 0111101uuIIIIIIIPPIiiiiiiiiddddd | Rd = mux(Pu,Ii,II) + hi->instruction = HEX_INS_C2_MUXII; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1800000) >> 23); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x7f0000) >> 15) | (((hi_u32)&0x2000) >> 13)); // II + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 7); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = mux(%s,%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), signed_imm[2], signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x73000000) { + // 011100110uusssssPP0iiiiiiiiddddd | Rd = mux(Pu,Rs,Ii) + hi->instruction = HEX_INS_C2_MUXIR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 7)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = mux(%s,%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x73800000) { + // 011100111uusssssPP0iiiiiiiiddddd | Rd = mux(Pu,Ii,Rs) + hi->instruction = HEX_INS_C2_MUXRI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x600000) >> 21); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = mux(%s,%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc0001c) == 0x75400010) { + // 0111010101isssssPPiiiiiiiii100dd | Pd = !cmp.gt(Rs,Ii) + hi->instruction = HEX_INS_C4_CMPLTEI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = !cmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0001c) == 0x75800010) { + // 01110101100sssssPPiiiiiiiii100dd | Pd = !cmp.gtu(Rs,Ii) + hi->instruction = HEX_INS_C4_CMPLTEUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = !cmp.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc0001c) == 0x75000010) { + // 0111010100isssssPPiiiiiiiii100dd | Pd = !cmp.eq(Rs,Ii) + hi->instruction = HEX_INS_C4_CMPNEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = !cmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x8(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe03fe0) == 0x8c800080) { + // 10001100100sssssPP000000100ddddd | Rd = abs(Rs) + hi->instruction = HEX_INS_A2_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = abs(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x808000c0) { + // 10000000100sssssPP000000110ddddd | Rdd = abs(Rss) + hi->instruction = HEX_INS_A2_ABSP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = abs(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c8000a0) { + // 10001100100sssssPP000000101ddddd | Rd = abs(Rs):sat + hi->instruction = HEX_INS_A2_ABSSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = abs(%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x808000a0) { + // 10000000100sssssPP000000101ddddd | Rdd = neg(Rss) + hi->instruction = HEX_INS_A2_NEGP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = neg(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c8000c0) { + // 10001100100sssssPP000000110ddddd | Rd = neg(Rs):sat + hi->instruction = HEX_INS_A2_NEGSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = neg(%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80800080) { + // 10000000100sssssPP000000100ddddd | Rdd = not(Rss) + hi->instruction = HEX_INS_A2_NOTP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = not(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88c00020) { + // 10001000110sssssPP000000001ddddd | Rd = round(Rss):sat + hi->instruction = HEX_INS_A2_ROUNDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = round(%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88c00000) { + // 10001000110sssssPP000000000ddddd | Rd = sat(Rss) + hi->instruction = HEX_INS_A2_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sat(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc000e0) { + // 10001100110sssssPP000000111ddddd | Rd = satb(Rs) + hi->instruction = HEX_INS_A2_SATB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = satb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc00080) { + // 10001100110sssssPP000000100ddddd | Rd = sath(Rs) + hi->instruction = HEX_INS_A2_SATH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sath(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc000c0) { + // 10001100110sssssPP000000110ddddd | Rd = satub(Rs) + hi->instruction = HEX_INS_A2_SATUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = satub(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8cc000a0) { + // 10001100110sssssPP000000101ddddd | Rd = satuh(Rs) + hi->instruction = HEX_INS_A2_SATUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = satuh(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c8000e0) { + // 10001100100sssssPP000000111ddddd | Rd = swiz(Rs) + hi->instruction = HEX_INS_A2_SWIZ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = swiz(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84400000) { + // 10000100010sssssPP000000000ddddd | Rdd = sxtw(Rs) + hi->instruction = HEX_INS_A2_SXTW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sxtw(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80400080) { + // 10000000010sssssPP000000100ddddd | Rdd = vabsh(Rss) + hi->instruction = HEX_INS_A2_VABSH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsh(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x804000a0) { + // 10000000010sssssPP000000101ddddd | Rdd = vabsh(Rss):sat + hi->instruction = HEX_INS_A2_VABSHSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsh(%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x804000c0) { + // 10000000010sssssPP000000110ddddd | Rdd = vabsw(Rss) + hi->instruction = HEX_INS_A2_VABSW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsw(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x804000e0) { + // 10000000010sssssPP000000111ddddd | Rdd = vabsw(Rss):sat + hi->instruction = HEX_INS_A2_VABSWSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsw(%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x808000e0) { + // 10000000100sssssPP000000111ddddd | Rdd = vconj(Rss):sat + hi->instruction = HEX_INS_A2_VCONJ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vconj(%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x88c00080) { + // 10001000110sssssPP0iiiii100ddddd | Rdd = bitsplit(Rs,Ii) + hi->instruction = HEX_INS_A4_BITSPLITI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = bitsplit(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8ce00000) { + // 10001100111sssssPP0iiiii000ddddd | Rd = cround(Rs,Ii) + hi->instruction = HEX_INS_A4_CROUND_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cround(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8ce00080) { + // 10001100111sssssPP0iiiii100ddddd | Rd = round(Rs,Ii) + hi->instruction = HEX_INS_A4_ROUND_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = round(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8ce000c0) { + // 10001100111sssssPP0iiiii110ddddd | Rd = round(Rs,Ii):sat + hi->instruction = HEX_INS_A4_ROUND_RI_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = round(%s,%s0x%x):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x88c000a0) { + // 10001000110sssssPP0iiiii101ddddd | Rd = clip(Rs,Ii) + hi->instruction = HEX_INS_A7_CLIP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = clip(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x8ce00040) { + // 10001100111sssssPPiiiiii010ddddd | Rdd = cround(Rss,Ii) + hi->instruction = HEX_INS_A7_CROUNDD_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cround(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x88c000c0) { + // 10001000110sssssPP0iiiii110ddddd | Rdd = vclip(Rss,Ii) + hi->instruction = HEX_INS_A7_VCLIP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vclip(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000fc) == 0x85800000) { + // 10000101100sssssPPiiiiii000000dd | Pd = bitsclr(Rs,Ii) + hi->instruction = HEX_INS_C2_BITSCLRI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = bitsclr(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3ce0) == 0x86000000) { + // 1000011000000000PP0000tt000ddddd | Rdd = mask(Pt) + hi->instruction = HEX_INS_C2_MASK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mask(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3fe0) == 0x89400000) { + // 10001001010000ssPP000000000ddddd | Rd = Ps + hi->instruction = HEX_INS_C2_TFRPR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ffc) == 0x85400000) { + // 10000101010sssssPP000000000000dd | Pd = Rs + hi->instruction = HEX_INS_C2_TFRRP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3ce0) == 0x89000000) { + // 10001001000000ssPP0000tt000ddddd | Rd = vitpack(Ps,Pt) + hi->instruction = HEX_INS_C2_VITPACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x30000) >> 16); // Ps4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x300) >> 8); // Pt4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vitpack(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_pred_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000fc) == 0x85a00000) { + // 10000101101sssssPPiiiiii000000dd | Pd = !bitsclr(Rs,Ii) + hi->instruction = HEX_INS_C4_NBITSCLRI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = !bitsclr(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00060) { + // 10000000111sssssPP000000011ddddd | Rdd = convert_d2df(Rss) + hi->instruction = HEX_INS_F2_CONV_D2DF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_D2df(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400020) { + // 10001000010sssssPP000000001ddddd | Rd = convert_d2sf(Rss) + hi->instruction = HEX_INS_F2_CONV_D2SF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_D2sf(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00000) { + // 10000000111sssssPP000000000ddddd | Rdd = convert_df2d(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2D; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2d(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e000c0) { + // 10000000111sssssPP000000110ddddd | Rdd = convert_df2d(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2D_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2d(%s):chop", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000020) { + // 10001000000sssssPP000000001ddddd | Rd = convert_df2sf(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2SF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2sf(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00020) { + // 10000000111sssssPP000000001ddddd | Rdd = convert_df2ud(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2UD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2ud(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e000e0) { + // 10000000111sssssPP000000111ddddd | Rdd = convert_df2ud(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2UD_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2ud(%s):chop", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88600020) { + // 10001000011sssssPP000000001ddddd | Rd = convert_df2uw(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2UW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2uw(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88a00020) { + // 10001000101sssssPP000000001ddddd | Rd = convert_df2uw(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2UW_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2uw(%s):chop", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800020) { + // 10001000100sssssPP000000001ddddd | Rd = convert_df2w(Rss) + hi->instruction = HEX_INS_F2_CONV_DF2W; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2w(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88e00020) { + // 10001000111sssssPP000000001ddddd | Rd = convert_df2w(Rss):chop + hi->instruction = HEX_INS_F2_CONV_DF2W_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_df2w(%s):chop", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800080) { + // 10000100100sssssPP000000100ddddd | Rdd = convert_sf2d(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2D; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2d(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x848000c0) { + // 10000100100sssssPP000000110ddddd | Rdd = convert_sf2d(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2D_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2d(%s):chop", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800000) { + // 10000100100sssssPP000000000ddddd | Rdd = convert_sf2df(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2DF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2df(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800060) { + // 10000100100sssssPP000000011ddddd | Rdd = convert_sf2ud(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2UD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2ud(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x848000a0) { + // 10000100100sssssPP000000101ddddd | Rdd = convert_sf2ud(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2UD_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2ud(%s):chop", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b600000) { + // 10001011011sssssPP000000000ddddd | Rd = convert_sf2uw(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2UW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2uw(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b600020) { + // 10001011011sssssPP000000001ddddd | Rd = convert_sf2uw(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2UW_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2uw(%s):chop", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b800000) { + // 10001011100sssssPP000000000ddddd | Rd = convert_sf2w(Rs) + hi->instruction = HEX_INS_F2_CONV_SF2W; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2w(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b800020) { + // 10001011100sssssPP000000001ddddd | Rd = convert_sf2w(Rs):chop + hi->instruction = HEX_INS_F2_CONV_SF2W_CHOP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_sf2w(%s):chop", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80e00040) { + // 10000000111sssssPP000000010ddddd | Rdd = convert_ud2df(Rss) + hi->instruction = HEX_INS_F2_CONV_UD2DF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_ud2df(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88200020) { + // 10001000001sssssPP000000001ddddd | Rd = convert_ud2sf(Rss) + hi->instruction = HEX_INS_F2_CONV_UD2SF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_ud2sf(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800020) { + // 10000100100sssssPP000000001ddddd | Rdd = convert_uw2df(Rs) + hi->instruction = HEX_INS_F2_CONV_UW2DF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_uw2df(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b200000) { + // 10001011001sssssPP000000000ddddd | Rd = convert_uw2sf(Rs) + hi->instruction = HEX_INS_F2_CONV_UW2SF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_uw2sf(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84800040) { + // 10000100100sssssPP000000010ddddd | Rdd = convert_w2df(Rs) + hi->instruction = HEX_INS_F2_CONV_W2DF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_W2df(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8b400000) { + // 10001011010sssssPP000000000ddddd | Rd = convert_w2sf(Rs) + hi->instruction = HEX_INS_F2_CONV_W2SF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = convert_W2sf(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x85e00000) { + // 10000101111sssssPP0iiiii000000dd | Pd = sfclass(Rs,Ii) + hi->instruction = HEX_INS_F2_SFCLASS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = sfclass(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8ba00000) { + // 10001011101sssssPP000000000ddddd | Rd = sffixupr(Rs) + hi->instruction = HEX_INS_F2_SFFIXUPR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sffixupr(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03f80) == 0x8be00000) { + // 10001011111sssssPP0000000eeddddd | Rd,Pe = sfinvsqrta(Rs) + hi->instruction = HEX_INS_F2_SFINVSQRTA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s,%s = sfinvsqrta(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x80000040) { + // 10000000000sssssPPiiiiii010ddddd | Rdd = asl(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asl(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x820000c0) { + // 10000010000sssssPPiiiiii110xxxxx | Rxx += asl(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += asl(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82400040) { + // 10000010010sssssPPiiiiii010xxxxx | Rxx &= asl(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= asl(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82000040) { + // 10000010000sssssPPiiiiii010xxxxx | Rxx -= asl(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= asl(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x824000c0) { + // 10000010010sssssPPiiiiii110xxxxx | Rxx |= asl(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= asl(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82800040) { + // 10000010100sssssPPiiiiii010xxxxx | Rxx ^= asl(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_P_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s ^= asl(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000040) { + // 10001100000sssssPP0iiiii010ddddd | Rd = asl(Rs,Ii) + hi->instruction = HEX_INS_S2_ASL_I_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asl(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e0000c0) { + // 10001110000sssssPP0iiiii110xxxxx | Rx += asl(Rs,Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += asl(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400040) { + // 10001110010sssssPP0iiiii010xxxxx | Rx &= asl(Rs,Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= asl(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000040) { + // 10001110000sssssPP0iiiii010xxxxx | Rx -= asl(Rs,Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= asl(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e4000c0) { + // 10001110010sssssPP0iiiii110xxxxx | Rx |= asl(Rs,Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= asl(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8c400040) { + // 10001100010sssssPP0iiiii010ddddd | Rd = asl(Rs,Ii):sat + hi->instruction = HEX_INS_S2_ASL_I_R_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asl(%s,%s0x%x):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e800040) { + // 10001110100sssssPP0iiiii010xxxxx | Rx ^= asl(Rs,Ii) + hi->instruction = HEX_INS_S2_ASL_I_R_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s ^= asl(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe030e0) == 0x80800040) { + // 10000000100sssssPP00iiii010ddddd | Rdd = vaslh(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vaslh(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x80400040) { + // 10000000010sssssPP0iiiii010ddddd | Rdd = vaslw(Rss,Ii) + hi->instruction = HEX_INS_S2_ASL_I_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vaslw(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x80000000) { + // 10000000000sssssPPiiiiii000ddddd | Rdd = asr(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82000080) { + // 10000010000sssssPPiiiiii100xxxxx | Rxx += asr(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += asr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82400000) { + // 10000010010sssssPPiiiiii000xxxxx | Rxx &= asr(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= asr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82000000) { + // 10000010000sssssPPiiiiii000xxxxx | Rxx -= asr(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= asr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82400080) { + // 10000010010sssssPPiiiiii100xxxxx | Rxx |= asr(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= asr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x80c000e0) { + // 10000000110sssssPPiiiiii111ddddd | Rdd = asr(Rss,Ii):rnd + hi->instruction = HEX_INS_S2_ASR_I_P_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asr(%s,%s0x%x):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000000) { + // 10001100000sssssPP0iiiii000ddddd | Rd = asr(Rs,Ii) + hi->instruction = HEX_INS_S2_ASR_I_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000080) { + // 10001110000sssssPP0iiiii100xxxxx | Rx += asr(Rs,Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += asr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400000) { + // 10001110010sssssPP0iiiii000xxxxx | Rx &= asr(Rs,Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= asr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000000) { + // 10001110000sssssPP0iiiii000xxxxx | Rx -= asr(Rs,Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= asr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400080) { + // 10001110010sssssPP0iiiii100xxxxx | Rx |= asr(Rs,Ii) + hi->instruction = HEX_INS_S2_ASR_I_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= asr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8c400000) { + // 10001100010sssssPP0iiiii000ddddd | Rd = asr(Rs,Ii):rnd + hi->instruction = HEX_INS_S2_ASR_I_R_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = asr(%s,%s0x%x):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x88c00040) { + // 10001000110sssssPP0iiiii010ddddd | Rd = vasrw(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_SVW_TRUN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vasrw(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe030e0) == 0x80800000) { + // 10000000100sssssPP00iiii000ddddd | Rdd = vasrh(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vasrh(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x80400000) { + // 10000000010sssssPP0iiiii000ddddd | Rdd = vasrw(Rss,Ii) + hi->instruction = HEX_INS_S2_ASR_I_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vasrw(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c4000c0) { + // 10001100010sssssPP000000110ddddd | Rd = brev(Rs) + hi->instruction = HEX_INS_S2_BREV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = brev(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80c000c0) { + // 10000000110sssssPP000000110ddddd | Rdd = brev(Rss) + hi->instruction = HEX_INS_S2_BREVP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = brev(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c0000a0) { + // 10001100000sssssPP000000101ddddd | Rd = cl0(Rs) + hi->instruction = HEX_INS_S2_CL0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cl0(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400040) { + // 10001000010sssssPP000000010ddddd | Rd = cl0(Rss) + hi->instruction = HEX_INS_S2_CL0P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cl0(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c0000c0) { + // 10001100000sssssPP000000110ddddd | Rd = cl1(Rs) + hi->instruction = HEX_INS_S2_CL1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cl1(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400080) { + // 10001000010sssssPP000000100ddddd | Rd = cl1(Rss) + hi->instruction = HEX_INS_S2_CL1P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cl1(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c000080) { + // 10001100000sssssPP000000100ddddd | Rd = clb(Rs) + hi->instruction = HEX_INS_S2_CLB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = clb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c0000e0) { + // 10001100000sssssPP000000111ddddd | Rd = normamt(Rs) + hi->instruction = HEX_INS_S2_CLBNORM; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = normamt(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88400000) { + // 10001000010sssssPP000000000ddddd | Rd = clb(Rss) + hi->instruction = HEX_INS_S2_CLBP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = clb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8cc00020) { + // 10001100110sssssPP0iiiii001ddddd | Rd = clrbit(Rs,Ii) + hi->instruction = HEX_INS_S2_CLRBIT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = clrbit(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c400080) { + // 10001100010sssssPP000000100ddddd | Rd = ct0(Rs) + hi->instruction = HEX_INS_S2_CT0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = ct0(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88e00040) { + // 10001000111sssssPP000000010ddddd | Rd = ct0(Rss) + hi->instruction = HEX_INS_S2_CT0P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = ct0(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c4000a0) { + // 10001100010sssssPP000000101ddddd | Rd = ct1(Rs) + hi->instruction = HEX_INS_S2_CT1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = ct1(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88e00080) { + // 10001000111sssssPP000000100ddddd | Rd = ct1(Rss) + hi->instruction = HEX_INS_S2_CT1P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = ct1(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80c00080) { + // 10000000110sssssPP000000100ddddd | Rdd = deinterleave(Rss) + hi->instruction = HEX_INS_S2_DEINTERLEAVE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = deinterleave(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x8d000000) { + // 100011010IIsssssPP0iiiiiIIIddddd | Rd = extractu(Rs,Ii,II) + hi->instruction = HEX_INS_S2_EXTRACTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = extractu(%s,%s0x%x,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000000) == 0x81000000) { + // 10000001IIIsssssPPiiiiiiIIIddddd | Rdd = extractu(Rss,Ii,II) + hi->instruction = HEX_INS_S2_EXTRACTUP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xe00000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = extractu(%s,%s0x%x,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x8f000000) { + // 100011110IIsssssPP0iiiiiIIIxxxxx | Rx = insert(Rs,Ii,II) + hi->instruction = HEX_INS_S2_INSERT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = insert(%s,%s0x%x,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000000) == 0x83000000) { + // 10000011IIIsssssPPiiiiiiIIIxxxxx | Rxx = insert(Rss,Ii,II) + hi->instruction = HEX_INS_S2_INSERTP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xe00000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = insert(%s,%s0x%x,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80c000a0) { + // 10000000110sssssPP000000101ddddd | Rdd = interleave(Rss) + hi->instruction = HEX_INS_S2_INTERLEAVE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = interleave(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x80000020) { + // 10000000000sssssPPiiiiii001ddddd | Rdd = lsr(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = lsr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x820000a0) { + // 10000010000sssssPPiiiiii101xxxxx | Rxx += lsr(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += lsr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82400020) { + // 10000010010sssssPPiiiiii001xxxxx | Rxx &= lsr(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= lsr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82000020) { + // 10000010000sssssPPiiiiii001xxxxx | Rxx -= lsr(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= lsr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x824000a0) { + // 10000010010sssssPPiiiiii101xxxxx | Rxx |= lsr(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= lsr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82800020) { + // 10000010100sssssPPiiiiii001xxxxx | Rxx ^= lsr(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_P_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s ^= lsr(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000020) { + // 10001100000sssssPP0iiiii001ddddd | Rd = lsr(Rs,Ii) + hi->instruction = HEX_INS_S2_LSR_I_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = lsr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e0000a0) { + // 10001110000sssssPP0iiiii101xxxxx | Rx += lsr(Rs,Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += lsr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400020) { + // 10001110010sssssPP0iiiii001xxxxx | Rx &= lsr(Rs,Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= lsr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000020) { + // 10001110000sssssPP0iiiii001xxxxx | Rx -= lsr(Rs,Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= lsr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e4000a0) { + // 10001110010sssssPP0iiiii101xxxxx | Rx |= lsr(Rs,Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= lsr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e800020) { + // 10001110100sssssPP0iiiii001xxxxx | Rx ^= lsr(Rs,Ii) + hi->instruction = HEX_INS_S2_LSR_I_R_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s ^= lsr(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe030e0) == 0x80800020) { + // 10000000100sssssPP00iiii001ddddd | Rdd = vlsrh(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vlsrh(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x80400020) { + // 10000000010sssssPP0iiiii001ddddd | Rdd = vlsrw(Rss,Ii) + hi->instruction = HEX_INS_S2_LSR_I_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vlsrw(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff9f2000) == 0x8d002000) { + // 100011010II00000PP1iiiiiIIIddddd | Rd = mask(Ii,II) + hi->instruction = HEX_INS_S2_MASK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = mask(%s0x%x,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8cc00000) { + // 10001100110sssssPP0iiiii000ddddd | Rd = setbit(Rs,Ii) + hi->instruction = HEX_INS_S2_SETBIT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = setbit(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c800000) { + // 10001100100sssssPP000000000ddddd | Rd = vsathb(Rs) + hi->instruction = HEX_INS_S2_SVSATHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsathb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c800040) { + // 10001100100sssssPP000000010ddddd | Rd = vsathub(Rs) + hi->instruction = HEX_INS_S2_SVSATHUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsathub(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x87000000) { + // 1000011100isssssPPIIIIIIiiixxxxx | Rx = tableidxb(Rs,Ii,II):raw + hi->instruction = HEX_INS_S2_TABLEIDXB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = tableidxb(%s,%s0x%x,%s):raw", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x87c00000) { + // 1000011111isssssPPIIIIIIiiixxxxx | Rx = tableidxd(Rs,Ii,II):raw + hi->instruction = HEX_INS_S2_TABLEIDXD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = tableidxd(%s,%s0x%x,%s):raw", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x87400000) { + // 1000011101isssssPPIIIIIIiiixxxxx | Rx = tableidxh(Rs,Ii,II):raw + hi->instruction = HEX_INS_S2_TABLEIDXH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = tableidxh(%s,%s0x%x,%s):raw", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0x87800000) { + // 1000011110isssssPPIIIIIIiiixxxxx | Rx = tableidxw(Rs,Ii,II):raw + hi->instruction = HEX_INS_S2_TABLEIDXW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 18) | (((hi_u32)&0xe0) >> 5)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x3f00) >> 8); // II + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = tableidxw(%s,%s0x%x,%s):raw", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8cc00040) { + // 10001100110sssssPP0iiiii010ddddd | Rd = togglebit(Rs,Ii) + hi->instruction = HEX_INS_S2_TOGGLEBIT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = togglebit(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x85000000) { + // 10000101000sssssPP0iiiii000000dd | Pd = tstbit(Rs,Ii) + hi->instruction = HEX_INS_S2_TSTBIT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = tstbit(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800080) { + // 10001000100sssssPP000000100ddddd | Rd = vrndwh(Rss) + hi->instruction = HEX_INS_S2_VRNDPACKWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrndwh(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x888000c0) { + // 10001000100sssssPP000000110ddddd | Rd = vrndwh(Rss):sat + hi->instruction = HEX_INS_S2_VRNDPACKWHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrndwh(%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x880000c0) { + // 10001000000sssssPP000000110ddddd | Rd = vsathb(Rss) + hi->instruction = HEX_INS_S2_VSATHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsathb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x800000e0) { + // 10000000000sssssPP000000111ddddd | Rdd = vsathb(Rss) + hi->instruction = HEX_INS_S2_VSATHB_NOPACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsathb(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000000) { + // 10001000000sssssPP000000000ddddd | Rd = vsathub(Rss) + hi->instruction = HEX_INS_S2_VSATHUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsathub(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x80000080) { + // 10000000000sssssPP000000100ddddd | Rdd = vsathub(Rss) + hi->instruction = HEX_INS_S2_VSATHUB_NOPACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsathub(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000040) { + // 10001000000sssssPP000000010ddddd | Rd = vsatwh(Rss) + hi->instruction = HEX_INS_S2_VSATWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsatwh(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x800000c0) { + // 10000000000sssssPP000000110ddddd | Rdd = vsatwh(Rss) + hi->instruction = HEX_INS_S2_VSATWH_NOPACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsatwh(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88000080) { + // 10001000000sssssPP000000100ddddd | Rd = vsatwuh(Rss) + hi->instruction = HEX_INS_S2_VSATWUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsatwuh(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x800000a0) { + // 10000000000sssssPP000000101ddddd | Rdd = vsatwuh(Rss) + hi->instruction = HEX_INS_S2_VSATWUH_NOPACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsatwuh(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x8c4000e0) { + // 10001100010sssssPP000000111ddddd | Rd = vsplatb(Rs) + hi->instruction = HEX_INS_S2_VSPLATRB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsplatb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84400040) { + // 10000100010sssssPP000000010ddddd | Rdd = vsplath(Rs) + hi->instruction = HEX_INS_S2_VSPLATRH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsplath(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84000000) { + // 10000100000sssssPP000000000ddddd | Rdd = vsxtbh(Rs) + hi->instruction = HEX_INS_S2_VSXTBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsxtbh(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84000080) { + // 10000100000sssssPP000000100ddddd | Rdd = vsxthw(Rs) + hi->instruction = HEX_INS_S2_VSXTHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsxthw(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800040) { + // 10001000100sssssPP000000010ddddd | Rd = vtrunehb(Rss) + hi->instruction = HEX_INS_S2_VTRUNEHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vtrunehb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88800000) { + // 10001000100sssssPP000000000ddddd | Rd = vtrunohb(Rss) + hi->instruction = HEX_INS_S2_VTRUNOHB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vtrunohb(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84000040) { + // 10000100000sssssPP000000010ddddd | Rdd = vzxtbh(Rs) + hi->instruction = HEX_INS_S2_VZXTBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vzxtbh(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x840000c0) { + // 10000100000sssssPP000000110ddddd | Rdd = vzxthw(Rs) + hi->instruction = HEX_INS_S2_VZXTHW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vzxthw(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x8c200000) { + // 10001100001sssssPPiiiiii000ddddd | Rd = add(clb(Rs),Ii) + hi->instruction = HEX_INS_S4_CLBADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(clb(%s),%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x88600040) { + // 10001000011sssssPPiiiiii010ddddd | Rd = add(clb(Rss),Ii) + hi->instruction = HEX_INS_S4_CLBPADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(clb(%s),%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88600000) { + // 10001000011sssssPP000000000ddddd | Rd = normamt(Rss) + hi->instruction = HEX_INS_S4_CLBPNORM; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = normamt(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff802000) == 0x8d800000) { + // 100011011IIsssssPP0iiiiiIIIddddd | Rd = extract(Rs,Ii,II) + hi->instruction = HEX_INS_S4_EXTRACT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = extract(%s,%s0x%x,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000000) == 0x8a000000) { + // 10001010IIIsssssPPiiiiiiIIIddddd | Rdd = extract(Rss,Ii,II) + hi->instruction = HEX_INS_S4_EXTRACTP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xe00000) >> 18) | (((hi_u32)&0xe0) >> 5)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = extract(%s,%s0x%x,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0x85200000) { + // 10000101001sssssPP0iiiii000000dd | Pd = !tstbit(Rs,Ii) + hi->instruction = HEX_INS_S4_NTSTBIT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = !tstbit(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe030e0) == 0x88600080) { + // 10001000011sssssPP00iiii100ddddd | Rd = vasrhub(Rss,Ii):raw + hi->instruction = HEX_INS_S5_ASRHUB_RND_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vasrhub(%s,%s0x%x):raw", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe030e0) == 0x886000a0) { + // 10001000011sssssPP00iiii101ddddd | Rd = vasrhub(Rss,Ii):sat + hi->instruction = HEX_INS_S5_ASRHUB_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vasrhub(%s,%s0x%x):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x88600060) { + // 10001000011sssssPP000000011ddddd | Rd = popcount(Rss) + hi->instruction = HEX_INS_S5_POPCOUNTP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = popcount(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe030e0) == 0x80200000) { + // 10000000001sssssPP00iiii000ddddd | Rdd = vasrh(Rss,Ii):raw + hi->instruction = HEX_INS_S5_VASRHRND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xf00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vasrh(%s,%s0x%x):raw", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x80000060) { + // 10000000000sssssPPiiiiii011ddddd | Rdd = rol(Rss,Ii) + hi->instruction = HEX_INS_S6_ROL_I_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = rol(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x820000e0) { + // 10000010000sssssPPiiiiii111xxxxx | Rxx += rol(Rss,Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += rol(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82400060) { + // 10000010010sssssPPiiiiii011xxxxx | Rxx &= rol(Rss,Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= rol(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82000060) { + // 10000010000sssssPPiiiiii011xxxxx | Rxx -= rol(Rss,Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= rol(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x824000e0) { + // 10000010010sssssPPiiiiii111xxxxx | Rxx |= rol(Rss,Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= rol(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000e0) == 0x82800060) { + // 10000010100sssssPPiiiiii011xxxxx | Rxx ^= rol(Rss,Ii) + hi->instruction = HEX_INS_S6_ROL_I_P_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s ^= rol(%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8c000060) { + // 10001100000sssssPP0iiiii011ddddd | Rd = rol(Rs,Ii) + hi->instruction = HEX_INS_S6_ROL_I_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = rol(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e0000e0) { + // 10001110000sssssPP0iiiii111xxxxx | Rx += rol(Rs,Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += rol(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e400060) { + // 10001110010sssssPP0iiiii011xxxxx | Rx &= rol(Rs,Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s &= rol(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e000060) { + // 10001110000sssssPP0iiiii011xxxxx | Rx -= rol(Rs,Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= rol(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e4000e0) { + // 10001110010sssssPP0iiiii111xxxxx | Rx |= rol(Rs,Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= rol(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x8e800060) { + // 10001110100sssssPP0iiiii011xxxxx | Rx ^= rol(Rs,Ii) + hi->instruction = HEX_INS_S6_ROL_I_R_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1f00) >> 8); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s ^= rol(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x84400080) { + // 10000100010sssssPP000000100ddddd | Rdd = vsplatb(Rs) + hi->instruction = HEX_INS_S6_VSPLATRBP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsplatb(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0x9(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe03fe0) == 0x90000000) { + // 10010000000sssssPP000000000ddddd | Rdd = deallocframe(Rs):raw + hi->instruction = HEX_INS_L2_DEALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = deallocframe(%s):raw", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x90800000) { + // 10010ii0100sssssPPiiiiiiiiiyyyyy | Ryy = memb_fifo(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADALIGNB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s+%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e800000) { + // 10011110100xxxxxPPu00000000yyyyy | Ryy = memb_fifo(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADALIGNB_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s++%s:brev)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x98800000) { + // 10011000100xxxxxPPu0000iiiiyyyyy | Ryy = memb_fifo(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNB_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s++%s:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x98800200) { + // 10011000100xxxxxPPu00010000yyyyy | Ryy = memb_fifo(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNB_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s++I:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9a800000) { + // 10011010100xxxxxPP00000iiiiyyyyy | Ryy = memb_fifo(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADALIGNB_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c800000) { + // 10011100100xxxxxPPu00000000yyyyy | Ryy = memb_fifo(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADALIGNB_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x90400000) { + // 10010ii0010sssssPPiiiiiiiiiyyyyy | Ryy = memh_fifo(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADALIGNH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s+%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e400000) { + // 10011110010xxxxxPPu00000000yyyyy | Ryy = memh_fifo(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADALIGNH_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s++%s:brev)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x98400000) { + // 10011000010xxxxxPPu0000iiiiyyyyy | Ryy = memh_fifo(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNH_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s++%s:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x98400200) { + // 10011000010xxxxxPPu00010000yyyyy | Ryy = memh_fifo(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADALIGNH_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s++I:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9a400000) { + // 10011010010xxxxxPP00000iiiiyyyyy | Ryy = memh_fifo(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADALIGNH_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c400000) { + // 10011100010xxxxxPPu00000000yyyyy | Ryy = memh_fifo(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADALIGNH_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x90200000) { + // 10010ii0001sssssPPiiiiiiiiiddddd | Rd = membh(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADBSW2_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e200000) { + // 10011110001xxxxxPPu00000000ddddd | Rd = membh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBSW2_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = membh(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x98200000) { + // 10011000001xxxxxPPu0000iiiiddddd | Rd = membh(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW2_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x98200200) { + // 10011000001xxxxxPPu00010000ddddd | Rd = membh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW2_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = membh(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9a200000) { + // 10011010001xxxxxPP00000iiiiddddd | Rd = membh(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADBSW2_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c200000) { + // 10011100001xxxxxPPu00000000ddddd | Rd = membh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBSW2_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = membh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x90e00000) { + // 10010ii0111sssssPPiiiiiiiiiddddd | Rdd = membh(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADBSW4_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 12)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 12); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s+%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ee00000) { + // 10011110111xxxxxPPu00000000ddddd | Rdd = membh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBSW4_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = membh(%s++%s:brev)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x98e00000) { + // 10011000111xxxxxPPu0000iiiiddddd | Rdd = membh(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW4_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s++%s:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x98e00200) { + // 10011000111xxxxxPPu00010000ddddd | Rdd = membh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBSW4_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = membh(%s++I:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9ae00000) { + // 10011010111xxxxxPP00000iiiiddddd | Rdd = membh(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADBSW4_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ce00000) { + // 10011100111xxxxxPPu00000000ddddd | Rdd = membh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBSW4_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = membh(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x90600000) { + // 10010ii0011sssssPPiiiiiiiiiddddd | Rd = memubh(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADBZW2_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9e600000) { + // 10011110011xxxxxPPu00000000ddddd | Rd = memubh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBZW2_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x98600000) { + // 10011000011xxxxxPPu0000iiiiddddd | Rd = memubh(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW2_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x98600200) { + // 10011000011xxxxxPPu00010000ddddd | Rd = memubh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW2_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memubh(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9a600000) { + // 10011010011xxxxxPP00000iiiiddddd | Rd = memubh(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADBZW2_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9c600000) { + // 10011100011xxxxxPPu00000000ddddd | Rd = memubh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBZW2_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x90a00000) { + // 10010ii0101sssssPPiiiiiiiiiddddd | Rdd = memubh(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADBZW4_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 12)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 12); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s+%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ea00000) { + // 10011110101xxxxxPPu00000000ddddd | Rdd = memubh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADBZW4_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s:brev)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x98a00000) { + // 10011000101xxxxxPPu0000iiiiddddd | Rdd = memubh(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW4_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x98a00200) { + // 10011000101xxxxxPPu00010000ddddd | Rdd = memubh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADBZW4_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memubh(%s++I:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9aa00000) { + // 10011010101xxxxxPP00000iiiiddddd | Rdd = memubh(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADBZW4_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9ca00000) { + // 10011100101xxxxxPPu00000000ddddd | Rdd = memubh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADBZW4_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memubh(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x91000000) { + // 10010ii1000sssssPPiiiiiiiiiddddd | Rd = memb(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADRB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f000000) { + // 10011111000xxxxxPPu00000000ddddd | Rd = memb(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRB_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memb(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x99000000) { + // 10011001000xxxxxPPu0000iiiiddddd | Rd = memb(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRB_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x99000200) { + // 10011001000xxxxxPPu00010000ddddd | Rd = memb(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRB_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memb(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9b000000) { + // 10011011000xxxxxPP00000iiiiddddd | Rd = memb(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADRB_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d000000) { + // 10011101000xxxxxPPu00000000ddddd | Rd = memb(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRB_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memb(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x91c00000) { + // 10010ii1110sssssPPiiiiiiiiiddddd | Rdd = memd(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADRD_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 13)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 13); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s+%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9fc00000) { + // 10011111110xxxxxPPu00000000ddddd | Rdd = memd(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRD_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memd(%s++%s:brev)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x99c00000) { + // 10011001110xxxxxPPu0000iiiiddddd | Rdd = memd(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRD_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s++%s:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x99c00200) { + // 10011001110xxxxxPPu00010000ddddd | Rdd = memd(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRD_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memd(%s++I:circ(%s))", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9bc00000) { + // 10011011110xxxxxPP00000iiiiddddd | Rdd = memd(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADRD_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9dc00000) { + // 10011101110xxxxxPPu00000000ddddd | Rdd = memd(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRD_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memd(%s++%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x91400000) { + // 10010ii1010sssssPPiiiiiiiiiddddd | Rd = memh(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADRH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f400000) { + // 10011111010xxxxxPPu00000000ddddd | Rd = memh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRH_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memh(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x99400000) { + // 10011001010xxxxxPPu0000iiiiddddd | Rd = memh(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRH_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x99400200) { + // 10011001010xxxxxPPu00010000ddddd | Rd = memh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRH_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memh(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9b400000) { + // 10011011010xxxxxPP00000iiiiddddd | Rd = memh(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADRH_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d400000) { + // 10011101010xxxxxPPu00000000ddddd | Rd = memh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRH_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x91800000) { + // 10010ii1100sssssPPiiiiiiiiiddddd | Rd = memw(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADRI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 12)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 12); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f800000) { + // 10011111100xxxxxPPu00000000ddddd | Rd = memw(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRI_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memw(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x99800000) { + // 10011001100xxxxxPPu0000iiiiddddd | Rd = memw(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRI_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x99800200) { + // 10011001100xxxxxPPu00010000ddddd | Rd = memw(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRI_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memw(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9b800000) { + // 10011011100xxxxxPP00000iiiiddddd | Rd = memw(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADRI_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d800000) { + // 10011101100xxxxxPPu00000000ddddd | Rd = memw(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRI_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memw(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x91200000) { + // 10010ii1001sssssPPiiiiiiiiiddddd | Rd = memub(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADRUB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 10)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f200000) { + // 10011111001xxxxxPPu00000000ddddd | Rd = memub(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRUB_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memub(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x99200000) { + // 10011001001xxxxxPPu0000iiiiddddd | Rd = memub(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUB_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x99200200) { + // 10011001001xxxxxPPu00010000ddddd | Rd = memub(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUB_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memub(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9b200000) { + // 10011011001xxxxxPP00000iiiiddddd | Rd = memub(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADRUB_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d200000) { + // 10011101001xxxxxPPu00000000ddddd | Rd = memub(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRUB_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memub(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0x91600000) { + // 10010ii1011sssssPPiiiiiiiiiddddd | Rd = memuh(Rs+Ii) + hi->instruction = HEX_INS_L2_LOADRUH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x3fe0) >> 5)) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 11)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s+%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9f600000) { + // 10011111011xxxxxPPu00000000ddddd | Rd = memuh(Rx++Mu:brev) + hi->instruction = HEX_INS_L2_LOADRUH_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memuh(%s++%s:brev)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01e00) == 0x99600000) { + // 10011001011xxxxxPPu0000iiiiddddd | Rd = memuh(Rx++Ii:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUH_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s++%s:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_mod_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x99600200) { + // 10011001011xxxxxPPu00010000ddddd | Rd = memuh(Rx++I:circ(Mu)) + hi->instruction = HEX_INS_L2_LOADRUH_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memuh(%s++I:circ(%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03e00) == 0x9b600000) { + // 10011011011xxxxxPP00000iiiiddddd | Rd = memuh(Rx++Ii) + hi->instruction = HEX_INS_L2_LOADRUH_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01fe0) == 0x9d600000) { + // 10011101011xxxxxPPu00000000ddddd | Rd = memuh(Rx++Mu) + hi->instruction = HEX_INS_L2_LOADRUH_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memuh(%s++%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x92000800) { + // 10010010000sssssPP001000000ddddd | Rd = memw_aq(Rs) + hi->instruction = HEX_INS_L2_LOADW_AQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memw_aq(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x92000000) { + // 10010010000sssssPP000000000ddddd | Rd = memw_locked(Rs) + hi->instruction = HEX_INS_L2_LOADW_LOCKED; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memw_locked(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b002800) { + // 10011011000xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memb(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRBF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memb(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b003800) { + // 10011011000xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memb(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRBFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memb(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b002000) { + // 10011011000xxxxxPP100ttiiiiddddd | if (Pt) Rd = memb(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRBT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memb(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b003000) { + // 10011011000xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memb(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRBTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memb(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9bc02800) { + // 10011011110xxxxxPP101ttiiiiddddd | if (!Pt) Rdd = memd(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRDF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memd(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9bc03800) { + // 10011011110xxxxxPP111ttiiiiddddd | if (!Pt.new) Rdd = memd(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRDFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memd(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9bc02000) { + // 10011011110xxxxxPP100ttiiiiddddd | if (Pt) Rdd = memd(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRDT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memd(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9bc03000) { + // 10011011110xxxxxPP110ttiiiiddddd | if (Pt.new) Rdd = memd(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRDTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 3; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 3; + if (hi->ops[3].op.imm & (1 << 6)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memd(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b402800) { + // 10011011010xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRHF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b403800) { + // 10011011010xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRHFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b402000) { + // 10011011010xxxxxPP100ttiiiiddddd | if (Pt) Rd = memh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRHT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b403000) { + // 10011011010xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRHTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b802800) { + // 10011011100xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memw(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRIF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memw(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b803800) { + // 10011011100xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memw(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRIFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memw(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b802000) { + // 10011011100xxxxxPP100ttiiiiddddd | if (Pt) Rd = memw(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRIT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memw(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b803000) { + // 10011011100xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memw(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRITNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 2; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 2; + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memw(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b202800) { + // 10011011001xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memub(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUBF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memub(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b203800) { + // 10011011001xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memub(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUBFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memub(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b202000) { + // 10011011001xxxxxPP100ttiiiiddddd | if (Pt) Rd = memub(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUBT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memub(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b203000) { + // 10011011001xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memub(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUBTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5); // Ii + if (hi->ops[3].op.imm & (1 << 3)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memub(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b602800) { + // 10011011011xxxxxPP101ttiiiiddddd | if (!Pt) Rd = memuh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUHF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memuh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b603800) { + // 10011011011xxxxxPP111ttiiiiddddd | if (!Pt.new) Rd = memuh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUHFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memuh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b602000) { + // 10011011011xxxxxPP100ttiiiiddddd | if (Pt) Rd = memuh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUHT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memuh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x9b603000) { + // 10011011011xxxxxPP110ttiiiiddddd | if (Pt.new) Rd = memuh(Rx++Ii) + hi->instruction = HEX_INS_L2_PLOADRUHTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1e0) >> 5) << 1; // scaled Ii + hi->ops[3].attr = HEX_OP_IMM_SCALED; + hi->ops[3].shift = 1; + if (hi->ops[3].op.imm & (1 << 4)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memuh(%s++%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9a801000) { + // 10011010100eeeeePP01IIII0IIyyyyy | Ryy = memb_fifo(Re=II) + hi->instruction = HEX_INS_L4_LOADALIGNB_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s=%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9c801000) { + // 10011100100tttttPPi1IIIIiIIyyyyy | Ryy = memb_fifo(Rt<instruction = HEX_INS_L4_LOADALIGNB_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memb_fifo(%s<<%s0x%x+%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9a401000) { + // 10011010010eeeeePP01IIII0IIyyyyy | Ryy = memh_fifo(Re=II) + hi->instruction = HEX_INS_L4_LOADALIGNH_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s=%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9c401000) { + // 10011100010tttttPPi1IIIIiIIyyyyy | Ryy = memh_fifo(Rt<instruction = HEX_INS_L4_LOADALIGNH_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Ryy32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memh_fifo(%s<<%s0x%x+%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9a201000) { + // 10011010001eeeeePP01IIII0IIddddd | Rd = membh(Re=II) + hi->instruction = HEX_INS_L4_LOADBSW2_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9c201000) { + // 10011100001tttttPPi1IIIIiIIddddd | Rd = membh(Rt<instruction = HEX_INS_L4_LOADBSW2_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9ae01000) { + // 10011010111eeeeePP01IIII0IIddddd | Rdd = membh(Re=II) + hi->instruction = HEX_INS_L4_LOADBSW4_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s=%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9ce01000) { + // 10011100111tttttPPi1IIIIiIIddddd | Rdd = membh(Rt<instruction = HEX_INS_L4_LOADBSW4_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = membh(%s<<%s0x%x+%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9a601000) { + // 10011010011eeeeePP01IIII0IIddddd | Rd = memubh(Re=II) + hi->instruction = HEX_INS_L4_LOADBZW2_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9c601000) { + // 10011100011tttttPPi1IIIIiIIddddd | Rd = memubh(Rt<instruction = HEX_INS_L4_LOADBZW2_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9aa01000) { + // 10011010101eeeeePP01IIII0IIddddd | Rdd = memubh(Re=II) + hi->instruction = HEX_INS_L4_LOADBZW4_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s=%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9ca01000) { + // 10011100101tttttPPi1IIIIiIIddddd | Rdd = memubh(Rt<instruction = HEX_INS_L4_LOADBZW4_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memubh(%s<<%s0x%x+%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x92001800) { + // 10010010000sssssPP011000000ddddd | Rdd = memd_aq(Rs) + hi->instruction = HEX_INS_L4_LOADD_AQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memd_aq(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x92001000) { + // 10010010000sssssPP010000000ddddd | Rdd = memd_locked(Rs) + hi->instruction = HEX_INS_L4_LOADD_LOCKED; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memd_locked(%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9b001000) { + // 10011011000eeeeePP01IIII0IIddddd | Rd = memb(Re=II) + hi->instruction = HEX_INS_L4_LOADRB_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9d001000) { + // 10011101000tttttPPi1IIIIiIIddddd | Rd = memb(Rt<instruction = HEX_INS_L4_LOADRB_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memb(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9bc01000) { + // 10011011110eeeeePP01IIII0IIddddd | Rdd = memd(Re=II) + hi->instruction = HEX_INS_L4_LOADRD_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s=%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9dc01000) { + // 10011101110tttttPPi1IIIIiIIddddd | Rdd = memd(Rt<instruction = HEX_INS_L4_LOADRD_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memd(%s<<%s0x%x+%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9b401000) { + // 10011011010eeeeePP01IIII0IIddddd | Rd = memh(Re=II) + hi->instruction = HEX_INS_L4_LOADRH_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9d401000) { + // 10011101010tttttPPi1IIIIiIIddddd | Rd = memh(Rt<instruction = HEX_INS_L4_LOADRH_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memh(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9b801000) { + // 10011011100eeeeePP01IIII0IIddddd | Rd = memw(Re=II) + hi->instruction = HEX_INS_L4_LOADRI_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9d801000) { + // 10011101100tttttPPi1IIIIiIIddddd | Rd = memw(Rt<instruction = HEX_INS_L4_LOADRI_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memw(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9b201000) { + // 10011011001eeeeePP01IIII0IIddddd | Rd = memub(Re=II) + hi->instruction = HEX_INS_L4_LOADRUB_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9d201000) { + // 10011101001tttttPPi1IIIIiIIddddd | Rd = memub(Rt<instruction = HEX_INS_L4_LOADRUB_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memub(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03080) == 0x9b601000) { + // 10011011011eeeeePP01IIII0IIddddd | Rd = memuh(Re=II) + hi->instruction = HEX_INS_L4_LOADRUH_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s=%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01000) == 0x9d601000) { + // 10011101011tttttPPi1IIIIiIIddddd | Rd = memuh(Rt<instruction = HEX_INS_L4_LOADRUH_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x80) >> 7)); // Ii + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0xf00) >> 6) | (((hi_u32)&0x60) >> 5)); // II + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = memuh(%s<<%s0x%x+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f002880) { + // 10011111000iiiiiPP101tti100ddddd | if (!Pt) Rd = memb(Ii) + hi->instruction = HEX_INS_L4_PLOADRBF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memb(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f003880) { + // 10011111000iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memb(Ii) + hi->instruction = HEX_INS_L4_PLOADRBFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memb(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f002080) { + // 10011111000iiiiiPP100tti100ddddd | if (Pt) Rd = memb(Ii) + hi->instruction = HEX_INS_L4_PLOADRBT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memb(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f003080) { + // 10011111000iiiiiPP110tti100ddddd | if (Pt.new) Rd = memb(Ii) + hi->instruction = HEX_INS_L4_PLOADRBTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memb(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc02880) { + // 10011111110iiiiiPP101tti100ddddd | if (!Pt) Rdd = memd(Ii) + hi->instruction = HEX_INS_L4_PLOADRDF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memd(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc03880) { + // 10011111110iiiiiPP111tti100ddddd | if (!Pt.new) Rdd = memd(Ii) + hi->instruction = HEX_INS_L4_PLOADRDFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memd(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc02080) { + // 10011111110iiiiiPP100tti100ddddd | if (Pt) Rdd = memd(Ii) + hi->instruction = HEX_INS_L4_PLOADRDT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memd(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9fc03080) { + // 10011111110iiiiiPP110tti100ddddd | if (Pt.new) Rdd = memd(Ii) + hi->instruction = HEX_INS_L4_PLOADRDTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memd(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f402880) { + // 10011111010iiiiiPP101tti100ddddd | if (!Pt) Rd = memh(Ii) + hi->instruction = HEX_INS_L4_PLOADRHF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f403880) { + // 10011111010iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memh(Ii) + hi->instruction = HEX_INS_L4_PLOADRHFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f402080) { + // 10011111010iiiiiPP100tti100ddddd | if (Pt) Rd = memh(Ii) + hi->instruction = HEX_INS_L4_PLOADRHT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f403080) { + // 10011111010iiiiiPP110tti100ddddd | if (Pt.new) Rd = memh(Ii) + hi->instruction = HEX_INS_L4_PLOADRHTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f802880) { + // 10011111100iiiiiPP101tti100ddddd | if (!Pt) Rd = memw(Ii) + hi->instruction = HEX_INS_L4_PLOADRIF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memw(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f803880) { + // 10011111100iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memw(Ii) + hi->instruction = HEX_INS_L4_PLOADRIFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memw(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f802080) { + // 10011111100iiiiiPP100tti100ddddd | if (Pt) Rd = memw(Ii) + hi->instruction = HEX_INS_L4_PLOADRIT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memw(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f803080) { + // 10011111100iiiiiPP110tti100ddddd | if (Pt.new) Rd = memw(Ii) + hi->instruction = HEX_INS_L4_PLOADRITNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memw(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f202880) { + // 10011111001iiiiiPP101tti100ddddd | if (!Pt) Rd = memub(Ii) + hi->instruction = HEX_INS_L4_PLOADRUBF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memub(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f203880) { + // 10011111001iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memub(Ii) + hi->instruction = HEX_INS_L4_PLOADRUBFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memub(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f202080) { + // 10011111001iiiiiPP100tti100ddddd | if (Pt) Rd = memub(Ii) + hi->instruction = HEX_INS_L4_PLOADRUBT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memub(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f203080) { + // 10011111001iiiiiPP110tti100ddddd | if (Pt.new) Rd = memub(Ii) + hi->instruction = HEX_INS_L4_PLOADRUBTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memub(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f602880) { + // 10011111011iiiiiPP101tti100ddddd | if (!Pt) Rd = memuh(Ii) + hi->instruction = HEX_INS_L4_PLOADRUHF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) %s = memuh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f603880) { + // 10011111011iiiiiPP111tti100ddddd | if (!Pt.new) Rd = memuh(Ii) + hi->instruction = HEX_INS_L4_PLOADRUHFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) %s = memuh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f602080) { + // 10011111011iiiiiPP100tti100ddddd | if (Pt) Rd = memuh(Ii) + hi->instruction = HEX_INS_L4_PLOADRUHT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) %s = memuh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038e0) == 0x9f603080) { + // 10011111011iiiiiPP110tti100ddddd | if (Pt.new) Rd = memuh(Ii) + hi->instruction = HEX_INS_L4_PLOADRUHTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x600) >> 9); // Pt4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x100) >> 8)); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) %s = memuh(%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0x96000000) { + // 10010110000sssssPP000000000ddddd | Rdd = dealloc_return(Rs):raw + hi->instruction = HEX_INS_L4_RETURN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_RET; + sprintf(hi->mnem_infix, "%s = dealloc_return(%s):raw", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x96003000) { + // 10010110000sssssPP1100vv000ddddd | if (!Pv) Rdd = dealloc_return(Rs):raw + hi->instruction = HEX_INS_L4_RETURN_F; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!%s) %s = dealloc_return(%s):raw", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x96002800) { + // 10010110000sssssPP1010vv000ddddd | if (!Pv.new) Rdd = dealloc_return(Rs):nt:raw + hi->instruction = HEX_INS_L4_RETURN_FNEW_PNT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!%s.new) %s = dealloc_return(%s):nt:raw", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x96003800) { + // 10010110000sssssPP1110vv000ddddd | if (!Pv.new) Rdd = dealloc_return(Rs):t:raw + hi->instruction = HEX_INS_L4_RETURN_FNEW_PT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (!%s.new) %s = dealloc_return(%s):t:raw", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x96001000) { + // 10010110000sssssPP0100vv000ddddd | if (Pv) Rdd = dealloc_return(Rs):raw + hi->instruction = HEX_INS_L4_RETURN_T; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (%s) %s = dealloc_return(%s):raw", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x96000800) { + // 10010110000sssssPP0010vv000ddddd | if (Pv.new) Rdd = dealloc_return(Rs):nt:raw + hi->instruction = HEX_INS_L4_RETURN_TNEW_PNT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (%s.new) %s = dealloc_return(%s):nt:raw", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ce0) == 0x96001800) { + // 10010110000sssssPP0110vv000ddddd | if (Pv.new) Rdd = dealloc_return(Rs):t:raw + hi->instruction = HEX_INS_L4_RETURN_TNEW_PT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x300) >> 8); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_CRET; + sprintf(hi->mnem_infix, "if (%s.new) %s = dealloc_return(%s):t:raw", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0x92000040) { + // 10010010000sssssPPuttttt01000000 | memcpy(Rs,Rt,Mu) + hi->instruction = HEX_INS_L6_MEMCPY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memcpy(%s,%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_mod_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x92000020) { + // 10010010000sssssPP0uuuuu001ddddd | Rd = vextract(Vu,Rs) + hi->instruction = HEX_INS_V6_EXTRACTW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Vu32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vextract(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_hvx_vr(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0x94000000) { + // 10010100000sssssPP000iiiiiiiiiii | dcfetch(Rs+Ii) + hi->instruction = HEX_INS_Y2_DCFETCHBO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7ff) >> 0) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "dcfetch(%s+%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0x92002000) { + // 10010010000sssssPP1ttttt000ddddd | Rd = memw_phys(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = memw_phys(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0xa(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe020fc) == 0xa0e0000c) { + // 10100000111sssssPP0000011 | release(Rs):at + hi->instruction = HEX_INS_R6_RELEASE_AT_VI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "release(%s):at", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e0002c) { + // 10100000111sssssPP0001011 | release(Rs):st + hi->instruction = HEX_INS_R6_RELEASE_ST_VI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "release(%s):st", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03800) == 0xa0800000) { + // 10100000100xxxxxPP000iiiiiiiiiii | allocframe(Rx,Ii):raw + hi->instruction = HEX_INS_S2_ALLOCFRAME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x7ff) >> 0) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "allocframe(%s,%s0x%x):raw", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab002004) { + // 10101011000xxxxxPP1ttttt0iiii1vv | if (!Pv) memb(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab002084) { + // 10101011000xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memb(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02004) { + // 10101011101xxxxxPP100ttt0iiii1vv | if (!Pv) memb(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02084) { + // 10101011101xxxxxPP100ttt1iiii1vv | if (!Pv.new) memb(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02000) { + // 10101011101xxxxxPP100ttt0iiii0vv | if (Pv) memb(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02080) { + // 10101011101xxxxxPP100ttt1iiii0vv | if (Pv.new) memb(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERBNEWTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab002000) { + // 10101011000xxxxxPP1ttttt0iiii0vv | if (Pv) memb(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab002080) { + // 10101011000xxxxxPP1ttttt1iiii0vv | if (Pv.new) memb(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERBTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[2].op.imm & (1 << 3)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xabc02004) { + // 10101011110xxxxxPP1ttttt0iiii1vv | if (!Pv) memd(Rx++Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memd(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xabc02084) { + // 10101011110xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memd(Rx++Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memd(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xabc02000) { + // 10101011110xxxxxPP1ttttt0iiii0vv | if (Pv) memd(Rx++Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memd(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xabc02080) { + // 10101011110xxxxxPP1ttttt1iiii0vv | if (Pv.new) memd(Rx++Ii) = Rtt + hi->instruction = HEX_INS_S2_PSTORERDTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 3; + if (hi->ops[2].op.imm & (1 << 6)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memd(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab602004) { + // 10101011011xxxxxPP1ttttt0iiii1vv | if (!Pv) memh(Rx++Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s++%s) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab602084) { + // 10101011011xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memh(Rx++Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s++%s) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab602000) { + // 10101011011xxxxxPP1ttttt0iiii0vv | if (Pv) memh(Rx++Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s++%s) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab602080) { + // 10101011011xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh(Rx++Ii) = Rt.h + hi->instruction = HEX_INS_S2_PSTORERFTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s++%s) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab402004) { + // 10101011010xxxxxPP1ttttt0iiii1vv | if (!Pv) memh(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab402084) { + // 10101011010xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memh(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02804) { + // 10101011101xxxxxPP101ttt0iiii1vv | if (!Pv) memh(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02884) { + // 10101011101xxxxxPP101ttt1iiii1vv | if (!Pv.new) memh(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02800) { + // 10101011101xxxxxPP101ttt0iiii0vv | if (Pv) memh(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba02880) { + // 10101011101xxxxxPP101ttt1iiii0vv | if (Pv.new) memh(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERHNEWTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab402000) { + // 10101011010xxxxxPP1ttttt0iiii0vv | if (Pv) memh(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab402080) { + // 10101011010xxxxxPP1ttttt1iiii0vv | if (Pv.new) memh(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERHTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 1; + if (hi->ops[2].op.imm & (1 << 4)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab802004) { + // 10101011100xxxxxPP1ttttt0iiii1vv | if (!Pv) memw(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab802084) { + // 10101011100xxxxxPP1ttttt1iiii1vv | if (!Pv.new) memw(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba03004) { + // 10101011101xxxxxPP110ttt0iiii1vv | if (!Pv) memw(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba03084) { + // 10101011101xxxxxPP110ttt1iiii1vv | if (!Pv.new) memw(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWFNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba03000) { + // 10101011101xxxxxPP110ttt0iiii0vv | if (Pv) memw(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03884) == 0xaba03080) { + // 10101011101xxxxxPP110ttt1iiii0vv | if (Pv.new) memw(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_PSTORERINEWTNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s++%s) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab802000) { + // 10101011100xxxxxPP1ttttt0iiii0vv | if (Pv) memw(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERIT_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02084) == 0xab802080) { + // 10101011100xxxxxPP1ttttt1iiii0vv | if (Pv.new) memw(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_PSTORERITNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s++%s) = %s", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0xa1000000) { + // 10100ii1000sssssPPitttttiiiiiiii | memb(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_STORERB_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xaf000000) { + // 10101111000xxxxxPPuttttt00000000 | memb(Rx++Mu:brev) = Rt + hi->instruction = HEX_INS_S2_STORERB_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memb(%s++%s:brev) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00087) == 0xa9000000) { + // 10101001000xxxxxPPuttttt0iiii000 | memb(Rx++Ii:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERB_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s++%s:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xa9000002) { + // 10101001000xxxxxPPuttttt00000010 | memb(Rx++I:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERB_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memb(%s++I:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02087) == 0xab000000) { + // 10101011000xxxxxPP0ttttt0iiii000 | memb(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_STORERB_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xad000000) { + // 10101101000xxxxxPPuttttt00000000 | memb(Rx++Mu) = Rt + hi->instruction = HEX_INS_S2_STORERB_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memb(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0xa1a00000) { + // 10100ii1101sssssPPi00tttiiiiiiii | memb(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)); // Ii + if (hi->ops[1].op.imm & (1 << 10)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 10); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s+%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xafa00000) { + // 10101111101xxxxxPPu00ttt00000000 | memb(Rx++Mu:brev) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memb(%s++%s:brev) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01887) == 0xa9a00000) { + // 10101001101xxxxxPPu00ttt0iiii000 | memb(Rx++Ii:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s++%s:circ(%s)) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xa9a00002) { + // 10101001101xxxxxPPu00ttt00000010 | memb(Rx++I:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memb(%s++I:circ(%s)) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03887) == 0xaba00000) { + // 10101011101xxxxxPP000ttt0iiii000 | memb(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3); // Ii + if (hi->ops[1].op.imm & (1 << 3)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 3); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xada00000) { + // 10101101101xxxxxPPu00ttt00000000 | memb(Rx++Mu) = Nt.new + hi->instruction = HEX_INS_S2_STORERBNEW_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memb(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0xa1c00000) { + // 10100ii1110sssssPPitttttiiiiiiii | memd(Rs+Ii) = Rtt + hi->instruction = HEX_INS_S2_STORERD_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 13)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 13); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memd(%s+%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xafc00000) { + // 10101111110xxxxxPPuttttt00000000 | memd(Rx++Mu:brev) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memd(%s++%s:brev) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00087) == 0xa9c00000) { + // 10101001110xxxxxPPuttttt0iiii000 | memd(Rx++Ii:circ(Mu)) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 6)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memd(%s++%s:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xa9c00002) { + // 10101001110xxxxxPPuttttt00000010 | memd(Rx++I:circ(Mu)) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memd(%s++I:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02087) == 0xabc00000) { + // 10101011110xxxxxPP0ttttt0iiii000 | memd(Rx++Ii) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 3; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 3; + if (hi->ops[1].op.imm & (1 << 6)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 6); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memd(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xadc00000) { + // 10101101110xxxxxPPuttttt00000000 | memd(Rx++Mu) = Rtt + hi->instruction = HEX_INS_S2_STORERD_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memd(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0xa1600000) { + // 10100ii1011sssssPPitttttiiiiiiii | memh(Rs+Ii) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 11)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xaf600000) { + // 10101111011xxxxxPPuttttt00000000 | memh(Rx++Mu:brev) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++%s:brev) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00087) == 0xa9600000) { + // 10101001011xxxxxPPuttttt0iiii000 | memh(Rx++Ii:circ(Mu)) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s++%s:circ(%s)) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xa9600002) { + // 10101001011xxxxxPPuttttt00000010 | memh(Rx++I:circ(Mu)) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++I:circ(%s)) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02087) == 0xab600000) { + // 10101011011xxxxxPP0ttttt0iiii000 | memh(Rx++Ii) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s++%s) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xad600000) { + // 10101101011xxxxxPPuttttt00000000 | memh(Rx++Mu) = Rt.h + hi->instruction = HEX_INS_S2_STORERF_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++%s) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0xa1400000) { + // 10100ii1010sssssPPitttttiiiiiiii | memh(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_STORERH_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 11)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xaf400000) { + // 10101111010xxxxxPPuttttt00000000 | memh(Rx++Mu:brev) = Rt + hi->instruction = HEX_INS_S2_STORERH_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++%s:brev) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00087) == 0xa9400000) { + // 10101001010xxxxxPPuttttt0iiii000 | memh(Rx++Ii:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERH_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s++%s:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xa9400002) { + // 10101001010xxxxxPPuttttt00000010 | memh(Rx++I:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERH_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++I:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02087) == 0xab400000) { + // 10101011010xxxxxPP0ttttt0iiii000 | memh(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_STORERH_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xad400000) { + // 10101101010xxxxxPPuttttt00000000 | memh(Rx++Mu) = Rt + hi->instruction = HEX_INS_S2_STORERH_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0xa1a00800) { + // 10100ii1101sssssPPi01tttiiiiiiii | memh(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 11)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 11); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s+%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xafa00800) { + // 10101111101xxxxxPPu01ttt00000000 | memh(Rx++Mu:brev) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++%s:brev) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01887) == 0xa9a00800) { + // 10101001101xxxxxPPu01ttt0iiii000 | memh(Rx++Ii:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s++%s:circ(%s)) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xa9a00802) { + // 10101001101xxxxxPPu01ttt00000010 | memh(Rx++I:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++I:circ(%s)) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03887) == 0xaba00800) { + // 10101011101xxxxxPP001ttt0iiii000 | memh(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 1; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 1; + if (hi->ops[1].op.imm & (1 << 4)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 4); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xada00800) { + // 10101101101xxxxxPPu01ttt00000000 | memh(Rx++Mu) = Nt.new + hi->instruction = HEX_INS_S2_STORERHNEW_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memh(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e00000) == 0xa1800000) { + // 10100ii1100sssssPPitttttiiiiiiii | memw(Rs+Ii) = Rt + hi->instruction = HEX_INS_S2_STORERI_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 12)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 12); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xaf800000) { + // 10101111100xxxxxPPuttttt00000000 | memw(Rx++Mu:brev) = Rt + hi->instruction = HEX_INS_S2_STORERI_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw(%s++%s:brev) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00087) == 0xa9800000) { + // 10101001100xxxxxPPuttttt0iiii000 | memw(Rx++Ii:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERI_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s++%s:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xa9800002) { + // 10101001100xxxxxPPuttttt00000010 | memw(Rx++I:circ(Mu)) = Rt + hi->instruction = HEX_INS_S2_STORERI_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw(%s++I:circ(%s)) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02087) == 0xab800000) { + // 10101011100xxxxxPP0ttttt0iiii000 | memw(Rx++Ii) = Rt + hi->instruction = HEX_INS_S2_STORERI_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000ff) == 0xad800000) { + // 10101101100xxxxxPPuttttt00000000 | memw(Rx++Mu) = Rt + hi->instruction = HEX_INS_S2_STORERI_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw(%s++%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xf9e01800) == 0xa1a01000) { + // 10100ii1101sssssPPi10tttiiiiiiii | memw(Rs+Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_IO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x6000000) >> 16) | (((hi_u32)&0x2000) >> 5) | (((hi_u32)&0xff) >> 0)) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 12)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 12); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s+%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xafa01000) { + // 10101111101xxxxxPPu10ttt00000000 | memw(Rx++Mu:brev) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw(%s++%s:brev) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01887) == 0xa9a01000) { + // 10101001101xxxxxPPu10ttt0iiii000 | memw(Rx++Ii:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s++%s:circ(%s)) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_mod_regs(hi->ops[2].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xa9a01002) { + // 10101001101xxxxxPPu10ttt00000010 | memw(Rx++I:circ(Mu)) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw(%s++I:circ(%s)) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03887) == 0xaba01000) { + // 10101011101xxxxxPP010ttt0iiii000 | memw(Rx++Ii) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x78) >> 3) << 2; // scaled Ii + hi->ops[1].attr = HEX_OP_IMM_SCALED; + hi->ops[1].shift = 2; + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe018ff) == 0xada01000) { + // 10101101101xxxxxPPu10ttt00000000 | memw(Rx++Mu) = Nt.new + hi->instruction = HEX_INS_S2_STORERINEW_PR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x2000) >> 13); // Mu2 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw(%s++%s) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), hex_get_mod_regs(hi->ops[1].op.reg), hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0a00000) { + // 10100000101sssssPP0ttttt000000dd | memw_locked(Rs,Pd) = Rt + hi->instruction = HEX_INS_S2_STOREW_LOCKED; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw_locked(%s,%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0a00008) { + // 10100000101sssssPP0ttttt000010 | memw_rl(Rs):at = Rt + hi->instruction = HEX_INS_S2_STOREW_RL_AT_VI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw_rl(%s):at = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0a00028) { + // 10100000101sssssPP0ttttt001010 | memw_rl(Rs):st = Rt + hi->instruction = HEX_INS_S2_STOREW_RL_ST_VI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memw_rl(%s):st = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf000084) { + // 10101111000000iiPP0ttttt1iiii1vv | if (!Pv) memb(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf002084) { + // 10101111000000iiPP1ttttt1iiii1vv | if (!Pv.new) memb(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00084) { + // 10101111101000iiPP000ttt1iiii1vv | if (!Pv) memb(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memb(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02084) { + // 10101111101000iiPP100ttt1iiii1vv | if (!Pv.new) memb(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memb(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00080) { + // 10101111101000iiPP000ttt1iiii0vv | if (Pv) memb(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02080) { + // 10101111101000iiPP100ttt1iiii0vv | if (Pv.new) memb(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERBNEWTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf000080) { + // 10101111000000iiPP0ttttt1iiii0vv | if (Pv) memb(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memb(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf002080) { + // 10101111000000iiPP1ttttt1iiii0vv | if (Pv.new) memb(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERBTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memb(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xafc00084) { + // 10101111110000iiPP0ttttt1iiii1vv | if (!Pv) memd(Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memd(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xafc02084) { + // 10101111110000iiPP1ttttt1iiii1vv | if (!Pv.new) memd(Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memd(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xafc00080) { + // 10101111110000iiPP0ttttt1iiii0vv | if (Pv) memd(Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memd(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xafc02080) { + // 10101111110000iiPP1ttttt1iiii0vv | if (Pv.new) memd(Ii) = Rtt + hi->instruction = HEX_INS_S4_PSTORERDTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memd(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf600084) { + // 10101111011000iiPP0ttttt1iiii1vv | if (!Pv) memh(Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf602084) { + // 10101111011000iiPP1ttttt1iiii1vv | if (!Pv.new) memh(Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf600080) { + // 10101111011000iiPP0ttttt1iiii0vv | if (Pv) memh(Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf602080) { + // 10101111011000iiPP1ttttt1iiii0vv | if (Pv.new) memh(Ii) = Rt.h + hi->instruction = HEX_INS_S4_PSTORERFTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s0x%x) = %s.h", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf400084) { + // 10101111010000iiPP0ttttt1iiii1vv | if (!Pv) memh(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf402084) { + // 10101111010000iiPP1ttttt1iiii1vv | if (!Pv.new) memh(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00884) { + // 10101111101000iiPP001ttt1iiii1vv | if (!Pv) memh(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memh(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02884) { + // 10101111101000iiPP101ttt1iiii1vv | if (!Pv.new) memh(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memh(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa00880) { + // 10101111101000iiPP001ttt1iiii0vv | if (Pv) memh(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa02880) { + // 10101111101000iiPP101ttt1iiii0vv | if (Pv.new) memh(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERHNEWTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf400080) { + // 10101111010000iiPP0ttttt1iiii0vv | if (Pv) memh(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memh(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf402080) { + // 10101111010000iiPP1ttttt1iiii0vv | if (Pv.new) memh(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERHTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memh(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf800084) { + // 10101111100000iiPP0ttttt1iiii1vv | if (!Pv) memw(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf802084) { + // 10101111100000iiPP1ttttt1iiii1vv | if (!Pv.new) memw(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa01084) { + // 10101111101000iiPP010ttt1iiii1vv | if (!Pv) memw(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWF_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s) memw(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa03084) { + // 10101111101000iiPP110ttt1iiii1vv | if (!Pv.new) memw(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWFNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (!%s.new) memw(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa01080) { + // 10101111101000iiPP010ttt1iiii0vv | if (Pv) memw(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc3884) == 0xafa03080) { + // 10101111101000iiPP110ttt1iiii0vv | if (Pv.new) memw(Ii) = Nt.new + hi->instruction = HEX_INS_S4_PSTORERINEWTNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s0x%x) = %s.new", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf800080) { + // 10101111100000iiPP0ttttt1iiii0vv | if (Pv) memw(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERIT_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s) memw(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xfffc2084) == 0xaf802080) { + // 10101111100000iiPP1ttttt1iiii0vv | if (Pv.new) memw(Ii) = Rt + hi->instruction = HEX_INS_S4_PSTORERITNEW_ABS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pv4 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x30000) >> 12) | (((hi_u32)&0x78) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "if (%s.new) memw(%s0x%x) = %s", hex_get_pred_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e00000) { + // 10100000111sssssPP0ttttt000000dd | memd_locked(Rs,Pd) = Rtt + hi->instruction = HEX_INS_S4_STORED_LOCKED; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memd_locked(%s,%s) = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e00008) { + // 10100000111sssssPP0ttttt000010 | memd_rl(Rs):at = Rtt + hi->instruction = HEX_INS_S4_STORED_RL_AT_VI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memd_rl(%s):at = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xa0e00028) { + // 10100000111sssssPP0ttttt001010 | memd_rl(Rs):st = Rtt + hi->instruction = HEX_INS_S4_STORED_RL_ST_VI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "memd_rl(%s):st = %s", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0xab000080) { + // 10101011000eeeeePP0ttttt10IIIIII | memb(Re=II) = Rt + hi->instruction = HEX_INS_S4_STORERB_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s=%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0xad000080) { + // 10101101000uuuuuPPittttt1iIIIIII | memb(Ru<instruction = HEX_INS_S4_STORERB_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s<<%s0x%x+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038c0) == 0xaba00080) { + // 10101011101eeeeePP000ttt10IIIIII | memb(Re=II) = Nt.new + hi->instruction = HEX_INS_S4_STORERBNEW_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memb(%s=%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01880) == 0xada00080) { + // 10101101101uuuuuPPi00ttt1iIIIIII | memb(Ru<instruction = HEX_INS_S4_STORERBNEW_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memb(%s<<%s0x%x+%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0xabc00080) { + // 10101011110eeeeePP0ttttt10IIIIII | memd(Re=II) = Rtt + hi->instruction = HEX_INS_S4_STORERD_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memd(%s=%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0xadc00080) { + // 10101101110uuuuuPPittttt1iIIIIII | memd(Ru<instruction = HEX_INS_S4_STORERD_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memd(%s<<%s0x%x+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0xab600080) { + // 10101011011eeeeePP0ttttt10IIIIII | memh(Re=II) = Rt.h + hi->instruction = HEX_INS_S4_STORERF_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s=%s0x%x) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0xad600080) { + // 10101101011uuuuuPPittttt1iIIIIII | memh(Ru<instruction = HEX_INS_S4_STORERF_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s<<%s0x%x+%s0x%x) = %s.h", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0xab400080) { + // 10101011010eeeeePP0ttttt10IIIIII | memh(Re=II) = Rt + hi->instruction = HEX_INS_S4_STORERH_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s=%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0xad400080) { + // 10101101010uuuuuPPittttt1iIIIIII | memh(Ru<instruction = HEX_INS_S4_STORERH_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s<<%s0x%x+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038c0) == 0xaba00880) { + // 10101011101eeeeePP001ttt10IIIIII | memh(Re=II) = Nt.new + hi->instruction = HEX_INS_S4_STORERHNEW_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memh(%s=%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01880) == 0xada00880) { + // 10101101101uuuuuPPi01ttt1iIIIIII | memh(Ru<instruction = HEX_INS_S4_STORERHNEW_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memh(%s<<%s0x%x+%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0xab800080) { + // 10101011100eeeeePP0ttttt10IIIIII | memw(Re=II) = Rt + hi->instruction = HEX_INS_S4_STORERI_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s=%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe00080) == 0xad800080) { + // 10101101100uuuuuPPittttt1iIIIIII | memw(Ru<instruction = HEX_INS_S4_STORERI_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s<<%s0x%x+%s0x%x) = %s", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe038c0) == 0xaba01080) { + // 10101011101eeeeePP010ttt10IIIIII | memw(Re=II) = Nt.new + hi->instruction = HEX_INS_S4_STORERINEW_AP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Re32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "memw(%s=%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[2].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe01880) == 0xada01080) { + // 10101101101uuuuuPPi10ttt1iIIIIII | memw(Ru<instruction = HEX_INS_S4_STORERINEW_UR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Ru32 + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x40) >> 6)); // Ii + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3f) >> 0); // II + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x700) >> 8); // Nt8 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "memw(%s<<%s0x%x+%s0x%x) = %s.new", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm, !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(resolve_n_register(hi->ops[3].op.reg, hi->addr, pkt))); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa8000000) { + // 1010100000000000PP00000000000000 | barrier + hi->instruction = HEX_INS_Y2_BARRIER; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "barrier"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa0000000) { + // 10100000000sssssPP00000000000000 | dccleana(Rs) + hi->instruction = HEX_INS_Y2_DCCLEANA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dccleana(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa0400000) { + // 10100000010sssssPP00000000000000 | dccleaninva(Rs) + hi->instruction = HEX_INS_Y2_DCCLEANINVA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dccleaninva(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa0200000) { + // 10100000001sssssPP00000000000000 | dcinva(Rs) + hi->instruction = HEX_INS_Y2_DCINVA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dcinva(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa0c00000) { + // 10100000110sssssPP00000000000000 | dczeroa(Rs) + hi->instruction = HEX_INS_Y2_DCZEROA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dczeroa(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa8400000) { + // 1010100001000000PP00000000000000 | syncht + hi->instruction = HEX_INS_Y2_SYNCHT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "syncht"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0xa6000000) { + // 10100110000sssssPP0ttttt00000000 | l2fetch(Rs,Rt) + hi->instruction = HEX_INS_Y4_L2FETCH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2fetch(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0xa6800000) { + // 10100110100sssssPP0ttttt00000000 | l2fetch(Rs,Rtt) + hi->instruction = HEX_INS_Y5_L2FETCH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2fetch(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0xa6000040) { + // 10100110000sssssPP0ttttt01000000 | dmlink(Rs,Rt) + hi->instruction = HEX_INS_Y6_DMLINK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dmlink(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fe0) == 0xa8000060) { + // 1010100000000000PP000000011ddddd | Rd = dmpause + hi->instruction = HEX_INS_Y6_DMPAUSE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dmpause", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fe0) == 0xa8000040) { + // 1010100000000000PP000000010ddddd | Rd = dmpoll + hi->instruction = HEX_INS_Y6_DMPOLL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dmpoll", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa6000080) { + // 10100110000sssssPP00000010000000 | dmresume(Rs) + hi->instruction = HEX_INS_Y6_DMRESUME; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dmresume(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa6000020) { + // 10100110000sssssPP00000000100000 | dmstart(Rs) + hi->instruction = HEX_INS_Y6_DMSTART; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dmstart(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fe0) == 0xa8000020) { + // 1010100000000000PP000000001ddddd | Rd = dmwait + hi->instruction = HEX_INS_Y6_DMWAIT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dmwait", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa2200000) { + // 10100010001sssssPP00000000000000 | dccleanidx(Rs) + hi->instruction = HEX_INS_IMPORTED_DCCLEANIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dccleanidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa8200000) { + // 1010100000100000PP00000000000000 | l2kill + hi->instruction = HEX_INS_IMPORTED_L2KILL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2kill"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa2600000) { + // 10100010011sssssPP00000000000000 | dccleaninvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_DCCLEANINVIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dccleaninvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa8201800) { + // 1010100000100000PP01100000000000 | l2gcleaninv + hi->instruction = HEX_INS_IMPORTED_L2GCLEANINV; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2gcleaninv"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0xa4400000) { + // 10100100010sssssPP0ttttt00000000 | l2tagw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_L2TAGW_RS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2tagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0xa4200000) { + // 10100100001sssssPP000000000ddddd | Rd = dctagr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_DCTAGR_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dctagr(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa2400000) { + // 10100010010sssssPP00000000000000 | dcinvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_DCINVIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dcinvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa8200800) { + // 1010100000100000PP00100000000000 | l2gunlock + hi->instruction = HEX_INS_IMPORTED_L2GUNLOCK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2gunlock"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03ffc) == 0xa0e02000) { + // 10100000111sssssPP100000000000dd | Pd = l2locka(Rs) + hi->instruction = HEX_INS_IMPORTED_PD_L2LOCKA_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = l2locka(%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fe0) == 0xa4600000) { + // 10100100011sssssPP000000000ddddd | Rd = l2tagr(Rs) + hi->instruction = HEX_INS_IMPORTED_RD_L2TAGR_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = l2tagr(%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020ff) == 0xa4000000) { + // 10100100000sssssPP0ttttt00000000 | dctagw(Rs,Rt) + hi->instruction = HEX_INS_IMPORTED_DCTAGW_RS_RT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dctagw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa8201000) { + // 1010100000100000PP01000000000000 | l2gclean + hi->instruction = HEX_INS_IMPORTED_L2GCLEAN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2gclean"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff3fff) == 0xa2000000) { + // 1010001000000000PP00000000000000 | dckill + hi->instruction = HEX_INS_IMPORTED_DCKILL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 0; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "dckill"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa6400000) { + // 10100110010sssssPP00000000000000 | l2invidx(Rs) + hi->instruction = HEX_INS_IMPORTED_L2INVIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2invidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20ff) == 0xa6a00000) { + // 1010011010100000PP0ttttt00000000 | l2gclean(Rtt) + hi->instruction = HEX_INS_IMPORTED_L2GCLEAN_RTT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2gclean(%s)", hex_get_double_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa8600000) { + // 10101000011sssssPP00000000000000 | l2cleaninvidx(Rs) + hi->instruction = HEX_INS_IMPORTED_L2CLEANINVIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2cleaninvidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa6600000) { + // 10100110011sssssPP00000000000000 | l2unlocka(Rs) + hi->instruction = HEX_INS_IMPORTED_L2UNLOCKA_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2unlocka(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03fff) == 0xa6200000) { + // 10100110001sssssPP00000000000000 | l2cleanidx(Rs) + hi->instruction = HEX_INS_IMPORTED_L2CLEANIDX_RS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2cleanidx(%s)", hex_get_int_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffff20ff) == 0xa6c00000) { + // 1010011011000000PP0ttttt00000000 | l2gcleaninv(Rtt) + hi->instruction = HEX_INS_IMPORTED_L2GCLEANINV_RTT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 1; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[0].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "l2gcleaninv(%s)", hex_get_double_regs(hi->ops[0].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0xb(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xf0000000) == 0xb0000000) { + // 1011iiiiiiisssssPPiiiiiiiiiddddd | Rd = add(Rs,Ii) + hi->instruction = HEX_INS_A2_ADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0xfe00000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 15)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 15); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0xc(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe02080) == 0xc2c00000) { + // 11000010110sssssPP0ttttt0xxddddd | Rdd = add(Rss,Rtt,Px):carry + hi->instruction = HEX_INS_A4_ADDP_C; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Px4 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s,%s):carry", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c000c0) { + // 11000111110sssssPP0ttttt110000dd | Pd = cmpb.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPBEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpb.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c00040) { + // 11000111110sssssPP0ttttt010000dd | Pd = cmpb.gt(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPBGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpb.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c000e0) { + // 11000111110sssssPP0ttttt111000dd | Pd = cmpb.gtu(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPBGTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpb.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c00060) { + // 11000111110sssssPP0ttttt011000dd | Pd = cmph.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPHEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmph.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c00080) { + // 11000111110sssssPP0ttttt100000dd | Pd = cmph.gt(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPHGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmph.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7c000a0) { + // 11000111110sssssPP0ttttt101000dd | Pd = cmph.gtu(Rs,Rt) + hi->instruction = HEX_INS_A4_CMPHGTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmph.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c00000) { + // 11000110110sssssPP0ttttt000ddddd | Rd = cround(Rs,Rt) + hi->instruction = HEX_INS_A4_CROUND_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cround(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c00080) { + // 11000110110sssssPP0ttttt100ddddd | Rd = round(Rs,Rt) + hi->instruction = HEX_INS_A4_ROUND_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = round(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c000c0) { + // 11000110110sssssPP0ttttt110ddddd | Rd = round(Rs,Rt):sat + hi->instruction = HEX_INS_A4_ROUND_RR_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = round(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xc2e00000) { + // 11000010111sssssPP0ttttt0xxddddd | Rdd = sub(Rss,Rtt,Px):carry + hi->instruction = HEX_INS_A4_SUBP_C; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Px4 + hi->ops[3].attr |= HEX_OP_REG_OUT; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s,%s,%s):carry", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb200020) { + // 11001011001sssssPP0xxxxx001uuuuu | Rxx = vrmaxh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmaxh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb202020) { + // 11001011001sssssPP1xxxxx001uuuuu | Rxx = vrmaxuh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmaxuh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb202040) { + // 11001011001sssssPP1xxxxx010uuuuu | Rxx = vrmaxuw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmaxuw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb200040) { + // 11001011001sssssPP0xxxxx010uuuuu | Rxx = vrmaxw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMAXW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmaxw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2000a0) { + // 11001011001sssssPP0xxxxx101uuuuu | Rxx = vrminh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrminh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2020a0) { + // 11001011001sssssPP1xxxxx101uuuuu | Rxx = vrminuh(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrminuh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2020c0) { + // 11001011001sssssPP1xxxxx110uuuuu | Rxx = vrminuw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrminuw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2000c0) { + // 11001011001sssssPP0xxxxx110uuuuu | Rxx = vrminw(Rss,Ru) + hi->instruction = HEX_INS_A4_VRMINW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrminw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400020) { + // 11000001010sssssPP0ttttt001ddddd | Rd = vaddhub(Rss,Rtt):sat + hi->instruction = HEX_INS_A5_VADDHUBS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddhub(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6c00040) { + // 11000110110sssssPP0ttttt010ddddd | Rdd = cround(Rss,Rt) + hi->instruction = HEX_INS_A7_CROUNDD_RR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cround(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7800000) { + // 11000111100sssssPP0ttttt000000dd | Pd = bitsclr(Rs,Rt) + hi->instruction = HEX_INS_C2_BITSCLR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = bitsclr(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7400000) { + // 11000111010sssssPP0ttttt000000dd | Pd = bitsset(Rs,Rt) + hi->instruction = HEX_INS_C2_BITSSET; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = bitsset(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7a00000) { + // 11000111101sssssPP0ttttt000000dd | Pd = !bitsclr(Rs,Rt) + hi->instruction = HEX_INS_C4_NBITSCLR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !bitsclr(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7600000) { + // 11000111011sssssPP0ttttt000000dd | Pd = !bitsset(Rs,Rt) + hi->instruction = HEX_INS_C4_NBITSSET; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !bitsset(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00060) { + // 11000111111sssssPP0ttttt011000dd | Pd = sfcmp.eq(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfcmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00000) { + // 11000111111sssssPP0ttttt000000dd | Pd = sfcmp.ge(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPGE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfcmp.ge(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00080) { + // 11000111111sssssPP0ttttt100000dd | Pd = sfcmp.gt(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfcmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7e00020) { + // 11000111111sssssPP0ttttt001000dd | Pd = sfcmp.uo(Rs,Rt) + hi->instruction = HEX_INS_F2_SFCMPUO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfcmp.uo(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc5000080) { + // 11000101000sssssPP0ttttt100ddddd | Rd = cmpyiwh(Rss,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYI_WH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiwh(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc50000a0) { + // 11000101000sssssPP0ttttt101ddddd | Rd = cmpyiwh(Rss,Rt*):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYI_WHC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiwh(%s,%s*):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc50000c0) { + // 11000101000sssssPP0ttttt110ddddd | Rd = cmpyrwh(Rss,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYR_WH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrwh(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc50000e0) { + // 11000101000sssssPP0ttttt111ddddd | Rd = cmpyrwh(Rss,Rt*):<<1:rnd:sat + hi->instruction = HEX_INS_M4_CMPYR_WHC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrwh(%s,%s*):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xca800000) { + // 11001010100sssssPP0ttttt000xxxxx | Rxx ^= xor(Rss,Rtt) + hi->instruction = HEX_INS_M4_XOR_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= xor(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xc4000000) { + // 11000100000sssssPP0tttttiiiddddd | Rd = addasl(Rt,Rs,Ii) + hi->instruction = HEX_INS_S2_ADDASL_RRRI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = addasl(%s,%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3800080) { + // 11000011100sssssPP0ttttt100ddddd | Rdd = asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc00080) { + // 11001011110sssssPP0ttttt100xxxxx | Rxx += asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += asl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb400080) { + // 11001011010sssssPP0ttttt100xxxxx | Rxx &= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= asl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb800080) { + // 11001011100sssssPP0ttttt100xxxxx | Rxx -= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= asl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb000080) { + // 11001011000sssssPP0ttttt100xxxxx | Rxx |= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= asl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb600080) { + // 11001011011sssssPP0ttttt100xxxxx | Rxx ^= asl(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_P_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= asl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6400080) { + // 11000110010sssssPP0ttttt100ddddd | Rd = asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xccc00080) { + // 11001100110sssssPP0ttttt100xxxxx | Rx += asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += asl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc400080) { + // 11001100010sssssPP0ttttt100xxxxx | Rx &= asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= asl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc800080) { + // 11001100100sssssPP0ttttt100xxxxx | Rx -= asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= asl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc000080) { + // 11001100000sssssPP0ttttt100xxxxx | Rx |= asl(Rs,Rt) + hi->instruction = HEX_INS_S2_ASL_R_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= asl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6000080) { + // 11000110000sssssPP0ttttt100ddddd | Rd = asl(Rs,Rt):sat + hi->instruction = HEX_INS_S2_ASL_R_R_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asl(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3400080) { + // 11000011010sssssPP0ttttt100ddddd | Rdd = vaslh(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaslh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3000080) { + // 11000011000sssssPP0ttttt100ddddd | Rdd = vaslw(Rss,Rt) + hi->instruction = HEX_INS_S2_ASL_R_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaslw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3800000) { + // 11000011100sssssPP0ttttt000ddddd | Rdd = asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc00000) { + // 11001011110sssssPP0ttttt000xxxxx | Rxx += asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += asr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb400000) { + // 11001011010sssssPP0ttttt000xxxxx | Rxx &= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= asr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb800000) { + // 11001011100sssssPP0ttttt000xxxxx | Rxx -= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= asr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb000000) { + // 11001011000sssssPP0ttttt000xxxxx | Rxx |= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= asr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb600000) { + // 11001011011sssssPP0ttttt000xxxxx | Rxx ^= asr(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_P_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= asr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6400000) { + // 11000110010sssssPP0ttttt000ddddd | Rd = asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xccc00000) { + // 11001100110sssssPP0ttttt000xxxxx | Rx += asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += asr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc400000) { + // 11001100010sssssPP0ttttt000xxxxx | Rx &= asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= asr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc800000) { + // 11001100100sssssPP0ttttt000xxxxx | Rx -= asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= asr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc000000) { + // 11001100000sssssPP0ttttt000xxxxx | Rx |= asr(Rs,Rt) + hi->instruction = HEX_INS_S2_ASR_R_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= asr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6000000) { + // 11000110000sssssPP0ttttt000ddddd | Rd = asr(Rs,Rt):sat + hi->instruction = HEX_INS_S2_ASR_R_R_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = asr(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc5000040) { + // 11000101000sssssPP0ttttt010ddddd | Rd = vasrw(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_SVW_TRUN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vasrw(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3400000) { + // 11000011010sssssPP0ttttt000ddddd | Rdd = vasrh(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vasrh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3000000) { + // 11000011000sssssPP0ttttt000ddddd | Rdd = vasrw(Rss,Rt) + hi->instruction = HEX_INS_S2_ASR_R_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vasrw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c000c0) { + // 11000001110sssssPP0ttttt110ddddd | Rdd = decbin(Rss,Rtt) + hi->instruction = HEX_INS_S2_CABACDECBIN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = decbin(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6800040) { + // 11000110100sssssPP0ttttt010ddddd | Rd = clrbit(Rs,Rt) + hi->instruction = HEX_INS_S2_CLRBIT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = clrbit(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc9000000) { + // 11001001000sssssPP0ttttt000ddddd | Rd = extractu(Rs,Rtt) + hi->instruction = HEX_INS_S2_EXTRACTU_RP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = extractu(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1000000) { + // 11000001000sssssPP0ttttt000ddddd | Rdd = extractu(Rss,Rtt) + hi->instruction = HEX_INS_S2_EXTRACTUP_RP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = extractu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc8000000) { + // 11001000000sssssPP0ttttt000xxxxx | Rx = insert(Rs,Rtt) + hi->instruction = HEX_INS_S2_INSERT_RP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = insert(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xca000000) { + // 11001010000sssssPP0ttttt000xxxxx | Rxx = insert(Rss,Rtt) + hi->instruction = HEX_INS_S2_INSERTP_RP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = insert(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc18000c0) { + // 11000001100sssssPP0ttttt110ddddd | Rdd = lfs(Rss,Rtt) + hi->instruction = HEX_INS_S2_LFSP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = lfs(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc38000c0) { + // 11000011100sssssPP0ttttt110ddddd | Rdd = lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = lsl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc000c0) { + // 11001011110sssssPP0ttttt110xxxxx | Rxx += lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += lsl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb4000c0) { + // 11001011010sssssPP0ttttt110xxxxx | Rxx &= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= lsl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb8000c0) { + // 11001011100sssssPP0ttttt110xxxxx | Rxx -= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= lsl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb0000c0) { + // 11001011000sssssPP0ttttt110xxxxx | Rxx |= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= lsl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb6000c0) { + // 11001011011sssssPP0ttttt110xxxxx | Rxx ^= lsl(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_P_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= lsl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc64000c0) { + // 11000110010sssssPP0ttttt110ddddd | Rd = lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = lsl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xccc000c0) { + // 11001100110sssssPP0ttttt110xxxxx | Rx += lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += lsl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc4000c0) { + // 11001100010sssssPP0ttttt110xxxxx | Rx &= lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= lsl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc8000c0) { + // 11001100100sssssPP0ttttt110xxxxx | Rx -= lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= lsl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc0000c0) { + // 11001100000sssssPP0ttttt110xxxxx | Rx |= lsl(Rs,Rt) + hi->instruction = HEX_INS_S2_LSL_R_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= lsl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc34000c0) { + // 11000011010sssssPP0ttttt110ddddd | Rdd = vlslh(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vlslh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc30000c0) { + // 11000011000sssssPP0ttttt110ddddd | Rdd = vlslw(Rss,Rt) + hi->instruction = HEX_INS_S2_LSL_R_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vlslw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3800040) { + // 11000011100sssssPP0ttttt010ddddd | Rdd = lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = lsr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcbc00040) { + // 11001011110sssssPP0ttttt010xxxxx | Rxx += lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += lsr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb400040) { + // 11001011010sssssPP0ttttt010xxxxx | Rxx &= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= lsr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb800040) { + // 11001011100sssssPP0ttttt010xxxxx | Rxx -= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= lsr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb000040) { + // 11001011000sssssPP0ttttt010xxxxx | Rxx |= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= lsr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb600040) { + // 11001011011sssssPP0ttttt010xxxxx | Rxx ^= lsr(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_P_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= lsr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6400040) { + // 11000110010sssssPP0ttttt010ddddd | Rd = lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = lsr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xccc00040) { + // 11001100110sssssPP0ttttt010xxxxx | Rx += lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += lsr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc400040) { + // 11001100010sssssPP0ttttt010xxxxx | Rx &= lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= lsr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc800040) { + // 11001100100sssssPP0ttttt010xxxxx | Rx -= lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_NAC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= lsr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcc000040) { + // 11001100000sssssPP0ttttt010xxxxx | Rx |= lsr(Rs,Rt) + hi->instruction = HEX_INS_S2_LSR_R_R_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= lsr(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3400040) { + // 11000011010sssssPP0ttttt010ddddd | Rdd = vlsrh(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_VH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vlsrh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3000040) { + // 11000011000sssssPP0ttttt010ddddd | Rdd = vlsrw(Rss,Rt) + hi->instruction = HEX_INS_S2_LSR_R_VW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vlsrw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6800000) { + // 11000110100sssssPP0ttttt000ddddd | Rd = setbit(Rs,Rt) + hi->instruction = HEX_INS_S2_SETBIT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = setbit(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1000040) { + // 11000001000sssssPP0ttttt010ddddd | Rdd = shuffeb(Rss,Rtt) + hi->instruction = HEX_INS_S2_SHUFFEB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = shuffeb(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc10000c0) { + // 11000001000sssssPP0ttttt110ddddd | Rdd = shuffeh(Rss,Rtt) + hi->instruction = HEX_INS_S2_SHUFFEH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = shuffeh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1000080) { + // 11000001000sssssPP0ttttt100ddddd | Rdd = shuffob(Rtt,Rss) + hi->instruction = HEX_INS_S2_SHUFFOB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = shuffob(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800000) { + // 11000001100sssssPP0ttttt000ddddd | Rdd = shuffoh(Rtt,Rss) + hi->instruction = HEX_INS_S2_SHUFFOH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = shuffoh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc6800080) { + // 11000110100sssssPP0ttttt100ddddd | Rd = togglebit(Rs,Rt) + hi->instruction = HEX_INS_S2_TOGGLEBIT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = togglebit(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7000000) { + // 11000111000sssssPP0ttttt000000dd | Pd = tstbit(Rs,Rt) + hi->instruction = HEX_INS_S2_TSTBIT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = tstbit(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xc0000000) { + // 11000000000sssssPP0tttttiiiddddd | Rdd = valignb(Rtt,Rss,Ii) + hi->instruction = HEX_INS_S2_VALIGNIB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = valignb(%s,%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xc2000000) { + // 11000010000sssssPP0ttttt0uuddddd | Rdd = valignb(Rtt,Rss,Pu) + hi->instruction = HEX_INS_S2_VALIGNRB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = valignb(%s,%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3c00040) { + // 11000011110sssssPP0ttttt010ddddd | Rdd = vcnegh(Rss,Rt) + hi->instruction = HEX_INS_S2_VCNEGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcnegh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc3c00000) { + // 11000011110sssssPP0ttttt000ddddd | Rdd = vcrotate(Rss,Rt) + hi->instruction = HEX_INS_S2_VCROTATE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcrotate(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xcb2020e0) { + // 11001011001sssssPP1ttttt111xxxxx | Rxx += vrcnegh(Rss,Rt) + hi->instruction = HEX_INS_S2_VRCNEGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcnegh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xc0800000) { + // 11000000100sssssPP0tttttiiiddddd | Rdd = vspliceb(Rss,Rtt,Ii) + hi->instruction = HEX_INS_S2_VSPLICEIB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0xe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = vspliceb(%s,%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xc2800000) { + // 11000010100sssssPP0ttttt0uuddddd | Rdd = vspliceb(Rss,Rtt,Pu) + hi->instruction = HEX_INS_S2_VSPLICERB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vspliceb(%s,%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800040) { + // 11000001100sssssPP0ttttt010ddddd | Rdd = vtrunewh(Rss,Rtt) + hi->instruction = HEX_INS_S2_VTRUNEWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vtrunewh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800080) { + // 11000001100sssssPP0ttttt100ddddd | Rdd = vtrunowh(Rss,Rtt) + hi->instruction = HEX_INS_S2_VTRUNOWH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vtrunowh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc9000040) { + // 11001001000sssssPP0ttttt010ddddd | Rd = extract(Rs,Rtt) + hi->instruction = HEX_INS_S4_EXTRACT_RP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = extract(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c00080) { + // 11000001110sssssPP0ttttt100ddddd | Rdd = extract(Rss,Rtt) + hi->instruction = HEX_INS_S4_EXTRACTP_RP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = extract(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020c0) == 0xc68000c0) { + // 11000110100iiiiiPP0ttttt11iddddd | Rd = lsl(Ii,Rt) + hi->instruction = HEX_INS_S4_LSLI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x1f0000) >> 15) | (((hi_u32)&0x20) >> 5)); // Ii + if (hi->ops[1].op.imm & (1 << 5)) { // signed + hi->ops[1].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[1].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[1].op.imm, tmp, 28); + sprintf(signed_imm[1], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[1], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[1].op.imm); + } + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = lsl(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), signed_imm[1], hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xc7200000) { + // 11000111001sssssPP0ttttt000000dd | Pd = !tstbit(Rs,Rt) + hi->instruction = HEX_INS_S4_NTSTBIT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !tstbit(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000c0) == 0xc3c000c0) { + // 11000011110sssssPPittttt11iddddd | Rdd = vrcrotate(Rss,Rt,Ii) + hi->instruction = HEX_INS_S4_VRCROTATE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x20) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = vrcrotate(%s,%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe000c0) == 0xcba00000) { + // 11001011101sssssPPittttt00ixxxxx | Rxx += vrcrotate(Rss,Rt,Ii) + hi->instruction = HEX_INS_S4_VRCROTATE_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x2000) >> 12) | (((hi_u32)&0x20) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s += vrcrotate(%s,%s,%s0x%x)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400080) { + // 11000001010sssssPP0ttttt100ddddd | Rdd = vxaddsubh(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXADDSUBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxaddsubh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c00000) { + // 11000001110sssssPP0ttttt000ddddd | Rdd = vxaddsubh(Rss,Rtt):rnd:>>1:sat + hi->instruction = HEX_INS_S4_VXADDSUBHR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxaddsubh(%s,%s):rnd:>>1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400000) { + // 11000001010sssssPP0ttttt000ddddd | Rdd = vxaddsubw(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXADDSUBW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxaddsubw(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc14000c0) { + // 11000001010sssssPP0ttttt110ddddd | Rdd = vxsubaddh(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXSUBADDH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxsubaddh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1c00040) { + // 11000001110sssssPP0ttttt010ddddd | Rdd = vxsubaddh(Rss,Rtt):rnd:>>1:sat + hi->instruction = HEX_INS_S4_VXSUBADDHR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxsubaddh(%s,%s):rnd:>>1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1400040) { + // 11000001010sssssPP0ttttt010ddddd | Rdd = vxsubaddw(Rss,Rtt):sat + hi->instruction = HEX_INS_S4_VXSUBADDW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vxsubaddw(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc1800060) { + // 11000001100sssssPP0ttttt011ddddd | Rdd = vtrunehb(Rss,Rtt) + hi->instruction = HEX_INS_S6_VTRUNEHB_PPP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vtrunehb(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xc18000a0) { + // 11000001100sssssPP0ttttt101ddddd | Rdd = vtrunohb(Rss,Rtt) + hi->instruction = HEX_INS_S6_VTRUNOHB_PPP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vtrunohb(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0xd(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe020e0) == 0xd5400060) { + // 11010101010sssssPP0ttttt011ddddd | Rd = add(Rt.h,Rs.h):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_HH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.h,%s.h):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400040) { + // 11010101010sssssPP0ttttt010ddddd | Rd = add(Rt.h,Rs.l):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.h,%s.l):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400020) { + // 11010101010sssssPP0ttttt001ddddd | Rd = add(Rt.l,Rs.h):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_LH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.h):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400000) { + // 11010101010sssssPP0ttttt000ddddd | Rd = add(Rt.l,Rs.l):<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.l):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd54000e0) { + // 11010101010sssssPP0ttttt111ddddd | Rd = add(Rt.h,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_HH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.h,%s.h):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd54000c0) { + // 11010101010sssssPP0ttttt110ddddd | Rd = add(Rt.h,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.h,%s.l):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd54000a0) { + // 11010101010sssssPP0ttttt101ddddd | Rd = add(Rt.l,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_LH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.h):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5400080) { + // 11010101010sssssPP0ttttt100ddddd | Rd = add(Rt.l,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_ADDH_H16_SAT_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.l):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5000040) { + // 11010101000sssssPP0ttttt010ddddd | Rd = add(Rt.l,Rs.h) + hi->instruction = HEX_INS_A2_ADDH_L16_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5000000) { + // 11010101000sssssPP0ttttt000ddddd | Rd = add(Rt.l,Rs.l) + hi->instruction = HEX_INS_A2_ADDH_L16_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd50000c0) { + // 11010101000sssssPP0ttttt110ddddd | Rd = add(Rt.l,Rs.h):sat + hi->instruction = HEX_INS_A2_ADDH_L16_SAT_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5000080) { + // 11010101000sssssPP0ttttt100ddddd | Rd = add(Rt.l,Rs.l):sat + hi->instruction = HEX_INS_A2_ADDH_L16_SAT_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s.l,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd30000e0) { + // 11010011000sssssPP0ttttt111ddddd | Rdd = add(Rss,Rtt) + hi->instruction = HEX_INS_A2_ADDP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd36000a0) { + // 11010011011sssssPP0ttttt101ddddd | Rdd = add(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_ADDPSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd36000e0) { + // 11010011011sssssPP0ttttt111ddddd | Rdd = add(Rss,Rtt):raw:hi + hi->instruction = HEX_INS_A2_ADDSPH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s):raw:hi", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd36000c0) { + // 11010011011sssssPP0ttttt110ddddd | Rdd = add(Rss,Rtt):raw:lo + hi->instruction = HEX_INS_A2_ADDSPL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s):raw:lo", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00000) { + // 11010011111sssssPP0ttttt000ddddd | Rdd = and(Rss,Rtt) + hi->instruction = HEX_INS_A2_ANDP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5c00000) { + // 11010101110sssssPP0ttttt000ddddd | Rd = max(Rs,Rt) + hi->instruction = HEX_INS_A2_MAX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = max(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00080) { + // 11010011110sssssPP0ttttt100ddddd | Rdd = max(Rss,Rtt) + hi->instruction = HEX_INS_A2_MAXP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = max(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5c00080) { + // 11010101110sssssPP0ttttt100ddddd | Rd = maxu(Rs,Rt) + hi->instruction = HEX_INS_A2_MAXU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = maxu(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c000a0) { + // 11010011110sssssPP0ttttt101ddddd | Rdd = maxu(Rss,Rtt) + hi->instruction = HEX_INS_A2_MAXUP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = maxu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5a00000) { + // 11010101101sssssPP0ttttt000ddddd | Rd = min(Rt,Rs) + hi->instruction = HEX_INS_A2_MIN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = min(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a000c0) { + // 11010011101sssssPP0ttttt110ddddd | Rdd = min(Rtt,Rss) + hi->instruction = HEX_INS_A2_MINP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = min(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5a00080) { + // 11010101101sssssPP0ttttt100ddddd | Rd = minu(Rt,Rs) + hi->instruction = HEX_INS_A2_MINU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = minu(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a000e0) { + // 11010011101sssssPP0ttttt111ddddd | Rdd = minu(Rtt,Rss) + hi->instruction = HEX_INS_A2_MINUP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = minu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00040) { + // 11010011111sssssPP0ttttt010ddddd | Rdd = or(Rss,Rtt) + hi->instruction = HEX_INS_A2_ORP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600060) { + // 11010101011sssssPP0ttttt011ddddd | Rd = sub(Rt.h,Rs.h):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_HH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.h,%s.h):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600040) { + // 11010101011sssssPP0ttttt010ddddd | Rd = sub(Rt.h,Rs.l):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.h,%s.l):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600020) { + // 11010101011sssssPP0ttttt001ddddd | Rd = sub(Rt.l,Rs.h):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_LH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.h):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600000) { + // 11010101011sssssPP0ttttt000ddddd | Rd = sub(Rt.l,Rs.l):<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.l):<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd56000e0) { + // 11010101011sssssPP0ttttt111ddddd | Rd = sub(Rt.h,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_HH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.h,%s.h):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd56000c0) { + // 11010101011sssssPP0ttttt110ddddd | Rd = sub(Rt.h,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.h,%s.l):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd56000a0) { + // 11010101011sssssPP0ttttt101ddddd | Rd = sub(Rt.l,Rs.h):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_LH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.h):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5600080) { + // 11010101011sssssPP0ttttt100ddddd | Rd = sub(Rt.l,Rs.l):sat:<<16 + hi->instruction = HEX_INS_A2_SUBH_H16_SAT_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.l):sat:<<16", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5200040) { + // 11010101001sssssPP0ttttt010ddddd | Rd = sub(Rt.l,Rs.h) + hi->instruction = HEX_INS_A2_SUBH_L16_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5200000) { + // 11010101001sssssPP0ttttt000ddddd | Rd = sub(Rt.l,Rs.l) + hi->instruction = HEX_INS_A2_SUBH_L16_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd52000c0) { + // 11010101001sssssPP0ttttt110ddddd | Rd = sub(Rt.l,Rs.h):sat + hi->instruction = HEX_INS_A2_SUBH_L16_SAT_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5200080) { + // 11010101001sssssPP0ttttt100ddddd | Rd = sub(Rt.l,Rs.l):sat + hi->instruction = HEX_INS_A2_SUBH_L16_SAT_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s.l,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd32000e0) { + // 11010011001sssssPP0ttttt111ddddd | Rdd = sub(Rtt,Rss) + hi->instruction = HEX_INS_A2_SUBP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000040) { + // 11010011000sssssPP0ttttt010ddddd | Rdd = vaddh(Rss,Rtt) + hi->instruction = HEX_INS_A2_VADDH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000060) { + // 11010011000sssssPP0ttttt011ddddd | Rdd = vaddh(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000000) { + // 11010011000sssssPP0ttttt000ddddd | Rdd = vaddub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VADDUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000020) { + // 11010011000sssssPP0ttttt001ddddd | Rdd = vaddub(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDUBS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddub(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3000080) { + // 11010011000sssssPP0ttttt100ddddd | Rdd = vadduh(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDUHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vadduh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd30000a0) { + // 11010011000sssssPP0ttttt101ddddd | Rdd = vaddw(Rss,Rtt) + hi->instruction = HEX_INS_A2_VADDW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd30000c0) { + // 11010011000sssssPP0ttttt110ddddd | Rdd = vaddw(Rss,Rtt):sat + hi->instruction = HEX_INS_A2_VADDWS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddw(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400040) { + // 11010011010sssssPP0ttttt010ddddd | Rdd = vavgh(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400080) { + // 11010011010sssssPP0ttttt100ddddd | Rdd = vavgh(Rss,Rtt):crnd + hi->instruction = HEX_INS_A2_VAVGHCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgh(%s,%s):crnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400060) { + // 11010011010sssssPP0ttttt011ddddd | Rdd = vavgh(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGHR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgh(%s,%s):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400000) { + // 11010011010sssssPP0ttttt000ddddd | Rdd = vavgub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3400020) { + // 11010011010sssssPP0ttttt001ddddd | Rdd = vavgub(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGUBR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgub(%s,%s):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd34000a0) { + // 11010011010sssssPP0ttttt101ddddd | Rdd = vavguh(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavguh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd34000c0) { + // 11010011010sssssPP0ttttt110ddddd | Rdd = vavguh(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGUHR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavguh(%s,%s):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600060) { + // 11010011011sssssPP0ttttt011ddddd | Rdd = vavguw(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavguw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600080) { + // 11010011011sssssPP0ttttt100ddddd | Rdd = vavguw(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGUWR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavguw(%s,%s):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600000) { + // 11010011011sssssPP0ttttt000ddddd | Rdd = vavgw(Rss,Rtt) + hi->instruction = HEX_INS_A2_VAVGW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600040) { + // 11010011011sssssPP0ttttt010ddddd | Rdd = vavgw(Rss,Rtt):crnd + hi->instruction = HEX_INS_A2_VAVGWCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgw(%s,%s):crnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3600020) { + // 11010011011sssssPP0ttttt001ddddd | Rdd = vavgw(Rss,Rtt):rnd + hi->instruction = HEX_INS_A2_VAVGWR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgw(%s,%s):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd20000c0) { + // 11010010000sssssPP0ttttt110000dd | Pd = vcmpb.eq(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPBEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpb.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd20000e0) { + // 11010010000sssssPP0ttttt111000dd | Pd = vcmpb.gtu(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPBGTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpb.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000060) { + // 11010010000sssssPP0ttttt011000dd | Pd = vcmph.eq(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPHEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmph.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000080) { + // 11010010000sssssPP0ttttt100000dd | Pd = vcmph.gt(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPHGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmph.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd20000a0) { + // 11010010000sssssPP0ttttt101000dd | Pd = vcmph.gtu(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPHGTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmph.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000000) { + // 11010010000sssssPP0ttttt000000dd | Pd = vcmpw.eq(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPWEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpw.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000020) { + // 11010010000sssssPP0ttttt001000dd | Pd = vcmpw.gt(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPWGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpw.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2000040) { + // 11010010000sssssPP0ttttt010000dd | Pd = vcmpw.gtu(Rss,Rtt) + hi->instruction = HEX_INS_A2_VCMPWGTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpw.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c000c0) { + // 11010011110sssssPP0ttttt110ddddd | Rdd = vmaxb(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmaxb(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00020) { + // 11010011110sssssPP0ttttt001ddddd | Rdd = vmaxh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmaxh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00000) { + // 11010011110sssssPP0ttttt000ddddd | Rdd = vmaxub(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmaxub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00040) { + // 11010011110sssssPP0ttttt010ddddd | Rdd = vmaxuh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmaxuh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a000a0) { + // 11010011101sssssPP0ttttt101ddddd | Rdd = vmaxuw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmaxuw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c00060) { + // 11010011110sssssPP0ttttt011ddddd | Rdd = vmaxw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMAXW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmaxw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3c000e0) { + // 11010011110sssssPP0ttttt111ddddd | Rdd = vminb(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vminb(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00020) { + // 11010011101sssssPP0ttttt001ddddd | Rdd = vminh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vminh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00000) { + // 11010011101sssssPP0ttttt000ddddd | Rdd = vminub(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vminub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00040) { + // 11010011101sssssPP0ttttt010ddddd | Rdd = vminuh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vminuh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00080) { + // 11010011101sssssPP0ttttt100ddddd | Rdd = vminuw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINUW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vminuw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3a00060) { + // 11010011101sssssPP0ttttt011ddddd | Rdd = vminw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VMINW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vminw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800000) { + // 11010011100sssssPP0ttttt000ddddd | Rdd = vnavgh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VNAVGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800040) { + // 11010011100sssssPP0ttttt010ddddd | Rdd = vnavgh(Rtt,Rss):crnd:sat + hi->instruction = HEX_INS_A2_VNAVGHCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgh(%s,%s):crnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800020) { + // 11010011100sssssPP0ttttt001ddddd | Rdd = vnavgh(Rtt,Rss):rnd:sat + hi->instruction = HEX_INS_A2_VNAVGHR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800060) { + // 11010011100sssssPP0ttttt011ddddd | Rdd = vnavgw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VNAVGW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd38000c0) { + // 11010011100sssssPP0ttttt110ddddd | Rdd = vnavgw(Rtt,Rss):crnd:sat + hi->instruction = HEX_INS_A2_VNAVGWCR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgw(%s,%s):crnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3800080) { + // 11010011100sssssPP0ttttt100ddddd | Rdd = vnavgw(Rtt,Rss):rnd:sat + hi->instruction = HEX_INS_A2_VNAVGWR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgw(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200040) { + // 11010011001sssssPP0ttttt010ddddd | Rdd = vsubh(Rtt,Rss) + hi->instruction = HEX_INS_A2_VSUBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200060) { + // 11010011001sssssPP0ttttt011ddddd | Rdd = vsubh(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200000) { + // 11010011001sssssPP0ttttt000ddddd | Rdd = vsubub(Rtt,Rss) + hi->instruction = HEX_INS_A2_VSUBUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200020) { + // 11010011001sssssPP0ttttt001ddddd | Rdd = vsubub(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBUBS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubub(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3200080) { + // 11010011001sssssPP0ttttt100ddddd | Rdd = vsubuh(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBUHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubuh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd32000a0) { + // 11010011001sssssPP0ttttt101ddddd | Rdd = vsubw(Rtt,Rss) + hi->instruction = HEX_INS_A2_VSUBW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd32000c0) { + // 11010011001sssssPP0ttttt110ddddd | Rdd = vsubw(Rtt,Rss):sat + hi->instruction = HEX_INS_A2_VSUBWS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubw(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00080) { + // 11010011111sssssPP0ttttt100ddddd | Rdd = xor(Rss,Rtt) + hi->instruction = HEX_INS_A2_XORP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = xor(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00020) { + // 11010011111sssssPP0ttttt001ddddd | Rdd = and(Rtt,~Rss) + hi->instruction = HEX_INS_A4_ANDNP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,~%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd4200000) { + // 11010100001sssssPP0ttttt000ddddd | Rdd = bitsplit(Rs,Rt) + hi->instruction = HEX_INS_A4_BITSPLIT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = bitsplit(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd20020a0) { + // 11010010000sssssPP1ttttt101000dd | Pd = boundscheck(Rss,Rtt):raw:hi + hi->instruction = HEX_INS_A4_BOUNDSCHECK_HI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = boundscheck(%s,%s):raw:hi", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002080) { + // 11010010000sssssPP1ttttt100000dd | Pd = boundscheck(Rss,Rtt):raw:lo + hi->instruction = HEX_INS_A4_BOUNDSCHECK_LO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = boundscheck(%s,%s):raw:lo", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdd000000) { + // 11011101000sssssPP0iiiiiiii000dd | Pd = cmpb.eq(Rs,Ii) + hi->instruction = HEX_INS_A4_CMPBEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmpb.eq(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdd200000) { + // 11011101001sssssPP0iiiiiiii000dd | Pd = cmpb.gt(Rs,Ii) + hi->instruction = HEX_INS_A4_CMPBGTI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmpb.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0301c) == 0xdd400000) { + // 11011101010sssssPP00iiiiiii000dd | Pd = cmpb.gtu(Rs,Ii) + hi->instruction = HEX_INS_A4_CMPBGTUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmpb.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdd000008) { + // 11011101000sssssPP0iiiiiiii010dd | Pd = cmph.eq(Rs,Ii) + hi->instruction = HEX_INS_A4_CMPHEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmph.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdd200008) { + // 11011101001sssssPP0iiiiiiii010dd | Pd = cmph.gt(Rs,Ii) + hi->instruction = HEX_INS_A4_CMPHGTI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmph.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0301c) == 0xdd400008) { + // 11011101010sssssPP00iiiiiii010dd | Pd = cmph.gtu(Rs,Ii) + hi->instruction = HEX_INS_A4_CMPHGTUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = cmph.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e000e0) { + // 11010011111sssssPP0ttttt111ddddd | Rd = modwrap(Rs,Rt) + hi->instruction = HEX_INS_A4_MODWRAPU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = modwrap(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd3e00060) { + // 11010011111sssssPP0ttttt011ddddd | Rdd = or(Rtt,~Rss) + hi->instruction = HEX_INS_A4_ORNP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,~%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002060) { + // 11010010000sssssPP1ttttt011000dd | Pd = tlbmatch(Rss,Rt) + hi->instruction = HEX_INS_A4_TLBMATCH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = tlbmatch(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002000) { + // 11010010000sssssPP1ttttt000000dd | Pd = any8(vcmpb.eq(Rss,Rtt)) + hi->instruction = HEX_INS_A4_VCMPBEQ_ANY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = any8(vcmpb.eq(%s,%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdc000000) { + // 11011100000sssssPP0iiiiiiii000dd | Pd = vcmpb.eq(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPBEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmpb.eq(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002040) { + // 11010010000sssssPP1ttttt010000dd | Pd = vcmpb.gt(Rss,Rtt) + hi->instruction = HEX_INS_A4_VCMPBGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpb.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdc200000) { + // 11011100001sssssPP0iiiiiiii000dd | Pd = vcmpb.gt(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPBGTI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmpb.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0301c) == 0xdc400000) { + // 11011100010sssssPP00iiiiiii000dd | Pd = vcmpb.gtu(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPBGTUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmpb.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdc000008) { + // 11011100000sssssPP0iiiiiiii010dd | Pd = vcmph.eq(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPHEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmph.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdc200008) { + // 11011100001sssssPP0iiiiiiii010dd | Pd = vcmph.gt(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPHGTI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmph.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0301c) == 0xdc400008) { + // 11011100010sssssPP00iiiiiii010dd | Pd = vcmph.gtu(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPHGTUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmph.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdc000010) { + // 11011100000sssssPP0iiiiiiii100dd | Pd = vcmpw.eq(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPWEQI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmpw.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0201c) == 0xdc200010) { + // 11011100001sssssPP0iiiiiiii100dd | Pd = vcmpw.gt(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPWGTI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "#" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "#" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmpw.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe0301c) == 0xdc400010) { + // 11011100010sssssPP00iiiiiii100dd | Pd = vcmpw.gtu(Rss,Ii) + hi->instruction = HEX_INS_A4_VCMPWGTUI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0xfe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = vcmpw.gtu(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2002020) { + // 11010010000sssssPP1ttttt001000dd | Pd = !any8(vcmpb.eq(Rss,Rtt)) + hi->instruction = HEX_INS_A6_VCMPBEQ_NOTANY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !any8(vcmpb.eq(%s,%s))", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2800000) { + // 11010010100sssssPP0ttttt000000dd | Pd = cmp.eq(Rss,Rtt) + hi->instruction = HEX_INS_C2_CMPEQP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2800040) { + // 11010010100sssssPP0ttttt010000dd | Pd = cmp.gt(Rss,Rtt) + hi->instruction = HEX_INS_C2_CMPGTP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2800080) { + // 11010010100sssssPP0ttttt100000dd | Pd = cmp.gtu(Rss,Rtt) + hi->instruction = HEX_INS_C2_CMPGTUP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xd1000000) { + // 11010001000sssssPP0ttttt0uuddddd | Rdd = vmux(Pu,Rss,Rtt) + hi->instruction = HEX_INS_C2_VMUX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmux(%s,%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe03c1c) == 0xdc800010) { + // 11011100100sssssPP0000iiiii100dd | Pd = dfclass(Rss,Ii) + hi->instruction = HEX_INS_F2_DFCLASS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x3e0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = dfclass(%s,%s0x%x)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00000) { + // 11010010111sssssPP0ttttt000000dd | Pd = dfcmp.eq(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfcmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00040) { + // 11010010111sssssPP0ttttt010000dd | Pd = dfcmp.ge(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPGE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfcmp.ge(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00020) { + // 11010010111sssssPP0ttttt001000dd | Pd = dfcmp.gt(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfcmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xd2e00060) { + // 11010010111sssssPP0ttttt011000dd | Pd = dfcmp.uo(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFCMPUO; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfcmp.uo(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffdf0000) == 0xd9400000) { + // 1101100101i00000PPiiiiiiiiiddddd | Rdd = dfmake(Ii):neg + hi->instruction = HEX_INS_F2_DFIMM_N; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = dfmake(%s0x%x):neg", hex_get_double_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffdf0000) == 0xd9000000) { + // 1101100100i00000PPiiiiiiiiiddddd | Rdd = dfmake(Ii):pos + hi->instruction = HEX_INS_F2_DFIMM_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = dfmake(%s0x%x):pos", hex_get_double_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffdf0000) == 0xd6400000) { + // 1101011001i00000PPiiiiiiiiiddddd | Rd = sfmake(Ii):neg + hi->instruction = HEX_INS_F2_SFIMM_N; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = sfmake(%s0x%x):neg", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffdf0000) == 0xd6000000) { + // 1101011000i00000PPiiiiiiiiiddddd | Rd = sfmake(Ii):pos + hi->instruction = HEX_INS_F2_SFIMM_P; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 2; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = sfmake(%s0x%x):pos", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[1].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000000) == 0xd8000000) { + // 11011000IiisssssPPidddddiiiIIIII | Rd = add(Ii,mpyi(Rs,II)) + hi->instruction = HEX_INS_M4_MPYRI_ADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x800000) >> 18) | (((hi_u32)&0x1f) >> 0)); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s0x%x,mpyi(%s,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff800000) == 0xdf800000) { + // 110111111iisssssPPidddddiiiuuuuu | Rd = add(Ru,mpyi(Rs,Ii)) + hi->instruction = HEX_INS_M4_MPYRI_ADDR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,mpyi(%s,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff800000) == 0xdf000000) { + // 110111110iisssssPPidddddiiiuuuuu | Rd = add(Ru,mpyi(Ii,Rs)) + hi->instruction = HEX_INS_M4_MPYRI_ADDR_U2; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)) << 2; // scaled Ii + hi->ops[2].attr = HEX_OP_IMM_SCALED; + hi->ops[2].shift = 2; + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,mpyi(%s0x%x,%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm, hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff800000) == 0xd7000000) { + // 110101110iisssssPPitttttiiiddddd | Rd = add(Ii,mpyi(Rs,Rt)) + hi->instruction = HEX_INS_M4_MPYRR_ADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s0x%x,mpyi(%s,%s))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd0000000) { + // 11010000000sssssPP0ttttt000ddddd | Rd = parity(Rss,Rtt) + hi->instruction = HEX_INS_S2_PARITYP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = parity(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff800000) == 0xdb000000) { + // 110110110iisssssPPidddddiiiuuuuu | Rd = add(Rs,add(Ru,Ii)) + hi->instruction = HEX_INS_S4_ADDADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + if (hi->ops[3].op.imm & (1 << 5)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,add(%s,%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000004) { + // 11011110iiixxxxxPPiIIIIIiii0i100 | Rx = add(Ii,asl(Rxin,II)) + hi->instruction = HEX_INS_S4_ADDI_ASL_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s0x%x,asl(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000014) { + // 11011110iiixxxxxPPiIIIIIiii1i100 | Rx = add(Ii,lsr(Rxin,II)) + hi->instruction = HEX_INS_S4_ADDI_LSR_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s0x%x,lsr(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000000) { + // 11011110iiixxxxxPPiIIIIIiii0i000 | Rx = and(Ii,asl(Rxin,II)) + hi->instruction = HEX_INS_S4_ANDI_ASL_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s0x%x,asl(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000010) { + // 11011110iiixxxxxPPiIIIIIiii1i000 | Rx = and(Ii,lsr(Rxin,II)) + hi->instruction = HEX_INS_S4_ANDI_LSR_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = and(%s0x%x,lsr(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0xda000000) { + // 1101101000isssssPPiiiiiiiiixxxxx | Rx |= and(Rs,Ii) + hi->instruction = HEX_INS_S4_OR_ANDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= and(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0xda400000) { + // 1101101001ixxxxxPPiiiiiiiiiuuuuu | Rx = or(Ru,and(Rxin,Ii)) + hi->instruction = HEX_INS_S4_OR_ANDIX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[3].op.imm & (1 << 9)) { // signed + hi->ops[3].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[3]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[3].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[3].op.imm, tmp, 28); + sprintf(signed_imm[3], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[3], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[3].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = or(%s,and(%sin,%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), signed_imm[3]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffc00000) == 0xda800000) { + // 1101101010isssssPPiiiiiiiiixxxxx | Rx |= or(Rs,Ii) + hi->instruction = HEX_INS_S4_OR_ORI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x200000) >> 12) | (((hi_u32)&0x3fe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 9)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 9); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s |= or(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000002) { + // 11011110iiixxxxxPPiIIIIIiii0i010 | Rx = or(Ii,asl(Rxin,II)) + hi->instruction = HEX_INS_S4_ORI_ASL_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = or(%s0x%x,asl(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000012) { + // 11011110iiixxxxxPPiIIIIIiii1i010 | Rx = or(Ii,lsr(Rxin,II)) + hi->instruction = HEX_INS_S4_ORI_LSR_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = or(%s0x%x,lsr(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5e00000) { + // 11010101111sssssPP0ttttt000ddddd | Rd = parity(Rs,Rt) + hi->instruction = HEX_INS_S4_PARITY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = parity(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff800000) == 0xdb800000) { + // 110110111iisssssPPidddddiiiuuuuu | Rd = add(Rs,sub(Ii,Ru)) + hi->instruction = HEX_INS_S4_SUBADDI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = ((((hi_u32)&0x600000) >> 17) | (((hi_u32)&0x2000) >> 10) | (((hi_u32)&0xe0) >> 5)); // Ii + if (hi->ops[2].op.imm & (1 << 5)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 5); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = add(%s,sub(%s,%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2], hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000006) { + // 11011110iiixxxxxPPiIIIIIiii0i110 | Rx = sub(Ii,asl(Rxin,II)) + hi->instruction = HEX_INS_S4_SUBI_ASL_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sub(%s0x%x,asl(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xff000017) == 0xde000016) { + // 11011110iiixxxxxPPiIIIIIiii1i110 | Rx = sub(Ii,lsr(Rxin,II)) + hi->instruction = HEX_INS_S4_SUBI_LSR_RI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_IMM; + hi->ops[1].op.imm = ((((hi_u32)&0xe00000) >> 16) | (((hi_u32)&0x2000) >> 9) | (((hi_u32)&0xe0) >> 4) | (((hi_u32)&0x8) >> 3)); // Ii + hex_extend_op(state, &(hi->ops[1]), false, addr); // Extension possible + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rx32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_IMM; + hi->ops[3].op.imm = (((hi_u32)&0x1f00) >> 8); // II + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[1].imm = hi->ops[1].op.imm; + hi->ana_op.analysis_vals[3].imm = hi->ops[3].op.imm; + sprintf(hi->mnem_infix, "%s = sub(%s0x%x,lsr(%sin,%s0x%x))", hex_get_int_regs(hi->ops[0].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[1].op.imm, hex_get_int_regs(hi->ops[2].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[3].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5800000) { + // 11010101100sssssPP0ttttt000ddddd | Rd = add(Rs,Rt):sat:deprecated + hi->instruction = HEX_INS_DEP_A2_ADDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s):sat:deprecated", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd5800080) { + // 11010101100sssssPP0ttttt100ddddd | Rd = sub(Rt,Rs):sat:deprecated + hi->instruction = HEX_INS_DEP_A2_SUBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s,%s):sat:deprecated", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xd4000000) { + // 11010100000sssssPP0ttttt000ddddd | Rdd = packhl(Rs,Rt):deprecated + hi->instruction = HEX_INS_DEP_S2_PACKHL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = packhl(%s,%s):deprecated", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0xe(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + char signed_imm[6][32] = { 0 }; + if ((hi_u32 & 0xffe020e0) == 0xe8400020) { + // 11101000010sssssPP0ttttt001ddddd | Rdd = vraddub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRADDUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vraddub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea400020) { + // 11101010010sssssPP0ttttt001xxxxx | Rxx += vraddub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRADDUB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vraddub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400040) { + // 11101000010sssssPP0ttttt010ddddd | Rdd = vrsadub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRSADUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrsadub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea400040) { + // 11101010010sssssPP0ttttt010xxxxx | Rxx += vrsadub(Rss,Rtt) + hi->instruction = HEX_INS_A2_VRSADUB_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrsadub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xeaa00000) { + // 11101010101sssssPP0ttttt0eexxxxx | Rxx,Pe = vacsh(Rss,Rtt) + hi->instruction = HEX_INS_A5_ACS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s,%s = vacsh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xeae00000) { + // 11101010111sssssPP0ttttt0eeddddd | Rdd,Pe = vminub(Rtt,Rss) + hi->instruction = HEX_INS_A6_VMINUB_RDP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[3].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s,%s = vminub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg), hex_get_double_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000060) { + // 11101000000sssssPP0ttttt011ddddd | Rdd = dfadd(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFADD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfadd(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8200060) { + // 11101000001sssssPP0ttttt011ddddd | Rdd = dfmax(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMAX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfmax(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00060) { + // 11101000110sssssPP0ttttt011ddddd | Rdd = dfmin(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMIN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfmin(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400060) { + // 11101000010sssssPP0ttttt011ddddd | Rdd = dfmpyfix(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYFIX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfmpyfix(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea800060) { + // 11101010100sssssPP0ttttt011xxxxx | Rxx += dfmpyhh(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYHH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += dfmpyhh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea000060) { + // 11101010000sssssPP0ttttt011xxxxx | Rxx += dfmpylh(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYLH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += dfmpylh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00060) { + // 11101000101sssssPP0ttttt011ddddd | Rdd = dfmpyll(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFMPYLL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfmpyll(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800060) { + // 11101000100sssssPP0ttttt011ddddd | Rdd = dfsub(Rss,Rtt) + hi->instruction = HEX_INS_F2_DFSUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = dfsub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeb000000) { + // 11101011000sssssPP0ttttt000ddddd | Rd = sfadd(Rs,Rt) + hi->instruction = HEX_INS_F2_SFADD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfadd(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xebc00020) { + // 11101011110sssssPP0ttttt001ddddd | Rd = sffixupd(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFIXUPD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sffixupd(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xebc00000) { + // 11101011110sssssPP0ttttt000ddddd | Rd = sffixupn(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFIXUPN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sffixupn(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef000080) { + // 11101111000sssssPP0ttttt100xxxxx | Rx += sfmpy(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFMA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += sfmpy(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef0000c0) { + // 11101111000sssssPP0ttttt110xxxxx | Rx += sfmpy(Rs,Rt):lib + hi->instruction = HEX_INS_F2_SFFMA_LIB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += sfmpy(%s,%s):lib", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xef600080) { + // 11101111011sssssPP0ttttt1uuxxxxx | Rx += sfmpy(Rs,Rt,Pu):scale + hi->instruction = HEX_INS_F2_SFFMA_SC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += sfmpy(%s,%s,%s):scale", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_pred_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef0000a0) { + // 11101111000sssssPP0ttttt101xxxxx | Rx -= sfmpy(Rs,Rt) + hi->instruction = HEX_INS_F2_SFFMS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= sfmpy(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef0000e0) { + // 11101111000sssssPP0ttttt111xxxxx | Rx -= sfmpy(Rs,Rt):lib + hi->instruction = HEX_INS_F2_SFFMS_LIB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= sfmpy(%s,%s):lib", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeb800000) { + // 11101011100sssssPP0ttttt000ddddd | Rd = sfmax(Rs,Rt) + hi->instruction = HEX_INS_F2_SFMAX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfmax(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeb800020) { + // 11101011100sssssPP0ttttt001ddddd | Rd = sfmin(Rs,Rt) + hi->instruction = HEX_INS_F2_SFMIN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfmin(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeb400000) { + // 11101011010sssssPP0ttttt000ddddd | Rd = sfmpy(Rs,Rt) + hi->instruction = HEX_INS_F2_SFMPY; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfmpy(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xebe00080) { + // 11101011111sssssPP0ttttt1eeddddd | Rd,Pe = sfrecipa(Rs,Rt) + hi->instruction = HEX_INS_F2_SFRECIPA; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pe4 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s,%s = sfrecipa(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeb000020) { + // 11101011000sssssPP0ttttt001ddddd | Rd = sfsub(Rs,Rt) + hi->instruction = HEX_INS_F2_SFSUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sfsub(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef000020) { + // 11101111000sssssPP0ttttt001xxxxx | Rx += add(Rs,Rt) + hi->instruction = HEX_INS_M2_ACCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += add(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xe2000000) { + // 11100010000sssssPP0iiiiiiiixxxxx | Rx += add(Rs,Ii) + hi->instruction = HEX_INS_M2_ACCII; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += add(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7000020) { + // 11100111000sssssPP0ttttt001xxxxx | Rxx += cmpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_CMACI_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpyi(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7000040) { + // 11100111000sssssPP0ttttt010xxxxx | Rxx += cmpyr(Rs,Rt) + hi->instruction = HEX_INS_M2_CMACR_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpyr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe70000c0) { + // 11100111000sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt):sat + hi->instruction = HEX_INS_M2_CMACS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpy(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe78000c0) { + // 11100111100sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_CMACS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpy(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe74000c0) { + // 11100111010sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt*):sat + hi->instruction = HEX_INS_M2_CMACSC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpy(%s,%s*):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7c000c0) { + // 11100111110sssssPP0ttttt110xxxxx | Rxx += cmpy(Rs,Rt*):<<1:sat + hi->instruction = HEX_INS_M2_CMACSC_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpy(%s,%s*):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5000020) { + // 11100101000sssssPP0ttttt001ddddd | Rdd = cmpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_CMPYI_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyi(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5000040) { + // 11100101000sssssPP0ttttt010ddddd | Rdd = cmpyr(Rs,Rt) + hi->instruction = HEX_INS_M2_CMPYR_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed2000c0) { + // 11101101001sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt):rnd:sat + hi->instruction = HEX_INS_M2_CMPYRS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeda000c0) { + // 11101101101sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_CMPYRS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed6000c0) { + // 11101101011sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt*):rnd:sat + hi->instruction = HEX_INS_M2_CMPYRSC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s*):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xede000c0) { + // 11101101111sssssPP0ttttt110ddddd | Rd = cmpy(Rs,Rt*):<<1:rnd:sat + hi->instruction = HEX_INS_M2_CMPYRSC_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s*):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe50000c0) { + // 11100101000sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt):sat + hi->instruction = HEX_INS_M2_CMPYS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe58000c0) { + // 11100101100sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_CMPYS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe54000c0) { + // 11100101010sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt*):sat + hi->instruction = HEX_INS_M2_CMPYSC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s*):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5c000c0) { + // 11100101110sssssPP0ttttt110ddddd | Rdd = cmpy(Rs,Rt*):<<1:sat + hi->instruction = HEX_INS_M2_CMPYSC_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpy(%s,%s*):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe70000e0) { + // 11100111000sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt):sat + hi->instruction = HEX_INS_M2_CNACS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= cmpy(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe78000e0) { + // 11100111100sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_CNACS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= cmpy(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe74000e0) { + // 11100111010sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt*):sat + hi->instruction = HEX_INS_M2_CNACSC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= cmpy(%s,%s*):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7c000e0) { + // 11100111110sssssPP0ttttt111xxxxx | Rxx -= cmpy(Rs,Rt*):<<1:sat + hi->instruction = HEX_INS_M2_CNACSC_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= cmpy(%s,%s*):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7000000) { + // 11100111000sssssPP0ttttt000xxxxx | Rxx += mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYSS_ACC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7200000) { + // 11100111001sssssPP0ttttt000xxxxx | Rxx -= mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYSS_NAC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed200020) { + // 11101101001sssssPP0ttttt001ddddd | Rd = mpy(Rs,Rt):rnd + hi->instruction = HEX_INS_M2_DPMPYSS_RND_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5000000) { + // 11100101000sssssPP0ttttt000ddddd | Rdd = mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYSS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7400000) { + // 11100111010sssssPP0ttttt000xxxxx | Rxx += mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYUU_ACC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7600000) { + // 11100111011sssssPP0ttttt000xxxxx | Rxx -= mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYUU_NAC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5400000) { + // 11100101010sssssPP0ttttt000ddddd | Rdd = mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_DPMPYUU_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00080) { + // 11101101101sssssPP0ttttt100ddddd | Rd = mpy(Rs,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_M2_HMMPYH_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s.h):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00000) { + // 11101101101sssssPP0ttttt000ddddd | Rd = mpy(Rs,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_HMMPYH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xede00080) { + // 11101101111sssssPP0ttttt100ddddd | Rd = mpy(Rs,Rt.l):<<1:rnd:sat + hi->instruction = HEX_INS_M2_HMMPYL_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s.l):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00020) { + // 11101101101sssssPP0ttttt001ddddd | Rd = mpy(Rs,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_HMMPYL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef000000) { + // 11101111000sssssPP0ttttt000xxxxx | Rx += mpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_MACI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyi(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xe1800000) { + // 11100001100sssssPP0iiiiiiiixxxxx | Rx -= mpyi(Rs,Ii) + hi->instruction = HEX_INS_M2_MACSIN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= mpyi(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xe1000000) { + // 11100001000sssssPP0iiiiiiiixxxxx | Rx += mpyi(Rs,Ii) + hi->instruction = HEX_INS_M2_MACSIP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s += mpyi(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea2000e0) { + // 11101010001sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACHS_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywoh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa000e0) { + // 11101010101sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACHS_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywoh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea0000e0) { + // 11101010000sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACHS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywoh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea8000e0) { + // 11101010100sssssPP0ttttt111xxxxx | Rxx += vmpywoh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACHS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywoh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea2000a0) { + // 11101010001sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACLS_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa000a0) { + // 11101010101sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACLS_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea0000a0) { + // 11101010000sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACLS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea8000a0) { + // 11101010100sssssPP0ttttt101xxxxx | Rxx += vmpyweh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACLS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea6000e0) { + // 11101010011sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACUHS_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywouh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeae000e0) { + // 11101010111sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACUHS_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywouh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea4000e0) { + // 11101010010sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACUHS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywouh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeac000e0) { + // 11101010110sssssPP0ttttt111xxxxx | Rxx += vmpywouh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACUHS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpywouh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea6000a0) { + // 11101010011sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMACULS_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweuh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeae000a0) { + // 11101010111sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMACULS_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweuh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea4000a0) { + // 11101010010sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMACULS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweuh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeac000a0) { + // 11101010110sssssPP0ttttt101xxxxx | Rxx += vmpyweuh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMACULS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyweuh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe82000e0) { + // 11101000001sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYH_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywoh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a000e0) { + // 11101000101sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYH_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywoh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe80000e0) { + // 11101000000sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywoh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe88000e0) { + // 11101000100sssssPP0ttttt111ddddd | Rdd = vmpywoh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywoh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe82000a0) { + // 11101000001sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYL_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a000a0) { + // 11101000101sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYL_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe80000a0) { + // 11101000000sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe88000a0) { + // 11101000100sssssPP0ttttt101ddddd | Rdd = vmpyweh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe86000e0) { + // 11101000011sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYUH_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywouh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e000e0) { + // 11101000111sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYUH_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywouh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe84000e0) { + // 11101000010sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYUH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywouh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c000e0) { + // 11101000110sssssPP0ttttt111ddddd | Rdd = vmpywouh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYUH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpywouh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe86000a0) { + // 11101000011sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_MMPYUL_RS0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweuh(%s,%s):rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e000a0) { + // 11101000111sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MMPYUL_RS1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweuh(%s,%s):<<1:rnd:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe84000a0) { + // 11101000010sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_MMPYUL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweuh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c000a0) { + // 11101000110sssssPP0ttttt101ddddd | Rdd = vmpyweuh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_MMPYUL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyweuh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef800000) { + // 11101111100sssssPP0ttttt000xxxxx | Rx -= mpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_MNACI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyi(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee000060) { + // 11101110000sssssPP0ttttt011xxxxx | Rx += mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPY_ACC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee800060) { + // 11101110100sssssPP0ttttt011xxxxx | Rx += mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee000040) { + // 11101110000sssssPP0ttttt010xxxxx | Rx += mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPY_ACC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee800040) { + // 11101110100sssssPP0ttttt010xxxxx | Rx += mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee000020) { + // 11101110000sssssPP0ttttt001xxxxx | Rx += mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPY_ACC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee800020) { + // 11101110100sssssPP0ttttt001xxxxx | Rx += mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee000000) { + // 11101110000sssssPP0ttttt000xxxxx | Rx += mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPY_ACC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee800000) { + // 11101110100sssssPP0ttttt000xxxxx | Rx += mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_ACC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee0000e0) { + // 11101110000sssssPP0ttttt111xxxxx | Rx += mpy(Rs.h,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee8000e0) { + // 11101110100sssssPP0ttttt111xxxxx | Rx += mpy(Rs.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee0000c0) { + // 11101110000sssssPP0ttttt110xxxxx | Rx += mpy(Rs.h,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee8000c0) { + // 11101110100sssssPP0ttttt110xxxxx | Rx += mpy(Rs.h,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee0000a0) { + // 11101110000sssssPP0ttttt101xxxxx | Rx += mpy(Rs.l,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee8000a0) { + // 11101110100sssssPP0ttttt101xxxxx | Rx += mpy(Rs.l,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee000080) { + // 11101110000sssssPP0ttttt100xxxxx | Rx += mpy(Rs.l,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee800080) { + // 11101110100sssssPP0ttttt100xxxxx | Rx += mpy(Rs.l,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_ACC_SAT_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec000060) { + // 11101100000sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPY_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec800060) { + // 11101100100sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec000040) { + // 11101100000sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPY_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec800040) { + // 11101100100sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec000020) { + // 11101100000sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPY_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec800020) { + // 11101100100sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec000000) { + // 11101100000sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPY_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec800000) { + // 11101100100sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee200060) { + // 11101110001sssssPP0ttttt011xxxxx | Rx -= mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPY_NAC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00060) { + // 11101110101sssssPP0ttttt011xxxxx | Rx -= mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee200040) { + // 11101110001sssssPP0ttttt010xxxxx | Rx -= mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPY_NAC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00040) { + // 11101110101sssssPP0ttttt010xxxxx | Rx -= mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee200020) { + // 11101110001sssssPP0ttttt001xxxxx | Rx -= mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPY_NAC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00020) { + // 11101110101sssssPP0ttttt001xxxxx | Rx -= mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee200000) { + // 11101110001sssssPP0ttttt000xxxxx | Rx -= mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPY_NAC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00000) { + // 11101110101sssssPP0ttttt000xxxxx | Rx -= mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPY_NAC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee2000e0) { + // 11101110001sssssPP0ttttt111xxxxx | Rx -= mpy(Rs.h,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea000e0) { + // 11101110101sssssPP0ttttt111xxxxx | Rx -= mpy(Rs.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee2000c0) { + // 11101110001sssssPP0ttttt110xxxxx | Rx -= mpy(Rs.h,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea000c0) { + // 11101110101sssssPP0ttttt110xxxxx | Rx -= mpy(Rs.h,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee2000a0) { + // 11101110001sssssPP0ttttt101xxxxx | Rx -= mpy(Rs.l,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea000a0) { + // 11101110101sssssPP0ttttt101xxxxx | Rx -= mpy(Rs.l,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee200080) { + // 11101110001sssssPP0ttttt100xxxxx | Rx -= mpy(Rs.l,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeea00080) { + // 11101110101sssssPP0ttttt100xxxxx | Rx -= mpy(Rs.l,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_NAC_SAT_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec200060) { + // 11101100001sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPY_RND_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00060) { + // 11101100101sssssPP0ttttt011ddddd | Rd = mpy(Rs.h,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):<<1:rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec200040) { + // 11101100001sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPY_RND_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00040) { + // 11101100101sssssPP0ttttt010ddddd | Rd = mpy(Rs.h,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):<<1:rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec200020) { + // 11101100001sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPY_RND_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00020) { + // 11101100101sssssPP0ttttt001ddddd | Rd = mpy(Rs.l,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):<<1:rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec200000) { + // 11101100001sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPY_RND_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00000) { + // 11101100101sssssPP0ttttt000ddddd | Rd = mpy(Rs.l,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPY_RND_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):<<1:rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec0000e0) { + // 11101100000sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_SAT_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec8000e0) { + // 11101100100sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec0000c0) { + // 11101100000sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_SAT_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec8000c0) { + // 11101100100sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec0000a0) { + // 11101100000sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):sat + hi->instruction = HEX_INS_M2_MPY_SAT_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec8000a0) { + // 11101100100sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec000080) { + // 11101100000sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):sat + hi->instruction = HEX_INS_M2_MPY_SAT_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec800080) { + // 11101100100sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):<<1:sat + hi->instruction = HEX_INS_M2_MPY_SAT_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec2000e0) { + // 11101100001sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca000e0) { + // 11101100101sssssPP0ttttt111ddddd | Rd = mpy(Rs.h,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec2000c0) { + // 11101100001sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca000c0) { + // 11101100101sssssPP0ttttt110ddddd | Rd = mpy(Rs.h,Rt.l):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec2000a0) { + // 11101100001sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca000a0) { + // 11101100101sssssPP0ttttt101ddddd | Rd = mpy(Rs.l,Rt.h):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec200080) { + // 11101100001sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeca00080) { + // 11101100101sssssPP0ttttt100ddddd | Rd = mpy(Rs.l,Rt.l):<<1:rnd:sat + hi->instruction = HEX_INS_M2_MPY_SAT_RND_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed000020) { + // 11101101000sssssPP0ttttt001ddddd | Rd = mpy(Rs,Rt) + hi->instruction = HEX_INS_M2_MPY_UP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeda00040) { + // 11101101101sssssPP0ttttt010ddddd | Rd = mpy(Rs,Rt):<<1 + hi->instruction = HEX_INS_M2_MPY_UP_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xede00000) { + // 11101101111sssssPP0ttttt000ddddd | Rd = mpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_MPY_UP_S1_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s,%s):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000060) { + // 11100110000sssssPP0ttttt011xxxxx | Rxx += mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_ACC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800060) { + // 11100110100sssssPP0ttttt011xxxxx | Rxx += mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000040) { + // 11100110000sssssPP0ttttt010xxxxx | Rxx += mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_ACC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800040) { + // 11100110100sssssPP0ttttt010xxxxx | Rxx += mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.h,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000020) { + // 11100110000sssssPP0ttttt001xxxxx | Rxx += mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_ACC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800020) { + // 11100110100sssssPP0ttttt001xxxxx | Rxx += mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6000000) { + // 11100110000sssssPP0ttttt000xxxxx | Rxx += mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_ACC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6800000) { + // 11100110100sssssPP0ttttt000xxxxx | Rxx += mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_ACC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s.l,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000060) { + // 11100100000sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800060) { + // 11100100100sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000040) { + // 11100100000sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800040) { + // 11100100100sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000020) { + // 11100100000sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800020) { + // 11100100100sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4000000) { + // 11100100000sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4800000) { + // 11100100100sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200060) { + // 11100110001sssssPP0ttttt011xxxxx | Rxx -= mpy(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_NAC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00060) { + // 11100110101sssssPP0ttttt011xxxxx | Rxx -= mpy(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200040) { + // 11100110001sssssPP0ttttt010xxxxx | Rxx -= mpy(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_NAC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00040) { + // 11100110101sssssPP0ttttt010xxxxx | Rxx -= mpy(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.h,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200020) { + // 11100110001sssssPP0ttttt001xxxxx | Rxx -= mpy(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYD_NAC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00020) { + // 11100110101sssssPP0ttttt001xxxxx | Rxx -= mpy(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6200000) { + // 11100110001sssssPP0ttttt000xxxxx | Rxx -= mpy(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYD_NAC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6a00000) { + // 11100110101sssssPP0ttttt000xxxxx | Rxx -= mpy(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYD_NAC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s.l,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200060) { + // 11100100001sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00060) { + // 11100100101sssssPP0ttttt011ddddd | Rdd = mpy(Rs.h,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.h):<<1:rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200040) { + // 11100100001sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00040) { + // 11100100101sssssPP0ttttt010ddddd | Rdd = mpy(Rs.h,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.h,%s.l):<<1:rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200020) { + // 11100100001sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00020) { + // 11100100101sssssPP0ttttt001ddddd | Rdd = mpy(Rs.l,Rt.h):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.h):<<1:rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4200000) { + // 11100100001sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l):rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4a00000) { + // 11100100101sssssPP0ttttt000ddddd | Rdd = mpy(Rs.l,Rt.l):<<1:rnd + hi->instruction = HEX_INS_M2_MPYD_RND_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpy(%s.l,%s.l):<<1:rnd", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed000000) { + // 11101101000sssssPP0ttttt000ddddd | Rd = mpyi(Rs,Rt) + hi->instruction = HEX_INS_M2_MPYI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyi(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xe0800000) { + // 11100000100sssssPP0iiiiiiiiddddd | Rd = -mpyi(Rs,Ii) + hi->instruction = HEX_INS_M2_MPYSIN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Only immediate, extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = -mpyi(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "#" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xe0000000) { + // 11100000000sssssPP0iiiiiiiiddddd | Rd = +mpyi(Rs,Ii) + hi->instruction = HEX_INS_M2_MPYSIP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s = +mpyi(%s,%s0x%x)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), !rz_asm->immdisp ? "##" : "", (ut32)hi->ops[2].op.imm); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed600020) { + // 11101101011sssssPP0ttttt001ddddd | Rd = mpysu(Rs,Rt) + hi->instruction = HEX_INS_M2_MPYSU_UP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpysu(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee400060) { + // 11101110010sssssPP0ttttt011xxxxx | Rx += mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_ACC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00060) { + // 11101110110sssssPP0ttttt011xxxxx | Rx += mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee400040) { + // 11101110010sssssPP0ttttt010xxxxx | Rx += mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_ACC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00040) { + // 11101110110sssssPP0ttttt010xxxxx | Rx += mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee400020) { + // 11101110010sssssPP0ttttt001xxxxx | Rx += mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_ACC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00020) { + // 11101110110sssssPP0ttttt001xxxxx | Rx += mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee400000) { + // 11101110010sssssPP0ttttt000xxxxx | Rx += mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_ACC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeec00000) { + // 11101110110sssssPP0ttttt000xxxxx | Rx += mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_ACC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec400060) { + // 11101100010sssssPP0ttttt011ddddd | Rd = mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00060) { + // 11101100110sssssPP0ttttt011ddddd | Rd = mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec400040) { + // 11101100010sssssPP0ttttt010ddddd | Rd = mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00040) { + // 11101100110sssssPP0ttttt010ddddd | Rd = mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec400020) { + // 11101100010sssssPP0ttttt001ddddd | Rd = mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00020) { + // 11101100110sssssPP0ttttt001ddddd | Rd = mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xec400000) { + // 11101100010sssssPP0ttttt000ddddd | Rd = mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xecc00000) { + // 11101100110sssssPP0ttttt000ddddd | Rd = mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee600060) { + // 11101110011sssssPP0ttttt011xxxxx | Rx -= mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_NAC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00060) { + // 11101110111sssssPP0ttttt011xxxxx | Rx -= mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee600040) { + // 11101110011sssssPP0ttttt010xxxxx | Rx -= mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_NAC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00040) { + // 11101110111sssssPP0ttttt010xxxxx | Rx -= mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee600020) { + // 11101110011sssssPP0ttttt001xxxxx | Rx -= mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYU_NAC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00020) { + // 11101110111sssssPP0ttttt001xxxxx | Rx -= mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.h):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xee600000) { + // 11101110011sssssPP0ttttt000xxxxx | Rx -= mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYU_NAC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeee00000) { + // 11101110111sssssPP0ttttt000xxxxx | Rx -= mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYU_NAC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.l):<<1", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed400020) { + // 11101101010sssssPP0ttttt001ddddd | Rd = mpyu(Rs,Rt) + hi->instruction = HEX_INS_M2_MPYU_UP; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400060) { + // 11100110010sssssPP0ttttt011xxxxx | Rxx += mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_ACC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00060) { + // 11100110110sssssPP0ttttt011xxxxx | Rxx += mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400040) { + // 11100110010sssssPP0ttttt010xxxxx | Rxx += mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_ACC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00040) { + // 11100110110sssssPP0ttttt010xxxxx | Rxx += mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.h,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400020) { + // 11100110010sssssPP0ttttt001xxxxx | Rxx += mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_ACC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00020) { + // 11100110110sssssPP0ttttt001xxxxx | Rxx += mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6400000) { + // 11100110010sssssPP0ttttt000xxxxx | Rxx += mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_ACC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6c00000) { + // 11100110110sssssPP0ttttt000xxxxx | Rxx += mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_ACC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpyu(%s.l,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400060) { + // 11100100010sssssPP0ttttt011ddddd | Rdd = mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00060) { + // 11100100110sssssPP0ttttt011ddddd | Rdd = mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400040) { + // 11100100010sssssPP0ttttt010ddddd | Rdd = mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00040) { + // 11100100110sssssPP0ttttt010ddddd | Rdd = mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.h,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400020) { + // 11100100010sssssPP0ttttt001ddddd | Rdd = mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00020) { + // 11100100110sssssPP0ttttt001ddddd | Rdd = mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4400000) { + // 11100100010sssssPP0ttttt000ddddd | Rdd = mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe4c00000) { + // 11100100110sssssPP0ttttt000ddddd | Rdd = mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mpyu(%s.l,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600060) { + // 11100110011sssssPP0ttttt011xxxxx | Rxx -= mpyu(Rs.h,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_NAC_HH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00060) { + // 11100110111sssssPP0ttttt011xxxxx | Rxx -= mpyu(Rs.h,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_HH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600040) { + // 11100110011sssssPP0ttttt010xxxxx | Rxx -= mpyu(Rs.h,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_NAC_HL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00040) { + // 11100110111sssssPP0ttttt010xxxxx | Rxx -= mpyu(Rs.h,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_HL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.h,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600020) { + // 11100110011sssssPP0ttttt001xxxxx | Rxx -= mpyu(Rs.l,Rt.h) + hi->instruction = HEX_INS_M2_MPYUD_NAC_LH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.h)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00020) { + // 11100110111sssssPP0ttttt001xxxxx | Rxx -= mpyu(Rs.l,Rt.h):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_LH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.h):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6600000) { + // 11100110011sssssPP0ttttt000xxxxx | Rxx -= mpyu(Rs.l,Rt.l) + hi->instruction = HEX_INS_M2_MPYUD_NAC_LL_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.l)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe6e00000) { + // 11100110111sssssPP0ttttt000xxxxx | Rxx -= mpyu(Rs.l,Rt.l):<<1 + hi->instruction = HEX_INS_M2_MPYUD_NAC_LL_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpyu(%s.l,%s.l):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef800020) { + // 11101111100sssssPP0ttttt001xxxxx | Rx -= add(Rs,Rt) + hi->instruction = HEX_INS_M2_NACCI; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= add(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02000) == 0xe2800000) { + // 11100010100sssssPP0iiiiiiiixxxxx | Rx -= add(Rs,Ii) + hi->instruction = HEX_INS_M2_NACCII; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_IMM; + hi->ops[2].op.imm = (((hi_u32)&0x1fe0) >> 5); // Ii + if (hi->ops[2].op.imm & (1 << 7)) { // signed + hi->ops[2].op.imm |= (0xffffffffffffffff << 7); + } + hex_extend_op(state, &(hi->ops[2]), false, addr); // Extension possible + if (rz_asm->immsign && ((st32)hi->ops[2].op.imm) < 0) { + char tmp[28] = { 0 }; + rz_hex_ut2st_str(hi->ops[2].op.imm, tmp, 28); + sprintf(signed_imm[2], "%s%s", !rz_asm->immdisp ? "##" : "", tmp); + } else { + sprintf(signed_imm[2], "%s0x%x", !rz_asm->immdisp ? "##" : "", (st32)hi->ops[2].op.imm); + } + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + hi->ana_op.analysis_vals[2].imm = hi->ops[2].op.imm; + sprintf(hi->mnem_infix, "%s -= add(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), signed_imm[2]); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef000060) { + // 11101111000sssssPP0ttttt011xxxxx | Rx += sub(Rt,Rs) + hi->instruction = HEX_INS_M2_SUBACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += sub(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8600000) { + // 11101000011sssssPP0ttttt000ddddd | Rdd = vabsdiffh(Rtt,Rss) + hi->instruction = HEX_INS_M2_VABSDIFFH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsdiffh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8200000) { + // 11101000001sssssPP0ttttt000ddddd | Rdd = vabsdiffw(Rtt,Rss) + hi->instruction = HEX_INS_M2_VABSDIFFW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsdiffw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea400080) { + // 11101010010sssssPP0ttttt100xxxxx | Rxx += vcmpyi(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMAC_S0_SAT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vcmpyi(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea200080) { + // 11101010001sssssPP0ttttt100xxxxx | Rxx += vcmpyr(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMAC_S0_SAT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vcmpyr(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe84000c0) { + // 11101000010sssssPP0ttttt110ddddd | Rdd = vcmpyi(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMPY_S0_SAT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpyi(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe82000c0) { + // 11101000001sssssPP0ttttt110ddddd | Rdd = vcmpyr(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VCMPY_S0_SAT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpyr(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c000c0) { + // 11101000110sssssPP0ttttt110ddddd | Rdd = vcmpyi(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VCMPY_S1_SAT_I; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpyi(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a000c0) { + // 11101000101sssssPP0ttttt110ddddd | Rdd = vcmpyr(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VCMPY_S1_SAT_R; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vcmpyr(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea000080) { + // 11101010000sssssPP0ttttt100xxxxx | Rxx += vdmpy(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VDMACS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vdmpy(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea800080) { + // 11101010100sssssPP0ttttt100xxxxx | Rxx += vdmpy(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VDMACS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vdmpy(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9000000) { + // 11101001000sssssPP0ttttt000ddddd | Rd = vdmpy(Rss,Rtt):rnd:sat + hi->instruction = HEX_INS_M2_VDMPYRS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdmpy(%s,%s):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9800000) { + // 11101001100sssssPP0ttttt000ddddd | Rd = vdmpy(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_VDMPYRS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdmpy(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000080) { + // 11101000000sssssPP0ttttt100ddddd | Rdd = vdmpy(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VDMPYS_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdmpy(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800080) { + // 11101000100sssssPP0ttttt100ddddd | Rdd = vdmpy(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VDMPYS_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdmpy(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7200020) { + // 11100111001sssssPP0ttttt001xxxxx | Rxx += vmpyh(Rs,Rt) + hi->instruction = HEX_INS_M2_VMAC2; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea200040) { + // 11101010001sssssPP0ttttt010xxxxx | Rxx += vmpyeh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VMAC2ES; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyeh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea0000c0) { + // 11101010000sssssPP0ttttt110xxxxx | Rxx += vmpyeh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VMAC2ES_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyeh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea8000c0) { + // 11101010100sssssPP0ttttt110xxxxx | Rxx += vmpyeh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VMAC2ES_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyeh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe70000a0) { + // 11100111000sssssPP0ttttt101xxxxx | Rxx += vmpyh(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMAC2S_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe78000a0) { + // 11100111100sssssPP0ttttt101xxxxx | Rxx += vmpyh(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMAC2S_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe76000a0) { + // 11100111011sssssPP0ttttt101xxxxx | Rxx += vmpyhsu(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMAC2SU_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyhsu(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7e000a0) { + // 11100111111sssssPP0ttttt101xxxxx | Rxx += vmpyhsu(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMAC2SU_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpyhsu(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe80000c0) { + // 11101000000sssssPP0ttttt110ddddd | Rdd = vmpyeh(Rss,Rtt):sat + hi->instruction = HEX_INS_M2_VMPY2ES_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyeh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe88000c0) { + // 11101000100sssssPP0ttttt110ddddd | Rdd = vmpyeh(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M2_VMPY2ES_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyeh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe50000a0) { + // 11100101000sssssPP0ttttt101ddddd | Rdd = vmpyh(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMPY2S_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyh(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xed2000e0) { + // 11101101001sssssPP0ttttt111ddddd | Rd = vmpyh(Rs,Rt):rnd:sat + hi->instruction = HEX_INS_M2_VMPY2S_S0PACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyh(%s,%s):rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe58000a0) { + // 11100101100sssssPP0ttttt101ddddd | Rdd = vmpyh(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMPY2S_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyh(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeda000e0) { + // 11101101101sssssPP0ttttt111ddddd | Rd = vmpyh(Rs,Rt):<<1:rnd:sat + hi->instruction = HEX_INS_M2_VMPY2S_S1PACK; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyh(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe50000e0) { + // 11100101000sssssPP0ttttt111ddddd | Rdd = vmpyhsu(Rs,Rt):sat + hi->instruction = HEX_INS_M2_VMPY2SU_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyhsu(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe58000e0) { + // 11100101100sssssPP0ttttt111ddddd | Rdd = vmpyhsu(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M2_VMPY2SU_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpyhsu(%s,%s):<<1:sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe92000e0) { + // 11101001001sssssPP0ttttt111ddddd | Rd = vraddh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRADDH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vraddh(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9000020) { + // 11101001000sssssPP0ttttt001ddddd | Rd = vradduh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRADDUH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vradduh(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea000000) { + // 11101010000sssssPP0ttttt000xxxxx | Rxx += vrcmpyi(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMACI_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcmpyi(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea400000) { + // 11101010010sssssPP0ttttt000xxxxx | Rxx += vrcmpyi(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMACI_S0C; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcmpyi(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea000020) { + // 11101010000sssssPP0ttttt001xxxxx | Rxx += vrcmpyr(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMACR_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcmpyr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea600020) { + // 11101010011sssssPP0ttttt001xxxxx | Rxx += vrcmpyr(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMACR_S0C; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcmpyr(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000000) { + // 11101000000sssssPP0ttttt000ddddd | Rdd = vrcmpyi(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMPYI_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpyi(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400000) { + // 11101000010sssssPP0ttttt000ddddd | Rdd = vrcmpyi(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMPYI_S0C; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpyi(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000020) { + // 11101000000sssssPP0ttttt001ddddd | Rdd = vrcmpyr(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRCMPYR_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpyr(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8600020) { + // 11101000011sssssPP0ttttt001ddddd | Rdd = vrcmpyr(Rss,Rtt*) + hi->instruction = HEX_INS_M2_VRCMPYR_S0C; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpyr(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa00080) { + // 11101010101sssssPP0ttttt100xxxxx | Rxx += vrcmpys(Rss,Rtt):<<1:sat:raw:hi + hi->instruction = HEX_INS_M2_VRCMPYS_ACC_S1_H; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcmpys(%s,%s):<<1:sat:raw:hi", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeae00080) { + // 11101010111sssssPP0ttttt100xxxxx | Rxx += vrcmpys(Rss,Rtt):<<1:sat:raw:lo + hi->instruction = HEX_INS_M2_VRCMPYS_ACC_S1_L; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrcmpys(%s,%s):<<1:sat:raw:lo", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00080) { + // 11101000101sssssPP0ttttt100ddddd | Rdd = vrcmpys(Rss,Rtt):<<1:sat:raw:hi + hi->instruction = HEX_INS_M2_VRCMPYS_S1_H; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpys(%s,%s):<<1:sat:raw:hi", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e00080) { + // 11101000111sssssPP0ttttt100ddddd | Rdd = vrcmpys(Rss,Rtt):<<1:sat:raw:lo + hi->instruction = HEX_INS_M2_VRCMPYS_S1_L; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpys(%s,%s):<<1:sat:raw:lo", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9a000c0) { + // 11101001101sssssPP0ttttt110ddddd | Rd = vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:hi + hi->instruction = HEX_INS_M2_VRCMPYS_S1RP_H; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpys(%s,%s):<<1:rnd:sat:raw:hi", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9a000e0) { + // 11101001101sssssPP0ttttt111ddddd | Rd = vrcmpys(Rss,Rtt):<<1:rnd:sat:raw:lo + hi->instruction = HEX_INS_M2_VRCMPYS_S1RP_L; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrcmpys(%s,%s):<<1:rnd:sat:raw:lo", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea000040) { + // 11101010000sssssPP0ttttt010xxxxx | Rxx += vrmpyh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRMAC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpyh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8000040) { + // 11101000000sssssPP0ttttt010ddddd | Rdd = vrmpyh(Rss,Rtt) + hi->instruction = HEX_INS_M2_VRMPY_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpyh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef800060) { + // 11101111100sssssPP0ttttt011xxxxx | Rx ^= xor(Rs,Rt) + hi->instruction = HEX_INS_M2_XOR_XACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= xor(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef400000) { + // 11101111010sssssPP0ttttt000xxxxx | Rx &= and(Rs,Rt) + hi->instruction = HEX_INS_M4_AND_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= and(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef200020) { + // 11101111001sssssPP0ttttt001xxxxx | Rx &= and(Rs,~Rt) + hi->instruction = HEX_INS_M4_AND_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= and(%s,~%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef400020) { + // 11101111010sssssPP0ttttt001xxxxx | Rx &= or(Rs,Rt) + hi->instruction = HEX_INS_M4_AND_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= or(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef400040) { + // 11101111010sssssPP0ttttt010xxxxx | Rx &= xor(Rs,Rt) + hi->instruction = HEX_INS_M4_AND_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s &= xor(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef600000) { + // 11101111011sssssPP0ttttt000xxxxx | Rx += mpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M4_MAC_UP_S1_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += mpy(%s,%s):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe3000000) { + // 11100011000sssssPP0yyyyy000uuuuu | Ry = add(Ru,mpyi(Ryin,Rs)) + hi->instruction = HEX_INS_M4_MPYRR_ADDR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f00) >> 8); // Ry32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Ru32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Ry32in + hi->ops[2].attr |= HEX_OP_REG_OUT; + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,mpyi(%sin,%s))", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef600020) { + // 11101111011sssssPP0ttttt001xxxxx | Rx -= mpy(Rs,Rt):<<1:sat + hi->instruction = HEX_INS_M4_NAC_UP_S1_SAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s -= mpy(%s,%s):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef400060) { + // 11101111010sssssPP0ttttt011xxxxx | Rx |= and(Rs,Rt) + hi->instruction = HEX_INS_M4_OR_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= and(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef200000) { + // 11101111001sssssPP0ttttt000xxxxx | Rx |= and(Rs,~Rt) + hi->instruction = HEX_INS_M4_OR_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= and(%s,~%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00000) { + // 11101111110sssssPP0ttttt000xxxxx | Rx |= or(Rs,Rt) + hi->instruction = HEX_INS_M4_OR_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= or(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00020) { + // 11101111110sssssPP0ttttt001xxxxx | Rx |= xor(Rs,Rt) + hi->instruction = HEX_INS_M4_OR_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s |= xor(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe54000e0) { + // 11100101010sssssPP0ttttt111ddddd | Rdd = pmpyw(Rs,Rt) + hi->instruction = HEX_INS_M4_PMPYW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = pmpyw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe72000e0) { + // 11100111001sssssPP0ttttt111xxxxx | Rxx ^= pmpyw(Rs,Rt) + hi->instruction = HEX_INS_M4_PMPYW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= pmpyw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5c000e0) { + // 11100101110sssssPP0ttttt111ddddd | Rdd = vpmpyh(Rs,Rt) + hi->instruction = HEX_INS_M4_VPMPYH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vpmpyh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7a000e0) { + // 11100111101sssssPP0ttttt111xxxxx | Rxx ^= vpmpyh(Rs,Rt) + hi->instruction = HEX_INS_M4_VPMPYH_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= vpmpyh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea2000c0) { + // 11101010001sssssPP0ttttt110xxxxx | Rxx += vrmpyweh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYEH_ACC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpyweh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeaa000c0) { + // 11101010101sssssPP0ttttt110xxxxx | Rxx += vrmpyweh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYEH_ACC_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpyweh(%s,%s):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8400080) { + // 11101000010sssssPP0ttttt100ddddd | Rdd = vrmpyweh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYEH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpyweh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00080) { + // 11101000110sssssPP0ttttt100ddddd | Rdd = vrmpyweh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYEH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpyweh(%s,%s):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea6000c0) { + // 11101010011sssssPP0ttttt110xxxxx | Rxx += vrmpywoh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYOH_ACC_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpywoh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeae000c0) { + // 11101010111sssssPP0ttttt110xxxxx | Rxx += vrmpywoh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYOH_ACC_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpywoh(%s,%s):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8200040) { + // 11101000001sssssPP0ttttt010ddddd | Rdd = vrmpywoh(Rss,Rtt) + hi->instruction = HEX_INS_M4_VRMPYOH_S0; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpywoh(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00040) { + // 11101000101sssssPP0ttttt010ddddd | Rdd = vrmpywoh(Rss,Rtt):<<1 + hi->instruction = HEX_INS_M4_VRMPYOH_S1; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpywoh(%s,%s):<<1", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00040) { + // 11101111110sssssPP0ttttt010xxxxx | Rx ^= and(Rs,Rt) + hi->instruction = HEX_INS_M4_XOR_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= and(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xef200040) { + // 11101111001sssssPP0ttttt010xxxxx | Rx ^= and(Rs,~Rt) + hi->instruction = HEX_INS_M4_XOR_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= and(%s,~%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xefc00060) { + // 11101111110sssssPP0ttttt011xxxxx | Rx ^= or(Rs,Rt) + hi->instruction = HEX_INS_M4_XOR_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s ^= or(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea200020) { + // 11101010001sssssPP0ttttt001xxxxx | Rxx += vdmpybsu(Rss,Rtt):sat + hi->instruction = HEX_INS_M5_VDMACBSU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vdmpybsu(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00020) { + // 11101000101sssssPP0ttttt001ddddd | Rdd = vdmpybsu(Rss,Rtt):sat + hi->instruction = HEX_INS_M5_VDMPYBSU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vdmpybsu(%s,%s):sat", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7c00020) { + // 11100111110sssssPP0ttttt001xxxxx | Rxx += vmpybsu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMACBSU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpybsu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe7800020) { + // 11100111100sssssPP0ttttt001xxxxx | Rxx += vmpybu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMACBUU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vmpybu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5400020) { + // 11100101010sssssPP0ttttt001ddddd | Rdd = vmpybsu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMPYBSU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpybsu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe5800020) { + // 11100101100sssssPP0ttttt001ddddd | Rdd = vmpybu(Rs,Rt) + hi->instruction = HEX_INS_M5_VMPYBUU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vmpybu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeac00020) { + // 11101010110sssssPP0ttttt001xxxxx | Rxx += vrmpybsu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMACBSU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpybsu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea800020) { + // 11101010100sssssPP0ttttt001xxxxx | Rxx += vrmpybu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMACBUU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += vrmpybu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00020) { + // 11101000110sssssPP0ttttt001ddddd | Rdd = vrmpybsu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMPYBSU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpybsu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800020) { + // 11101000100sssssPP0ttttt001ddddd | Rdd = vrmpybu(Rss,Rtt) + hi->instruction = HEX_INS_M5_VRMPYBUU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vrmpybu(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e00000) { + // 11101000111sssssPP0ttttt000ddddd | Rdd = vabsdiffb(Rtt,Rss) + hi->instruction = HEX_INS_M6_VABSDIFFB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsdiffb(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8a00000) { + // 11101000101sssssPP0ttttt000ddddd | Rdd = vabsdiffub(Rtt,Rss) + hi->instruction = HEX_INS_M6_VABSDIFFUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vabsdiffub(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8600040) { + // 11101000011sssssPP0ttttt010ddddd | Rdd = cmpyiw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYIW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea600040) { + // 11101010011sssssPP0ttttt010xxxxx | Rxx += cmpyiw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYIW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpyiw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8e00040) { + // 11101000111sssssPP0ttttt010ddddd | Rdd = cmpyiw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYIWC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiw(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea4000c0) { + // 11101010010sssssPP0ttttt110xxxxx | Rxx += cmpyiw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYIWC_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpyiw(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8800040) { + // 11101000100sssssPP0ttttt010ddddd | Rdd = cmpyrw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYRW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xea800040) { + // 11101010100sssssPP0ttttt010xxxxx | Rxx += cmpyrw(Rss,Rtt) + hi->instruction = HEX_INS_M7_DCMPYRW_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpyrw(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe8c00040) { + // 11101000110sssssPP0ttttt010ddddd | Rdd = cmpyrw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYRWC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrw(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xeac00040) { + // 11101010110sssssPP0ttttt010xxxxx | Rxx += cmpyrw(Rss,Rtt*) + hi->instruction = HEX_INS_M7_DCMPYRWC_ACC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rxx32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s += cmpyrw(%s,%s*)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9200000) { + // 11101001001sssssPP0ttttt000ddddd | Rd = cmpyiw(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYIW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiw(%s,%s):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9a00000) { + // 11101001101sssssPP0ttttt000ddddd | Rd = cmpyiw(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYIW_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiw(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9000080) { + // 11101001000sssssPP0ttttt100ddddd | Rd = cmpyiw(Rss,Rtt*):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYIWC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiw(%s,%s*):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9800080) { + // 11101001100sssssPP0ttttt100ddddd | Rd = cmpyiw(Rss,Rtt*):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYIWC_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyiw(%s,%s*):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9400000) { + // 11101001010sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYRW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrw(%s,%s):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9c00000) { + // 11101001110sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYRW_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrw(%s,%s):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9600000) { + // 11101001011sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt*):<<1:sat + hi->instruction = HEX_INS_M7_WCMPYRWC; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrw(%s,%s*):<<1:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xe9e00000) { + // 11101001111sssssPP0ttttt000ddddd | Rd = cmpyrw(Rss,Rtt*):<<1:rnd:sat + hi->instruction = HEX_INS_M7_WCMPYRWC_RND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rss32 + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rtt32 + hi->ops[2].attr |= HEX_OP_REG_PAIR; + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmpyrw(%s,%s*):<<1:rnd:sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_double_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +void hexagon_disasm_0xf(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, HexInsn *hi, const ut32 addr, HexPkt *pkt) { + if ((hi_u32 & 0xffe020e0) == 0xf3000000) { + // 11110011000sssssPP0ttttt000ddddd | Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_ADD; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6400000) { + // 11110110010sssssPP0ttttt000ddddd | Rd = add(Rs,Rt):sat + hi->instruction = HEX_INS_A2_ADDSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = add(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf1000000) { + // 11110001000sssssPP0ttttt000ddddd | Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_AND; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3800000) { + // 11110011100sssssPP0ttttt000ddddd | Rd = combine(Rt.h,Rs.h) + hi->instruction = HEX_INS_A2_COMBINE_HH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s.h,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3a00000) { + // 11110011101sssssPP0ttttt000ddddd | Rd = combine(Rt.h,Rs.l) + hi->instruction = HEX_INS_A2_COMBINE_HL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s.h,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3c00000) { + // 11110011110sssssPP0ttttt000ddddd | Rd = combine(Rt.l,Rs.h) + hi->instruction = HEX_INS_A2_COMBINE_LH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s.l,%s.h)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3e00000) { + // 11110011111sssssPP0ttttt000ddddd | Rd = combine(Rt.l,Rs.l) + hi->instruction = HEX_INS_A2_COMBINE_LL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s.l,%s.l)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf5000000) { + // 11110101000sssssPP0ttttt000ddddd | Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_A2_COMBINEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = combine(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf1200000) { + // 11110001001sssssPP0ttttt000ddddd | Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_OR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb000080) { + // 11111011000sssssPP0ttttt1uuddddd | if (!Pu) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb002080) { + // 11111011000sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb000000) { + // 11111011000sssssPP0ttttt0uuddddd | if (Pu) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb002000) { + // 11111011000sssssPP1ttttt0uuddddd | if (Pu.new) Rd = add(Rs,Rt) + hi->instruction = HEX_INS_A2_PADDTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = add(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9000080) { + // 11111001000sssssPP0ttttt1uuddddd | if (!Pu) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = and(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9002080) { + // 11111001000sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = and(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9000000) { + // 11111001000sssssPP0ttttt0uuddddd | if (Pu) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = and(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9002000) { + // 11111001000sssssPP1ttttt0uuddddd | if (Pu.new) Rd = and(Rs,Rt) + hi->instruction = HEX_INS_A2_PANDTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = and(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9200080) { + // 11111001001sssssPP0ttttt1uuddddd | if (!Pu) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = or(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9202080) { + // 11111001001sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = or(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9200000) { + // 11111001001sssssPP0ttttt0uuddddd | if (Pu) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = or(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9202000) { + // 11111001001sssssPP1ttttt0uuddddd | if (Pu.new) Rd = or(Rs,Rt) + hi->instruction = HEX_INS_A2_PORTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = or(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb200080) { + // 11111011001sssssPP0ttttt1uuddddd | if (!Pu) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = sub(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb202080) { + // 11111011001sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = sub(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb200000) { + // 11111011001sssssPP0ttttt0uuddddd | if (Pu) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = sub(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfb202000) { + // 11111011001sssssPP1ttttt0uuddddd | if (Pu.new) Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_PSUBTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = sub(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9600080) { + // 11111001011sssssPP0ttttt1uuddddd | if (!Pu) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = xor(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9602080) { + // 11111001011sssssPP1ttttt1uuddddd | if (!Pu.new) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORFNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = xor(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9600000) { + // 11111001011sssssPP0ttttt0uuddddd | if (Pu) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = xor(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf9602000) { + // 11111001011sssssPP1ttttt0uuddddd | if (Pu.new) Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_PXORTNEW; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = xor(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3200000) { + // 11110011001sssssPP0ttttt000ddddd | Rd = sub(Rt,Rs) + hi->instruction = HEX_INS_A2_SUB; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6c00000) { + // 11110110110sssssPP0ttttt000ddddd | Rd = sub(Rt,Rs):sat + hi->instruction = HEX_INS_A2_SUBSAT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = sub(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6000000) { + // 11110110000sssssPP0ttttt000ddddd | Rd = vaddh(Rs,Rt) + hi->instruction = HEX_INS_A2_SVADDH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddh(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6200000) { + // 11110110001sssssPP0ttttt000ddddd | Rd = vaddh(Rs,Rt):sat + hi->instruction = HEX_INS_A2_SVADDHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vaddh(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6600000) { + // 11110110011sssssPP0ttttt000ddddd | Rd = vadduh(Rs,Rt):sat + hi->instruction = HEX_INS_A2_SVADDUHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vadduh(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf7000000) { + // 11110111000sssssPP0ttttt000ddddd | Rd = vavgh(Rs,Rt) + hi->instruction = HEX_INS_A2_SVAVGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgh(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf7200000) { + // 11110111001sssssPP0ttttt000ddddd | Rd = vavgh(Rs,Rt):rnd + hi->instruction = HEX_INS_A2_SVAVGHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vavgh(%s,%s):rnd", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf7600000) { + // 11110111011sssssPP0ttttt000ddddd | Rd = vnavgh(Rt,Rs) + hi->instruction = HEX_INS_A2_SVNAVGH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vnavgh(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6800000) { + // 11110110100sssssPP0ttttt000ddddd | Rd = vsubh(Rt,Rs) + hi->instruction = HEX_INS_A2_SVSUBH; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubh(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6a00000) { + // 11110110101sssssPP0ttttt000ddddd | Rd = vsubh(Rt,Rs):sat + hi->instruction = HEX_INS_A2_SVSUBHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubh(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf6e00000) { + // 11110110111sssssPP0ttttt000ddddd | Rd = vsubuh(Rt,Rs):sat + hi->instruction = HEX_INS_A2_SVSUBUHS; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = vsubuh(%s,%s):sat", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf1600000) { + // 11110001011sssssPP0ttttt000ddddd | Rd = xor(Rs,Rt) + hi->instruction = HEX_INS_A2_XOR; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = xor(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf1800000) { + // 11110001100sssssPP0ttttt000ddddd | Rd = and(Rt,~Rs) + hi->instruction = HEX_INS_A4_ANDN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = and(%s,~%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf1a00000) { + // 11110001101sssssPP0ttttt000ddddd | Rd = or(Rt,~Rs) + hi->instruction = HEX_INS_A4_ORN; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = or(%s,~%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3400000) { + // 11110011010sssssPP0ttttt000ddddd | Rd = cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_RCMPEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.eq(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf3600000) { + // 11110011011sssssPP0ttttt000ddddd | Rd = !cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_A4_RCMPNEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !cmp.eq(%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfd000080) { + // 11111101000sssssPP0ttttt1uuddddd | if (!Pu) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s) %s = combine(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfd002080) { + // 11111101000sssssPP1ttttt1uuddddd | if (!Pu.new) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWNEWF; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_FALSE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (!%s.new) %s = combine(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfd002000) { + // 11111101000sssssPP1ttttt0uuddddd | if (Pu.new) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWNEWT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE | HEX_PRED_NEW; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s.new) %s = combine(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xfd000000) { + // 11111101000sssssPP0ttttt0uuddddd | if (Pu) Rdd = combine(Rs,Rt) + hi->instruction = HEX_INS_C2_CCOMBINEWT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_PRED_TRUE; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[1].attr |= HEX_OP_REG_OUT; + hi->ops[1].attr |= HEX_OP_REG_PAIR; + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_COND; + sprintf(hi->mnem_infix, "if (%s) %s = combine(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_double_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xf2000000) { + // 11110010000sssssPP0ttttt000000dd | Pd = cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_C2_CMPEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xf2400000) { + // 11110010010sssssPP0ttttt000000dd | Pd = cmp.gt(Rs,Rt) + hi->instruction = HEX_INS_C2_CMPGT; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xf2600000) { + // 11110010011sssssPP0ttttt000000dd | Pd = cmp.gtu(Rs,Rt) + hi->instruction = HEX_INS_C2_CMPGTU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = cmp.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe02080) == 0xf4000000) { + // 11110100000sssssPP0ttttt0uuddddd | Rd = mux(Pu,Rs,Rt) + hi->instruction = HEX_INS_C2_MUX; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 4; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x60) >> 5); // Pu4 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[3].type = HEX_OP_TYPE_REG; + hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = mux(%s,%s,%s)", hex_get_int_regs(hi->ops[0].op.reg), hex_get_pred_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg), hex_get_int_regs(hi->ops[3].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xf2400010) { + // 11110010010sssssPP0ttttt000100dd | Pd = !cmp.gt(Rs,Rt) + hi->instruction = HEX_INS_C4_CMPLTE; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !cmp.gt(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xf2600010) { + // 11110010011sssssPP0ttttt000100dd | Pd = !cmp.gtu(Rs,Rt) + hi->instruction = HEX_INS_C4_CMPLTEU; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !cmp.gtu(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020fc) == 0xf2000010) { + // 11110010000sssssPP0ttttt000100dd | Pd = !cmp.eq(Rs,Rt) + hi->instruction = HEX_INS_C4_CMPNEQ; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x3) >> 0); // Pd4 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = !cmp.eq(%s,%s)", hex_get_pred_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } + if ((hi_u32 & 0xffe020e0) == 0xf5800000) { + // 11110101100sssssPP0ttttt000ddddd | Rdd = packhl(Rs,Rt) + hi->instruction = HEX_INS_S2_PACKHL; + hi->opcode = hi_u32; + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + hi->pred = HEX_NOPRED; + hi->op_count = 3; + hi->ops[0].type = HEX_OP_TYPE_REG; + hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rdd32 + hi->ops[0].attr |= HEX_OP_REG_OUT; + hi->ops[0].attr |= HEX_OP_REG_PAIR; + hi->ops[1].type = HEX_OP_TYPE_REG; + hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs32 + hi->ops[2].type = HEX_OP_TYPE_REG; + hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt32 + // Set RzAnalysisOp values + hi->ana_op.addr = hi->addr; + hi->ana_op.id = hi->instruction; + hi->ana_op.size = 4; + hi->ana_op.type |= RZ_ANALYSIS_OP_TYPE_NULL; + sprintf(hi->mnem_infix, "%s = packhl(%s,%s)", hex_get_double_regs(hi->ops[0].op.reg), hex_get_int_regs(hi->ops[1].op.reg), hex_get_int_regs(hi->ops[2].op.reg)); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + return; + } +} + +int hexagon_disasm_instruction(const RzAsm *rz_asm, HexState *state, const ut32 hi_u32, RZ_INOUT HexInsn *hi, HexPkt *pkt) { + ut32 addr = hi->addr; + switch (hex_get_loop_flag(pkt)) { + default: break; + case HEX_LOOP_01: + hi->ana_op.type = RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.fail = pkt->hw_loop0_addr; + hi->ana_op.jump = pkt->hw_loop1_addr; + hi->ana_op.val = hi->ana_op.jump; + hi->ana_op.analysis_vals[0].imm = (st64)hi->ana_op.fail; + pkt->hw_loop1_addr = 0; + pkt->hw_loop0_addr = 0; + break; + case HEX_LOOP_0: + hi->ana_op.type = RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->hw_loop0_addr; + hi->ana_op.val = hi->ana_op.jump; + pkt->hw_loop0_addr = 0; + break; + case HEX_LOOP_1: + hi->ana_op.type = RZ_ANALYSIS_OP_TYPE_CJMP; + hi->ana_op.jump = pkt->hw_loop1_addr; + hi->ana_op.val = hi->ana_op.jump; + pkt->hw_loop1_addr = 0; + break; + } + if (hi_u32 != 0x00000000) { + // DUPLEXES + if (((hi_u32 >> 14) & 0x3) == 0) { + switch ((((hi_u32 >> 29) & 0xF) << 1) | ((hi_u32 >> 13) & 1)) { + case 0x0: + hexagon_disasm_duplex_0x0(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfa02080) == 0xb002000) { - // Instruction: 15: 111110110-0sssssPP1ttttt0uuddddd | if (Pu.new) Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x1: + hexagon_disasm_duplex_0x1(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfa02080) == 0xb002080) { - // Instruction: 15: 111110110-0sssssPP1ttttt1uuddddd | if !Pu.new Rd = add (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = add (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x2: + hexagon_disasm_duplex_0x2(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf002080) == 0xd000000) { - // Instruction: 15: 11111101---sssssPP0ttttt0uuddddd | if (Pu) Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x3: + hexagon_disasm_duplex_0x3(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf002080) == 0xd000080) { - // Instruction: 15: 11111101---sssssPP0ttttt1uuddddd | if !Pu Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x4: + hexagon_disasm_duplex_0x4(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf002080) == 0xd002000) { - // Instruction: 15: 11111101---sssssPP1ttttt0uuddddd | if (Pu.new) Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x5: + hexagon_disasm_duplex_0x5(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf002080) == 0xd002080) { - // Instruction: 15: 11111101---sssssPP1ttttt1uuddddd | if !Pu.new Rdd = combine (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RDD___COMBINE__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].attr |= HEX_OP_REG_PAIR; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d:R%d = combine (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg + 1, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x6: + hexagon_disasm_duplex_0x6(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9000000) { - // Instruction: 15: 11111001-00sssssPP0ttttt0uuddddd | if (Pu) Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x7: + hexagon_disasm_duplex_0x7(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9000080) { - // Instruction: 15: 11111001-00sssssPP0ttttt1uuddddd | if !Pu Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x8: + hexagon_disasm_duplex_0x8(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9002000) { - // Instruction: 15: 11111001-00sssssPP1ttttt0uuddddd | if (Pu.new) Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x9: + hexagon_disasm_duplex_0x9(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9002080) { - // Instruction: 15: 11111001-00sssssPP1ttttt1uuddddd | if !Pu.new Rd = and (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___AND__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = and (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0xa: + hexagon_disasm_duplex_0xa(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9200000) { - // Instruction: 15: 11111001-01sssssPP0ttttt0uuddddd | if (Pu) Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0xb: + hexagon_disasm_duplex_0xb(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9200080) { - // Instruction: 15: 11111001-01sssssPP0ttttt1uuddddd | if !Pu Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0xc: + hexagon_disasm_duplex_0xc(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9202000) { - // Instruction: 15: 11111001-01sssssPP1ttttt0uuddddd | if (Pu.new) Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0xd: + hexagon_disasm_duplex_0xd(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9202080) { - // Instruction: 15: 11111001-01sssssPP1ttttt1uuddddd | if !Pu.new Rd = or (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___OR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = or (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0xe: + hexagon_disasm_duplex_0xe(rz_asm, state, hi_u32, hi, addr, pkt); break; } - if ((hi_u32 & 0xf602080) == 0x9600000) { - // Instruction: 15: 11111001-11sssssPP0ttttt0uuddddd | if (Pu) Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__PU__RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + } else { + switch ((hi_u32 >> 28) & 0xF) { + case 0x0: + hexagon_disasm_0x0(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9600080) { - // Instruction: 15: 11111001-11sssssPP0ttttt1uuddddd | if !Pu Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x1: + hexagon_disasm_0x1(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9602000) { - // Instruction: 15: 11111001-11sssssPP1ttttt0uuddddd | if (Pu.new) Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__PU_NEW__RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x2: + hexagon_disasm_0x2(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf602080) == 0x9602080) { - // Instruction: 15: 11111001-11sssssPP1ttttt1uuddddd | if !Pu.new Rd = xor (Rs, Rt) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___XOR__RS__RT_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = xor (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x3: + hexagon_disasm_0x3(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfa02080) == 0xb200000) { - // Instruction: 15: 111110110-1sssssPP0ttttt0uuddddd | if (Pu) Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__PU__RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE; // if (Pu) - sprintf(hi->mnem, "if (P%d) R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x4: + hexagon_disasm_0x4(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfa02080) == 0xb200080) { - // Instruction: 15: 111110110-1sssssPP0ttttt1uuddddd | if !Pu Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__NOT_PU_RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE; // if !Pu - sprintf(hi->mnem, "if !P%d R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x5: + hexagon_disasm_0x5(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfa02080) == 0xb202000) { - // Instruction: 15: 111110110-1sssssPP1ttttt0uuddddd | if (Pu.new) Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__PU_NEW__RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_TRUE_NEW; // if (Pu.new) - sprintf(hi->mnem, "if (P%d.new) R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x6: + hexagon_disasm_0x6(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfa02080) == 0xb202080) { - // Instruction: 15: 111110110-1sssssPP1ttttt1uuddddd | if !Pu.new Rd = sub (Rt, Rs) - hi->instruction = HEX_INS_IF__NOT_PU_NEW_RD___SUB__RT__RS_; - hi->op_count = 4; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x60) >> 5); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->ops[3].type = HEX_OP_TYPE_REG; - hi->ops[3].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->predicate = HEX_PRED_FALSE_NEW; // if !Pu.new - sprintf(hi->mnem, "if !P%d.new R%d = sub (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg, hi->ops[3].op.reg); + case 0x7: + hexagon_disasm_0x7(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf60001c) == 0x2000000) { - // Instruction: 15: 11110010-00sssssPP-ttttt---000dd | Pd = cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0x8: + hexagon_disasm_0x8(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf60001c) == 0x2000010) { - // Instruction: 15: 11110010-00sssssPP-ttttt---100dd | Pd = !cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !cmp.eq (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0x9: + hexagon_disasm_0x9(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf60001c) == 0x2400000) { - // Instruction: 15: 11110010-10sssssPP-ttttt---000dd | Pd = cmp.gt (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0xa: + hexagon_disasm_0xa(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf60001c) == 0x2400010) { - // Instruction: 15: 11110010-10sssssPP-ttttt---100dd | Pd = !cmp.gt (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_CMP_GT__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !cmp.gt (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0xb: + hexagon_disasm_0xb(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf60001c) == 0x2600000) { - // Instruction: 15: 11110010-11sssssPP-ttttt---000dd | Pd = cmp.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD___CMP_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = cmp.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0xc: + hexagon_disasm_0xc(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xf60001c) == 0x2600010) { - // Instruction: 15: 11110010-11sssssPP-ttttt---100dd | Pd = !cmp.gtu (Rs, Rt) - hi->instruction = HEX_INS_PD____NOT_CMP_GTU__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_PREDICATE; - hi->ops[0].op.pred = (((hi_u32)&0x3) >> 0); - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "P%d = !cmp.gtu (R%d, R%d)", hi->ops[0].op.pred, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0xd: + hexagon_disasm_0xd(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfe00000) == 0x3400000) { - // Instruction: 15: 11110011010sssssPP-ttttt---ddddd | Rd = cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_RD___CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = cmp.eq (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0xe: + hexagon_disasm_0xe(rz_asm, state, hi_u32, hi, addr, pkt); break; - } - if ((hi_u32 & 0xfe00000) == 0x3600000) { - // Instruction: 15: 11110011011sssssPP-ttttt---ddddd | Rd = !cmp.eq (Rs, Rt) - hi->instruction = HEX_INS_RD____NOT_CMP_EQ__RS__RT_; - hi->op_count = 3; - hi->ops[0].type = HEX_OP_TYPE_REG; - hi->ops[0].op.reg = (((hi_u32)&0x1f) >> 0); // Rd - hi->ops[1].type = HEX_OP_TYPE_REG; - hi->ops[1].op.reg = (((hi_u32)&0x1f0000) >> 16); // Rs - hi->ops[2].type = HEX_OP_TYPE_REG; - hi->ops[2].op.reg = (((hi_u32)&0x1f00) >> 8); // Rt - hi->predicate = HEX_NOPRED; - sprintf(hi->mnem, "R%d = !cmp.eq (R%d, R%d)", hi->ops[0].op.reg, hi->ops[1].op.reg, hi->ops[2].op.reg); + case 0xf: + hexagon_disasm_0xf(rz_asm, state, hi_u32, hi, addr, pkt); break; } - break; - } } } + if (pkt->is_eob && is_last_instr(hi->parse_bits)) { + hi->ana_op.eob = true; + } + if (hi->instruction == HEX_INS_INVALID_DECODE) { + hi->parse_bits = ((hi_u32)&0xc000) >> 14; + sprintf(hi->mnem_infix, "invalid"); + sprintf(hi->mnem, "%s%s%s", hi->pkt_info.syntax_prefix, hi->mnem_infix, hi->pkt_info.syntax_postfix); + } return 4; -} +} \ No newline at end of file diff --git a/librz/asm/arch/hexagon/hexagon_insn.h b/librz/asm/arch/hexagon/hexagon_insn.h index 73a3acffacc..f376a909763 100644 --- a/librz/asm/arch/hexagon/hexagon_insn.h +++ b/librz/asm/arch/hexagon/hexagon_insn.h @@ -1,2812 +1,3619 @@ -// THIS FILE IS AUTOGENERATED - SEE IMPORTER.PY FILE - -// SPDX-FileCopyrightText: 2018-2021 Anton Kochkov +// SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + #ifndef HEXAGON_INSN_H #define HEXAGON_INSN_H enum HEX_INS { - HEX_INS_UNKNOWN, - HEX_INS_IMMEXT, - HEX_INS_RD___ADD__RS___S16_, - HEX_INS_RD___ADD__RS__RT_, - HEX_INS_RD___ADD__RS__RT___SAT, - HEX_INS_RD___AND__RS___S10_, - HEX_INS_RD___OR__RS___S10_, - HEX_INS_RD___AND__RS__RT_, - HEX_INS_RD___OR__RS__RT_, - HEX_INS_RD___XOR__RS__RT_, - HEX_INS_RD___AND__RT___RS_, - HEX_INS_RD___OR__RT___RS_, - HEX_INS_NOP, - HEX_INS_RD___SUB___S10__RS_, - HEX_INS_RD___SUB__RT__RS_, - HEX_INS_RD___SUB__RT__RS___SAT, - HEX_INS_RD___SXTB__RS_, - HEX_INS_RD___SXTH__RS_, - HEX_INS_RX_L____U16, - HEX_INS_RX_H____U16, - HEX_INS_RD____S16, - HEX_INS_RD___RS, - HEX_INS_RD___VADDH__RS__RT_, - HEX_INS_RD___VADDH__RS__RT___SAT, - HEX_INS_RD___VADDUH__RS__RT___SAT, - HEX_INS_RD___VAVGH__RS__RT_, - HEX_INS_RD___VAVGH__RS__RT___RND, - HEX_INS_RD___VNAVGH__RT__RS_, - HEX_INS_RD___VSUBH__RT__RS_, - HEX_INS_RD___VSUBH__RT__RS___SAT, - HEX_INS_RD___VSUBUH__RT__RS___SAT, - HEX_INS_RD___ZXTH__RS_, - HEX_INS_RDD___COMBINE__RS___S8_, - HEX_INS_RDD___COMBINE___S8__RS_, - HEX_INS_RDD___COMBINE___S8___S8_, - HEX_INS_RDD___COMBINE___S8___U6_, - HEX_INS_RD___COMBINE__RT_H__RS_H_, - HEX_INS_RD___COMBINE__RT_H__RS_L_, - HEX_INS_RD___COMBINE__RT_L__RS_H_, - HEX_INS_RD___COMBINE__RT_L__RS_L_, - HEX_INS_RDD___COMBINE__RS__RT_, - HEX_INS_RD___MUX__PU__RS___S8_, - HEX_INS_RD___MUX__PU___S8__RS_, - HEX_INS_RD___MUX__PU___S8___S8_, - HEX_INS_RD___MUX__PU__RS__RT_, - HEX_INS_RD___ASLH__RS_, - HEX_INS_RD___ASRH__RS_, - HEX_INS_RDD___PACKHL__RS__RT_, - HEX_INS_IF__PU__RD___ADD__RS___S8_, - HEX_INS_IF__PU_NEW__RD___ADD__RS___S8_, - HEX_INS_IF__NOT_PU_RD___ADD__RS___S8_, - HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS___S8_, - HEX_INS_IF__PU__RD___ADD__RS__RT_, - HEX_INS_IF__NOT_PU_RD___ADD__RS__RT_, - HEX_INS_IF__PU_NEW__RD___ADD__RS__RT_, - HEX_INS_IF__NOT_PU_NEW_RD___ADD__RS__RT_, - HEX_INS_IF__PU__RD___ASLH__RS_, - HEX_INS_IF__PU_NEW__RD___ASLH__RS_, - HEX_INS_IF__NOT_PU_RD___ASLH__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___ASLH__RS_, - HEX_INS_IF__PU__RD___ASRH__RS_, - HEX_INS_IF__PU_NEW__RD___ASRH__RS_, - HEX_INS_IF__NOT_PU_RD___ASRH__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___ASRH__RS_, - HEX_INS_IF__PU__RDD___COMBINE__RS__RT_, - HEX_INS_IF__NOT_PU_RDD___COMBINE__RS__RT_, - HEX_INS_IF__PU_NEW__RDD___COMBINE__RS__RT_, - HEX_INS_IF__NOT_PU_NEW_RDD___COMBINE__RS__RT_, - HEX_INS_IF__PU__RD___AND__RS__RT_, - HEX_INS_IF__NOT_PU_RD___AND__RS__RT_, - HEX_INS_IF__PU_NEW__RD___AND__RS__RT_, - HEX_INS_IF__NOT_PU_NEW_RD___AND__RS__RT_, - HEX_INS_IF__PU__RD___OR__RS__RT_, - HEX_INS_IF__NOT_PU_RD___OR__RS__RT_, - HEX_INS_IF__PU_NEW__RD___OR__RS__RT_, - HEX_INS_IF__NOT_PU_NEW_RD___OR__RS__RT_, - HEX_INS_IF__PU__RD___XOR__RS__RT_, - HEX_INS_IF__NOT_PU_RD___XOR__RS__RT_, - HEX_INS_IF__PU_NEW__RD___XOR__RS__RT_, - HEX_INS_IF__NOT_PU_NEW_RD___XOR__RS__RT_, - HEX_INS_IF__PU__RD___SUB__RT__RS_, - HEX_INS_IF__NOT_PU_RD___SUB__RT__RS_, - HEX_INS_IF__PU_NEW__RD___SUB__RT__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___SUB__RT__RS_, - HEX_INS_IF__PU__RD___SXTB__RS_, - HEX_INS_IF__PU_NEW__RD___SXTB__RS_, - HEX_INS_IF__NOT_PU_RD___SXTB__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___SXTB__RS_, - HEX_INS_IF__PU__RD___SXTH__RS_, - HEX_INS_IF__PU_NEW__RD___SXTH__RS_, - HEX_INS_IF__NOT_PU_RD___SXTH__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___SXTH__RS_, - HEX_INS_IF__PU__RD____S12, - HEX_INS_IF__PU_NEW__RD____S12, - HEX_INS_IF__NOT_PU_RD____S12, - HEX_INS_IF__NOT_PU_NEW_RD____S12, - HEX_INS_IF__PU__RD___ZXTB__RS_, - HEX_INS_IF__PU_NEW__RD___ZXTB__RS_, - HEX_INS_IF__NOT_PU_RD___ZXTB__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___ZXTB__RS_, - HEX_INS_IF__PU__RD___ZXTH__RS_, - HEX_INS_IF__PU_NEW__RD___ZXTH__RS_, - HEX_INS_IF__NOT_PU_RD___ZXTH__RS_, - HEX_INS_IF__NOT_PU_NEW_RD___ZXTH__RS_, - HEX_INS_PD___CMP_EQ__RS___S10_, - HEX_INS_PD____NOT_CMP_EQ__RS___S10_, - HEX_INS_PD___CMP_GT__RS___S10_, - HEX_INS_PD____NOT_CMP_GT__RS___S10_, - HEX_INS_PD___CMP_GTU__RS___U9_, - HEX_INS_PD____NOT_CMP_GTU__RS___U9_, - HEX_INS_PD___CMP_EQ__RS__RT_, - HEX_INS_PD____NOT_CMP_EQ__RS__RT_, - HEX_INS_PD___CMP_GT__RS__RT_, - HEX_INS_PD____NOT_CMP_GT__RS__RT_, - HEX_INS_PD___CMP_GTU__RS__RT_, - HEX_INS_PD____NOT_CMP_GTU__RS__RT_, - HEX_INS_RD___CMP_EQ__RS___S8_, - HEX_INS_RD____NOT_CMP_EQ__RS___S8_, - HEX_INS_RD___CMP_EQ__RS__RT_, - HEX_INS_RD____NOT_CMP_EQ__RS__RT_, - HEX_INS_PD___FASTCORNER9__PS__PT_, - HEX_INS_PD____NOT_FASTCORNER9__PS__PT_, - HEX_INS_PD___ANY8__PS_, - HEX_INS_PD___ALL8__PS_, - HEX_INS_LOOP0___R7_2__RS_, - HEX_INS_LOOP1___R7_2__RS_, - HEX_INS_LOOP0___R7_2___U10_, - HEX_INS_LOOP1___R7_2___U10_, - HEX_INS_RD___ADD__PC___U6_, - HEX_INS_P3___SP1LOOP0___R7_2__RS_, - HEX_INS_P3___SP2LOOP0___R7_2__RS_, - HEX_INS_P3___SP3LOOP0___R7_2__RS_, - HEX_INS_P3___SP1LOOP0___R7_2___U10_, - HEX_INS_P3___SP2LOOP0___R7_2___U10_, - HEX_INS_P3___SP3LOOP0___R7_2___U10_, - HEX_INS_PD___AND__PT__PS_, - HEX_INS_PD___AND__PS__AND__PT__PU__, - HEX_INS_PD___OR__PT__PS_, - HEX_INS_PD___AND__PS__OR__PT__PU__, - HEX_INS_PD___XOR__PS__PT_, - HEX_INS_PD___OR__PS__AND__PT__PU__, - HEX_INS_PD___AND__PT___NOT_PS_, - HEX_INS_PD___OR__PS__OR__PT__PU__, - HEX_INS_PD___AND__PS__AND__PT___NOT_PU__, - HEX_INS_PD___AND__PS__OR__PT___NOT_PU__, - HEX_INS_PD___NOT__PS_, - HEX_INS_PD___OR__PS__AND__PT___NOT_PU__, - HEX_INS_PD___OR__PT___NOT_PS_, - HEX_INS_PD___OR__PS__OR__PT___NOT_PU__, - HEX_INS_CD___RS, - HEX_INS_CDD___RSS, - HEX_INS_RDD___CSS, - HEX_INS_RD___CS, - HEX_INS_CALLR_RS, - HEX_INS_IF__PU__CALLR_RS, - HEX_INS_IF__NOT_PU_CALLR_RS, - HEX_INS_HINTJR__RS_, - HEX_INS_JUMPR_RS, - HEX_INS_IF__PU__JUMPR_NT_RS, - HEX_INS_IF__PU_NEW__JUMPR_NT_RS, - HEX_INS_IF__PU__JUMPR_T_RS, - HEX_INS_IF__PU_NEW__JUMPR_T_RS, - HEX_INS_IF__NOT_PU_JUMPR_NT_RS, - HEX_INS_IF__NOT_PU_NEW_JUMPR_NT_RS, - HEX_INS_IF__NOT_PU_JUMPR_T_RS, - HEX_INS_IF__NOT_PU_NEW_JUMPR_T_RS, - HEX_INS_CALL__R22_2, - HEX_INS_IF__PU__CALL__R15_2, - HEX_INS_IF__NOT_PU_CALL__R15_2, - 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HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___MEMUH__RS____U3_1____JUMPR_LR, - HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RD___MEMUH__RU____U3_1____MEMW__RS____U4_2_____1, - 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HEX_INS_DUPLEX_RD___SXTB__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTB__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RD___SXTB__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____JUMPR_LR, - HEX_INS_DUPLEX_RD___SXTB__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RD___SXTB__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RS__RX_, - HEX_INS_DUPLEX_RD___SXTB__RU____RX___ADD__RX__RS_, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RD___SXTB__RU____MEMB__RS____U4_0____RT, - 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HEX_INS_DUPLEX_RD___ZXTH__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RD___ZXTH__RU____P0___CMP_EQ__RS___U2_, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RS____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___0__RU____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___1___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___2___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE___3___U2____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____JUMPR_LR, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___COMBINE__RS___0____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___COMBINE__RU___0____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____ALLOCFRAME___U5_3_, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____0, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0_____1, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMB__RS____U4_0____RT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMD__SP____S6_3____RTT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMH__RS____U3_1____RT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____0, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2_____1, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__RS____U4_2____RT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____MEMW__SP____U5_2____RT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____DEALLOCFRAME, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF___NOT__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__DEALLOC_RETURN, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0__JUMPR_LR, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__DEALLOC_RETURN_NT, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____IF__P0_NEW__JUMPR_NT_LR, - HEX_INS_DUPLEX_RDD___MEMD__SP____U5_3____JUMPR_LR, - HEX_INS_DUPLEX_RE_____1___RD_____1, - HEX_INS_DUPLEX_RE_____1___RD___MEMB__RS____U3_0_, - HEX_INS_DUPLEX_RE_____1___RD___MEMH__RS____U3_1_, - HEX_INS_DUPLEX_RE_____1___RD___MEMUB__RS____U4_0_, - HEX_INS_DUPLEX_RE_____1___RD___MEMUH__RS____U3_1_, - HEX_INS_DUPLEX_RE_____1___RD___MEMW__RS____U4_2_, - HEX_INS_DUPLEX_RE_____1___RD___MEMW__SP____U5_2_, - HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0___U2_, - HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___0__RS_, - HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___1___U2_, - HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___2___U2_, - HEX_INS_DUPLEX_RE_____1___RDD___COMBINE___3___U2_, - HEX_INS_DUPLEX_RE_____1___RDD___COMBINE__RS___0_, - HEX_INS_DUPLEX_RE_____1___RDD___MEMD__SP____U5_3_, - HEX_INS_DUPLEX_RE_____1___IF___NOT__P0__RD____0, - HEX_INS_DUPLEX_RE_____1___IF___NOT__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE_____1___IF__P0__RD____0, - HEX_INS_DUPLEX_RE_____1___IF__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE____U6___RD_____1, - HEX_INS_DUPLEX_RE____U6___RD____U6, - HEX_INS_DUPLEX_RE____U6___RD___ADD__RS____1_, - HEX_INS_DUPLEX_RE____U6___RD___ADD__RS___1_, - HEX_INS_DUPLEX_RE____U6___RD___ADD__SP___U6_2_, - HEX_INS_DUPLEX_RE____U6___RD___AND__RS___1_, - HEX_INS_DUPLEX_RE____U6___RD___AND__RS___255_, - HEX_INS_DUPLEX_RE____U6___RD___MEMB__RS____U3_0_, - HEX_INS_DUPLEX_RE____U6___RD___MEMH__RS____U3_1_, - HEX_INS_DUPLEX_RE____U6___RD___MEMUB__RS____U4_0_, - HEX_INS_DUPLEX_RE____U6___RD___MEMUH__RS____U3_1_, - HEX_INS_DUPLEX_RE____U6___RD___MEMW__RS____U4_2_, - HEX_INS_DUPLEX_RE____U6___RD___MEMW__SP____U5_2_, - HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0___U2_, - HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___0__RS_, - HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___1___U2_, - HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___2___U2_, - HEX_INS_DUPLEX_RE____U6___RDD___COMBINE___3___U2_, - HEX_INS_DUPLEX_RE____U6___RDD___COMBINE__RS___0_, - HEX_INS_DUPLEX_RE____U6___RDD___MEMD__SP____U5_3_, - HEX_INS_DUPLEX_RE____U6___IF___NOT__P0__RD____0, - HEX_INS_DUPLEX_RE____U6___IF___NOT__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE____U6___IF__P0__RD____0, - HEX_INS_DUPLEX_RE____U6___IF__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE____U6___RD___RS, - HEX_INS_DUPLEX_RE____U6___RD___SXTB__RS_, - HEX_INS_DUPLEX_RE____U6___RD___SXTH__RS_, - HEX_INS_DUPLEX_RE____U6___RD___ZXTH__RS_, - HEX_INS_DUPLEX_RE___RS___RD_____1, - HEX_INS_DUPLEX_RE___RS___RD___MEMW__SP____U5_2_, - HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___0___U2_, - HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___1___U2_, - HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___2___U2_, - HEX_INS_DUPLEX_RE___RS___RDD___COMBINE___3___U2_, - HEX_INS_DUPLEX_RE___RS___RDD___MEMD__SP____U5_3_, - HEX_INS_DUPLEX_RE___RS___IF___NOT__P0__RD____0, - HEX_INS_DUPLEX_RE___RS___IF___NOT__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE___RS___IF__P0__RD____0, - HEX_INS_DUPLEX_RE___RS___IF__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE___RU___RD___RS, - HEX_INS_DUPLEX_RE___RU___RD___ADD__RS____1_, - HEX_INS_DUPLEX_RE___RU___RD___ADD__RS___1_, - HEX_INS_DUPLEX_RE___RU___RD___AND__RS___1_, - HEX_INS_DUPLEX_RE___RU___RD___AND__RS___255_, - HEX_INS_DUPLEX_RE___RU___RD___MEMB__RS____U3_0_, - HEX_INS_DUPLEX_RE___RU___RD___MEMH__RS____U3_1_, - HEX_INS_DUPLEX_RE___RU___RD___MEMUB__RS____U4_0_, - HEX_INS_DUPLEX_RE___RU___RD___MEMUH__RS____U3_1_, - HEX_INS_DUPLEX_RE___RU___RD___MEMW__RS____U4_2_, - HEX_INS_DUPLEX_RE___RU___RD___SXTB__RS_, - HEX_INS_DUPLEX_RE___RU___RD___SXTH__RS_, - HEX_INS_DUPLEX_RE___RU___RD___ZXTH__RS_, - HEX_INS_DUPLEX_RE___RU___RDD___COMBINE___0__RS_, - HEX_INS_DUPLEX_RE___RU___RDD___COMBINE__RS___0_, - HEX_INS_DUPLEX_RE___ADD__RS____1____RD_____1, - HEX_INS_DUPLEX_RE___ADD__RS____1____RD___MEMW__SP____U5_2_, - HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___0___U2_, - HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___1___U2_, - HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___2___U2_, - HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___COMBINE___3___U2_, - HEX_INS_DUPLEX_RE___ADD__RS____1____RDD___MEMD__SP____U5_3_, - HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS____1____IF___NOT__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS____1____IF__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS___1____RD_____1, - HEX_INS_DUPLEX_RE___ADD__RS___1____RD___MEMW__SP____U5_2_, - HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___0___U2_, - HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___1___U2_, - HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___2___U2_, - HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___COMBINE___3___U2_, - HEX_INS_DUPLEX_RE___ADD__RS___1____RDD___MEMD__SP____U5_3_, - HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS___1____IF___NOT__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0__RD____0, - HEX_INS_DUPLEX_RE___ADD__RS___1____IF__P0_NEW__RD____0, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ADD__RS____1_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___AND__RS___255_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMB__RS____U3_0_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMH__RS____U3_1_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUB__RS____U4_0_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMUH__RS____U3_1_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___MEMW__RS____U4_2_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTB__RS_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___SXTH__RS_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RD___ZXTH__RS_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE___0__RS_, - HEX_INS_DUPLEX_RE___ADD__RU____1____RDD___COMBINE__RS___0_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS____1_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ADD__RS___1_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___1_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___AND__RS___255_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMB__RS____U3_0_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMH__RS____U3_1_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUB__RS____U4_0_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMUH__RS____U3_1_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___MEMW__RS____U4_2_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTB__RS_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___SXTH__RS_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RD___ZXTH__RS_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE___0__RS_, - HEX_INS_DUPLEX_RE___ADD__RU___1____RDD___COMBINE__RS___0_, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD_____1, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS____1_, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__RS___1_, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___ADD__SP___U6_2_, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___1_, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___AND__RS___255_, - HEX_INS_DUPLEX_RE___ADD__SP___U6_2____RD___MEMB__RS____U3_0_, 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HEX_INS_A2_ADDPSAT, + HEX_INS_A2_ADDSAT, + HEX_INS_A2_ADDSPH, + HEX_INS_A2_ADDSPL, + HEX_INS_A2_AND, + HEX_INS_A2_ANDIR, + HEX_INS_A2_ANDP, + HEX_INS_A2_ASLH, + HEX_INS_A2_ASRH, + HEX_INS_A2_COMBINE_HH, + HEX_INS_A2_COMBINE_HL, + HEX_INS_A2_COMBINE_LH, + HEX_INS_A2_COMBINE_LL, + HEX_INS_A2_COMBINEII, + HEX_INS_A2_COMBINEW, + HEX_INS_A2_MAX, + HEX_INS_A2_MAXP, + HEX_INS_A2_MAXU, + HEX_INS_A2_MAXUP, + HEX_INS_A2_MIN, + HEX_INS_A2_MINP, + HEX_INS_A2_MINU, + HEX_INS_A2_MINUP, + HEX_INS_A2_NEGP, + HEX_INS_A2_NEGSAT, + HEX_INS_A2_NOP, + HEX_INS_A2_NOTP, + HEX_INS_A2_OR, + HEX_INS_A2_ORIR, + HEX_INS_A2_ORP, + HEX_INS_A2_PADDF, + HEX_INS_A2_PADDFNEW, + HEX_INS_A2_PADDIF, + HEX_INS_A2_PADDIFNEW, + HEX_INS_A2_PADDIT, + HEX_INS_A2_PADDITNEW, + HEX_INS_A2_PADDT, + HEX_INS_A2_PADDTNEW, + HEX_INS_A2_PANDF, + HEX_INS_A2_PANDFNEW, + HEX_INS_A2_PANDT, + HEX_INS_A2_PANDTNEW, + HEX_INS_A2_PORF, + HEX_INS_A2_PORFNEW, + HEX_INS_A2_PORT, + HEX_INS_A2_PORTNEW, + HEX_INS_A2_PSUBF, + HEX_INS_A2_PSUBFNEW, + HEX_INS_A2_PSUBT, + HEX_INS_A2_PSUBTNEW, + HEX_INS_A2_PXORF, + HEX_INS_A2_PXORFNEW, + HEX_INS_A2_PXORT, + HEX_INS_A2_PXORTNEW, + HEX_INS_A2_ROUNDSAT, + HEX_INS_A2_SAT, + HEX_INS_A2_SATB, + HEX_INS_A2_SATH, + HEX_INS_A2_SATUB, + HEX_INS_A2_SATUH, + HEX_INS_A2_SUB, + HEX_INS_A2_SUBH_H16_HH, + HEX_INS_A2_SUBH_H16_HL, + HEX_INS_A2_SUBH_H16_LH, + HEX_INS_A2_SUBH_H16_LL, + HEX_INS_A2_SUBH_H16_SAT_HH, + HEX_INS_A2_SUBH_H16_SAT_HL, + HEX_INS_A2_SUBH_H16_SAT_LH, + HEX_INS_A2_SUBH_H16_SAT_LL, + HEX_INS_A2_SUBH_L16_HL, + HEX_INS_A2_SUBH_L16_LL, + HEX_INS_A2_SUBH_L16_SAT_HL, + HEX_INS_A2_SUBH_L16_SAT_LL, + HEX_INS_A2_SUBP, + HEX_INS_A2_SUBRI, + HEX_INS_A2_SUBSAT, + HEX_INS_A2_SVADDH, + HEX_INS_A2_SVADDHS, + HEX_INS_A2_SVADDUHS, + HEX_INS_A2_SVAVGH, + HEX_INS_A2_SVAVGHS, + HEX_INS_A2_SVNAVGH, + HEX_INS_A2_SVSUBH, + HEX_INS_A2_SVSUBHS, + HEX_INS_A2_SVSUBUHS, + HEX_INS_A2_SWIZ, + HEX_INS_A2_SXTB, + HEX_INS_A2_SXTH, + HEX_INS_A2_SXTW, + HEX_INS_A2_TFR, + HEX_INS_A2_TFRCRR, + HEX_INS_A2_TFRIH, + HEX_INS_A2_TFRIL, + HEX_INS_A2_TFRRCR, + HEX_INS_A2_TFRSI, + HEX_INS_A2_VABSH, + HEX_INS_A2_VABSHSAT, + HEX_INS_A2_VABSW, + HEX_INS_A2_VABSWSAT, + HEX_INS_A2_VADDH, + HEX_INS_A2_VADDHS, + HEX_INS_A2_VADDUB, + HEX_INS_A2_VADDUBS, + HEX_INS_A2_VADDUHS, + HEX_INS_A2_VADDW, + HEX_INS_A2_VADDWS, + HEX_INS_A2_VAVGH, + HEX_INS_A2_VAVGHCR, + HEX_INS_A2_VAVGHR, + HEX_INS_A2_VAVGUB, + HEX_INS_A2_VAVGUBR, + HEX_INS_A2_VAVGUH, + HEX_INS_A2_VAVGUHR, + HEX_INS_A2_VAVGUW, + HEX_INS_A2_VAVGUWR, + HEX_INS_A2_VAVGW, + HEX_INS_A2_VAVGWCR, + HEX_INS_A2_VAVGWR, + HEX_INS_A2_VCMPBEQ, + HEX_INS_A2_VCMPBGTU, + HEX_INS_A2_VCMPHEQ, + HEX_INS_A2_VCMPHGT, + HEX_INS_A2_VCMPHGTU, + HEX_INS_A2_VCMPWEQ, + HEX_INS_A2_VCMPWGT, + HEX_INS_A2_VCMPWGTU, + HEX_INS_A2_VCONJ, + HEX_INS_A2_VMAXB, + HEX_INS_A2_VMAXH, + HEX_INS_A2_VMAXUB, + HEX_INS_A2_VMAXUH, + HEX_INS_A2_VMAXUW, + HEX_INS_A2_VMAXW, + HEX_INS_A2_VMINB, + HEX_INS_A2_VMINH, + HEX_INS_A2_VMINUB, + HEX_INS_A2_VMINUH, + HEX_INS_A2_VMINUW, + HEX_INS_A2_VMINW, + HEX_INS_A2_VNAVGH, + HEX_INS_A2_VNAVGHCR, + HEX_INS_A2_VNAVGHR, + HEX_INS_A2_VNAVGW, + HEX_INS_A2_VNAVGWCR, + HEX_INS_A2_VNAVGWR, + HEX_INS_A2_VRADDUB, + HEX_INS_A2_VRADDUB_ACC, + HEX_INS_A2_VRSADUB, + HEX_INS_A2_VRSADUB_ACC, + HEX_INS_A2_VSUBH, + HEX_INS_A2_VSUBHS, + HEX_INS_A2_VSUBUB, + HEX_INS_A2_VSUBUBS, + HEX_INS_A2_VSUBUHS, + HEX_INS_A2_VSUBW, + HEX_INS_A2_VSUBWS, + HEX_INS_A2_XOR, + HEX_INS_A2_XORP, + HEX_INS_A2_ZXTH, + HEX_INS_A4_ADDP_C, + HEX_INS_A4_ANDN, + HEX_INS_A4_ANDNP, + HEX_INS_A4_BITSPLIT, + HEX_INS_A4_BITSPLITI, + HEX_INS_A4_BOUNDSCHECK_HI, + HEX_INS_A4_BOUNDSCHECK_LO, + HEX_INS_A4_CMPBEQ, + HEX_INS_A4_CMPBEQI, + HEX_INS_A4_CMPBGT, + HEX_INS_A4_CMPBGTI, + HEX_INS_A4_CMPBGTU, + HEX_INS_A4_CMPBGTUI, + HEX_INS_A4_CMPHEQ, + HEX_INS_A4_CMPHEQI, + HEX_INS_A4_CMPHGT, + HEX_INS_A4_CMPHGTI, + HEX_INS_A4_CMPHGTU, + HEX_INS_A4_CMPHGTUI, + HEX_INS_A4_COMBINEII, + HEX_INS_A4_COMBINEIR, + HEX_INS_A4_COMBINERI, + HEX_INS_A4_CROUND_RI, + HEX_INS_A4_CROUND_RR, + HEX_INS_A4_EXT, + HEX_INS_A4_MODWRAPU, + HEX_INS_A4_ORN, + HEX_INS_A4_ORNP, + HEX_INS_A4_PASLHF, + HEX_INS_A4_PASLHFNEW, + HEX_INS_A4_PASLHT, + HEX_INS_A4_PASLHTNEW, + HEX_INS_A4_PASRHF, + HEX_INS_A4_PASRHFNEW, + HEX_INS_A4_PASRHT, + HEX_INS_A4_PASRHTNEW, + HEX_INS_A4_PSXTBF, + HEX_INS_A4_PSXTBFNEW, + HEX_INS_A4_PSXTBT, + HEX_INS_A4_PSXTBTNEW, + HEX_INS_A4_PSXTHF, + HEX_INS_A4_PSXTHFNEW, + HEX_INS_A4_PSXTHT, + HEX_INS_A4_PSXTHTNEW, + HEX_INS_A4_PZXTBF, + HEX_INS_A4_PZXTBFNEW, + HEX_INS_A4_PZXTBT, + HEX_INS_A4_PZXTBTNEW, + HEX_INS_A4_PZXTHF, + HEX_INS_A4_PZXTHFNEW, + HEX_INS_A4_PZXTHT, + HEX_INS_A4_PZXTHTNEW, + HEX_INS_A4_RCMPEQ, + HEX_INS_A4_RCMPEQI, + HEX_INS_A4_RCMPNEQ, + HEX_INS_A4_RCMPNEQI, + HEX_INS_A4_ROUND_RI, + HEX_INS_A4_ROUND_RI_SAT, + HEX_INS_A4_ROUND_RR, + HEX_INS_A4_ROUND_RR_SAT, + HEX_INS_A4_SUBP_C, + HEX_INS_A4_TFRCPP, + HEX_INS_A4_TFRPCP, + HEX_INS_A4_TLBMATCH, + HEX_INS_A4_VCMPBEQ_ANY, + HEX_INS_A4_VCMPBEQI, + HEX_INS_A4_VCMPBGT, + HEX_INS_A4_VCMPBGTI, + HEX_INS_A4_VCMPBGTUI, + HEX_INS_A4_VCMPHEQI, + HEX_INS_A4_VCMPHGTI, + HEX_INS_A4_VCMPHGTUI, + HEX_INS_A4_VCMPWEQI, + HEX_INS_A4_VCMPWGTI, + HEX_INS_A4_VCMPWGTUI, + HEX_INS_A4_VRMAXH, + HEX_INS_A4_VRMAXUH, + HEX_INS_A4_VRMAXUW, + HEX_INS_A4_VRMAXW, + HEX_INS_A4_VRMINH, + HEX_INS_A4_VRMINUH, + HEX_INS_A4_VRMINUW, + HEX_INS_A4_VRMINW, + HEX_INS_A5_ACS, + HEX_INS_A5_VADDHUBS, + HEX_INS_A6_VCMPBEQ_NOTANY, + HEX_INS_A6_VMINUB_RDP, + HEX_INS_A7_CLIP, + HEX_INS_A7_CROUNDD_RI, + HEX_INS_A7_CROUNDD_RR, + HEX_INS_A7_VCLIP, + HEX_INS_C2_ALL8, + HEX_INS_C2_AND, + HEX_INS_C2_ANDN, + HEX_INS_C2_ANY8, + HEX_INS_C2_BITSCLR, + HEX_INS_C2_BITSCLRI, + HEX_INS_C2_BITSSET, + HEX_INS_C2_CCOMBINEWF, + HEX_INS_C2_CCOMBINEWNEWF, + HEX_INS_C2_CCOMBINEWNEWT, + HEX_INS_C2_CCOMBINEWT, + HEX_INS_C2_CMOVEIF, + HEX_INS_C2_CMOVEIT, + HEX_INS_C2_CMOVENEWIF, + HEX_INS_C2_CMOVENEWIT, + HEX_INS_C2_CMPEQ, + HEX_INS_C2_CMPEQI, + HEX_INS_C2_CMPEQP, + HEX_INS_C2_CMPGT, + HEX_INS_C2_CMPGTI, + HEX_INS_C2_CMPGTP, + HEX_INS_C2_CMPGTU, + HEX_INS_C2_CMPGTUI, + HEX_INS_C2_CMPGTUP, + HEX_INS_C2_MASK, + HEX_INS_C2_MUX, + HEX_INS_C2_MUXII, + HEX_INS_C2_MUXIR, + HEX_INS_C2_MUXRI, + HEX_INS_C2_NOT, + HEX_INS_C2_OR, + HEX_INS_C2_ORN, + HEX_INS_C2_TFRPR, + HEX_INS_C2_TFRRP, + HEX_INS_C2_VITPACK, + HEX_INS_C2_VMUX, + HEX_INS_C2_XOR, + HEX_INS_C4_ADDIPC, + HEX_INS_C4_AND_AND, + HEX_INS_C4_AND_ANDN, + HEX_INS_C4_AND_OR, + HEX_INS_C4_AND_ORN, + HEX_INS_C4_CMPLTE, + HEX_INS_C4_CMPLTEI, + HEX_INS_C4_CMPLTEU, + HEX_INS_C4_CMPLTEUI, + HEX_INS_C4_CMPNEQ, + HEX_INS_C4_CMPNEQI, + HEX_INS_C4_FASTCORNER9, + HEX_INS_C4_FASTCORNER9_NOT, + HEX_INS_C4_NBITSCLR, + HEX_INS_C4_NBITSCLRI, + HEX_INS_C4_NBITSSET, + HEX_INS_C4_OR_AND, + HEX_INS_C4_OR_ANDN, + HEX_INS_C4_OR_OR, + HEX_INS_C4_OR_ORN, + HEX_INS_F2_CONV_D2DF, + HEX_INS_F2_CONV_D2SF, + HEX_INS_F2_CONV_DF2D, + HEX_INS_F2_CONV_DF2D_CHOP, + HEX_INS_F2_CONV_DF2SF, + HEX_INS_F2_CONV_DF2UD, + HEX_INS_F2_CONV_DF2UD_CHOP, + HEX_INS_F2_CONV_DF2UW, + HEX_INS_F2_CONV_DF2UW_CHOP, + HEX_INS_F2_CONV_DF2W, + HEX_INS_F2_CONV_DF2W_CHOP, + HEX_INS_F2_CONV_SF2D, + HEX_INS_F2_CONV_SF2D_CHOP, + HEX_INS_F2_CONV_SF2DF, + HEX_INS_F2_CONV_SF2UD, + HEX_INS_F2_CONV_SF2UD_CHOP, + HEX_INS_F2_CONV_SF2UW, + HEX_INS_F2_CONV_SF2UW_CHOP, + HEX_INS_F2_CONV_SF2W, + HEX_INS_F2_CONV_SF2W_CHOP, + HEX_INS_F2_CONV_UD2DF, + HEX_INS_F2_CONV_UD2SF, + HEX_INS_F2_CONV_UW2DF, + HEX_INS_F2_CONV_UW2SF, + HEX_INS_F2_CONV_W2DF, + HEX_INS_F2_CONV_W2SF, + HEX_INS_F2_DFADD, + HEX_INS_F2_DFCLASS, + HEX_INS_F2_DFCMPEQ, + HEX_INS_F2_DFCMPGE, + HEX_INS_F2_DFCMPGT, + HEX_INS_F2_DFCMPUO, + HEX_INS_F2_DFIMM_N, + HEX_INS_F2_DFIMM_P, + HEX_INS_F2_DFMAX, + HEX_INS_F2_DFMIN, + HEX_INS_F2_DFMPYFIX, + HEX_INS_F2_DFMPYHH, + HEX_INS_F2_DFMPYLH, + HEX_INS_F2_DFMPYLL, + HEX_INS_F2_DFSUB, + HEX_INS_F2_SFADD, + HEX_INS_F2_SFCLASS, + HEX_INS_F2_SFCMPEQ, + HEX_INS_F2_SFCMPGE, + HEX_INS_F2_SFCMPGT, + HEX_INS_F2_SFCMPUO, + HEX_INS_F2_SFFIXUPD, + HEX_INS_F2_SFFIXUPN, + HEX_INS_F2_SFFIXUPR, + HEX_INS_F2_SFFMA, + HEX_INS_F2_SFFMA_LIB, + HEX_INS_F2_SFFMA_SC, + HEX_INS_F2_SFFMS, + HEX_INS_F2_SFFMS_LIB, + HEX_INS_F2_SFIMM_N, + HEX_INS_F2_SFIMM_P, + HEX_INS_F2_SFINVSQRTA, + HEX_INS_F2_SFMAX, + HEX_INS_F2_SFMIN, + HEX_INS_F2_SFMPY, + HEX_INS_F2_SFRECIPA, + HEX_INS_F2_SFSUB, + HEX_INS_G4_TFRGCPP, + HEX_INS_G4_TFRGCRR, + HEX_INS_G4_TFRGPCP, + HEX_INS_G4_TFRGRCR, + HEX_INS_J2_CALL, + HEX_INS_J2_CALLF, + HEX_INS_J2_CALLR, + HEX_INS_J2_CALLRF, + HEX_INS_J2_CALLRT, + HEX_INS_J2_CALLT, + HEX_INS_J2_JUMP, + HEX_INS_J2_JUMPF, + HEX_INS_J2_JUMPFNEW, + HEX_INS_J2_JUMPFNEWPT, + HEX_INS_J2_JUMPFPT, + HEX_INS_J2_JUMPR, + HEX_INS_J2_JUMPRF, + HEX_INS_J2_JUMPRFNEW, + HEX_INS_J2_JUMPRFNEWPT, + HEX_INS_J2_JUMPRFPT, + HEX_INS_J2_JUMPRGTEZ, + HEX_INS_J2_JUMPRGTEZPT, + HEX_INS_J2_JUMPRLTEZ, + HEX_INS_J2_JUMPRLTEZPT, + HEX_INS_J2_JUMPRNZ, + HEX_INS_J2_JUMPRNZPT, + HEX_INS_J2_JUMPRT, + HEX_INS_J2_JUMPRTNEW, + HEX_INS_J2_JUMPRTNEWPT, + HEX_INS_J2_JUMPRTPT, + HEX_INS_J2_JUMPRZ, + HEX_INS_J2_JUMPRZPT, + HEX_INS_J2_JUMPT, + HEX_INS_J2_JUMPTNEW, + HEX_INS_J2_JUMPTNEWPT, + HEX_INS_J2_JUMPTPT, + HEX_INS_J2_LOOP0I, + HEX_INS_J2_LOOP0R, + HEX_INS_J2_LOOP1I, + HEX_INS_J2_LOOP1R, + HEX_INS_J2_PAUSE, + HEX_INS_J2_PLOOP1SI, + HEX_INS_J2_PLOOP1SR, + HEX_INS_J2_PLOOP2SI, + HEX_INS_J2_PLOOP2SR, + HEX_INS_J2_PLOOP3SI, + HEX_INS_J2_PLOOP3SR, + HEX_INS_J2_TRAP0, + HEX_INS_J2_TRAP1, + HEX_INS_J4_CMPEQ_F_JUMPNV_NT, + HEX_INS_J4_CMPEQ_F_JUMPNV_T, + HEX_INS_J4_CMPEQ_FP0_JUMP_NT, + HEX_INS_J4_CMPEQ_FP0_JUMP_T, + HEX_INS_J4_CMPEQ_FP1_JUMP_NT, + HEX_INS_J4_CMPEQ_FP1_JUMP_T, + HEX_INS_J4_CMPEQ_T_JUMPNV_NT, + HEX_INS_J4_CMPEQ_T_JUMPNV_T, + HEX_INS_J4_CMPEQ_TP0_JUMP_NT, + HEX_INS_J4_CMPEQ_TP0_JUMP_T, + HEX_INS_J4_CMPEQ_TP1_JUMP_NT, + HEX_INS_J4_CMPEQ_TP1_JUMP_T, + HEX_INS_J4_CMPEQI_F_JUMPNV_NT, + HEX_INS_J4_CMPEQI_F_JUMPNV_T, + HEX_INS_J4_CMPEQI_FP0_JUMP_NT, + HEX_INS_J4_CMPEQI_FP0_JUMP_T, + HEX_INS_J4_CMPEQI_FP1_JUMP_NT, + HEX_INS_J4_CMPEQI_FP1_JUMP_T, + HEX_INS_J4_CMPEQI_T_JUMPNV_NT, + HEX_INS_J4_CMPEQI_T_JUMPNV_T, + HEX_INS_J4_CMPEQI_TP0_JUMP_NT, + HEX_INS_J4_CMPEQI_TP0_JUMP_T, + HEX_INS_J4_CMPEQI_TP1_JUMP_NT, + HEX_INS_J4_CMPEQI_TP1_JUMP_T, + HEX_INS_J4_CMPEQN1_F_JUMPNV_NT, + HEX_INS_J4_CMPEQN1_F_JUMPNV_T, + HEX_INS_J4_CMPEQN1_FP0_JUMP_NT, + HEX_INS_J4_CMPEQN1_FP0_JUMP_T, + HEX_INS_J4_CMPEQN1_FP1_JUMP_NT, + HEX_INS_J4_CMPEQN1_FP1_JUMP_T, + HEX_INS_J4_CMPEQN1_T_JUMPNV_NT, + HEX_INS_J4_CMPEQN1_T_JUMPNV_T, + HEX_INS_J4_CMPEQN1_TP0_JUMP_NT, + HEX_INS_J4_CMPEQN1_TP0_JUMP_T, + HEX_INS_J4_CMPEQN1_TP1_JUMP_NT, + HEX_INS_J4_CMPEQN1_TP1_JUMP_T, + HEX_INS_J4_CMPGT_F_JUMPNV_NT, + HEX_INS_J4_CMPGT_F_JUMPNV_T, + HEX_INS_J4_CMPGT_FP0_JUMP_NT, + HEX_INS_J4_CMPGT_FP0_JUMP_T, + HEX_INS_J4_CMPGT_FP1_JUMP_NT, + HEX_INS_J4_CMPGT_FP1_JUMP_T, + HEX_INS_J4_CMPGT_T_JUMPNV_NT, + HEX_INS_J4_CMPGT_T_JUMPNV_T, + HEX_INS_J4_CMPGT_TP0_JUMP_NT, + HEX_INS_J4_CMPGT_TP0_JUMP_T, + HEX_INS_J4_CMPGT_TP1_JUMP_NT, + HEX_INS_J4_CMPGT_TP1_JUMP_T, + HEX_INS_J4_CMPGTI_F_JUMPNV_NT, + HEX_INS_J4_CMPGTI_F_JUMPNV_T, + HEX_INS_J4_CMPGTI_FP0_JUMP_NT, + HEX_INS_J4_CMPGTI_FP0_JUMP_T, + HEX_INS_J4_CMPGTI_FP1_JUMP_NT, + HEX_INS_J4_CMPGTI_FP1_JUMP_T, + HEX_INS_J4_CMPGTI_T_JUMPNV_NT, + HEX_INS_J4_CMPGTI_T_JUMPNV_T, + HEX_INS_J4_CMPGTI_TP0_JUMP_NT, + HEX_INS_J4_CMPGTI_TP0_JUMP_T, + HEX_INS_J4_CMPGTI_TP1_JUMP_NT, + HEX_INS_J4_CMPGTI_TP1_JUMP_T, + HEX_INS_J4_CMPGTN1_F_JUMPNV_NT, + HEX_INS_J4_CMPGTN1_F_JUMPNV_T, + HEX_INS_J4_CMPGTN1_FP0_JUMP_NT, + HEX_INS_J4_CMPGTN1_FP0_JUMP_T, + HEX_INS_J4_CMPGTN1_FP1_JUMP_NT, + HEX_INS_J4_CMPGTN1_FP1_JUMP_T, + HEX_INS_J4_CMPGTN1_T_JUMPNV_NT, + HEX_INS_J4_CMPGTN1_T_JUMPNV_T, + HEX_INS_J4_CMPGTN1_TP0_JUMP_NT, + HEX_INS_J4_CMPGTN1_TP0_JUMP_T, + HEX_INS_J4_CMPGTN1_TP1_JUMP_NT, + HEX_INS_J4_CMPGTN1_TP1_JUMP_T, + HEX_INS_J4_CMPGTU_F_JUMPNV_NT, + HEX_INS_J4_CMPGTU_F_JUMPNV_T, + HEX_INS_J4_CMPGTU_FP0_JUMP_NT, + HEX_INS_J4_CMPGTU_FP0_JUMP_T, + HEX_INS_J4_CMPGTU_FP1_JUMP_NT, + HEX_INS_J4_CMPGTU_FP1_JUMP_T, + HEX_INS_J4_CMPGTU_T_JUMPNV_NT, + HEX_INS_J4_CMPGTU_T_JUMPNV_T, + HEX_INS_J4_CMPGTU_TP0_JUMP_NT, + HEX_INS_J4_CMPGTU_TP0_JUMP_T, + HEX_INS_J4_CMPGTU_TP1_JUMP_NT, + HEX_INS_J4_CMPGTU_TP1_JUMP_T, + HEX_INS_J4_CMPGTUI_F_JUMPNV_NT, + HEX_INS_J4_CMPGTUI_F_JUMPNV_T, + HEX_INS_J4_CMPGTUI_FP0_JUMP_NT, + HEX_INS_J4_CMPGTUI_FP0_JUMP_T, + HEX_INS_J4_CMPGTUI_FP1_JUMP_NT, + HEX_INS_J4_CMPGTUI_FP1_JUMP_T, + HEX_INS_J4_CMPGTUI_T_JUMPNV_NT, + HEX_INS_J4_CMPGTUI_T_JUMPNV_T, + HEX_INS_J4_CMPGTUI_TP0_JUMP_NT, + HEX_INS_J4_CMPGTUI_TP0_JUMP_T, + HEX_INS_J4_CMPGTUI_TP1_JUMP_NT, + HEX_INS_J4_CMPGTUI_TP1_JUMP_T, + HEX_INS_J4_CMPLT_F_JUMPNV_NT, + HEX_INS_J4_CMPLT_F_JUMPNV_T, + HEX_INS_J4_CMPLT_T_JUMPNV_NT, + HEX_INS_J4_CMPLT_T_JUMPNV_T, + HEX_INS_J4_CMPLTU_F_JUMPNV_NT, + HEX_INS_J4_CMPLTU_F_JUMPNV_T, + HEX_INS_J4_CMPLTU_T_JUMPNV_NT, + HEX_INS_J4_CMPLTU_T_JUMPNV_T, + HEX_INS_J4_HINTJUMPR, + HEX_INS_J4_JUMPSETI, + HEX_INS_J4_JUMPSETR, + HEX_INS_J4_TSTBIT0_F_JUMPNV_NT, + HEX_INS_J4_TSTBIT0_F_JUMPNV_T, + HEX_INS_J4_TSTBIT0_FP0_JUMP_NT, + HEX_INS_J4_TSTBIT0_FP0_JUMP_T, + HEX_INS_J4_TSTBIT0_FP1_JUMP_NT, + HEX_INS_J4_TSTBIT0_FP1_JUMP_T, + HEX_INS_J4_TSTBIT0_T_JUMPNV_NT, + HEX_INS_J4_TSTBIT0_T_JUMPNV_T, + HEX_INS_J4_TSTBIT0_TP0_JUMP_NT, + HEX_INS_J4_TSTBIT0_TP0_JUMP_T, + HEX_INS_J4_TSTBIT0_TP1_JUMP_NT, + HEX_INS_J4_TSTBIT0_TP1_JUMP_T, + HEX_INS_L2_DEALLOCFRAME, + HEX_INS_L2_LOADALIGNB_IO, + HEX_INS_L2_LOADALIGNB_PBR, + HEX_INS_L2_LOADALIGNB_PCI, + HEX_INS_L2_LOADALIGNB_PCR, + HEX_INS_L2_LOADALIGNB_PI, + HEX_INS_L2_LOADALIGNB_PR, + HEX_INS_L2_LOADALIGNH_IO, + HEX_INS_L2_LOADALIGNH_PBR, + HEX_INS_L2_LOADALIGNH_PCI, + HEX_INS_L2_LOADALIGNH_PCR, + HEX_INS_L2_LOADALIGNH_PI, + HEX_INS_L2_LOADALIGNH_PR, + HEX_INS_L2_LOADBSW2_IO, + HEX_INS_L2_LOADBSW2_PBR, + HEX_INS_L2_LOADBSW2_PCI, + HEX_INS_L2_LOADBSW2_PCR, + HEX_INS_L2_LOADBSW2_PI, + HEX_INS_L2_LOADBSW2_PR, + HEX_INS_L2_LOADBSW4_IO, + HEX_INS_L2_LOADBSW4_PBR, + HEX_INS_L2_LOADBSW4_PCI, + HEX_INS_L2_LOADBSW4_PCR, + HEX_INS_L2_LOADBSW4_PI, + HEX_INS_L2_LOADBSW4_PR, + HEX_INS_L2_LOADBZW2_IO, + HEX_INS_L2_LOADBZW2_PBR, + HEX_INS_L2_LOADBZW2_PCI, + HEX_INS_L2_LOADBZW2_PCR, + HEX_INS_L2_LOADBZW2_PI, + HEX_INS_L2_LOADBZW2_PR, + HEX_INS_L2_LOADBZW4_IO, + HEX_INS_L2_LOADBZW4_PBR, + HEX_INS_L2_LOADBZW4_PCI, + HEX_INS_L2_LOADBZW4_PCR, + HEX_INS_L2_LOADBZW4_PI, + HEX_INS_L2_LOADBZW4_PR, + HEX_INS_L2_LOADRB_IO, + HEX_INS_L2_LOADRB_PBR, + HEX_INS_L2_LOADRB_PCI, + HEX_INS_L2_LOADRB_PCR, + HEX_INS_L2_LOADRB_PI, + HEX_INS_L2_LOADRB_PR, + HEX_INS_L2_LOADRBGP, + HEX_INS_L2_LOADRD_IO, + HEX_INS_L2_LOADRD_PBR, + HEX_INS_L2_LOADRD_PCI, + HEX_INS_L2_LOADRD_PCR, + HEX_INS_L2_LOADRD_PI, + HEX_INS_L2_LOADRD_PR, + HEX_INS_L2_LOADRDGP, + HEX_INS_L2_LOADRH_IO, + HEX_INS_L2_LOADRH_PBR, + HEX_INS_L2_LOADRH_PCI, + HEX_INS_L2_LOADRH_PCR, + HEX_INS_L2_LOADRH_PI, + HEX_INS_L2_LOADRH_PR, + HEX_INS_L2_LOADRHGP, + HEX_INS_L2_LOADRI_IO, + HEX_INS_L2_LOADRI_PBR, + HEX_INS_L2_LOADRI_PCI, + HEX_INS_L2_LOADRI_PCR, + HEX_INS_L2_LOADRI_PI, + HEX_INS_L2_LOADRI_PR, + HEX_INS_L2_LOADRIGP, + HEX_INS_L2_LOADRUB_IO, + HEX_INS_L2_LOADRUB_PBR, + HEX_INS_L2_LOADRUB_PCI, + HEX_INS_L2_LOADRUB_PCR, + HEX_INS_L2_LOADRUB_PI, + HEX_INS_L2_LOADRUB_PR, + HEX_INS_L2_LOADRUBGP, + HEX_INS_L2_LOADRUH_IO, + HEX_INS_L2_LOADRUH_PBR, + HEX_INS_L2_LOADRUH_PCI, + HEX_INS_L2_LOADRUH_PCR, + HEX_INS_L2_LOADRUH_PI, + HEX_INS_L2_LOADRUH_PR, + HEX_INS_L2_LOADRUHGP, + HEX_INS_L2_LOADW_AQ, + HEX_INS_L2_LOADW_LOCKED, + HEX_INS_L2_PLOADRBF_IO, + HEX_INS_L2_PLOADRBF_PI, + HEX_INS_L2_PLOADRBFNEW_IO, + HEX_INS_L2_PLOADRBFNEW_PI, + HEX_INS_L2_PLOADRBT_IO, + HEX_INS_L2_PLOADRBT_PI, + HEX_INS_L2_PLOADRBTNEW_IO, + HEX_INS_L2_PLOADRBTNEW_PI, + HEX_INS_L2_PLOADRDF_IO, + HEX_INS_L2_PLOADRDF_PI, + HEX_INS_L2_PLOADRDFNEW_IO, + HEX_INS_L2_PLOADRDFNEW_PI, + HEX_INS_L2_PLOADRDT_IO, + HEX_INS_L2_PLOADRDT_PI, + HEX_INS_L2_PLOADRDTNEW_IO, + HEX_INS_L2_PLOADRDTNEW_PI, + HEX_INS_L2_PLOADRHF_IO, + HEX_INS_L2_PLOADRHF_PI, + HEX_INS_L2_PLOADRHFNEW_IO, + HEX_INS_L2_PLOADRHFNEW_PI, + HEX_INS_L2_PLOADRHT_IO, + HEX_INS_L2_PLOADRHT_PI, + HEX_INS_L2_PLOADRHTNEW_IO, + HEX_INS_L2_PLOADRHTNEW_PI, + HEX_INS_L2_PLOADRIF_IO, + HEX_INS_L2_PLOADRIF_PI, + HEX_INS_L2_PLOADRIFNEW_IO, + HEX_INS_L2_PLOADRIFNEW_PI, + HEX_INS_L2_PLOADRIT_IO, + HEX_INS_L2_PLOADRIT_PI, + HEX_INS_L2_PLOADRITNEW_IO, + HEX_INS_L2_PLOADRITNEW_PI, + HEX_INS_L2_PLOADRUBF_IO, + HEX_INS_L2_PLOADRUBF_PI, + HEX_INS_L2_PLOADRUBFNEW_IO, + HEX_INS_L2_PLOADRUBFNEW_PI, + HEX_INS_L2_PLOADRUBT_IO, + HEX_INS_L2_PLOADRUBT_PI, + HEX_INS_L2_PLOADRUBTNEW_IO, + HEX_INS_L2_PLOADRUBTNEW_PI, + HEX_INS_L2_PLOADRUHF_IO, + HEX_INS_L2_PLOADRUHF_PI, + HEX_INS_L2_PLOADRUHFNEW_IO, + HEX_INS_L2_PLOADRUHFNEW_PI, + HEX_INS_L2_PLOADRUHT_IO, + HEX_INS_L2_PLOADRUHT_PI, + HEX_INS_L2_PLOADRUHTNEW_IO, + HEX_INS_L2_PLOADRUHTNEW_PI, + HEX_INS_L4_ADD_MEMOPB_IO, + HEX_INS_L4_ADD_MEMOPH_IO, + HEX_INS_L4_ADD_MEMOPW_IO, + HEX_INS_L4_AND_MEMOPB_IO, + HEX_INS_L4_AND_MEMOPH_IO, + HEX_INS_L4_AND_MEMOPW_IO, + HEX_INS_L4_IADD_MEMOPB_IO, + HEX_INS_L4_IADD_MEMOPH_IO, + HEX_INS_L4_IADD_MEMOPW_IO, + HEX_INS_L4_IAND_MEMOPB_IO, + HEX_INS_L4_IAND_MEMOPH_IO, + HEX_INS_L4_IAND_MEMOPW_IO, + HEX_INS_L4_IOR_MEMOPB_IO, + HEX_INS_L4_IOR_MEMOPH_IO, + HEX_INS_L4_IOR_MEMOPW_IO, + HEX_INS_L4_ISUB_MEMOPB_IO, + HEX_INS_L4_ISUB_MEMOPH_IO, + HEX_INS_L4_ISUB_MEMOPW_IO, + HEX_INS_L4_LOADALIGNB_AP, + HEX_INS_L4_LOADALIGNB_UR, + HEX_INS_L4_LOADALIGNH_AP, + HEX_INS_L4_LOADALIGNH_UR, + HEX_INS_L4_LOADBSW2_AP, + HEX_INS_L4_LOADBSW2_UR, + HEX_INS_L4_LOADBSW4_AP, + HEX_INS_L4_LOADBSW4_UR, + HEX_INS_L4_LOADBZW2_AP, + HEX_INS_L4_LOADBZW2_UR, + HEX_INS_L4_LOADBZW4_AP, + HEX_INS_L4_LOADBZW4_UR, + HEX_INS_L4_LOADD_AQ, + HEX_INS_L4_LOADD_LOCKED, + HEX_INS_L4_LOADRB_AP, + HEX_INS_L4_LOADRB_RR, + HEX_INS_L4_LOADRB_UR, + HEX_INS_L4_LOADRD_AP, + HEX_INS_L4_LOADRD_RR, + HEX_INS_L4_LOADRD_UR, + HEX_INS_L4_LOADRH_AP, + HEX_INS_L4_LOADRH_RR, + HEX_INS_L4_LOADRH_UR, + HEX_INS_L4_LOADRI_AP, + HEX_INS_L4_LOADRI_RR, + HEX_INS_L4_LOADRI_UR, + HEX_INS_L4_LOADRUB_AP, + HEX_INS_L4_LOADRUB_RR, + HEX_INS_L4_LOADRUB_UR, + HEX_INS_L4_LOADRUH_AP, + HEX_INS_L4_LOADRUH_RR, + HEX_INS_L4_LOADRUH_UR, + HEX_INS_L4_OR_MEMOPB_IO, + HEX_INS_L4_OR_MEMOPH_IO, + HEX_INS_L4_OR_MEMOPW_IO, + HEX_INS_L4_PLOADRBF_ABS, + HEX_INS_L4_PLOADRBF_RR, + HEX_INS_L4_PLOADRBFNEW_ABS, + HEX_INS_L4_PLOADRBFNEW_RR, + HEX_INS_L4_PLOADRBT_ABS, + HEX_INS_L4_PLOADRBT_RR, + HEX_INS_L4_PLOADRBTNEW_ABS, + HEX_INS_L4_PLOADRBTNEW_RR, + HEX_INS_L4_PLOADRDF_ABS, + HEX_INS_L4_PLOADRDF_RR, + HEX_INS_L4_PLOADRDFNEW_ABS, + HEX_INS_L4_PLOADRDFNEW_RR, + HEX_INS_L4_PLOADRDT_ABS, + HEX_INS_L4_PLOADRDT_RR, + HEX_INS_L4_PLOADRDTNEW_ABS, + HEX_INS_L4_PLOADRDTNEW_RR, + HEX_INS_L4_PLOADRHF_ABS, + HEX_INS_L4_PLOADRHF_RR, + HEX_INS_L4_PLOADRHFNEW_ABS, + HEX_INS_L4_PLOADRHFNEW_RR, + HEX_INS_L4_PLOADRHT_ABS, + HEX_INS_L4_PLOADRHT_RR, + HEX_INS_L4_PLOADRHTNEW_ABS, + HEX_INS_L4_PLOADRHTNEW_RR, + HEX_INS_L4_PLOADRIF_ABS, + HEX_INS_L4_PLOADRIF_RR, + HEX_INS_L4_PLOADRIFNEW_ABS, + HEX_INS_L4_PLOADRIFNEW_RR, + HEX_INS_L4_PLOADRIT_ABS, + HEX_INS_L4_PLOADRIT_RR, + HEX_INS_L4_PLOADRITNEW_ABS, + HEX_INS_L4_PLOADRITNEW_RR, + HEX_INS_L4_PLOADRUBF_ABS, + HEX_INS_L4_PLOADRUBF_RR, + HEX_INS_L4_PLOADRUBFNEW_ABS, + HEX_INS_L4_PLOADRUBFNEW_RR, + HEX_INS_L4_PLOADRUBT_ABS, + HEX_INS_L4_PLOADRUBT_RR, + HEX_INS_L4_PLOADRUBTNEW_ABS, + HEX_INS_L4_PLOADRUBTNEW_RR, + HEX_INS_L4_PLOADRUHF_ABS, + HEX_INS_L4_PLOADRUHF_RR, + HEX_INS_L4_PLOADRUHFNEW_ABS, + HEX_INS_L4_PLOADRUHFNEW_RR, + HEX_INS_L4_PLOADRUHT_ABS, + HEX_INS_L4_PLOADRUHT_RR, + HEX_INS_L4_PLOADRUHTNEW_ABS, + HEX_INS_L4_PLOADRUHTNEW_RR, + HEX_INS_L4_RETURN, + HEX_INS_L4_RETURN_F, + HEX_INS_L4_RETURN_FNEW_PNT, + HEX_INS_L4_RETURN_FNEW_PT, + HEX_INS_L4_RETURN_T, + HEX_INS_L4_RETURN_TNEW_PNT, + HEX_INS_L4_RETURN_TNEW_PT, + HEX_INS_L4_SUB_MEMOPB_IO, + HEX_INS_L4_SUB_MEMOPH_IO, + HEX_INS_L4_SUB_MEMOPW_IO, + HEX_INS_L6_MEMCPY, + HEX_INS_M2_ACCI, + HEX_INS_M2_ACCII, + HEX_INS_M2_CMACI_S0, + HEX_INS_M2_CMACR_S0, + HEX_INS_M2_CMACS_S0, + HEX_INS_M2_CMACS_S1, + HEX_INS_M2_CMACSC_S0, + HEX_INS_M2_CMACSC_S1, + HEX_INS_M2_CMPYI_S0, + HEX_INS_M2_CMPYR_S0, + HEX_INS_M2_CMPYRS_S0, + HEX_INS_M2_CMPYRS_S1, + HEX_INS_M2_CMPYRSC_S0, + HEX_INS_M2_CMPYRSC_S1, + HEX_INS_M2_CMPYS_S0, + HEX_INS_M2_CMPYS_S1, + HEX_INS_M2_CMPYSC_S0, + HEX_INS_M2_CMPYSC_S1, + HEX_INS_M2_CNACS_S0, + HEX_INS_M2_CNACS_S1, + HEX_INS_M2_CNACSC_S0, + HEX_INS_M2_CNACSC_S1, + HEX_INS_M2_DPMPYSS_ACC_S0, + HEX_INS_M2_DPMPYSS_NAC_S0, + HEX_INS_M2_DPMPYSS_RND_S0, + HEX_INS_M2_DPMPYSS_S0, + HEX_INS_M2_DPMPYUU_ACC_S0, + HEX_INS_M2_DPMPYUU_NAC_S0, + HEX_INS_M2_DPMPYUU_S0, + HEX_INS_M2_HMMPYH_RS1, + HEX_INS_M2_HMMPYH_S1, + HEX_INS_M2_HMMPYL_RS1, + HEX_INS_M2_HMMPYL_S1, + HEX_INS_M2_MACI, + HEX_INS_M2_MACSIN, + HEX_INS_M2_MACSIP, + HEX_INS_M2_MMACHS_RS0, + HEX_INS_M2_MMACHS_RS1, + HEX_INS_M2_MMACHS_S0, + HEX_INS_M2_MMACHS_S1, + HEX_INS_M2_MMACLS_RS0, + HEX_INS_M2_MMACLS_RS1, + HEX_INS_M2_MMACLS_S0, + HEX_INS_M2_MMACLS_S1, + HEX_INS_M2_MMACUHS_RS0, + HEX_INS_M2_MMACUHS_RS1, + HEX_INS_M2_MMACUHS_S0, + HEX_INS_M2_MMACUHS_S1, + HEX_INS_M2_MMACULS_RS0, + HEX_INS_M2_MMACULS_RS1, + HEX_INS_M2_MMACULS_S0, + HEX_INS_M2_MMACULS_S1, + HEX_INS_M2_MMPYH_RS0, + HEX_INS_M2_MMPYH_RS1, + HEX_INS_M2_MMPYH_S0, + HEX_INS_M2_MMPYH_S1, + HEX_INS_M2_MMPYL_RS0, + HEX_INS_M2_MMPYL_RS1, + HEX_INS_M2_MMPYL_S0, + HEX_INS_M2_MMPYL_S1, + HEX_INS_M2_MMPYUH_RS0, + HEX_INS_M2_MMPYUH_RS1, + HEX_INS_M2_MMPYUH_S0, + HEX_INS_M2_MMPYUH_S1, + HEX_INS_M2_MMPYUL_RS0, + HEX_INS_M2_MMPYUL_RS1, + HEX_INS_M2_MMPYUL_S0, + HEX_INS_M2_MMPYUL_S1, + HEX_INS_M2_MNACI, + HEX_INS_M2_MPY_ACC_HH_S0, + HEX_INS_M2_MPY_ACC_HH_S1, + HEX_INS_M2_MPY_ACC_HL_S0, + HEX_INS_M2_MPY_ACC_HL_S1, + HEX_INS_M2_MPY_ACC_LH_S0, + HEX_INS_M2_MPY_ACC_LH_S1, + HEX_INS_M2_MPY_ACC_LL_S0, + HEX_INS_M2_MPY_ACC_LL_S1, + HEX_INS_M2_MPY_ACC_SAT_HH_S0, + HEX_INS_M2_MPY_ACC_SAT_HH_S1, + HEX_INS_M2_MPY_ACC_SAT_HL_S0, + HEX_INS_M2_MPY_ACC_SAT_HL_S1, + HEX_INS_M2_MPY_ACC_SAT_LH_S0, + HEX_INS_M2_MPY_ACC_SAT_LH_S1, + HEX_INS_M2_MPY_ACC_SAT_LL_S0, + HEX_INS_M2_MPY_ACC_SAT_LL_S1, + HEX_INS_M2_MPY_HH_S0, + HEX_INS_M2_MPY_HH_S1, + HEX_INS_M2_MPY_HL_S0, + HEX_INS_M2_MPY_HL_S1, + HEX_INS_M2_MPY_LH_S0, + HEX_INS_M2_MPY_LH_S1, + HEX_INS_M2_MPY_LL_S0, + HEX_INS_M2_MPY_LL_S1, + HEX_INS_M2_MPY_NAC_HH_S0, + HEX_INS_M2_MPY_NAC_HH_S1, + HEX_INS_M2_MPY_NAC_HL_S0, + HEX_INS_M2_MPY_NAC_HL_S1, + HEX_INS_M2_MPY_NAC_LH_S0, + HEX_INS_M2_MPY_NAC_LH_S1, + HEX_INS_M2_MPY_NAC_LL_S0, + HEX_INS_M2_MPY_NAC_LL_S1, + HEX_INS_M2_MPY_NAC_SAT_HH_S0, + HEX_INS_M2_MPY_NAC_SAT_HH_S1, + HEX_INS_M2_MPY_NAC_SAT_HL_S0, + HEX_INS_M2_MPY_NAC_SAT_HL_S1, + HEX_INS_M2_MPY_NAC_SAT_LH_S0, + HEX_INS_M2_MPY_NAC_SAT_LH_S1, + HEX_INS_M2_MPY_NAC_SAT_LL_S0, + HEX_INS_M2_MPY_NAC_SAT_LL_S1, + HEX_INS_M2_MPY_RND_HH_S0, + HEX_INS_M2_MPY_RND_HH_S1, + HEX_INS_M2_MPY_RND_HL_S0, + HEX_INS_M2_MPY_RND_HL_S1, + HEX_INS_M2_MPY_RND_LH_S0, + HEX_INS_M2_MPY_RND_LH_S1, + HEX_INS_M2_MPY_RND_LL_S0, + HEX_INS_M2_MPY_RND_LL_S1, + HEX_INS_M2_MPY_SAT_HH_S0, + HEX_INS_M2_MPY_SAT_HH_S1, + HEX_INS_M2_MPY_SAT_HL_S0, + HEX_INS_M2_MPY_SAT_HL_S1, + HEX_INS_M2_MPY_SAT_LH_S0, + HEX_INS_M2_MPY_SAT_LH_S1, + HEX_INS_M2_MPY_SAT_LL_S0, + HEX_INS_M2_MPY_SAT_LL_S1, + HEX_INS_M2_MPY_SAT_RND_HH_S0, + HEX_INS_M2_MPY_SAT_RND_HH_S1, + HEX_INS_M2_MPY_SAT_RND_HL_S0, + HEX_INS_M2_MPY_SAT_RND_HL_S1, + HEX_INS_M2_MPY_SAT_RND_LH_S0, + HEX_INS_M2_MPY_SAT_RND_LH_S1, + HEX_INS_M2_MPY_SAT_RND_LL_S0, + HEX_INS_M2_MPY_SAT_RND_LL_S1, + HEX_INS_M2_MPY_UP, + HEX_INS_M2_MPY_UP_S1, + HEX_INS_M2_MPY_UP_S1_SAT, + HEX_INS_M2_MPYD_ACC_HH_S0, + HEX_INS_M2_MPYD_ACC_HH_S1, + HEX_INS_M2_MPYD_ACC_HL_S0, + HEX_INS_M2_MPYD_ACC_HL_S1, + HEX_INS_M2_MPYD_ACC_LH_S0, + HEX_INS_M2_MPYD_ACC_LH_S1, + HEX_INS_M2_MPYD_ACC_LL_S0, + HEX_INS_M2_MPYD_ACC_LL_S1, + HEX_INS_M2_MPYD_HH_S0, + HEX_INS_M2_MPYD_HH_S1, + HEX_INS_M2_MPYD_HL_S0, + HEX_INS_M2_MPYD_HL_S1, + HEX_INS_M2_MPYD_LH_S0, + HEX_INS_M2_MPYD_LH_S1, + HEX_INS_M2_MPYD_LL_S0, + HEX_INS_M2_MPYD_LL_S1, + HEX_INS_M2_MPYD_NAC_HH_S0, + HEX_INS_M2_MPYD_NAC_HH_S1, + HEX_INS_M2_MPYD_NAC_HL_S0, + HEX_INS_M2_MPYD_NAC_HL_S1, + HEX_INS_M2_MPYD_NAC_LH_S0, + HEX_INS_M2_MPYD_NAC_LH_S1, + HEX_INS_M2_MPYD_NAC_LL_S0, + HEX_INS_M2_MPYD_NAC_LL_S1, + HEX_INS_M2_MPYD_RND_HH_S0, + HEX_INS_M2_MPYD_RND_HH_S1, + HEX_INS_M2_MPYD_RND_HL_S0, + HEX_INS_M2_MPYD_RND_HL_S1, + HEX_INS_M2_MPYD_RND_LH_S0, + HEX_INS_M2_MPYD_RND_LH_S1, + HEX_INS_M2_MPYD_RND_LL_S0, + HEX_INS_M2_MPYD_RND_LL_S1, + HEX_INS_M2_MPYI, + HEX_INS_M2_MPYSIN, + HEX_INS_M2_MPYSIP, + HEX_INS_M2_MPYSU_UP, + HEX_INS_M2_MPYU_ACC_HH_S0, + HEX_INS_M2_MPYU_ACC_HH_S1, + HEX_INS_M2_MPYU_ACC_HL_S0, + HEX_INS_M2_MPYU_ACC_HL_S1, + HEX_INS_M2_MPYU_ACC_LH_S0, + HEX_INS_M2_MPYU_ACC_LH_S1, + HEX_INS_M2_MPYU_ACC_LL_S0, + HEX_INS_M2_MPYU_ACC_LL_S1, + HEX_INS_M2_MPYU_HH_S0, + HEX_INS_M2_MPYU_HH_S1, + HEX_INS_M2_MPYU_HL_S0, + HEX_INS_M2_MPYU_HL_S1, + HEX_INS_M2_MPYU_LH_S0, + HEX_INS_M2_MPYU_LH_S1, + HEX_INS_M2_MPYU_LL_S0, + HEX_INS_M2_MPYU_LL_S1, + HEX_INS_M2_MPYU_NAC_HH_S0, + HEX_INS_M2_MPYU_NAC_HH_S1, + HEX_INS_M2_MPYU_NAC_HL_S0, + HEX_INS_M2_MPYU_NAC_HL_S1, + HEX_INS_M2_MPYU_NAC_LH_S0, + HEX_INS_M2_MPYU_NAC_LH_S1, + HEX_INS_M2_MPYU_NAC_LL_S0, + HEX_INS_M2_MPYU_NAC_LL_S1, + HEX_INS_M2_MPYU_UP, + HEX_INS_M2_MPYUD_ACC_HH_S0, + HEX_INS_M2_MPYUD_ACC_HH_S1, + HEX_INS_M2_MPYUD_ACC_HL_S0, + HEX_INS_M2_MPYUD_ACC_HL_S1, + HEX_INS_M2_MPYUD_ACC_LH_S0, + HEX_INS_M2_MPYUD_ACC_LH_S1, + HEX_INS_M2_MPYUD_ACC_LL_S0, + HEX_INS_M2_MPYUD_ACC_LL_S1, + HEX_INS_M2_MPYUD_HH_S0, + HEX_INS_M2_MPYUD_HH_S1, + HEX_INS_M2_MPYUD_HL_S0, + HEX_INS_M2_MPYUD_HL_S1, + HEX_INS_M2_MPYUD_LH_S0, + HEX_INS_M2_MPYUD_LH_S1, + HEX_INS_M2_MPYUD_LL_S0, + HEX_INS_M2_MPYUD_LL_S1, + HEX_INS_M2_MPYUD_NAC_HH_S0, + HEX_INS_M2_MPYUD_NAC_HH_S1, + HEX_INS_M2_MPYUD_NAC_HL_S0, + HEX_INS_M2_MPYUD_NAC_HL_S1, + HEX_INS_M2_MPYUD_NAC_LH_S0, + HEX_INS_M2_MPYUD_NAC_LH_S1, + HEX_INS_M2_MPYUD_NAC_LL_S0, + HEX_INS_M2_MPYUD_NAC_LL_S1, + HEX_INS_M2_NACCI, + HEX_INS_M2_NACCII, + HEX_INS_M2_SUBACC, + HEX_INS_M2_VABSDIFFH, + HEX_INS_M2_VABSDIFFW, + HEX_INS_M2_VCMAC_S0_SAT_I, + HEX_INS_M2_VCMAC_S0_SAT_R, + HEX_INS_M2_VCMPY_S0_SAT_I, + HEX_INS_M2_VCMPY_S0_SAT_R, + HEX_INS_M2_VCMPY_S1_SAT_I, + HEX_INS_M2_VCMPY_S1_SAT_R, + HEX_INS_M2_VDMACS_S0, + HEX_INS_M2_VDMACS_S1, + HEX_INS_M2_VDMPYRS_S0, + HEX_INS_M2_VDMPYRS_S1, + HEX_INS_M2_VDMPYS_S0, + HEX_INS_M2_VDMPYS_S1, + HEX_INS_M2_VMAC2, + HEX_INS_M2_VMAC2ES, + HEX_INS_M2_VMAC2ES_S0, + HEX_INS_M2_VMAC2ES_S1, + HEX_INS_M2_VMAC2S_S0, + HEX_INS_M2_VMAC2S_S1, + HEX_INS_M2_VMAC2SU_S0, + HEX_INS_M2_VMAC2SU_S1, + HEX_INS_M2_VMPY2ES_S0, + HEX_INS_M2_VMPY2ES_S1, + HEX_INS_M2_VMPY2S_S0, + HEX_INS_M2_VMPY2S_S0PACK, + HEX_INS_M2_VMPY2S_S1, + HEX_INS_M2_VMPY2S_S1PACK, + HEX_INS_M2_VMPY2SU_S0, + HEX_INS_M2_VMPY2SU_S1, + HEX_INS_M2_VRADDH, + HEX_INS_M2_VRADDUH, + HEX_INS_M2_VRCMACI_S0, + HEX_INS_M2_VRCMACI_S0C, + HEX_INS_M2_VRCMACR_S0, + HEX_INS_M2_VRCMACR_S0C, + HEX_INS_M2_VRCMPYI_S0, + HEX_INS_M2_VRCMPYI_S0C, + HEX_INS_M2_VRCMPYR_S0, + HEX_INS_M2_VRCMPYR_S0C, + HEX_INS_M2_VRCMPYS_ACC_S1_H, + HEX_INS_M2_VRCMPYS_ACC_S1_L, + HEX_INS_M2_VRCMPYS_S1_H, + HEX_INS_M2_VRCMPYS_S1_L, + HEX_INS_M2_VRCMPYS_S1RP_H, + HEX_INS_M2_VRCMPYS_S1RP_L, + HEX_INS_M2_VRMAC_S0, + HEX_INS_M2_VRMPY_S0, + HEX_INS_M2_XOR_XACC, + HEX_INS_M4_AND_AND, + HEX_INS_M4_AND_ANDN, + HEX_INS_M4_AND_OR, + HEX_INS_M4_AND_XOR, + HEX_INS_M4_CMPYI_WH, + HEX_INS_M4_CMPYI_WHC, + HEX_INS_M4_CMPYR_WH, + HEX_INS_M4_CMPYR_WHC, + HEX_INS_M4_MAC_UP_S1_SAT, + HEX_INS_M4_MPYRI_ADDI, + HEX_INS_M4_MPYRI_ADDR, + HEX_INS_M4_MPYRI_ADDR_U2, + HEX_INS_M4_MPYRR_ADDI, + HEX_INS_M4_MPYRR_ADDR, + HEX_INS_M4_NAC_UP_S1_SAT, + HEX_INS_M4_OR_AND, + HEX_INS_M4_OR_ANDN, + HEX_INS_M4_OR_OR, + HEX_INS_M4_OR_XOR, + HEX_INS_M4_PMPYW, + HEX_INS_M4_PMPYW_ACC, + HEX_INS_M4_VPMPYH, + HEX_INS_M4_VPMPYH_ACC, + HEX_INS_M4_VRMPYEH_ACC_S0, + HEX_INS_M4_VRMPYEH_ACC_S1, + HEX_INS_M4_VRMPYEH_S0, + HEX_INS_M4_VRMPYEH_S1, + HEX_INS_M4_VRMPYOH_ACC_S0, + HEX_INS_M4_VRMPYOH_ACC_S1, + HEX_INS_M4_VRMPYOH_S0, + HEX_INS_M4_VRMPYOH_S1, + HEX_INS_M4_XOR_AND, + HEX_INS_M4_XOR_ANDN, + HEX_INS_M4_XOR_OR, + HEX_INS_M4_XOR_XACC, + HEX_INS_M5_VDMACBSU, + HEX_INS_M5_VDMPYBSU, + HEX_INS_M5_VMACBSU, + HEX_INS_M5_VMACBUU, + HEX_INS_M5_VMPYBSU, + HEX_INS_M5_VMPYBUU, + HEX_INS_M5_VRMACBSU, + HEX_INS_M5_VRMACBUU, + HEX_INS_M5_VRMPYBSU, + HEX_INS_M5_VRMPYBUU, + HEX_INS_M6_VABSDIFFB, + HEX_INS_M6_VABSDIFFUB, + HEX_INS_M7_DCMPYIW, + HEX_INS_M7_DCMPYIW_ACC, + HEX_INS_M7_DCMPYIWC, + HEX_INS_M7_DCMPYIWC_ACC, + HEX_INS_M7_DCMPYRW, + HEX_INS_M7_DCMPYRW_ACC, + HEX_INS_M7_DCMPYRWC, + HEX_INS_M7_DCMPYRWC_ACC, + HEX_INS_M7_WCMPYIW, + HEX_INS_M7_WCMPYIW_RND, + HEX_INS_M7_WCMPYIWC, + HEX_INS_M7_WCMPYIWC_RND, + HEX_INS_M7_WCMPYRW, + HEX_INS_M7_WCMPYRW_RND, + HEX_INS_M7_WCMPYRWC, + HEX_INS_M7_WCMPYRWC_RND, + HEX_INS_PS_LOADRBABS, + HEX_INS_PS_LOADRDABS, + HEX_INS_PS_LOADRHABS, + HEX_INS_PS_LOADRIABS, + HEX_INS_PS_LOADRUBABS, + HEX_INS_PS_LOADRUHABS, + HEX_INS_PS_STORERBABS, + HEX_INS_PS_STORERBNEWABS, + HEX_INS_PS_STORERDABS, + HEX_INS_PS_STORERFABS, + HEX_INS_PS_STORERHABS, + HEX_INS_PS_STORERHNEWABS, + HEX_INS_PS_STORERIABS, + HEX_INS_PS_STORERINEWABS, + HEX_INS_PS_TRAP1, + HEX_INS_R6_RELEASE_AT_VI, + HEX_INS_R6_RELEASE_ST_VI, + HEX_INS_S2_ADDASL_RRRI, + HEX_INS_S2_ALLOCFRAME, + HEX_INS_S2_ASL_I_P, + HEX_INS_S2_ASL_I_P_ACC, + HEX_INS_S2_ASL_I_P_AND, + HEX_INS_S2_ASL_I_P_NAC, + HEX_INS_S2_ASL_I_P_OR, + HEX_INS_S2_ASL_I_P_XACC, + HEX_INS_S2_ASL_I_R, + HEX_INS_S2_ASL_I_R_ACC, + HEX_INS_S2_ASL_I_R_AND, + HEX_INS_S2_ASL_I_R_NAC, + HEX_INS_S2_ASL_I_R_OR, + HEX_INS_S2_ASL_I_R_SAT, + HEX_INS_S2_ASL_I_R_XACC, + HEX_INS_S2_ASL_I_VH, + HEX_INS_S2_ASL_I_VW, + HEX_INS_S2_ASL_R_P, + HEX_INS_S2_ASL_R_P_ACC, + HEX_INS_S2_ASL_R_P_AND, + HEX_INS_S2_ASL_R_P_NAC, + HEX_INS_S2_ASL_R_P_OR, + HEX_INS_S2_ASL_R_P_XOR, + HEX_INS_S2_ASL_R_R, + HEX_INS_S2_ASL_R_R_ACC, + HEX_INS_S2_ASL_R_R_AND, + HEX_INS_S2_ASL_R_R_NAC, + HEX_INS_S2_ASL_R_R_OR, + HEX_INS_S2_ASL_R_R_SAT, + HEX_INS_S2_ASL_R_VH, + HEX_INS_S2_ASL_R_VW, + HEX_INS_S2_ASR_I_P, + HEX_INS_S2_ASR_I_P_ACC, + HEX_INS_S2_ASR_I_P_AND, + HEX_INS_S2_ASR_I_P_NAC, + HEX_INS_S2_ASR_I_P_OR, + HEX_INS_S2_ASR_I_P_RND, + HEX_INS_S2_ASR_I_R, + HEX_INS_S2_ASR_I_R_ACC, + HEX_INS_S2_ASR_I_R_AND, + HEX_INS_S2_ASR_I_R_NAC, + HEX_INS_S2_ASR_I_R_OR, + HEX_INS_S2_ASR_I_R_RND, + HEX_INS_S2_ASR_I_SVW_TRUN, + HEX_INS_S2_ASR_I_VH, + HEX_INS_S2_ASR_I_VW, + HEX_INS_S2_ASR_R_P, + HEX_INS_S2_ASR_R_P_ACC, + HEX_INS_S2_ASR_R_P_AND, + HEX_INS_S2_ASR_R_P_NAC, + HEX_INS_S2_ASR_R_P_OR, + HEX_INS_S2_ASR_R_P_XOR, + HEX_INS_S2_ASR_R_R, + HEX_INS_S2_ASR_R_R_ACC, + HEX_INS_S2_ASR_R_R_AND, + HEX_INS_S2_ASR_R_R_NAC, + HEX_INS_S2_ASR_R_R_OR, + HEX_INS_S2_ASR_R_R_SAT, + HEX_INS_S2_ASR_R_SVW_TRUN, + HEX_INS_S2_ASR_R_VH, + HEX_INS_S2_ASR_R_VW, + HEX_INS_S2_BREV, + HEX_INS_S2_BREVP, + HEX_INS_S2_CABACDECBIN, + HEX_INS_S2_CL0, + HEX_INS_S2_CL0P, + HEX_INS_S2_CL1, + HEX_INS_S2_CL1P, + HEX_INS_S2_CLB, + HEX_INS_S2_CLBNORM, + HEX_INS_S2_CLBP, + HEX_INS_S2_CLRBIT_I, + HEX_INS_S2_CLRBIT_R, + HEX_INS_S2_CT0, + HEX_INS_S2_CT0P, + HEX_INS_S2_CT1, + HEX_INS_S2_CT1P, + HEX_INS_S2_DEINTERLEAVE, + HEX_INS_S2_EXTRACTU, + HEX_INS_S2_EXTRACTU_RP, + HEX_INS_S2_EXTRACTUP, + HEX_INS_S2_EXTRACTUP_RP, + HEX_INS_S2_INSERT, + HEX_INS_S2_INSERT_RP, + HEX_INS_S2_INSERTP, + HEX_INS_S2_INSERTP_RP, + HEX_INS_S2_INTERLEAVE, + HEX_INS_S2_LFSP, + HEX_INS_S2_LSL_R_P, + HEX_INS_S2_LSL_R_P_ACC, + HEX_INS_S2_LSL_R_P_AND, + HEX_INS_S2_LSL_R_P_NAC, + HEX_INS_S2_LSL_R_P_OR, + HEX_INS_S2_LSL_R_P_XOR, + HEX_INS_S2_LSL_R_R, + HEX_INS_S2_LSL_R_R_ACC, + HEX_INS_S2_LSL_R_R_AND, + HEX_INS_S2_LSL_R_R_NAC, + HEX_INS_S2_LSL_R_R_OR, + HEX_INS_S2_LSL_R_VH, + HEX_INS_S2_LSL_R_VW, + HEX_INS_S2_LSR_I_P, + HEX_INS_S2_LSR_I_P_ACC, + HEX_INS_S2_LSR_I_P_AND, + HEX_INS_S2_LSR_I_P_NAC, + HEX_INS_S2_LSR_I_P_OR, + HEX_INS_S2_LSR_I_P_XACC, + HEX_INS_S2_LSR_I_R, + HEX_INS_S2_LSR_I_R_ACC, + HEX_INS_S2_LSR_I_R_AND, + HEX_INS_S2_LSR_I_R_NAC, + HEX_INS_S2_LSR_I_R_OR, + HEX_INS_S2_LSR_I_R_XACC, + HEX_INS_S2_LSR_I_VH, + HEX_INS_S2_LSR_I_VW, + HEX_INS_S2_LSR_R_P, + HEX_INS_S2_LSR_R_P_ACC, + HEX_INS_S2_LSR_R_P_AND, + HEX_INS_S2_LSR_R_P_NAC, + HEX_INS_S2_LSR_R_P_OR, + HEX_INS_S2_LSR_R_P_XOR, + HEX_INS_S2_LSR_R_R, + HEX_INS_S2_LSR_R_R_ACC, + HEX_INS_S2_LSR_R_R_AND, + HEX_INS_S2_LSR_R_R_NAC, + HEX_INS_S2_LSR_R_R_OR, + HEX_INS_S2_LSR_R_VH, + HEX_INS_S2_LSR_R_VW, + HEX_INS_S2_MASK, + HEX_INS_S2_PACKHL, + HEX_INS_S2_PARITYP, + HEX_INS_S2_PSTORERBF_IO, + HEX_INS_S2_PSTORERBF_PI, + HEX_INS_S2_PSTORERBFNEW_PI, + HEX_INS_S2_PSTORERBNEWF_IO, + HEX_INS_S2_PSTORERBNEWF_PI, + HEX_INS_S2_PSTORERBNEWFNEW_PI, + HEX_INS_S2_PSTORERBNEWT_IO, + HEX_INS_S2_PSTORERBNEWT_PI, + HEX_INS_S2_PSTORERBNEWTNEW_PI, + HEX_INS_S2_PSTORERBT_IO, + HEX_INS_S2_PSTORERBT_PI, + HEX_INS_S2_PSTORERBTNEW_PI, + HEX_INS_S2_PSTORERDF_IO, + HEX_INS_S2_PSTORERDF_PI, + HEX_INS_S2_PSTORERDFNEW_PI, + HEX_INS_S2_PSTORERDT_IO, + HEX_INS_S2_PSTORERDT_PI, + HEX_INS_S2_PSTORERDTNEW_PI, + HEX_INS_S2_PSTORERFF_IO, + HEX_INS_S2_PSTORERFF_PI, + HEX_INS_S2_PSTORERFFNEW_PI, + HEX_INS_S2_PSTORERFT_IO, + HEX_INS_S2_PSTORERFT_PI, + HEX_INS_S2_PSTORERFTNEW_PI, + HEX_INS_S2_PSTORERHF_IO, + HEX_INS_S2_PSTORERHF_PI, + HEX_INS_S2_PSTORERHFNEW_PI, + HEX_INS_S2_PSTORERHNEWF_IO, + HEX_INS_S2_PSTORERHNEWF_PI, + HEX_INS_S2_PSTORERHNEWFNEW_PI, + HEX_INS_S2_PSTORERHNEWT_IO, + HEX_INS_S2_PSTORERHNEWT_PI, + HEX_INS_S2_PSTORERHNEWTNEW_PI, + HEX_INS_S2_PSTORERHT_IO, + HEX_INS_S2_PSTORERHT_PI, + HEX_INS_S2_PSTORERHTNEW_PI, + HEX_INS_S2_PSTORERIF_IO, + HEX_INS_S2_PSTORERIF_PI, + HEX_INS_S2_PSTORERIFNEW_PI, + HEX_INS_S2_PSTORERINEWF_IO, + HEX_INS_S2_PSTORERINEWF_PI, + HEX_INS_S2_PSTORERINEWFNEW_PI, + HEX_INS_S2_PSTORERINEWT_IO, + HEX_INS_S2_PSTORERINEWT_PI, + HEX_INS_S2_PSTORERINEWTNEW_PI, + HEX_INS_S2_PSTORERIT_IO, + HEX_INS_S2_PSTORERIT_PI, + HEX_INS_S2_PSTORERITNEW_PI, + HEX_INS_S2_SETBIT_I, + HEX_INS_S2_SETBIT_R, + HEX_INS_S2_SHUFFEB, + HEX_INS_S2_SHUFFEH, + HEX_INS_S2_SHUFFOB, + HEX_INS_S2_SHUFFOH, + HEX_INS_S2_STORERB_IO, + HEX_INS_S2_STORERB_PBR, + HEX_INS_S2_STORERB_PCI, + HEX_INS_S2_STORERB_PCR, + HEX_INS_S2_STORERB_PI, + HEX_INS_S2_STORERB_PR, + HEX_INS_S2_STORERBGP, + HEX_INS_S2_STORERBNEW_IO, + HEX_INS_S2_STORERBNEW_PBR, + HEX_INS_S2_STORERBNEW_PCI, + HEX_INS_S2_STORERBNEW_PCR, + HEX_INS_S2_STORERBNEW_PI, + HEX_INS_S2_STORERBNEW_PR, + HEX_INS_S2_STORERBNEWGP, + HEX_INS_S2_STORERD_IO, + HEX_INS_S2_STORERD_PBR, + HEX_INS_S2_STORERD_PCI, + HEX_INS_S2_STORERD_PCR, + HEX_INS_S2_STORERD_PI, + HEX_INS_S2_STORERD_PR, + HEX_INS_S2_STORERDGP, + HEX_INS_S2_STORERF_IO, + HEX_INS_S2_STORERF_PBR, + HEX_INS_S2_STORERF_PCI, + HEX_INS_S2_STORERF_PCR, + HEX_INS_S2_STORERF_PI, + HEX_INS_S2_STORERF_PR, + HEX_INS_S2_STORERFGP, + HEX_INS_S2_STORERH_IO, + HEX_INS_S2_STORERH_PBR, + HEX_INS_S2_STORERH_PCI, + HEX_INS_S2_STORERH_PCR, + HEX_INS_S2_STORERH_PI, + HEX_INS_S2_STORERH_PR, + HEX_INS_S2_STORERHGP, + HEX_INS_S2_STORERHNEW_IO, + HEX_INS_S2_STORERHNEW_PBR, + HEX_INS_S2_STORERHNEW_PCI, + HEX_INS_S2_STORERHNEW_PCR, + HEX_INS_S2_STORERHNEW_PI, + HEX_INS_S2_STORERHNEW_PR, + HEX_INS_S2_STORERHNEWGP, + HEX_INS_S2_STORERI_IO, + HEX_INS_S2_STORERI_PBR, + HEX_INS_S2_STORERI_PCI, + HEX_INS_S2_STORERI_PCR, + HEX_INS_S2_STORERI_PI, + HEX_INS_S2_STORERI_PR, + HEX_INS_S2_STORERIGP, + HEX_INS_S2_STORERINEW_IO, + HEX_INS_S2_STORERINEW_PBR, + HEX_INS_S2_STORERINEW_PCI, + HEX_INS_S2_STORERINEW_PCR, + HEX_INS_S2_STORERINEW_PI, + HEX_INS_S2_STORERINEW_PR, + HEX_INS_S2_STORERINEWGP, + HEX_INS_S2_STOREW_LOCKED, + HEX_INS_S2_STOREW_RL_AT_VI, + HEX_INS_S2_STOREW_RL_ST_VI, + HEX_INS_S2_SVSATHB, + HEX_INS_S2_SVSATHUB, + HEX_INS_S2_TABLEIDXB, + HEX_INS_S2_TABLEIDXD, + HEX_INS_S2_TABLEIDXH, + HEX_INS_S2_TABLEIDXW, + HEX_INS_S2_TOGGLEBIT_I, + HEX_INS_S2_TOGGLEBIT_R, + HEX_INS_S2_TSTBIT_I, + HEX_INS_S2_TSTBIT_R, + HEX_INS_S2_VALIGNIB, + HEX_INS_S2_VALIGNRB, + HEX_INS_S2_VCNEGH, + HEX_INS_S2_VCROTATE, + HEX_INS_S2_VRCNEGH, + HEX_INS_S2_VRNDPACKWH, + HEX_INS_S2_VRNDPACKWHS, + HEX_INS_S2_VSATHB, + HEX_INS_S2_VSATHB_NOPACK, + HEX_INS_S2_VSATHUB, + HEX_INS_S2_VSATHUB_NOPACK, + HEX_INS_S2_VSATWH, + HEX_INS_S2_VSATWH_NOPACK, + HEX_INS_S2_VSATWUH, + HEX_INS_S2_VSATWUH_NOPACK, + HEX_INS_S2_VSPLATRB, + HEX_INS_S2_VSPLATRH, + HEX_INS_S2_VSPLICEIB, + HEX_INS_S2_VSPLICERB, + HEX_INS_S2_VSXTBH, + HEX_INS_S2_VSXTHW, + HEX_INS_S2_VTRUNEHB, + HEX_INS_S2_VTRUNEWH, + HEX_INS_S2_VTRUNOHB, + HEX_INS_S2_VTRUNOWH, + HEX_INS_S2_VZXTBH, + HEX_INS_S2_VZXTHW, + HEX_INS_S4_ADDADDI, + HEX_INS_S4_ADDI_ASL_RI, + HEX_INS_S4_ADDI_LSR_RI, + HEX_INS_S4_ANDI_ASL_RI, + HEX_INS_S4_ANDI_LSR_RI, + HEX_INS_S4_CLBADDI, + HEX_INS_S4_CLBPADDI, + HEX_INS_S4_CLBPNORM, + HEX_INS_S4_EXTRACT, + HEX_INS_S4_EXTRACT_RP, + HEX_INS_S4_EXTRACTP, + HEX_INS_S4_EXTRACTP_RP, + HEX_INS_S4_LSLI, + HEX_INS_S4_NTSTBIT_I, + HEX_INS_S4_NTSTBIT_R, + HEX_INS_S4_OR_ANDI, + HEX_INS_S4_OR_ANDIX, + HEX_INS_S4_OR_ORI, + HEX_INS_S4_ORI_ASL_RI, + HEX_INS_S4_ORI_LSR_RI, + HEX_INS_S4_PARITY, + HEX_INS_S4_PSTORERBF_ABS, + HEX_INS_S4_PSTORERBF_RR, + HEX_INS_S4_PSTORERBFNEW_ABS, + HEX_INS_S4_PSTORERBFNEW_IO, + HEX_INS_S4_PSTORERBFNEW_RR, + HEX_INS_S4_PSTORERBNEWF_ABS, + HEX_INS_S4_PSTORERBNEWF_RR, + HEX_INS_S4_PSTORERBNEWFNEW_ABS, + HEX_INS_S4_PSTORERBNEWFNEW_IO, + HEX_INS_S4_PSTORERBNEWFNEW_RR, + HEX_INS_S4_PSTORERBNEWT_ABS, + HEX_INS_S4_PSTORERBNEWT_RR, + HEX_INS_S4_PSTORERBNEWTNEW_ABS, + HEX_INS_S4_PSTORERBNEWTNEW_IO, + HEX_INS_S4_PSTORERBNEWTNEW_RR, + HEX_INS_S4_PSTORERBT_ABS, + HEX_INS_S4_PSTORERBT_RR, + HEX_INS_S4_PSTORERBTNEW_ABS, + HEX_INS_S4_PSTORERBTNEW_IO, + HEX_INS_S4_PSTORERBTNEW_RR, + HEX_INS_S4_PSTORERDF_ABS, + HEX_INS_S4_PSTORERDF_RR, + HEX_INS_S4_PSTORERDFNEW_ABS, + HEX_INS_S4_PSTORERDFNEW_IO, + HEX_INS_S4_PSTORERDFNEW_RR, + HEX_INS_S4_PSTORERDT_ABS, + HEX_INS_S4_PSTORERDT_RR, + HEX_INS_S4_PSTORERDTNEW_ABS, + HEX_INS_S4_PSTORERDTNEW_IO, + HEX_INS_S4_PSTORERDTNEW_RR, + HEX_INS_S4_PSTORERFF_ABS, + HEX_INS_S4_PSTORERFF_RR, + HEX_INS_S4_PSTORERFFNEW_ABS, + HEX_INS_S4_PSTORERFFNEW_IO, + HEX_INS_S4_PSTORERFFNEW_RR, + HEX_INS_S4_PSTORERFT_ABS, + HEX_INS_S4_PSTORERFT_RR, + HEX_INS_S4_PSTORERFTNEW_ABS, + HEX_INS_S4_PSTORERFTNEW_IO, + HEX_INS_S4_PSTORERFTNEW_RR, + HEX_INS_S4_PSTORERHF_ABS, + HEX_INS_S4_PSTORERHF_RR, + HEX_INS_S4_PSTORERHFNEW_ABS, + HEX_INS_S4_PSTORERHFNEW_IO, + HEX_INS_S4_PSTORERHFNEW_RR, + HEX_INS_S4_PSTORERHNEWF_ABS, + HEX_INS_S4_PSTORERHNEWF_RR, + HEX_INS_S4_PSTORERHNEWFNEW_ABS, + HEX_INS_S4_PSTORERHNEWFNEW_IO, + HEX_INS_S4_PSTORERHNEWFNEW_RR, + HEX_INS_S4_PSTORERHNEWT_ABS, + HEX_INS_S4_PSTORERHNEWT_RR, + HEX_INS_S4_PSTORERHNEWTNEW_ABS, + HEX_INS_S4_PSTORERHNEWTNEW_IO, + HEX_INS_S4_PSTORERHNEWTNEW_RR, + HEX_INS_S4_PSTORERHT_ABS, + HEX_INS_S4_PSTORERHT_RR, + HEX_INS_S4_PSTORERHTNEW_ABS, + HEX_INS_S4_PSTORERHTNEW_IO, + HEX_INS_S4_PSTORERHTNEW_RR, + HEX_INS_S4_PSTORERIF_ABS, + HEX_INS_S4_PSTORERIF_RR, + HEX_INS_S4_PSTORERIFNEW_ABS, + HEX_INS_S4_PSTORERIFNEW_IO, + HEX_INS_S4_PSTORERIFNEW_RR, + HEX_INS_S4_PSTORERINEWF_ABS, + HEX_INS_S4_PSTORERINEWF_RR, + HEX_INS_S4_PSTORERINEWFNEW_ABS, + HEX_INS_S4_PSTORERINEWFNEW_IO, + HEX_INS_S4_PSTORERINEWFNEW_RR, + HEX_INS_S4_PSTORERINEWT_ABS, + HEX_INS_S4_PSTORERINEWT_RR, + HEX_INS_S4_PSTORERINEWTNEW_ABS, + HEX_INS_S4_PSTORERINEWTNEW_IO, + HEX_INS_S4_PSTORERINEWTNEW_RR, + HEX_INS_S4_PSTORERIT_ABS, + HEX_INS_S4_PSTORERIT_RR, + HEX_INS_S4_PSTORERITNEW_ABS, + HEX_INS_S4_PSTORERITNEW_IO, + HEX_INS_S4_PSTORERITNEW_RR, + HEX_INS_S4_STORED_LOCKED, + HEX_INS_S4_STORED_RL_AT_VI, + HEX_INS_S4_STORED_RL_ST_VI, + HEX_INS_S4_STOREIRB_IO, + HEX_INS_S4_STOREIRBF_IO, + HEX_INS_S4_STOREIRBFNEW_IO, + HEX_INS_S4_STOREIRBT_IO, + HEX_INS_S4_STOREIRBTNEW_IO, + HEX_INS_S4_STOREIRH_IO, + HEX_INS_S4_STOREIRHF_IO, + HEX_INS_S4_STOREIRHFNEW_IO, + HEX_INS_S4_STOREIRHT_IO, + HEX_INS_S4_STOREIRHTNEW_IO, + HEX_INS_S4_STOREIRI_IO, + HEX_INS_S4_STOREIRIF_IO, + HEX_INS_S4_STOREIRIFNEW_IO, + HEX_INS_S4_STOREIRIT_IO, + HEX_INS_S4_STOREIRITNEW_IO, + HEX_INS_S4_STORERB_AP, + HEX_INS_S4_STORERB_RR, + HEX_INS_S4_STORERB_UR, + HEX_INS_S4_STORERBNEW_AP, + HEX_INS_S4_STORERBNEW_RR, + HEX_INS_S4_STORERBNEW_UR, + HEX_INS_S4_STORERD_AP, + HEX_INS_S4_STORERD_RR, + HEX_INS_S4_STORERD_UR, + HEX_INS_S4_STORERF_AP, + HEX_INS_S4_STORERF_RR, + HEX_INS_S4_STORERF_UR, + HEX_INS_S4_STORERH_AP, + HEX_INS_S4_STORERH_RR, + HEX_INS_S4_STORERH_UR, + HEX_INS_S4_STORERHNEW_AP, + HEX_INS_S4_STORERHNEW_RR, + HEX_INS_S4_STORERHNEW_UR, + HEX_INS_S4_STORERI_AP, + HEX_INS_S4_STORERI_RR, + HEX_INS_S4_STORERI_UR, + HEX_INS_S4_STORERINEW_AP, + HEX_INS_S4_STORERINEW_RR, + HEX_INS_S4_STORERINEW_UR, + HEX_INS_S4_SUBADDI, + HEX_INS_S4_SUBI_ASL_RI, + HEX_INS_S4_SUBI_LSR_RI, + HEX_INS_S4_VRCROTATE, + HEX_INS_S4_VRCROTATE_ACC, + HEX_INS_S4_VXADDSUBH, + HEX_INS_S4_VXADDSUBHR, + HEX_INS_S4_VXADDSUBW, + HEX_INS_S4_VXSUBADDH, + HEX_INS_S4_VXSUBADDHR, + HEX_INS_S4_VXSUBADDW, + HEX_INS_S5_ASRHUB_RND_SAT, + HEX_INS_S5_ASRHUB_SAT, + HEX_INS_S5_POPCOUNTP, + HEX_INS_S5_VASRHRND, + HEX_INS_S6_ROL_I_P, + HEX_INS_S6_ROL_I_P_ACC, + HEX_INS_S6_ROL_I_P_AND, + HEX_INS_S6_ROL_I_P_NAC, + HEX_INS_S6_ROL_I_P_OR, + HEX_INS_S6_ROL_I_P_XACC, + HEX_INS_S6_ROL_I_R, + HEX_INS_S6_ROL_I_R_ACC, + HEX_INS_S6_ROL_I_R_AND, + HEX_INS_S6_ROL_I_R_NAC, + HEX_INS_S6_ROL_I_R_OR, + HEX_INS_S6_ROL_I_R_XACC, + HEX_INS_S6_VSPLATRBP, + HEX_INS_S6_VTRUNEHB_PPP, + HEX_INS_S6_VTRUNOHB_PPP, + HEX_INS_V6_EXTRACTW, + HEX_INS_V6_LVSPLATB, + HEX_INS_V6_LVSPLATH, + HEX_INS_V6_LVSPLATW, + HEX_INS_V6_PRED_AND, + HEX_INS_V6_PRED_AND_N, + HEX_INS_V6_PRED_NOT, + HEX_INS_V6_PRED_OR, + HEX_INS_V6_PRED_OR_N, + HEX_INS_V6_PRED_SCALAR2, + HEX_INS_V6_PRED_SCALAR2V2, + HEX_INS_V6_PRED_XOR, + HEX_INS_V6_SHUFFEQH, + HEX_INS_V6_SHUFFEQW, + HEX_INS_V6_V6MPYHUBS10, + HEX_INS_V6_V6MPYHUBS10_VXX, + HEX_INS_V6_V6MPYVUBS10, + HEX_INS_V6_V6MPYVUBS10_VXX, + HEX_INS_V6_VL32UB_AI, + HEX_INS_V6_VL32UB_PI, + HEX_INS_V6_VL32UB_PPU, + HEX_INS_V6_VL32B_AI, + HEX_INS_V6_VL32B_CUR_AI, + HEX_INS_V6_VL32B_CUR_NPRED_AI, + HEX_INS_V6_VL32B_CUR_NPRED_PI, + HEX_INS_V6_VL32B_CUR_NPRED_PPU, + HEX_INS_V6_VL32B_CUR_PI, + HEX_INS_V6_VL32B_CUR_PPU, + HEX_INS_V6_VL32B_CUR_PRED_AI, + HEX_INS_V6_VL32B_CUR_PRED_PI, + HEX_INS_V6_VL32B_CUR_PRED_PPU, + HEX_INS_V6_VL32B_NPRED_AI, + HEX_INS_V6_VL32B_NPRED_PI, + HEX_INS_V6_VL32B_NPRED_PPU, + HEX_INS_V6_VL32B_NT_AI, + HEX_INS_V6_VL32B_NT_CUR_AI, + HEX_INS_V6_VL32B_NT_CUR_NPRED_AI, + HEX_INS_V6_VL32B_NT_CUR_NPRED_PI, + HEX_INS_V6_VL32B_NT_CUR_NPRED_PPU, + HEX_INS_V6_VL32B_NT_CUR_PI, + HEX_INS_V6_VL32B_NT_CUR_PPU, + HEX_INS_V6_VL32B_NT_CUR_PRED_AI, + HEX_INS_V6_VL32B_NT_CUR_PRED_PI, + HEX_INS_V6_VL32B_NT_CUR_PRED_PPU, + HEX_INS_V6_VL32B_NT_NPRED_AI, + HEX_INS_V6_VL32B_NT_NPRED_PI, + HEX_INS_V6_VL32B_NT_NPRED_PPU, + HEX_INS_V6_VL32B_NT_PI, + HEX_INS_V6_VL32B_NT_PPU, + HEX_INS_V6_VL32B_NT_PRED_AI, + HEX_INS_V6_VL32B_NT_PRED_PI, + HEX_INS_V6_VL32B_NT_PRED_PPU, + HEX_INS_V6_VL32B_NT_TMP_AI, + HEX_INS_V6_VL32B_NT_TMP_NPRED_AI, + HEX_INS_V6_VL32B_NT_TMP_NPRED_PI, + HEX_INS_V6_VL32B_NT_TMP_NPRED_PPU, + HEX_INS_V6_VL32B_NT_TMP_PI, + HEX_INS_V6_VL32B_NT_TMP_PPU, + HEX_INS_V6_VL32B_NT_TMP_PRED_AI, + HEX_INS_V6_VL32B_NT_TMP_PRED_PI, + HEX_INS_V6_VL32B_NT_TMP_PRED_PPU, + HEX_INS_V6_VL32B_PI, + HEX_INS_V6_VL32B_PPU, + HEX_INS_V6_VL32B_PRED_AI, + HEX_INS_V6_VL32B_PRED_PI, + HEX_INS_V6_VL32B_PRED_PPU, + HEX_INS_V6_VL32B_TMP_AI, + HEX_INS_V6_VL32B_TMP_NPRED_AI, + HEX_INS_V6_VL32B_TMP_NPRED_PI, + HEX_INS_V6_VL32B_TMP_NPRED_PPU, + HEX_INS_V6_VL32B_TMP_PI, + HEX_INS_V6_VL32B_TMP_PPU, + HEX_INS_V6_VL32B_TMP_PRED_AI, + HEX_INS_V6_VL32B_TMP_PRED_PI, + HEX_INS_V6_VL32B_TMP_PRED_PPU, + HEX_INS_V6_VS32UB_AI, + HEX_INS_V6_VS32UB_NPRED_AI, + HEX_INS_V6_VS32UB_NPRED_PI, + HEX_INS_V6_VS32UB_NPRED_PPU, + HEX_INS_V6_VS32UB_PI, + HEX_INS_V6_VS32UB_PPU, + HEX_INS_V6_VS32UB_PRED_AI, + HEX_INS_V6_VS32UB_PRED_PI, + HEX_INS_V6_VS32UB_PRED_PPU, + HEX_INS_V6_VS32B_AI, + HEX_INS_V6_VS32B_NEW_AI, + HEX_INS_V6_VS32B_NEW_NPRED_AI, + HEX_INS_V6_VS32B_NEW_NPRED_PI, + HEX_INS_V6_VS32B_NEW_NPRED_PPU, + HEX_INS_V6_VS32B_NEW_PI, + HEX_INS_V6_VS32B_NEW_PPU, + HEX_INS_V6_VS32B_NEW_PRED_AI, + HEX_INS_V6_VS32B_NEW_PRED_PI, + HEX_INS_V6_VS32B_NEW_PRED_PPU, + HEX_INS_V6_VS32B_NPRED_AI, + HEX_INS_V6_VS32B_NPRED_PI, + HEX_INS_V6_VS32B_NPRED_PPU, + HEX_INS_V6_VS32B_NQPRED_AI, + HEX_INS_V6_VS32B_NQPRED_PI, + HEX_INS_V6_VS32B_NQPRED_PPU, + HEX_INS_V6_VS32B_NT_AI, + HEX_INS_V6_VS32B_NT_NEW_AI, + HEX_INS_V6_VS32B_NT_NEW_NPRED_AI, + HEX_INS_V6_VS32B_NT_NEW_NPRED_PI, + HEX_INS_V6_VS32B_NT_NEW_NPRED_PPU, + HEX_INS_V6_VS32B_NT_NEW_PI, + HEX_INS_V6_VS32B_NT_NEW_PPU, + HEX_INS_V6_VS32B_NT_NEW_PRED_AI, + HEX_INS_V6_VS32B_NT_NEW_PRED_PI, + HEX_INS_V6_VS32B_NT_NEW_PRED_PPU, + HEX_INS_V6_VS32B_NT_NPRED_AI, + HEX_INS_V6_VS32B_NT_NPRED_PI, + HEX_INS_V6_VS32B_NT_NPRED_PPU, + HEX_INS_V6_VS32B_NT_NQPRED_AI, + HEX_INS_V6_VS32B_NT_NQPRED_PI, + HEX_INS_V6_VS32B_NT_NQPRED_PPU, + HEX_INS_V6_VS32B_NT_PI, + HEX_INS_V6_VS32B_NT_PPU, + HEX_INS_V6_VS32B_NT_PRED_AI, + HEX_INS_V6_VS32B_NT_PRED_PI, + HEX_INS_V6_VS32B_NT_PRED_PPU, + HEX_INS_V6_VS32B_NT_QPRED_AI, + HEX_INS_V6_VS32B_NT_QPRED_PI, + HEX_INS_V6_VS32B_NT_QPRED_PPU, + HEX_INS_V6_VS32B_PI, + HEX_INS_V6_VS32B_PPU, + HEX_INS_V6_VS32B_PRED_AI, + HEX_INS_V6_VS32B_PRED_PI, + HEX_INS_V6_VS32B_PRED_PPU, + HEX_INS_V6_VS32B_QPRED_AI, + HEX_INS_V6_VS32B_QPRED_PI, + HEX_INS_V6_VS32B_QPRED_PPU, + HEX_INS_V6_VS32B_SRLS_AI, + HEX_INS_V6_VS32B_SRLS_PI, + HEX_INS_V6_VS32B_SRLS_PPU, + HEX_INS_V6_VABSB, + HEX_INS_V6_VABSB_SAT, + HEX_INS_V6_VABSDIFFH, + HEX_INS_V6_VABSDIFFUB, + HEX_INS_V6_VABSDIFFUH, + HEX_INS_V6_VABSDIFFW, + HEX_INS_V6_VABSH, + HEX_INS_V6_VABSH_SAT, + HEX_INS_V6_VABSW, + HEX_INS_V6_VABSW_SAT, + HEX_INS_V6_VADDB, + HEX_INS_V6_VADDB_DV, + HEX_INS_V6_VADDBNQ, + HEX_INS_V6_VADDBQ, + HEX_INS_V6_VADDBSAT, + HEX_INS_V6_VADDBSAT_DV, + HEX_INS_V6_VADDCARRY, + HEX_INS_V6_VADDCARRYO, + HEX_INS_V6_VADDCARRYSAT, + HEX_INS_V6_VADDCLBH, + HEX_INS_V6_VADDCLBW, + HEX_INS_V6_VADDH, + HEX_INS_V6_VADDH_DV, + HEX_INS_V6_VADDHNQ, + HEX_INS_V6_VADDHQ, + HEX_INS_V6_VADDHSAT, + HEX_INS_V6_VADDHSAT_DV, + HEX_INS_V6_VADDHW, + HEX_INS_V6_VADDHW_ACC, + HEX_INS_V6_VADDUBH, + HEX_INS_V6_VADDUBH_ACC, + HEX_INS_V6_VADDUBSAT, + HEX_INS_V6_VADDUBSAT_DV, + HEX_INS_V6_VADDUBUBB_SAT, + HEX_INS_V6_VADDUHSAT, + HEX_INS_V6_VADDUHSAT_DV, + HEX_INS_V6_VADDUHW, + HEX_INS_V6_VADDUHW_ACC, + HEX_INS_V6_VADDUWSAT, + HEX_INS_V6_VADDUWSAT_DV, + HEX_INS_V6_VADDW, + HEX_INS_V6_VADDW_DV, + HEX_INS_V6_VADDWNQ, + HEX_INS_V6_VADDWQ, + HEX_INS_V6_VADDWSAT, + HEX_INS_V6_VADDWSAT_DV, + HEX_INS_V6_VALIGNB, + HEX_INS_V6_VALIGNBI, + HEX_INS_V6_VAND, + HEX_INS_V6_VANDNQRT, + HEX_INS_V6_VANDNQRT_ACC, + HEX_INS_V6_VANDQRT, + HEX_INS_V6_VANDQRT_ACC, + HEX_INS_V6_VANDVNQV, + HEX_INS_V6_VANDVQV, + HEX_INS_V6_VANDVRT, + HEX_INS_V6_VANDVRT_ACC, + HEX_INS_V6_VASLH, + HEX_INS_V6_VASLH_ACC, + HEX_INS_V6_VASLHV, + HEX_INS_V6_VASLW, + HEX_INS_V6_VASLW_ACC, + HEX_INS_V6_VASLWV, + HEX_INS_V6_VASR_INTO, + HEX_INS_V6_VASRH, + HEX_INS_V6_VASRH_ACC, + HEX_INS_V6_VASRHBRNDSAT, + HEX_INS_V6_VASRHBSAT, + HEX_INS_V6_VASRHUBRNDSAT, + HEX_INS_V6_VASRHUBSAT, + HEX_INS_V6_VASRHV, + HEX_INS_V6_VASRUHUBRNDSAT, + HEX_INS_V6_VASRUHUBSAT, + HEX_INS_V6_VASRUWUHRNDSAT, + HEX_INS_V6_VASRUWUHSAT, + HEX_INS_V6_VASRW, + HEX_INS_V6_VASRW_ACC, + HEX_INS_V6_VASRWH, + HEX_INS_V6_VASRWHRNDSAT, + HEX_INS_V6_VASRWHSAT, + HEX_INS_V6_VASRWUHRNDSAT, + HEX_INS_V6_VASRWUHSAT, + HEX_INS_V6_VASRWV, + HEX_INS_V6_VASSIGN, + HEX_INS_V6_VAVGB, + HEX_INS_V6_VAVGBRND, + HEX_INS_V6_VAVGH, + HEX_INS_V6_VAVGHRND, + HEX_INS_V6_VAVGUB, + HEX_INS_V6_VAVGUBRND, + HEX_INS_V6_VAVGUH, + HEX_INS_V6_VAVGUHRND, + HEX_INS_V6_VAVGUW, + HEX_INS_V6_VAVGUWRND, + HEX_INS_V6_VAVGW, + HEX_INS_V6_VAVGWRND, + HEX_INS_V6_VCCOMBINE, + HEX_INS_V6_VCL0H, + HEX_INS_V6_VCL0W, + HEX_INS_V6_VCMOV, + HEX_INS_V6_VCOMBINE, + HEX_INS_V6_VDEAL, + HEX_INS_V6_VDEALB, + HEX_INS_V6_VDEALB4W, + HEX_INS_V6_VDEALH, + HEX_INS_V6_VDEALVDD, + HEX_INS_V6_VDELTA, + HEX_INS_V6_VDMPYBUS, + HEX_INS_V6_VDMPYBUS_ACC, + HEX_INS_V6_VDMPYBUS_DV, + HEX_INS_V6_VDMPYBUS_DV_ACC, + HEX_INS_V6_VDMPYHB, + HEX_INS_V6_VDMPYHB_ACC, + HEX_INS_V6_VDMPYHB_DV, + HEX_INS_V6_VDMPYHB_DV_ACC, + HEX_INS_V6_VDMPYHISAT, + HEX_INS_V6_VDMPYHISAT_ACC, + HEX_INS_V6_VDMPYHSAT, + HEX_INS_V6_VDMPYHSAT_ACC, + HEX_INS_V6_VDMPYHSUISAT, + HEX_INS_V6_VDMPYHSUISAT_ACC, + HEX_INS_V6_VDMPYHSUSAT, + HEX_INS_V6_VDMPYHSUSAT_ACC, + HEX_INS_V6_VDMPYHVSAT, + HEX_INS_V6_VDMPYHVSAT_ACC, + HEX_INS_V6_VDSADUH, + HEX_INS_V6_VDSADUH_ACC, + HEX_INS_V6_VEQB, + HEX_INS_V6_VEQB_AND, + HEX_INS_V6_VEQB_OR, + HEX_INS_V6_VEQB_XOR, + HEX_INS_V6_VEQH, + HEX_INS_V6_VEQH_AND, + HEX_INS_V6_VEQH_OR, + HEX_INS_V6_VEQH_XOR, + HEX_INS_V6_VEQW, + HEX_INS_V6_VEQW_AND, + HEX_INS_V6_VEQW_OR, + HEX_INS_V6_VEQW_XOR, + HEX_INS_V6_VGATHERMH, + HEX_INS_V6_VGATHERMHQ, + HEX_INS_V6_VGATHERMHW, + HEX_INS_V6_VGATHERMHWQ, + HEX_INS_V6_VGATHERMW, + HEX_INS_V6_VGATHERMWQ, + HEX_INS_V6_VGTB, + HEX_INS_V6_VGTB_AND, + HEX_INS_V6_VGTB_OR, + HEX_INS_V6_VGTB_XOR, + HEX_INS_V6_VGTH, + HEX_INS_V6_VGTH_AND, + HEX_INS_V6_VGTH_OR, + HEX_INS_V6_VGTH_XOR, + HEX_INS_V6_VGTUB, + HEX_INS_V6_VGTUB_AND, + HEX_INS_V6_VGTUB_OR, + HEX_INS_V6_VGTUB_XOR, + HEX_INS_V6_VGTUH, + HEX_INS_V6_VGTUH_AND, + HEX_INS_V6_VGTUH_OR, + HEX_INS_V6_VGTUH_XOR, + HEX_INS_V6_VGTUW, + HEX_INS_V6_VGTUW_AND, + HEX_INS_V6_VGTUW_OR, + HEX_INS_V6_VGTUW_XOR, + HEX_INS_V6_VGTW, + HEX_INS_V6_VGTW_AND, + HEX_INS_V6_VGTW_OR, + HEX_INS_V6_VGTW_XOR, + HEX_INS_V6_VHIST, + HEX_INS_V6_VHISTQ, + HEX_INS_V6_VINSERTWR, + HEX_INS_V6_VLALIGNB, + HEX_INS_V6_VLALIGNBI, + HEX_INS_V6_VLSRB, + HEX_INS_V6_VLSRH, + HEX_INS_V6_VLSRHV, + HEX_INS_V6_VLSRW, + HEX_INS_V6_VLSRWV, + HEX_INS_V6_VLUT4, + HEX_INS_V6_VLUTVVB, + HEX_INS_V6_VLUTVVB_NM, + HEX_INS_V6_VLUTVVB_ORACC, + HEX_INS_V6_VLUTVVB_ORACCI, + HEX_INS_V6_VLUTVVBI, + HEX_INS_V6_VLUTVWH, + HEX_INS_V6_VLUTVWH_NM, + HEX_INS_V6_VLUTVWH_ORACC, + HEX_INS_V6_VLUTVWH_ORACCI, + HEX_INS_V6_VLUTVWHI, + HEX_INS_V6_VMAXB, + HEX_INS_V6_VMAXH, + HEX_INS_V6_VMAXUB, + HEX_INS_V6_VMAXUH, + HEX_INS_V6_VMAXW, + HEX_INS_V6_VMINB, + HEX_INS_V6_VMINH, + HEX_INS_V6_VMINUB, + HEX_INS_V6_VMINUH, + HEX_INS_V6_VMINW, + HEX_INS_V6_VMPABUS, + HEX_INS_V6_VMPABUS_ACC, + HEX_INS_V6_VMPABUSV, + HEX_INS_V6_VMPABUU, + HEX_INS_V6_VMPABUU_ACC, + HEX_INS_V6_VMPABUUV, + HEX_INS_V6_VMPAHB, + HEX_INS_V6_VMPAHB_ACC, + HEX_INS_V6_VMPAHHSAT, + HEX_INS_V6_VMPAUHB, + HEX_INS_V6_VMPAUHB_ACC, + HEX_INS_V6_VMPAUHUHSAT, + HEX_INS_V6_VMPSUHUHSAT, + HEX_INS_V6_VMPYBUS, + HEX_INS_V6_VMPYBUS_ACC, + HEX_INS_V6_VMPYBUSV, + HEX_INS_V6_VMPYBUSV_ACC, + HEX_INS_V6_VMPYBV, + HEX_INS_V6_VMPYBV_ACC, + HEX_INS_V6_VMPYEWUH, + HEX_INS_V6_VMPYEWUH_64, + HEX_INS_V6_VMPYH, + HEX_INS_V6_VMPYH_ACC, + HEX_INS_V6_VMPYHSAT_ACC, + HEX_INS_V6_VMPYHSRS, + HEX_INS_V6_VMPYHSS, + HEX_INS_V6_VMPYHUS, + HEX_INS_V6_VMPYHUS_ACC, + HEX_INS_V6_VMPYHV, + HEX_INS_V6_VMPYHV_ACC, + HEX_INS_V6_VMPYHVSRS, + HEX_INS_V6_VMPYIEOH, + HEX_INS_V6_VMPYIEWH_ACC, + HEX_INS_V6_VMPYIEWUH, + HEX_INS_V6_VMPYIEWUH_ACC, + HEX_INS_V6_VMPYIH, + HEX_INS_V6_VMPYIH_ACC, + HEX_INS_V6_VMPYIHB, + HEX_INS_V6_VMPYIHB_ACC, + HEX_INS_V6_VMPYIOWH, + HEX_INS_V6_VMPYIWB, + HEX_INS_V6_VMPYIWB_ACC, + HEX_INS_V6_VMPYIWH, + HEX_INS_V6_VMPYIWH_ACC, + HEX_INS_V6_VMPYIWUB, + HEX_INS_V6_VMPYIWUB_ACC, + HEX_INS_V6_VMPYOWH, + HEX_INS_V6_VMPYOWH_64_ACC, + HEX_INS_V6_VMPYOWH_RND, + HEX_INS_V6_VMPYOWH_RND_SACC, + HEX_INS_V6_VMPYOWH_SACC, + HEX_INS_V6_VMPYUB, + HEX_INS_V6_VMPYUB_ACC, + HEX_INS_V6_VMPYUBV, + HEX_INS_V6_VMPYUBV_ACC, + HEX_INS_V6_VMPYUH, + HEX_INS_V6_VMPYUH_ACC, + HEX_INS_V6_VMPYUHE, + HEX_INS_V6_VMPYUHE_ACC, + HEX_INS_V6_VMPYUHV, + HEX_INS_V6_VMPYUHV_ACC, + HEX_INS_V6_VMUX, + HEX_INS_V6_VNAVGB, + HEX_INS_V6_VNAVGH, + HEX_INS_V6_VNAVGUB, + HEX_INS_V6_VNAVGW, + HEX_INS_V6_VNCCOMBINE, + HEX_INS_V6_VNCMOV, + HEX_INS_V6_VNORMAMTH, + HEX_INS_V6_VNORMAMTW, + HEX_INS_V6_VNOT, + HEX_INS_V6_VOR, + HEX_INS_V6_VPACKEB, + HEX_INS_V6_VPACKEH, + HEX_INS_V6_VPACKHB_SAT, + HEX_INS_V6_VPACKHUB_SAT, + HEX_INS_V6_VPACKOB, + HEX_INS_V6_VPACKOH, + HEX_INS_V6_VPACKWH_SAT, + HEX_INS_V6_VPACKWUH_SAT, + HEX_INS_V6_VPOPCOUNTH, + HEX_INS_V6_VPREFIXQB, + HEX_INS_V6_VPREFIXQH, + HEX_INS_V6_VPREFIXQW, + HEX_INS_V6_VRDELTA, + HEX_INS_V6_VRMPYBUB_RTT, + HEX_INS_V6_VRMPYBUB_RTT_ACC, + HEX_INS_V6_VRMPYBUS, + HEX_INS_V6_VRMPYBUS_ACC, + HEX_INS_V6_VRMPYBUSI, + HEX_INS_V6_VRMPYBUSI_ACC, + HEX_INS_V6_VRMPYBUSV, + HEX_INS_V6_VRMPYBUSV_ACC, + HEX_INS_V6_VRMPYBV, + HEX_INS_V6_VRMPYBV_ACC, + HEX_INS_V6_VRMPYUB, + HEX_INS_V6_VRMPYUB_ACC, + HEX_INS_V6_VRMPYUB_RTT, + HEX_INS_V6_VRMPYUB_RTT_ACC, + HEX_INS_V6_VRMPYUBI, + HEX_INS_V6_VRMPYUBI_ACC, + HEX_INS_V6_VRMPYUBV, + HEX_INS_V6_VRMPYUBV_ACC, + HEX_INS_V6_VRMPYZBB_RT, + HEX_INS_V6_VRMPYZBB_RT_ACC, + HEX_INS_V6_VRMPYZBB_RX, + HEX_INS_V6_VRMPYZBB_RX_ACC, + HEX_INS_V6_VRMPYZBUB_RT, + HEX_INS_V6_VRMPYZBUB_RT_ACC, + HEX_INS_V6_VRMPYZBUB_RX, + HEX_INS_V6_VRMPYZBUB_RX_ACC, + HEX_INS_V6_VRMPYZCB_RT, + HEX_INS_V6_VRMPYZCB_RT_ACC, + HEX_INS_V6_VRMPYZCB_RX, + HEX_INS_V6_VRMPYZCB_RX_ACC, + HEX_INS_V6_VRMPYZCBS_RT, + HEX_INS_V6_VRMPYZCBS_RT_ACC, + HEX_INS_V6_VRMPYZCBS_RX, + HEX_INS_V6_VRMPYZCBS_RX_ACC, + HEX_INS_V6_VRMPYZNB_RT, + HEX_INS_V6_VRMPYZNB_RT_ACC, + HEX_INS_V6_VRMPYZNB_RX, + HEX_INS_V6_VRMPYZNB_RX_ACC, + HEX_INS_V6_VROR, + HEX_INS_V6_VROTR, + HEX_INS_V6_VROUNDHB, + HEX_INS_V6_VROUNDHUB, + HEX_INS_V6_VROUNDUHUB, + HEX_INS_V6_VROUNDUWUH, + HEX_INS_V6_VROUNDWH, + HEX_INS_V6_VROUNDWUH, + HEX_INS_V6_VRSADUBI, + HEX_INS_V6_VRSADUBI_ACC, + HEX_INS_V6_VSATDW, + HEX_INS_V6_VSATHUB, + HEX_INS_V6_VSATUWUH, + HEX_INS_V6_VSATWH, + HEX_INS_V6_VSB, + HEX_INS_V6_VSCATTERMH, + HEX_INS_V6_VSCATTERMH_ADD, + HEX_INS_V6_VSCATTERMHQ, + HEX_INS_V6_VSCATTERMHW, + HEX_INS_V6_VSCATTERMHW_ADD, + HEX_INS_V6_VSCATTERMHWQ, + HEX_INS_V6_VSCATTERMW, + HEX_INS_V6_VSCATTERMW_ADD, + HEX_INS_V6_VSCATTERMWQ, + HEX_INS_V6_VSH, + HEX_INS_V6_VSHUFEH, + HEX_INS_V6_VSHUFF, + HEX_INS_V6_VSHUFFB, + HEX_INS_V6_VSHUFFEB, + HEX_INS_V6_VSHUFFH, + HEX_INS_V6_VSHUFFOB, + HEX_INS_V6_VSHUFFVDD, + HEX_INS_V6_VSHUFOEB, + HEX_INS_V6_VSHUFOEH, + HEX_INS_V6_VSHUFOH, + HEX_INS_V6_VSUBB, + HEX_INS_V6_VSUBB_DV, + HEX_INS_V6_VSUBBNQ, + HEX_INS_V6_VSUBBQ, + HEX_INS_V6_VSUBBSAT, + HEX_INS_V6_VSUBBSAT_DV, + HEX_INS_V6_VSUBCARRY, + HEX_INS_V6_VSUBCARRYO, + HEX_INS_V6_VSUBH, + HEX_INS_V6_VSUBH_DV, + HEX_INS_V6_VSUBHNQ, + HEX_INS_V6_VSUBHQ, + HEX_INS_V6_VSUBHSAT, + HEX_INS_V6_VSUBHSAT_DV, + HEX_INS_V6_VSUBHW, + HEX_INS_V6_VSUBUBH, + HEX_INS_V6_VSUBUBSAT, + HEX_INS_V6_VSUBUBSAT_DV, + HEX_INS_V6_VSUBUBUBB_SAT, + HEX_INS_V6_VSUBUHSAT, + HEX_INS_V6_VSUBUHSAT_DV, + HEX_INS_V6_VSUBUHW, + HEX_INS_V6_VSUBUWSAT, + HEX_INS_V6_VSUBUWSAT_DV, + HEX_INS_V6_VSUBW, + HEX_INS_V6_VSUBW_DV, + HEX_INS_V6_VSUBWNQ, + HEX_INS_V6_VSUBWQ, + HEX_INS_V6_VSUBWSAT, + HEX_INS_V6_VSUBWSAT_DV, + HEX_INS_V6_VSWAP, + HEX_INS_V6_VTMPYB, + HEX_INS_V6_VTMPYB_ACC, + HEX_INS_V6_VTMPYBUS, + HEX_INS_V6_VTMPYBUS_ACC, + HEX_INS_V6_VTMPYHB, + HEX_INS_V6_VTMPYHB_ACC, + HEX_INS_V6_VUNPACKB, + HEX_INS_V6_VUNPACKH, + HEX_INS_V6_VUNPACKOB, + HEX_INS_V6_VUNPACKOH, + HEX_INS_V6_VUNPACKUB, + HEX_INS_V6_VUNPACKUH, + HEX_INS_V6_VWHIST128, + HEX_INS_V6_VWHIST128M, + HEX_INS_V6_VWHIST128Q, + HEX_INS_V6_VWHIST128QM, + HEX_INS_V6_VWHIST256, + HEX_INS_V6_VWHIST256_SAT, + HEX_INS_V6_VWHIST256Q, + HEX_INS_V6_VWHIST256Q_SAT, + HEX_INS_V6_VXOR, + HEX_INS_V6_VZB, + HEX_INS_V6_VZH, + HEX_INS_V6_ZLD_AI, + HEX_INS_V6_ZLD_PI, + HEX_INS_V6_ZLD_PPU, + HEX_INS_V6_ZLD_PRED_AI, + HEX_INS_V6_ZLD_PRED_PI, + HEX_INS_V6_ZLD_PRED_PPU, + HEX_INS_V6_ZEXTRACT, + HEX_INS_Y2_BARRIER, + HEX_INS_Y2_BREAK, + HEX_INS_Y2_DCCLEANA, + HEX_INS_Y2_DCCLEANINVA, + HEX_INS_Y2_DCFETCHBO, + HEX_INS_Y2_DCINVA, + HEX_INS_Y2_DCZEROA, + HEX_INS_Y2_ICINVA, + HEX_INS_Y2_ISYNC, + HEX_INS_Y2_SYNCHT, + HEX_INS_Y2_WAIT, + HEX_INS_Y4_L2FETCH, + HEX_INS_Y4_TRACE, + HEX_INS_Y5_L2FETCH, + HEX_INS_Y6_DIAG, + HEX_INS_Y6_DIAG0, + HEX_INS_Y6_DIAG1, + HEX_INS_Y6_DMLINK, + HEX_INS_Y6_DMPAUSE, + HEX_INS_Y6_DMPOLL, + HEX_INS_Y6_DMRESUME, + HEX_INS_Y6_DMSTART, + HEX_INS_Y6_DMWAIT, + HEX_INS_DEP_A2_ADDSAT, + HEX_INS_DEP_A2_SUBSAT, + HEX_INS_DEP_S2_PACKHL, + HEX_INS_IMPORTED_DCCLEANIDX_RS, + HEX_INS_IMPORTED_RESUME_RS, + HEX_INS_IMPORTED_L2KILL, + HEX_INS_IMPORTED_K0UNLOCK, + HEX_INS_IMPORTED_STOP_RS, + HEX_INS_IMPORTED_CIAD_RS, + HEX_INS_IMPORTED_ICKILL, + HEX_INS_IMPORTED_RD_GETIMASK_RS, + HEX_INS_IMPORTED_DCCLEANINVIDX_RS, + HEX_INS_IMPORTED_SWI_RS, + HEX_INS_IMPORTED_TLBW_RSS_RT, + HEX_INS_IMPORTED_L2GCLEANINV, + HEX_INS_IMPORTED_RD_CTLBW_RSS_RT, + HEX_INS_IMPORTED_ICINVIDX_RS, + HEX_INS_IMPORTED_K0LOCK, + HEX_INS_IMPORTED_L2TAGW_RS_RT, + HEX_INS_IMPORTED_ICDATAW_RS_RT, + HEX_INS_IMPORTED_RTE, + HEX_INS_IMPORTED_RD_DCTAGR_RS, + HEX_INS_IMPORTED_RD_IASSIGNR_RS, + HEX_INS_IMPORTED_RDD_SSS, + HEX_INS_IMPORTED_DCINVIDX_RS, + HEX_INS_IMPORTED_L2GUNLOCK, + HEX_INS_IMPORTED_RD_SS, + HEX_INS_IMPORTED_ICTAGW_RS_RT, + HEX_INS_IMPORTED_PD_L2LOCKA_RS, + HEX_INS_IMPORTED_RD_TLBP_RS, + HEX_INS_IMPORTED_RD_L2TAGR_RS, + HEX_INS_IMPORTED_IASSIGNW_RS, + HEX_INS_IMPORTED_NMI_RS, + HEX_INS_IMPORTED_TLBINVASID_RS, + HEX_INS_IMPORTED_SDD_RSS, + HEX_INS_IMPORTED_DCTAGW_RS_RT, + HEX_INS_IMPORTED_L2GCLEAN, + HEX_INS_IMPORTED_DCKILL, + HEX_INS_IMPORTED_L2INVIDX_RS, + HEX_INS_IMPORTED_SETIMASK_PT_RS, + HEX_INS_IMPORTED_CRSWAP_RX_SGP0, + HEX_INS_IMPORTED_TLBLOCK, + HEX_INS_IMPORTED_CRSWAP_RX_SGP1, + HEX_INS_IMPORTED_L2GCLEAN_RTT, + HEX_INS_IMPORTED_RDD_TLBR_RS, + HEX_INS_IMPORTED_L2CLEANINVIDX_RS, + HEX_INS_IMPORTED_L2UNLOCKA_RS, + HEX_INS_IMPORTED_SD_RS, + HEX_INS_IMPORTED_TLBUNLOCK, + HEX_INS_IMPORTED_RD_MEMW_PHYS_RS_RT, + HEX_INS_IMPORTED_RD_TLBOC_RSS, + HEX_INS_IMPORTED_CRSWAP_RXX_SGP1_0, + HEX_INS_IMPORTED_SETPRIO_PT_RS, + HEX_INS_IMPORTED_CSWI_RS, + HEX_INS_IMPORTED_SIAD_RS, + HEX_INS_IMPORTED_RD_ICDATAR_RS, + HEX_INS_IMPORTED_L2CLEANIDX_RS, + HEX_INS_IMPORTED_RD_ICTAGR_RS, + HEX_INS_IMPORTED_L2GCLEANINV_RTT, + HEX_INS_IMPORTED_START_RS, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ADDRX, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ADDSP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_AND1, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_AND1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRF, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRFNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRT, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CLRTNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_CMPEQI, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE0I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE1I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE2I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINE3I, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINERZ, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_COMBINEZR, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_DEC, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_DEC, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_INC, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_INC, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_SETIN1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_SXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_SXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_TFR, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_TFR, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ZXTB, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_INC_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SA1_ZXTH, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL1_LOADRI_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL1_LOADRUB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_DEALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_JUMPR31_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRD_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRI_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_LOADRUH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_F, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_FNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_T, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_INC_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SL2_RETURN_TNEW, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS1_STOREB_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS1_STOREW_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_ALLOCFRAME, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREBI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI0_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREBI1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREBI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STORED_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREH_IO, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREW_SP, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREWI0, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDRX_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDSP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_AND1_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRF_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRFNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRT_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CLRTNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_CMPEQI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE0I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE1I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE2I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINE3I_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINERZ_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_COMBINEZR_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_DEC_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_INC_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SETI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SETIN1_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTB_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_SXTH_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_TFR_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTB_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ZXTH_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRI_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL1_LOADRUB_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_DEALLOCFRAME_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRB_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRD_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRH_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRI_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_LOADRUH_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_F_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_FNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_T_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SL2_RETURN_TNEW_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREB_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS1_STOREW_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STORED_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREH_IO_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREW_SP_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI0_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SS2_STOREWI1_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_SS2_STOREWI1, + HEX_INS_X2_AUTOJOIN_SA1_ADDI_UNDOCUMENTED_SA2_TFRSI, + HEX_INS_X2_AUTOJOIN_SA1_SETI_UNDOCUMENTED_SA2_TFRSI, + HEX_INS_X2_AUTOJOIN_UNDOCUMENTED_SA2_TFRSI_UNDOCUMENTED_SA2_TFRSI, }; -#endif +#endif \ No newline at end of file diff --git a/librz/asm/arch/include/elf/common.h b/librz/asm/arch/include/elf/common.h index 826174f86f8..f9662c43b7c 100644 --- a/librz/asm/arch/include/elf/common.h +++ b/librz/asm/arch/include/elf/common.h @@ -189,6 +189,7 @@ #define EM_CRX 114 /* National Semiconductor CRX */ #define EM_CR16 115 /* National Semiconductor CompactRISC - CR16 */ #define EM_SCORE 135 /* Sunplus Score */ +#define EM_QDSP6 164 /* Qualcomm DSP6 */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision diff --git a/librz/asm/meson.build b/librz/asm/meson.build index a6ea5f7a41a..3a542c1ba02 100644 --- a/librz/asm/meson.build +++ b/librz/asm/meson.build @@ -103,6 +103,7 @@ rz_asm_sources = [ #'arch/gb/gbdis.c', 'arch/h8300/h8300_disas.c', 'arch/hexagon/hexagon.c', + 'arch/hexagon/hexagon_arch.c', 'arch/hexagon/hexagon_disas.c', #'arch/hexagon/gnu/hexagon-dis.c', #'arch/hexagon/gnu/hexagon-opc.c', diff --git a/librz/asm/p/asm_hexagon.c b/librz/asm/p/asm_hexagon.c index 6040fce610d..92e394b938f 100644 --- a/librz/asm/p/asm_hexagon.c +++ b/librz/asm/p/asm_hexagon.c @@ -1,18 +1,34 @@ -// SPDX-FileCopyrightText: 2018 xvilka +// SPDX-FileCopyrightText: 2021 Rot127 // SPDX-License-Identifier: LGPL-3.0-only +//======================================== +// The following code is generated. +// Do not edit. Repository of code generator: +// https://github.com/rizinorg/rz-hexagon + #include #include #include #include #include "hexagon.h" #include "hexagon_insn.h" +#include "hexagon_arch.h" +/** + * \brief Disassembles a hexagon opcode, write info to op and returns its size. + * + * \param a The current RzAsm struct. + * \param op The RzAsmOp which is be filled with the reversed opcode information. + * \param buf The buffer with the opcode. + * \param l The size to read from the buffer. + * \return int Size of the reversed opcode. + */ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int l) { - HexInsn hi = { 0 }; - ut32 data = rz_read_le32(buf); - op->size = hexagon_disasm_instruction(data, &hi, (ut32)a->pc); - rz_strbuf_set(&op->buf_asm, hi.mnem); + ut32 addr = (ut32)a->pc; + HexReversedOpcode rev = { .action = HEXAGON_DISAS, .ana_op = NULL, .asm_op = op }; + + hexagon_reverse_opcode(a, &rev, buf, addr); + return op->size; } diff --git a/librz/bin/format/elf/glibc_elf.h b/librz/bin/format/elf/glibc_elf.h index b25edd183b0..314fbc5eefb 100644 --- a/librz/bin/format/elf/glibc_elf.h +++ b/librz/bin/format/elf/glibc_elf.h @@ -4074,6 +4074,163 @@ enum { #define RZ_ARC_TLS_LE_S9 0x4a #define RZ_ARC_TLS_LE_32 0x4b +/* Qualcomm QDSP6 (Hexagon) specific definitions. */ + +/* Legal values for e_type (object file type). */ +#define ET_HEXAGON_IR 0xff00 + +/* Values for Elf32_Ehdr.e_flags. */ +/* Object processor version flags, bits[11:0] */ +#define EF_HEXAGON_MACH_V2 0x1 +#define EF_HEXAGON_MACH_V3 0x2 +#define EF_HEXAGON_MACH_V4 0x3 +#define EF_HEXAGON_MACH_V5 0x4 +#define EF_HEXAGON_MACH_V55 0x5 +#define EF_HEXAGON_MACH_V60 0x60 +#define EF_HEXAGON_MACH_V61 0x61 +#define EF_HEXAGON_MACH_V62 0x62 +#define EF_HEXAGON_MACH_V65 0x65 +#define EF_HEXAGON_MACH_V66 0x66 +#define EF_HEXAGON_MACH_V67 0x67 +#define EF_HEXAGON_MACH_V67T 0x8067 /* Hexagon V67 Small Core (V67t) */ +#define EF_HEXAGON_MACH_V68 = 0x68 + +/* Highest ISA version flags */ +#define EF_HEXAGON_ISA_MACH 0x0 /* Same as specified in bits[11:0] of e_flags */ +#define EF_HEXAGON_ISA_V2 0x10 +#define EF_HEXAGON_ISA_V3 0x20 +#define EF_HEXAGON_ISA_V4 0x30 +#define EF_HEXAGON_ISA_V5 0x40 +#define EF_HEXAGON_ISA_V55 0x50 +#define EF_HEXAGON_ISA_V60 0x60 +#define EF_HEXAGON_ISA_V62 0x62 +#define EF_HEXAGON_ISA_V65 0x65 +#define EF_HEXAGON_ISA_V66 0x66 +#define EF_HEXAGON_ISA_V67 0x67 +#define EF_HEXAGON_ISA_V68 0x68 + +/* Special section indices. */ +#define SHN_HEXAGON_SCOMMON 0xff00 /* Other access sizes */ +#define SHN_HEXAGON_SCOMMON_1 0xff01 /* Byte-sized access */ +#define SHN_HEXAGON_SCOMMON_2 0xff02 /* Half-word-sized access */ +#define SHN_HEXAGON_SCOMMON_4 0xff03 /* Word-size access */ +#define SHN_HEXAGON_SCOMMON_8 0xff04 /* Double-word-size access */ + +/* Legal values for sh_flags (section flags). */ +#define SHF_HEXAGON_GPREL 0x10000000 /* Section resides in the small data area */ + +/* Legal values for sh_type (section type). */ +#define SHT_HEX_ORDERED 0x70000000 /* Link editor is to sort the entries in this section based on their sizes. */ + +/* Qualcomm QDSP6 relocations */ +/* Name Value Field Relocation Result Action */ +#define R_HEX_NONE 0 /* None None None None */ +#define R_HEX_B22_PCREL 1 /* Word32_B22 (S + A - P) >> 2 Signed Verify */ +#define R_HEX_B15_PCREL 2 /* Word32_B15 (S + A - P) >> 2 Signed Verify */ +#define R_HEX_B7_PCREL 3 /* Word32_B7 (S + A - P) >> 2 Signed Verify */ +#define R_HEX_LO16 4 /* Word32_LO (S + A) Unsigned Truncate */ +#define R_HEX_HI16 5 /* Word32_LO (S + A) >> 16 Unsigned Truncate */ +#define R_HEX_32 6 /* Word32 (S + A) Unsigned Truncate */ +#define R_HEX_16 7 /* Word16 (S + A) Unsigned Truncate */ +#define R_HEX_8 8 /* Word8 (S + A) Unsigned Truncate */ +#define R_HEX_GPREL16_0 9 /* Word32_GP (S + A - GP) Unsigned Verify */ +#define R_HEX_GPREL16_1 10 /* Word32_GP (S + A - GP) >> 1 Unsigned Verify */ +#define R_HEX_GPREL16_2 11 /* Word32_GP (S + A - GP) >> 2 Unsigned Verify */ +#define R_HEX_GPREL16_3 12 /* Word32_GP (S + A - GP) >> 3 Unsigned Verify */ +#define R_HEX_HL16 13 /* Word32_HL (S + A)>>16 & (S + A) Unsigned Truncate */ +#define R_HEX_B13_PCREL 14 /* Word32_B13 (S + A - P) >> 2 Signed Verify */ +#define R_HEX_B9_PCREL 15 /* Word32_B9 (S + A - P) >> 2 Signed Verify */ +#define R_HEX_B32_PCREL_X 16 /* Word32_X26 (S + A - P) >> 6 Signed Truncate */ +#define R_HEX_32_6_X 17 /* Word32_X26 (S + A) >> 6 Unsigned Verify */ +#define R_HEX_B22_PCREL_X 18 /* Word32_B22 (S + A - P) & 0x3f Signed Verify */ +#define R_HEX_B15_PCREL_X 19 /* Word32_B15 (S + A - P) & 0x3f Signed Verify */ +#define R_HEX_B13_PCREL_X 20 /* Word32_B13 (S + A - P) & 0x3f Signed Verify */ +#define R_HEX_B9_PCREL_X 21 /* Word32_B9 (S + A - P) & 0x3f Signed Verify */ +#define R_HEX_B7_PCREL_X 22 /* Word32_B7 (S + A - P) & 0x3f Signed Verify */ +#define R_HEX_16_X 23 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_12_X 24 /* Word32_R6 (S + A) Unsigned Truncate */ +#define R_HEX_11_X 25 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_10_X 26 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_9_X 27 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_8_X 28 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_7_X 29 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_6_X 30 /* Word32_U6 (S + A) Unsigned Truncate */ +#define R_HEX_32_PCREL 31 /* Word32 (S + A - P) Signed Verify */ +#define R_HEX_COPY 32 /* Word32 (See ABI docs) */ +#define R_HEX_GLOB_DAT 33 /* Word32 (S + A) (See ABI docs)Unsigned Truncate */ +#define R_HEX_JMP_SLOT 34 /* Word32 (S + A) (see ABI docs)Unsigned Truncate */ +#define R_HEX_RELATIVE 35 /* Word32 (B + A) (see ABI docs)Unsigned Truncate */ +#define R_HEX_PLT_B22_PCREL 36 /* Word32_B22 (L + A - P) >> 2 Signed Verify */ +#define R_HEX_GOTREL_LO16 37 /* Word32_LO (S + A - GOT) Signed Truncate */ +#define R_HEX_GOTREL_HI16 38 /* Word32_LO (S + A - GOT) >> 16 Signed Truncate */ +#define R_HEX_GOTREL_32 39 /* Word32 (S + A - GOT) Signed Truncate */ +#define R_HEX_GOT_LO16 40 /* Word32_LO (G) Signed Truncate */ +#define R_HEX_GOT_HI16 41 /* Word32_LO (G) >> 16 Signed Truncate */ +#define R_HEX_GOT_32 42 /* Word32 (G) Signed Truncate */ +#define R_HEX_GOT_16 43 /* Word32_U16 (G) Signed Verify */ +#define R_HEX_DTPMOD_32 44 /* Word32 */ +#define R_HEX_DTPREL_LO16 45 /* Word32_LO (S + A - T) Signed Truncate */ +#define R_HEX_DTPREL_HI16 46 /* Word32_LO (S + A - T) >> 16 Signed Truncate */ +#define R_HEX_DTPREL_32 47 /* Word32 (S + A - T) Signed Truncate */ +#define R_HEX_DTPREL_16 48 /* Word32_U16 (S + A - T) Signed Verify */ +#define R_HEX_GD_PLT_B22_PCREL 49 /* Word32_B22 (L + A - P) >> 2 Signed Verify */ +#define R_HEX_GD_GOT_LO16 50 /* Word32_LO (G) Signed Truncate */ +#define R_HEX_GD_GOT_HI16 51 /* Word32_LO (G) >> 16 Signed Truncate */ +#define R_HEX_GD_GOT_32 52 /* Word32 (G) Signed Truncate */ +#define R_HEX_GD_GOT_16 53 /* Word32_U16 (G) Signed Verify */ +#define R_HEX_IE_LO16 54 /* Word32_LO (G + GOT) Signed Truncate */ +#define R_HEX_IE_HI16 55 /* Word32_LO (G + GOT) >> 16 Signed Truncate */ +#define R_HEX_IE_32 56 /* Word32 (G + GOT) Signed Truncate */ +#define R_HEX_IE_GOT_LO16 57 /* Word32_LO (G) Signed Truncate */ +#define R_HEX_IE_GOT_HI16 58 /* Word32_LO (G) >> 16 Signed Truncate */ +#define R_HEX_IE_GOT_32 59 /* Word32 (G) Signed Truncate */ +#define R_HEX_IE_GOT_16 60 /* Word32_U16 (G) Signed Verify */ +#define R_HEX_TPREL_LO16 61 /* Word32_LO (TLS - S - A) Signed Truncate */ +#define R_HEX_TPREL_HI16 62 /* Word32_LO (TLS - S - A) >> 16 Signed Truncate */ +#define R_HEX_TPREL_32 63 /* Word32 (TLS - S - A) Signed Truncate */ +#define R_HEX_TPREL_16 64 /* Word32_U16 (TLS - S - A) Signed Verify */ +#define R_HEX_6_PCREL_X 65 /* Word32_U6 (S + A - P) Unsigned Truncate */ +#define R_HEX_GOTREL_32_6_X 66 /* Word32_X26 (S + A - GOT) >> 6 Signed Truncate */ +#define R_HEX_GOTREL_16_X 67 /* Word32_U6 (S + A - GOT) Unsigned Truncate */ +#define R_HEX_GOTREL_11_X 68 /* Word32_U6 (S + A - GOT) Unsigned Truncate */ +#define R_HEX_GOT_32_6_X 69 /* Word32_X26 (G) >> 6 Signed Truncate */ +#define R_HEX_GOT_16_X 70 /* Word32_U6 (G) Signed Truncate */ +#define R_HEX_GOT_11_X 71 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_DTPREL_32_6_X 72 /* Word32_X26 (S + A - T) >> 6 Signed Truncate */ +#define R_HEX_DTPREL_16_X 73 /* Word32_U6 (S + A - T) Unsigned Truncate */ +#define R_HEX_DTPREL_11_X 74 /* Word32_U6 (S + A - T) Unsigned Truncate */ +#define R_HEX_GD_GOT_32_6_X 75 /* Word32_X26 (G) >> 6 Signed Truncate */ +#define R_HEX_GD_GOT_16_X 76 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_GD_GOT_11_X 77 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_IE_32_6_X 78 /* Word32_X26 (G + GOT) >> 6 Signed Truncate */ +#define R_HEX_IE_16_X 79 /* Word32_U6 (G + GOT) Unsigned Truncate */ +#define R_HEX_IE_GOT_32_6_X 80 /* Word32_X26 (G) >> 6 Signed Truncate */ +#define R_HEX_IE_GOT_16_X 81 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_IE_GOT_11_X 82 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_TPREL_32_6_X 83 /* Word32_X26 (TLS - S - A) >> 6 Signed Truncate */ +#define R_HEX_TPREL_16_X 84 /* Word32_U6 (TLS - S - A) Unsigned Truncate */ +#define R_HEX_TPREL_11_X 85 /* Word32_U6 (TLS - S - A) Unsigned Truncate */ +#define R_HEX_LD_PLT_B22_PCREL 86 /* Word32_B22 (L + A - P) >> 2 Signed Verify */ +#define R_HEX_LD_GOT_LO16 87 /* Word32_LO (G) Signed Truncate */ +#define R_HEX_LD_GOT_HI16 88 /* Word32_LO (G) >> 16 Signed Truncate */ +#define R_HEX_LD_GOT_32 89 /* Word32 (G) Signed Truncate */ +#define R_HEX_LD_GOT_16 90 /* Word32_R16 (G) Signed Verify */ +#define R_HEX_LD_GOT_32_6_X 91 /* Word32_X26 (G) >> 6 Signed Truncate */ +#define R_HEX_LD_GOT_16_X 92 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_LD_GOT_11_X 93 /* Word32_U6 (G) Unsigned Truncate */ +#define R_HEX_23_REG 94 /* Word32_B21 (S + A - MB) >> 2 Unsigned Verify */ +#define R_HEX_GD_PLT_B22_PCREL_X 95 /* Word32_B22 (S + A - P) & 0x3f Signed Truncate */ +#define R_HEX_GD_PLT_B32_PCREL_X 96 /* Word32_X26 (S + A - P) >> 6 Signed Truncate */ +#define R_HEX_LD_PLT_B22_PCREL_X 97 /* Word32_B22 (S + A - P) & 0x3f Signed Truncate */ +#define R_HEX_LD_PLT_B32_PCREL_X 98 /* Word32_X26 (S + A - P) >> 6 Signed Truncate */ +#define R_HEX_27_REG 99 /* Word32_M25 (S + A - MB) >> 2 Unsigned Verify */ + +/* Dynamic array tags */ + +#define DT_HEXAGON_SYMSZ 0x70000000 +#define DT_HEXAGON_VER 0x70000001 +#define DT_HEXAGON_PLT 0x70000002 + __END_DECLS #endif /* elf.h */ diff --git a/librz/bin/p/bin_elf.inc b/librz/bin/p/bin_elf.inc index cba8f4aed01..14ebce3d145 100644 --- a/librz/bin/p/bin_elf.inc +++ b/librz/bin/p/bin_elf.inc @@ -24,6 +24,20 @@ #define rz_buf_append_word rz_buf_append_ut32 #endif +typedef struct rz_bin_reloc_formular_symbols_t { + ut64 A; // Appendend + ut64 B; // Base address + ut64 G; // Offset into GOT for symbol entry. + ut64 GOT; // Address of entry zero in GOT. + ut64 L; // Offset into POT for symbo, entry. + ut64 P; // Place address of the field being relocated. + ut64 S; // Value of symbol. + ut64 TLS; // Thread-pointer-relative offset to a thread-local symbol. + ut64 T; // Base address of the static thread-local tmeplate that contains a thread-local symbol. + ut64 MB; // Base address of all strings consumed by compiler message base optimization (Hexagon specific). + ut64 GP; // Value of GP register (Hexagon specific). +} RzBinRelocFormularSymbols; + static RzBinInfo *info(RzBinFile *bf); static void patch_relocs(RzBinFile *bf, struct Elf_(rz_bin_elf_obj_t) * bin); static RzList *imports(RzBinFile *bf); @@ -640,13 +654,245 @@ static ut64 reloc_targets_vfile_size(RzBinFile *bf, ELFOBJ *obj) { return Elf_(rz_bin_elf_get_relocs_count)(obj) * reloc_target_size(obj); } -static void patch_reloc(struct Elf_(rz_bin_elf_obj_t) * obj, RzBinElfReloc *rel, ut64 S, ut64 B, ut64 L) { +/** + * \brief Patches the opcode at a given address depending on the relocation type. + * + * \param buf_patched Buffer from which the opcode is read and the patched opcode is written to. + * \param patch_addr The address of the opcode being patched. + * \param rel_type The relocation type. + * \param fs Formular values to calculate the new relocation value. + */ +static void patch_reloc_hexagon(RZ_INOUT RzBuffer *buf_patched, const ut64 patch_addr, const int rel_type, const RzBinRelocFormularSymbols *fs) { + ut8 buf[8] = { 0 }; + ut8 word = 0; + ut64 val = 0; + ut64 bitmask = UT64_MAX; // Mask of patched opcode bits. + + switch (rel_type) { + default: + RZ_LOG_ERROR("Patching for reloc type %d not implemented.", rel_type); + rz_warn_if_reached(); + return; + case R_HEX_NONE: + return; + case R_HEX_GLOB_DAT: + word = 4; + val = (fs->S + fs->A); + break; + case R_HEX_JMP_SLOT: + word = 4; + val = (fs->S + fs->A); + break; + case R_HEX_RELATIVE: + word = 4; + val = (fs->B + fs->A); + break; + case R_HEX_B22_PCREL: + word = 4; + val = (fs->S + fs->A - fs->P) >> 2; + break; + case R_HEX_B15_PCREL: + bitmask = 0x00df20fe; + word = 4; + val = (fs->S + fs->A - fs->P) >> 2; + break; + case R_HEX_B7_PCREL: + bitmask = 0x00001f18; + word = 4; + val = (fs->S + fs->A - fs->P) >> 2; + break; + case R_HEX_LO16: + bitmask = 0x00c03fff; + word = 4; + val = (fs->S + fs->A); + break; + case R_HEX_HI16: + bitmask = 0x00c03fff; + word = 4; + val = (fs->S + fs->A) >> 16; + break; + case R_HEX_32: + word = 4; + val = (fs->S + fs->A); + break; + case R_HEX_16: + bitmask = 0xffff; + word = 2; + val = (fs->S + fs->A); + break; + case R_HEX_8: + bitmask = 0xff; + word = 1; + val = (fs->S + fs->A); + break; + case R_HEX_HL16: + bitmask = 0x00c03fff; + word = 4; + val = (fs->S + fs->A); + break; + case R_HEX_B13_PCREL: + bitmask = 0x00202ffe; + word = 4; + val = (fs->S + fs->A - fs->P) >> 2; + break; + case R_HEX_B9_PCREL: + bitmask = 0x003000fe; + word = 4; + val = (fs->S + fs->A - fs->P) >> 2; + break; + case R_HEX_B32_PCREL_X: + word = 4; + val = (fs->S + fs->A - fs->P) >> 6; + break; + case R_HEX_32_6_X: + word = 4; + val = (fs->S + fs->A) >> 6; + break; + case R_HEX_B22_PCREL_X: + bitmask = 0x01ff3ffe; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_B15_PCREL_X: + bitmask = 0x00df20fe; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_B13_PCREL_X: + bitmask = 0x00202ffe; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_B9_PCREL_X: + bitmask = 0x003000fe; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_B7_PCREL_X: + bitmask = 0x00001f18; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_12_X: + bitmask = 0x000007e0; + word = 4; + val = (fs->S + fs->A); + break; + case R_HEX_32_PCREL: + word = 4; + val = (fs->S + fs->A - fs->P); + break; + case R_HEX_PLT_B22_PCREL: + bitmask = 0x01ff3ffe; + word = 4; + val = (fs->L + fs->A - fs->P) >> 2; + break; + case R_HEX_GOTREL_LO16: + bitmask = 0x00c03fff; + word = 4; + val = (fs->S + fs->A - fs->GOT); + break; + case R_HEX_GOTREL_HI16: + bitmask = 0x00c03fff; + word = 4; + val = (fs->S + fs->A - fs->GOT) >> 16; + break; + case R_HEX_GOTREL_32: + word = 4; + val = (fs->S + fs->A - fs->GOT); + break; + case R_HEX_GOTREL_32_6_X: + word = 4; + val = (fs->S + fs->A - fs->GOT) >> 6; + break; + case R_HEX_LD_PLT_B22_PCREL: + bitmask = 0x01ff3ffe; + word = 4; + val = (fs->L + fs->A - fs->P) >> 2; + break; + case R_HEX_GD_PLT_B22_PCREL: + bitmask = 0x01ff3ffe; + word = 4; + val = (fs->L + fs->A - fs->P) >> 2; + break; + case R_HEX_GD_PLT_B22_PCREL_X: + bitmask = 0x01ff3ffe; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_GD_PLT_B32_PCREL_X: + word = 4; + val = (fs->S + fs->A - fs->P) >> 6; + break; + case R_HEX_LD_PLT_B22_PCREL_X: + bitmask = 0x01ff3ffe; + word = 4; + val = (fs->S + fs->A - fs->P) & 0x3f; + break; + case R_HEX_LD_PLT_B32_PCREL_X: + word = 4; + val = (fs->S + fs->A - fs->P) >> 6; + break; + } + + // Patch two opcodes at once. + if (rel_type == R_HEX_HL16) { + ut32 val1 = val >> 16; + ut32 val2 = val & 0xffffffff; + ut32 opcode_val1 = 0, opcode_val2 = 0, pos = 1, vpos = 1; + for (ut8 i = 0; i < 32; ++i) { + if (bitmask & pos) { + opcode_val1 |= (val1 & vpos); + opcode_val2 |= (val2 & vpos); + vpos = vpos << 1; + } + pos = pos << 1; + } + rz_buf_read_at(buf_patched, patch_addr, buf, 8); + ut64 opcode1 = (rz_read_le64(buf) & 0xffffffff); + ut64 opcode2 = (rz_read_le64(buf) >> 32); + opcode1 &= ~bitmask; + opcode2 &= ~bitmask; + opcode1 |= opcode_val1; + opcode2 |= opcode_val2; + ut64 opcode12 = opcode1 & (opcode2 << 32); + rz_write_le64(buf, opcode12); + rz_buf_write_at(buf_patched, patch_addr, buf, 8); + } else { + if (bitmask != 0xff && bitmask != 0xffff && bitmask != UT64_MAX) { + // Reposition bits of val to fit bit position in the opcode. + ut64 pos = 1, vpos = 1; + ut64 opcode_val = 0; + for (ut8 i = 0; i < word * 8; ++i) { + if (bitmask & pos) { + opcode_val |= (val & vpos); + vpos = vpos << 1; + } + pos = pos << 1; + } + } else { + val = val & bitmask; + } + rz_buf_read_at(buf_patched, patch_addr, buf, 4); + ut64 opcode = rz_read_le32(buf); + opcode &= ~bitmask; + opcode |= val; + rz_write_le32(buf, opcode); + rz_buf_write_at(buf_patched, patch_addr, buf, 4); + } +} + +static void patch_reloc(struct Elf_(rz_bin_elf_obj_t) * obj, RzBinElfReloc *rel, ut64 S, ut64 B, ut64 L, ut64 GOT) { ut16 e_machine = obj->ehdr.e_machine; - ut64 val; + ut64 val = 0; ut64 A = rel->addend, P = rel->vaddr; + RzBinRelocFormularSymbols formular_sym = { .A = A, .B = B, .GOT = GOT, .L = L, .S = S, .P = P, .MB = 0, .G = 0, .GP = 0, .T = 0, .TLS = 0 }; ut64 patch_addr = rel->paddr != UT64_MAX ? rel->paddr : Elf_(rz_bin_elf_v2p_new)(obj, rel->vaddr); ut8 buf[8]; switch (e_machine) { + case EM_QDSP6: + patch_reloc_hexagon(obj->buf_patched, patch_addr, rel->type, &formular_sym); + break; case EM_ARM: val = S + A; rz_write_le32(buf, val); @@ -792,6 +1038,24 @@ static void patch_reloc(struct Elf_(rz_bin_elf_obj_t) * obj, RzBinElfReloc *rel, } } +static ut64 get_got_addr(ELFOBJ *bin) { + if (!Elf_(rz_bin_elf_has_sections)(bin)) { + return 0; + } + + RzBinElfSection *section = Elf_(rz_bin_elf_get_section_with_name)(bin, ".got"); + if (section) { + return section->offset; + } + + section = Elf_(rz_bin_elf_get_section_with_name)(bin, ".got.plt"); + if (section) { + return section->offset; + } + + return 0; +} + static RzBinReloc *reloc_convert(ELFOBJ *bin, RzBinElfReloc *rel, ut64 GOT) { rz_return_val_if_fail(bin && rel, NULL); @@ -946,6 +1210,9 @@ static void patch_relocs(RzBinFile *bf, ELFOBJ *bin) { return; } RzBinElfReloc *reloc; + ut64 got_addr = get_got_addr(bin); + ut64 baddr = bf->o->opts.baseaddr; + rz_bin_elf_foreach_relocs(bin, reloc) { ut64 sym_addr = 0; if (reloc->sym) { @@ -964,8 +1231,7 @@ static void patch_relocs(RzBinFile *bf, ELFOBJ *bin) { } } } - // TODO relocation types B, L - patch_reloc(bin, reloc, sym_addr, 0, sym_addr); + patch_reloc(bin, reloc, sym_addr, baddr, sym_addr, got_addr); reloc->target_vaddr = sym_addr; } rz_bin_reloc_target_builder_free(targets); @@ -1229,24 +1495,6 @@ static RzList *libs(RzBinFile *bf) { return Elf_(rz_bin_elf_get_libs)(bf->o->bin_obj); } -static ut64 get_got_addr(ELFOBJ *bin) { - if (!Elf_(rz_bin_elf_has_sections)(bin)) { - return 0; - } - - RzBinElfSection *section = Elf_(rz_bin_elf_get_section_with_name)(bin, ".got"); - if (section) { - return section->offset; - } - - section = Elf_(rz_bin_elf_get_section_with_name)(bin, ".got.plt"); - if (section) { - return section->offset; - } - - return 0; -} - static RzList *relocs(RzBinFile *bf) { rz_return_val_if_fail(bf && bf->o && bf->o->bin_obj, NULL); RzList *ret = NULL; diff --git a/librz/core/casm.c b/librz/core/casm.c index dfa4aa38e6a..f8704343b83 100644 --- a/librz/core/casm.c +++ b/librz/core/casm.c @@ -262,15 +262,26 @@ RZ_API RzList *rz_core_asm_strsearch(RzCore *core, const char *input, ut64 from, idx++; // TODO: honor mininstrsz continue; } - ut64 val = analop.val; // maybe chk for ptr or others? + ut64 val = analop.val; // Referenced value + bool match = (val != UT64_MAX && val >= usrimm && val <= usrimm2); + + if (!match) { + for (size_t i = 0; i < 6; ++i) { + st64 v = analop.analysis_vals[i].imm; + match = (v != ST64_MAX && v >= usrimm && v <= usrimm2); + if (match) { + break; + } + } + } if (!match) { ut64 val = analop.disp; match = (val != UT64_MAX && val >= usrimm && val <= usrimm2); } if (!match) { - ut64 val = analop.ptr; - match = (val != UT64_MAX && val >= usrimm && val <= usrimm2); + st64 val = analop.ptr; + match = (val != ST64_MAX && val >= usrimm && val <= usrimm2); } if (match) { if (!(hit = rz_core_asm_hit_new())) { diff --git a/librz/core/cconfig.c b/librz/core/cconfig.c index 5b07e6d7764..c5991cac07b 100644 --- a/librz/core/cconfig.c +++ b/librz/core/cconfig.c @@ -843,13 +843,20 @@ static bool cb_emuskip(void *user, void *data) { return true; } -static bool cb_asm_armimm(void *user, void *data) { +static bool cb_asm_immhash(void *user, void *data) { RzCore *core = (RzCore *)user; RzConfigNode *node = (RzConfigNode *)data; core->rasm->immdisp = node->i_value ? true : false; return true; } +static bool cb_asm_immsign(void *user, void *data) { + RzCore *core = (RzCore *)user; + RzConfigNode *node = (RzConfigNode *)data; + core->rasm->immsign = node->i_value; + return true; +} + static bool cb_asm_invhex(void *user, void *data) { RzCore *core = (RzCore *)user; RzConfigNode *node = (RzConfigNode *)data; @@ -2413,7 +2420,9 @@ static bool cb_tracetag(void *user, void *data) { } static bool cb_utf8(void *user, void *data) { + RzCore *core = (RzCore *)user; RzConfigNode *node = (RzConfigNode *)data; + core->rasm->utf8 = (bool)node->i_value; rz_cons_set_utf8((bool)node->i_value); return true; } @@ -3080,7 +3089,8 @@ RZ_API int rz_core_config_init(RzCore *core) { SETI("asm.hint.pos", 1, "Shortcut hint position (-1, 0, 1)"); SETBPREF("asm.slow", "true", "Perform slow analysis operations in disasm"); SETBPREF("asm.decode", "false", "Use code analysis as a disassembler"); - SETICB("asm.imm.arm", false, &cb_asm_armimm, "Display # for immediates in ARM"); + SETICB("asm.imm.hash", 0, &cb_asm_immhash, "Display # for immediates in ARM and Hexagon (0 = on)"); + SETCB("asm.imm.sign", "true", &cb_asm_immsign, "False: Print signed immediates in unsigned representation. True: Print them with sign."); SETBPREF("asm.imm.str", "true", "Show immediates values as strings"); SETBPREF("asm.imm.trim", "false", "Remove all offsets and constants from disassembly"); SETBPREF("asm.indent", "false", "Indent disassembly based on reflines depth"); diff --git a/librz/include/rz_analysis.h b/librz/include/rz_analysis.h index a885783c8bb..e7d171556ed 100644 --- a/librz/include/rz_analysis.h +++ b/librz/include/rz_analysis.h @@ -838,6 +838,7 @@ typedef struct rz_analysis_op_t { RzAnalysisOpDirection direction; st64 ptr; /* reference to memory */ /* XXX signed? */ ut64 val; /* reference to value */ /* XXX signed? */ + RzAnalysisValue analysis_vals[6]; /* Analyzable values */ int ptrsize; /* f.ex: zero extends for 8, 16 or 32 bits only */ st64 stackptr; /* stack pointer */ int refptr; /* if (0) ptr = "reference" else ptr = "load memory of refptr bytes" */ diff --git a/librz/include/rz_asm.h b/librz/include/rz_asm.h index 201aa68a905..6a1290bd645 100644 --- a/librz/include/rz_asm.h +++ b/librz/include/rz_asm.h @@ -115,7 +115,9 @@ typedef struct rz_asm_t { int pcalign; int dataalign; int bitshift; - bool immdisp; // Display immediates with # symbol (for arm stuff). + bool immdisp; // Display immediates with # symbol (for arm/hexagon architectures). false = show hashs + bool immsign; // Print signed immediates as negative values, not their unsigned representation. + bool utf8; // Flag for plugins: Use utf-8 characters. HtPP *flags; int seggrn; bool pseudo; diff --git a/librz/include/rz_util/rz_hex.h b/librz/include/rz_util/rz_hex.h index 7761515c317..b8c514588f4 100644 --- a/librz/include/rz_util/rz_hex.h +++ b/librz/include/rz_util/rz_hex.h @@ -9,6 +9,7 @@ RZ_API int rz_hex_pair2bin(const char *arg); RZ_API int rz_hex_str2binmask(const char *in, ut8 *out, ut8 *mask); RZ_API int rz_hex_str2bin(const char *in, ut8 *out); RZ_API int rz_hex_bin2str(const ut8 *in, int len, char *out); +RZ_API void rz_hex_ut2st_str(const ut64 in, RZ_INOUT char *out, const int len); RZ_API char *rz_hex_bin2strdup(const ut8 *in, int len); RZ_API bool rz_hex_to_byte(ut8 *val, ut8 c); RZ_API int rz_hex_str_is_valid(const char *s); diff --git a/librz/reg/rvalue.c b/librz/reg/rvalue.c index 4f9831a9ef8..d86cfb41477 100644 --- a/librz/reg/rvalue.c +++ b/librz/reg/rvalue.c @@ -62,7 +62,6 @@ RZ_API ut64 rz_reg_get_value_big(RzReg *reg, RzRegItem *item, utX *val) { ret = val->v256.Low.Low; break; default: - eprintf("rz_reg_get_value_big: Bit size %d not supported\n", item->size); break; } return ret; @@ -130,7 +129,6 @@ RZ_API ut64 rz_reg_get_value(RzReg *reg, RzRegItem *item) { // XXX 128 & 256 bit return (ut64)rz_reg_get_longdouble(reg, item); default: - eprintf("rz_reg_get_value: Bit size %d not supported\n", item->size); break; } return 0LL; diff --git a/librz/util/hex.c b/librz/util/hex.c index c183640ee41..bd6926981c9 100644 --- a/librz/util/hex.c +++ b/librz/util/hex.c @@ -393,6 +393,25 @@ RZ_API int rz_hex_bin2str(const ut8 *in, int len, char *out) { return len; } +/** + * \brief Takes an unsigned integer and returns the signed integer in hex format as string. + * E.g.: 0xffffffffffffffff -> "-0x1" + * + * \param in The integer to convert to the signed string. + * \param out The buffer to write the signed hex string to. + * \param len Length of the out buffer. + * \return char* The signed integer as hex string. + */ +RZ_API void rz_hex_ut2st_str(const ut64 in, RZ_INOUT char *out, const int len) { + if (len < 20) { + RZ_LOG_FATAL("Output buffer too small for 64bit value.\n"); + } + char tmp[20]; + sprintf(tmp, "-0x%x", abs((st64)in)); + memcpy(out, tmp, 20); + return; +} + RZ_API char *rz_hex_bin2strdup(const ut8 *in, int len) { int i, idx; char tmp[5], *out; diff --git a/test/db/analysis/hexagon b/test/db/analysis/hexagon index 1239bb45fd2..bfdb7fbf569 100644 --- a/test/db/analysis/hexagon +++ b/test/db/analysis/hexagon @@ -1,19 +1,356 @@ NAME=hexagon jumps FILE=bins/elf/analysis/hexagon-hello-loop CMDS=< 0x00005128 jump 0x5128 -c 0x00005134 -> 0x00005138 jump 0x5138 -C 0x00005138 -> 0x000050e0 call sym.pHello -C 0x0000513c -> 0x000050f8 call sym.pWorld -c 0x00005140 -> 0x00005144 jump 0x5144 -c 0x00005150 -> 0x00005128 jump 0x5128 -call sym.pHello -call sym.pWorld +c 0x00005124 -> 0x00005128 ? jump 0x5128 +c 0x00005130 -> 0x00005154 ? if (P0) jump:nt 0x5154 +c 0x00005134 -> 0x00005138 [ jump 0x5138 +C 0x00005138 -> 0x000050e0 [ call sym.pHello +C 0x0000513c -> 0x000050f8 [ call sym.pWorld +c 0x00005140 -> 0x00005144 [ jump 0x5144 +c 0x00005150 -> 0x00005128 ? jump 0x5128 EOF RUN + +NAME=hexagon immext +FILE=bins/elf/analysis/hexagon-hello-loop +CMDS=<