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Tracking Issue for f16
and f128
float types
#116909
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A blocking issue should be added: ensure C compatibility with ABI-cafe or similar |
Implementation steps (massive todo list moved to the top post) @rustbot claim |
…=compiler-errors Fix `is_val_statically_known` for floats The LLVM intrinsic name for floats differs from the LLVM type name, so handle them explicitly. Also adds support for `f16` and `f128`. `f16`/`f128` tracking issue: rust-lang#116909
…=compiler-errors Fix `is_val_statically_known` for floats The LLVM intrinsic name for floats differs from the LLVM type name, so handle them explicitly. Also adds support for `f16` and `f128`. `f16`/`f128` tracking issue: rust-lang#116909
…=compiler-errors Fix `is_val_statically_known` for floats The LLVM intrinsic name for floats differs from the LLVM type name, so handle them explicitly. Also adds support for `f16` and `f128`. `f16`/`f128` tracking issue: rust-lang#116909
…=compiler-errors Fix `is_val_statically_known` for floats The LLVM intrinsic name for floats differs from the LLVM type name, so handle them explicitly. Also adds support for `f16` and `f128`. `f16`/`f128` tracking issue: rust-lang#116909
Rollup merge of rust-lang#129173 - beetrees:statically-known-float, r=compiler-errors Fix `is_val_statically_known` for floats The LLVM intrinsic name for floats differs from the LLVM type name, so handle them explicitly. Also adds support for `f16` and `f128`. `f16`/`f128` tracking issue: rust-lang#116909
…, r=<try> Add `f16` and `f128` inline ASM support for `aarch64` Adds `f16` and `f128` inline ASM support for `aarch64`. SIMD vector types are taken from [the ARM intrinsics list](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:`@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiesarchitectures=[A64]).` Based on the work of `@lengrongfu` in rust-lang#127043. Relevant issue: rust-lang#125398 Tracking issue: rust-lang#116909 `@rustbot` label +F-f16_and_f128 try-job: aarch64-gnu try-job: aarch64-apple
…, r=<try> Add `f16` and `f128` inline ASM support for `aarch64` Adds `f16` and `f128` inline ASM support for `aarch64`. SIMD vector types are taken from [the ARM intrinsics list](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:`@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiesarchitectures=[A64]).` Based on the work of `@lengrongfu` in rust-lang#127043. Relevant issue: rust-lang#125398 Tracking issue: rust-lang#116909 `@rustbot` label +F-f16_and_f128 try-job: aarch64-gnu try-job: aarch64-apple
…64, r=Amanieu Add `f16` and `f128` inline ASM support for `aarch64` Adds `f16` and `f128` inline ASM support for `aarch64`. SIMD vector types are taken from [the ARM intrinsics list](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:`@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiesarchitectures=[A64]).` Based on the work of `@lengrongfu` in rust-lang#127043. Relevant issue: rust-lang#125398 Tracking issue: rust-lang#116909 `@rustbot` label +F-f16_and_f128 try-job: aarch64-gnu try-job: aarch64-apple
Rollup merge of rust-lang#129536 - beetrees:f16-f128-inline-asm-aarch64, r=Amanieu Add `f16` and `f128` inline ASM support for `aarch64` Adds `f16` and `f128` inline ASM support for `aarch64`. SIMD vector types are taken from [the ARM intrinsics list](https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:`@navigationhierarchiesreturnbasetype=[float]&f:@navigationhierarchieselementbitsize=[16]&f:@navigationhierarchiesarchitectures=[A64]).` Based on the work of `@lengrongfu` in rust-lang#127043. Relevant issue: rust-lang#125398 Tracking issue: rust-lang#116909 `@rustbot` label +F-f16_and_f128 try-job: aarch64-gnu try-job: aarch64-apple
llvm/llvm-project#104915: |
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…anieu Support input/output in vector registers of s390x inline assembly (under asm_experimental_reg feature) This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types, floats (f32/f64/f128), and integers (i32/i64/i128) as input/output. This is unstable and gated under new `#![feature(asm_experimental_reg)]` (tracking issue: rust-lang#133416). If the feature is not enabled, only clober is supported as before. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | s390x | `vreg` | `vector` | `i32`, `f32`, `i64`, `f64`, `i128`, `f128`, `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` | This matches the list of types that are supported by the vector registers in LLVM: https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L301-L313 In addition to `core::simd` types and floats listed above, custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types other than i32/f32/i64/f64/i128, and relevant target features are currently unstable. Currently there is no SIMD type for s390x in `core::arch`, but this is tracked in rust-lang#130869. cc rust-lang#130869 about vector facility support in s390x cc rust-lang#125398 & rust-lang#116909 about f128 support in asm `@rustbot` label +O-SystemZ +A-inline-assembly
Rollup merge of rust-lang#131664 - taiki-e:s390x-asm-vreg-inout, r=Amanieu Support input/output in vector registers of s390x inline assembly (under asm_experimental_reg feature) This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types, floats (f32/f64/f128), and integers (i32/i64/i128) as input/output. This is unstable and gated under new `#![feature(asm_experimental_reg)]` (tracking issue: rust-lang#133416). If the feature is not enabled, only clober is supported as before. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | s390x | `vreg` | `vector` | `i32`, `f32`, `i64`, `f64`, `i128`, `f128`, `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` | This matches the list of types that are supported by the vector registers in LLVM: https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L301-L313 In addition to `core::simd` types and floats listed above, custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types other than i32/f32/i64/f64/i128, and relevant target features are currently unstable. Currently there is no SIMD type for s390x in `core::arch`, but this is tracked in rust-lang#130869. cc rust-lang#130869 about vector facility support in s390x cc rust-lang#125398 & rust-lang#116909 about f128 support in asm `@rustbot` label +O-SystemZ +A-inline-assembly
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Support input/output in vector registers of s390x inline assembly (under asm_experimental_reg feature) This extends currently clobber-only vector registers (`vreg`) support to allow passing `#[repr(simd)]` types, floats (f32/f64/f128), and integers (i32/i64/i128) as input/output. This is unstable and gated under new `#![feature(asm_experimental_reg)]` (tracking issue: rust-lang/rust#133416). If the feature is not enabled, only clober is supported as before. | Architecture | Register class | Target feature | Allowed types | | ------------ | -------------- | -------------- | -------------- | | s390x | `vreg` | `vector` | `i32`, `f32`, `i64`, `f64`, `i128`, `f128`, `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` | This matches the list of types that are supported by the vector registers in LLVM: https://github.com/llvm/llvm-project/blob/llvmorg-19.1.0/llvm/lib/Target/SystemZ/SystemZRegisterInfo.td#L301-L313 In addition to `core::simd` types and floats listed above, custom `#[repr(simd)]` types of the same size and type are also allowed. All allowed types other than i32/f32/i64/f64/i128, and relevant target features are currently unstable. Currently there is no SIMD type for s390x in `core::arch`, but this is tracked in rust-lang/rust#130869. cc rust-lang/rust#130869 about vector facility support in s390x cc rust-lang/rust#125398 & rust-lang/rust#116909 about f128 support in asm `@rustbot` label +O-SystemZ +A-inline-assembly
Could we have |
Iirc we didn't do this originally because it would require further work in the compiler to feature gate properly (I don't remember why but |
This is a tracking issue for the RFC 3453 (rust-lang/rfcs#3453).
The feature gate for the issue is
#![feature(f16_and_f128)]
.From the RFC:
About tracking issues
Tracking issues are used to record the overall progress of implementation. They are also used as hubs connecting to other relevant issues, e.g., bugs or open design questions. A tracking issue is however not meant for large scale discussion, questions, or bug reports about a feature. Instead, open a dedicated issue for the specific matter and add the relevant feature gate label.
Steps
Unresolved questions
Implementation history
f16
andf128
#121728f16
andf128
step 2: intrinsics #121841 (comment)f16
andf128
step 3: compiler support & feature gate #121926rustc
more or less expects for primitives Add basic trait impls forf16
andf128
#123085f16
andf128
to rustdoc'sPrimitiveType
#123581Some parts are blocked on const eval, compiler builtins updates, and LLVM lowering bugs.hooray, this part is done!f16
andf128
step 4: basic library support #122470Debug
impl and some basic functions tof16
andf128
#123783f16
andf128
#126608f16
andf128
math functions #127027f16
/f128
float conversions compiler-builtins#593f128
compiler-builtins#606f128
float to integer conversion functions compiler-builtins#613__divtf3
compiler-builtins#622__powitf2
symbol forf128
integer exponentiation compiler-builtins#614test-float-parse
in Rust #127510f16
, which should be straightforward Addf16
formatting and parsing #127013f128
which will not be straightforward. Our current implementations are prettyu64
-dependent so they can't fit af128
mantissa. We could make them generic but probably want to instead use an implementation that is slower but better for size.f16
andf128
const eval for binary and unary operationations #126429f16
andf128
#127032Add encoding forAdd v0 symbol mangling forf16
andf128
#122106f16
andf128
#123816Ensure known demanglers get updated or at least have issues for adding the new typesunneeded with the forward-compatible demanglingf16
andf128
in assembly on platforms that support it #125398f16
andf128
inline ASM support foraarch64
#129536f16
andf128
inline ASM support forx86
andx86-64
#126417f16
inline ASM support for RISC-V #126530f16
inline ASM support for 32-bit ARM #126555f16
andf128
rustc_codegen_gcc#461 (merged upstream, waiting on sync)f16
andf128
rustc_codegen_cranelift#1461unimplemented
s andFIXME
s are removed from tools that need library supportf16
andf128
unimplemented!
/FIXME
s #126636f16
andf128
pattern matching stubs with real implementations #123088f16
/f128
FIXMEs that needed(NEG_)INFINITY
#127496f16_nan
f16
generates code that uses the incorrect ABI for compiler-rt #123885half
operations by using too much precision on several backends llvm/llvm-project#97975 LLVM miscompiles passing/returninghalf
on several backends by using lossy conversions llvm/llvm-project#97981@llvm.fabs.f16
generates call to__extendhfsf2
llvm/llvm-project#104915 (comment)f128
symbols on powerpc64 give inaccurate results #125109f128
from_bits
/to_bits
sometimes gets reversed on ppc #125102f128 as f16
casting bug LLVM f128 -> f16 conversion selection failure on powerpc64le llvm/llvm-project#92866fp128
->half
uses__trunctfhf2
but should be__trunckfhf2
llvm/llvm-project#98126+f
and+d
llvm/llvm-project#93894 (fixed upstream)half
orfp128
onarm64ec
llvm/llvm-project#94434wasm32
,half
operation results aren't correctly rounded between each operation llvm/llvm-project#96437fp128
causes compilation failures when compiling fornvptx64-nvidia-cuda
llvm/llvm-project#95471f128
Compiler crash when targetingmips64
when returningfp128
after calling a function returning{ i8, i128 }
llvm/llvm-project#96432powerpc64-ibm-aix
doesn't currently supportf128
arguments:fp128
arguments cause a compiler error onpowerpc64-ibm-aix
llvm/llvm-project#101545-Ctarget-feature
#116344 (and in particular Figure out which target features are required/incompatible for which ABI #131799) for all targets; those issues are mostly focusing on f32 and f64 so there might be more target features we have to worry about for f16/f128fma.f16
incorrectlyllvm.fma.f16
intrinsic is expanded incorrectly on targets without nativehalf
FMA support llvm/llvm-project#98389powi.f16
constant folding returns incorrect values Misoptimization:EarlyCSEPass
uses replacespowi.f16
withfloat
result llvm/llvm-project#98665Note that
unimplemented!("f16_f128")
and// FIXME(f16_f128)
is being used where relevant, to make the todo list easily greppable.Nice to have changes:
f16
: Add Natvis visualiser and debuginfo tests forf16
#127001f128
f16
andf128
support (add toFloatTy
) rust-analyzer#17451f16
andf128
under a nightly flag Lokathor/bytemuck#250The text was updated successfully, but these errors were encountered: