A toy Harvard-architecture uCPU realized in Verilog and VHDL. Assembler included. (C) 2022-2023, Stanislav Maslovski stanislav.maslovski@gmail.com
For documentation please see the comments within the source code.
Source code directory tree structure:
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rtl - single-cycle uCPU in Verilog.
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tb - simple testbench in Verilog.
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vhdl/rtl - single-cycle uCPU in VHDL.
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vhdl/tb - simple testbench in VHDL.
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pipelined/rtl - pipelined uCPU in Verilog.
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pipelined/tb - simple testbench in Verilog.
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assembler - two-pass assembler for uCPU written in C with example programs.
