SystemVerilog feature request: Default port values

[nakengelhardt]

It seems that icarus verilog does not currently support default port values (as defined in 23.2.2.4 of the SystemVerilog standard), like in the following example:

module test (input a = 0, output x); 
  assign x = a; 
endmodule

How difficult would this be to add? We have some issues with the Yosys cell simulation library (e.g. YosysHQ/yosys#2390) that would be best solved by using default values, but we want to avoid breaking simulation with iverilog.

[martinwhitaker]

At first glance this doesn't seem too hard. I'll see what I can do.

[martinwhitaker]

This is now supported in the master branch. I still need to do a bit more work to restrict it to constant expressions.

[martinwhitaker]

I've added the restriction that port default values must be constant expressions (as specified in the LRM), so marking this as done.

[nakengelhardt]

Awesome, thanks a lot!

[meawoppl]

Is there a flag you need to pass to support this?

[Forty-Bot]

Is there a flag you need to pass to support this?

-g2009 (or -g2012)

---

This doesn't support things like

module test (input a = 0, b, output x); 
  assign x = a; 
endmodule

which are allowed by the standard (see 23.2.2.2).

[larsclausen]

@Forty-Bot Currently only default values on output ports are supported. I have plans for adding support adding support for input default values. But feel free to create a ticket so this doesn't get forgotten.

[martinwhitaker]

@larsclausen, see earlier comments in this issue. I added support for default values on input ports in March last year.

@Forty-Bot, your example compiles without error. What exactly doesn't work?

[larsclausen]

@martinwhitaker My bad. I tested it a earlier this year and it did not work. But it looks as if it only does not work for top-level modules. Everywhere else it works.

[Forty-Bot]

Sorry, it should be something like

module test (input a, b = 0, output x); 
  assign x = a; 
endmodule

---

edit: I opened #754, which was resolved.

[nachiket]

Does this work for top-level ports with v12.0? I can't seem to make this work.

$ iverilog -g2012 test.sv

$ ./a.out
x=z,a=z
test.sv:5: $finish called at 2 (1s)

$ cat test.sv
module test (input a, input b = 0, output x);
  assign x = a;
  initial begin
    #1 $monitor("x=%d,a=%d",x,a);
    #1 $finish();
  end
endmodule

[larsclausen]

This is not working for top-level ports. Can you create a new ticket?

[nachiket]

Created #1202 -- not sure if this is what you meant by a new ticket.

[larsclausen]

yes, thanks.