Chapter3.tex

\chapter{Solutions for Chapter 3}

\ex{3.1}
\begin{circuit}{fig:3.1.1}{JFET current source}
    (0,0) node[njfet] (Q1) {$Q_1$}
    (Q1.D) to[generic, l=load] ++(0,2)
    (Q1.S) to[R, l=$R_\text{S}$] ++(0,-2) coordinate(RS)
    node[ground] {}
    (RS) to[short] (RS-|Q1.G)
    (Q1.G) to[short] (Q1.G|-RS)
\end{circuit}

From Figure 3.21 of the book, one can see that a drain current equal to \SI{1}{\milli\ampere} corresponds to a gate-source voltage of \SI{-0.6}{\volt}.
Therefore:
\[\mans{R_\text{S}=\frac{\SI{0.6}{\volt}}{\SI{1}{\milli\ampere}}=\SI{600}{\ohm}}\]

\ex{3.2}
At $V_\text{GS}=V_\text{G0}$:
\[r_\text{GS}=r_\text{G0}=\frac{1}{2k\left(V_\text{G0}-V_\text{th}\right)}\]
The ratio between $r_\text{DS}$ and $R_\text{G0}$ returns:
\[\mans{\frac{r_\text{DS}}{r_\text{G0}}=\frac{2k\left(V_\text{G0}-V_\text{th}\right)}{2k\left(V_\text{GS}-V_\text{th}\right)}}\]

\ex{3.3}
Being $g_\text{m}$ the differential conductance of the FET operated in aturation region, it can be expressed as:
\[g_\text{m}=\frac{\partial I_\text{D}}{\partial V_\text{GS}}=\frac{\partial}{\partial V_\text{GS}}k\left(V_\text{GS}-V_\text{th}\right)^2=2k\left(V_\text{GS}-V_\text{th}\right)\]
Therefore:
\[\mans{g_\text{m}=\frac{1}{r_\text{DS}}}\]

\ex{3.4}
\begin{enumerate}
    \item The voltage change across the drain-gate capacitance when the JFET is switched on ($V_\text{DS}=\SI{0}{\volt}$) is equal to \SI{50}{\volt}-(\SI{0}{\volt}-\SI{10}{\volt})=\SI{60}{\volt}. Considering a maximum current across this capacitance equal to \SI{1}{\ampere}:
    \[\mans{t_\text{ON}=\frac{\SI{60}{\volt}\,\SI{200}{\pico\farad}}{\SI{1}{\ampere}}=\SI{12}{\nano\second}}\]
    \item Since the current is equal to the charge over time, we have:
    \[\mans{t_\text{ON}=\frac{\SI{40}{\nano\coulomb}}{\SI{1}{\ampere}}=\SI{40}{\nano\second}}\]
\end{enumerate}

\ex{3.5}
The \SI{1}{\pico\farad} drain-source capacitance happens to be in series with the \SI{10}{\kilo\ohm} load resistance. The capacitive reactance is:
\[X_\text{DS}=\frac{1}{2\pi\SI{1}{\mega\hertz}\,\SI{1}{\pico\farad}}=\SI{160}{\kilo\ohm}\]
Therefore, the feedthrough is given by:
\[\mans{20\log_{10}\frac{\SI{10}{\kilo\ohm}}{\SI{10}{\kilo\ohm}+\SI{160}{\kilo\ohm}}=\SI{-25}{\decibel}}\]

\ex{3.6}
In this case, the output \SI{10}{\kilo\ohm} resistance is in parallel with the \SI{50}{\ohm} $R_\text{ON}$ resistance. Their equivalent resistance is about \SI{50}{\ohm}. Similarly to the previous exercise, the feedthorugh is given by:
\[\mans{20\log_{10}\frac{\SI{50}{\ohm}}{\SI{50}{\ohm}+\SI{160}{\kilo\ohm}}=\SI{-70}{\decibel}}\]

\ex{3.7}
\begin{circuit}{fig:3.7.1}{Zero ohm $R_\text{ON}$}
    (0,0) node[ocirc] {}
    node[above] {in}
    (0,0) to[R,l=$R_\text{S}$] ++(2,0) coordinate(Rs)
    to[C,l=$C_\text{D}$] ++(0,-2)
    node[ground] {}
    (Rs) -- ++(2,0) coordinate(out)
    to[C,l=$C_\text{S}$] ++(0,-2) 
    node[ground] {}
    (out) -- ++(1,0)
    node[ocirc] {}
    node[above] {out}
\end{circuit}

\begin{circuit}{fig:3.7.2}{\SI{75}{\ohm} $R_\text{ON}$}
    (0,0) node[ocirc] {}
    node[above] {in}
    (0,0) to[short] ++(1,0) coordinate(Rs)
    to[C,l=$C_\text{D}$] ++(0,-2)
    node[ground] {}
    (Rs) to[R,l=$R_\text{ON}$] ++(2.5,0) coordinate(out)
    to[C,l=$C_\text{S}$] ++(0,-2) 
    node[ground] {}
    (out) -- ++(1,0)
    node[ocirc] {}
    node[above] {out}
\end{circuit}

For this exercise we assume that the load resistance of \SI{100}{\kilo\ohm} does not load the circuit. 
\begin{enumerate}
    \item The circuit is that of Figure \ref{fig:3.7.1}. Since $C_\text{D}=C_\text{S}=C_\text{T}=\SI{8}{\pico\farad}$, there is a single pole at the frequency $f_\text{p}$:
    \[\mans{f_\text{p}=\frac{1}{4\pi R_\text{S}C_\text{T}}\approx\SI{1}{\mega\hertz}}\]
    \item In this case the circuit is depicted in Figure \ref{fig:3.7.2}. The circuit has one pole at DC and another pole at $f_\text{p}$:
    \[\mans{f_\text{p}=\frac{1}{2\pi R_\text{ON}C_\text{T}}\approx\SI{265}{\mega\hertz}}\]
\end{enumerate}

\ex{3.8}
\begin{circuit}{fig:3.8.1}{OFF-OFF}
    (0,0) node[ocirc] {}
    node[above] {in}
    (0,0) to[R,l=$R_\text{S}$] ++(2,0) coordinate(Rs)
    to[C,l_=$C_\text{C}$] ++(0,-2)
    to[C,l=$C_\text{DS}$] ++(2,0)
    (Rs) to[C,l=$C_\text{DS}$] ++(2,0)
    to[C,l=$C_\text{C}$] ++(0,-2) 
    -- ++(1,0)
    node[ocirc] {}
    node[above] {out}
    to[R,l=$R_\text{out}$] ++(0,-2)
    node[ground] {}
\end{circuit}
\begin{circuit}{fig:3.8.2}{OFF-ON}
    (0,0) node[ocirc] {}
    node[above] {in}
    (0,0) to[R,l=$R_\text{S}$] ++(2,0) coordinate(Rs)
    to[C,l_=$C_\text{C}$] ++(0,-2)
    to[short] ++(2,0)
    (Rs) to[C,l=$C_\text{DS}$] ++(2,0)
    to[C,l=$C_\text{C}$] ++(0,-2) 
    -- ++(1,0)
    node[ocirc] {}
    node[above] {out}
    to[R,l=$R_\text{out}$] ++(0,-2)
    node[ground] {}
\end{circuit}
\begin{circuit}{fig:3.8.3}{ON-OFF}
    (0,0) node[ocirc] {}
    node[above] {in}
    (0,0) to[R,l=$R_\text{S}$] ++(2,0) coordinate(Rs)
    to[C,l_=$C_\text{C}$] ++(0,-2)
    to[C,l=$C_\text{DS}$] ++(2,0)
    (Rs) to[short] ++(2,0)
    to[C,l=$C_\text{C}$] ++(0,-2) 
    -- ++(1,0)
    node[ocirc] {}
    node[above] {out}
    to[R,l=$R_\text{out}$] ++(0,-2)
    node[ground] {}
\end{circuit}
\begin{circuit}{fig:3.8.4}{ON-ON}
    (0,0) node[ocirc] {}
    node[above] {in}
    (0,0) to[R,l=$R_\text{S}$] ++(2,0) coordinate(Rs)
    to[C,l_=$C_\text{C}$] ++(0,-2)
    to[short] ++(2,0)
    (Rs) to[short] ++(2,0)
    to[C,l=$C_\text{C}$] ++(0,-2) 
    -- ++(1,0)
    node[ocirc] {}
    node[above] {out}
    to[R,l=$R_\text{out}$] ++(0,-2)
    node[ground] {}
\end{circuit}

\begin{enumerate}
\item In this case the reference circuit is depicted in Figure \ref{fig:3.8.1}. The cross-coupling is given by:
\[\mans{20\log_{10}\frac{R_\text{out}}{R_\text{out}+R_\text{S}+0.5(X_\text{C}+X_\text{DS})}=\SI{-10.75}{\decibel}}\]
being $X_\text{C}=\frac{1}{2\pi f\,C_\text{C}}=\SI{320}{\kilo\ohm}$ and $X_\text{DS}=\frac{1}{2\pi f\,C_\text{DS}}=\SI{160}{\kilo\ohm}$
\item In this case the reference circuit is depicted in Figure \ref{fig:3.8.2}. The cross-coupling is given by:
\[\mans{20\log_{10}\frac{R_\text{out}}{R_\text{out}+R_\text{S}+\frac{X_\text{C}(X_\text{C}+X_\text{DS})}{2X_\text{C}+X_\text{DS}}}=\SI{-9.6}{\decibel}}\]
\item In this case the reference circuit is depicted in Figure \ref{fig:3.8.3}. The cross-coupling is the same as before
\item In this case the reference circuit is depicted in Figure \ref{fig:3.8.4}. The cross-coupling is given by:
\[\mans{20\log_{10}\frac{R_\text{out}}{R_\text{out}+R_\text{S}+0.5X_\text{C}}=\SI{-8.6}{\decibel}}\]
\end{enumerate}

\ex{3.9}
\begin{enumerate}
    \item Considering the different combinations of resistors, the \SI{-3}{\decibel} frequencies can be computed as:
    \[\mans{f_\text{3dB,n}=\frac{n\,G_\text{10k}}{2\pi C}\quad n=1\dots 15}\]
    where $C=\SI{0.01}{\micro\farad}$ and $G_\text{10k}=\SI{0.1}{\milli\siemens}$
    \item The glitch amplitude voltage can be computed as:
    \[\mans{\Delta V=\frac{\SI{20}{\pico\coulomb}}{C}=\SI{2}{\milli\volt}}\]
\end{enumerate}

\ex{3.10}
The peak output current that the buffer has to provide can be given as the peak time derivative of the output voltage across the \SI{10}{\nano\farad} capacitor multiplied by its value:
\[\mans{I_\text{p}=\left.\SI{10}{\nano\farad}\frac{dV}{dt}\right|_\text{p}=\SI{10}{\nano\farad}\,2\pi\SI{10}{\kilo\hertz}\,\SI{1}{\volt}=\SI{0.6}{\milli\ampere}}\]

\ex{3.11}
\begin{circuit}{fig:3.11.1}{BJT-based inverter logic circuit}
    (0,0) node[npn] (Q1) {$Q_1$}
    (Q1.C) -- ++(0,0.5)
    node[pnp, anchor=C] (Q2) {$Q_2$}
    (Q2.E) -- ++(-0.5,0) -- ++(1,0)
    node[above] {$V_\text{cc}$}
    (Q1.B) to[short] (Q2.B)
    ($(Q1.B)!0.5!(Q2.B)$) to[short] ++(-0.5,0)
    node[ocirc] {}
    node[above] {in}
    ($(Q1.C)!0.5!(Q2.C)$) to[short] ++(0.5,0)
    node[ocirc] {}
    node[above] {out}
    (Q1.E) node[ground] {}
\end{circuit}

The circuit of Figure \ref{fig:3.11.1} represents the complementary bjt inverter. It's easy to see that without a proper bias, if the input is grounder (low level) the $V_\text{BE}$ of the pnp transistor is equal to $V_\text{cc}$ which is likely to damage the transistor in a very short time

\ex{3.12}
\begin{circuit}{fig:3.12.1}{Logic AND symbols}
    (0,0) node[nand port] (nand) {}
    node[not port, anchor=in] (not) {}
    (nand.in 1) node[above] {a}
    (nand.in 2) node[above] {b}
    (not.out) node[above] {out}
\end{circuit}

\begin{circuit}{fig:3.12.2}{Logic AND symbol and circuit}
    (0,0) node[nmos] (Q1) {$Q_1$}
    (Q1.D) -- ++(0,0.5)
    node[pmos, anchor=D] (Q2) {$Q_2$}
    (Q2.S) -- ++(-0.5,0) -- ++(1,0)
    node[above] {$V_\text{dd}$}
    (Q1.G) to[short] (Q2.G)
    ($(Q1.B)!0.5!(Q2.B)$) to[short] ++(-0.5,0) coordinate(NOT_IN)
    node[ocirc] {}
    ($(Q1.D)!0.5!(Q2.D)$) to[short] ++(0.5,0)
    node[ocirc] {}
    node[above] {out}
    (Q1.S) node[ground] {}
    (NOT_IN) node[nand port, anchor=out] (nand) {}
    (nand.in 1) node[above] {a}
    (nand.in 2) node[above] {b}
\end{circuit}
In order to transform a NAND port into an AND port, we can use a NOT port as shown in Figures \ref{fig:3.12.1} and \ref{fig:3.12.2}

\ex{3.13}
\begin{circuit}{fig:3.13.1}{NOR circuit}
    (0,0) node[nmos] (Q1) {$Q_1$}
    (Q1.D) -- ++(0,0.5) coordinate(A)
    -- ++(2,0) coordinate(B)
    -- ++(0,-0.5) 
    node[nmos, anchor=D, xscale=-1] (Q2) {\ctikzflipx{$Q_2$}}
    (Q1.S) to[short] (Q2.S)
    ($(Q1.S)!0.5!(Q2.S)$) to[short] ++(0,-0.5)
    node[ground] {}
    ($(A)!0.5!(B)$) to[short] ++(0,0.5)
    node[pmos, anchor=D] (Q3) {$Q_3$}
    (Q3.S) node[pmos, anchor=D, xscale=-1] (Q4) {\ctikzflipx{$Q_4$}}
    (Q4.S) ++(-0.5,0) -- ++(1,0)
    node[above] {$V_\text{DD}$}
    (Q1.G) to[short] (Q1.G |- Q3.G) coordinate(C)
    to[short] (Q3.G)
    ($(Q1.G)!0.5!(C)$) to[short] ++(-0.5,0)
    node[ocirc] {}
    node[above] {a}
    (Q2.G) to[short] (Q2.G |- Q4.G) coordinate(D)
    to[short] (Q4.G)
    ($(Q2.G)!0.5!(D)$) to[short] ++(0.5,0)
    node[ocirc] {}
    node[above] {b}
    (Q3.D) to[short] ++(0.5,0)
    node[ocirc] {}
    node[above] {out}
\end{circuit}

The solution is presented in Figure \ref{fig:3.13.1}

\ex{3.14}
\begin{circuit}{fig:3.14.1}{Logic OR symbols}
    (0,0) node[nor port] (nor) {}
    node[not port, anchor=in] (not) {}
    (nor.in 1) node[above] {a}
    (nor.in 2) node[above] {b}
    (not.out) node[above] {out}
\end{circuit}

The OR circuit can be easily obtained by cascading a NOT circuit to the NOR circuit designed in exercise 3.13.

\ex{3.15}
\begin{circuit}{fig:3.15.1}{Three ports NAND circuit}
    (0,0) node[pmos] (Q1) {$Q_1$}
    (2,0) node[pmos] (Q2) {$Q_2$}
    (4,0) node[pmos] (Q3) {$Q_3$}
    (Q1.S) ++(-0.5,0) -- (Q3.S) -- ++(0.5,0)
    node[above] {$V_\text{DD}$}
    (Q1.D) to[short,*-*] (Q2.D)
    (Q2.D) to[short,*-*] (Q3.D)
    (Q3.D) to[short] ++(0,-0.5)
    node[nmos, anchor=D] (Q4) {$Q_4$}
    (Q4.S) node[nmos, anchor=D] (Q5) {$Q_5$}
    (Q5.S) node[nmos, anchor=D] (Q6) {$Q_6$}
    (Q6.S) node[ground] {}
    (Q1.G) to[short,-*] (Q1.G |- Q4.G)
    ++(-0.5,0)
    node[ocirc] {}
    node[above] {a}
    to[short] (Q4.G)
    (Q2.G) to[short,-*] (Q2.G |- Q5.G)
    ++(-0.5,0)
    node[ocirc] {}
    node[above] {b}
    to[short] (Q5.G)
    (Q3.G) to[short,-*] (Q3.G |- Q6.G)
    ++(-0.5,0)
    node[ocirc] {}
    node[above] {c}
    to[short] (Q6.G)
    (Q4.D) to[short] ++(0.5,0)
    node[ocirc] {}
    node[above] {out}
\end{circuit}
The solution is represented in Figure \ref{fig:3.15.1}. The gate comply with the following truth table
\begin{center}
\begin{tabular}{c c c | c}
    a & b & c & out \\
    \hline
    1 & 1 & 1 & 0 \\
    1 & 1 & 0 & 1 \\
    1 & 0 & 0 & 1 \\
    1 & 0 & 1 & 1 \\
    0 & 0 & 1 & 1 \\
    0 & 1 & 0 & 1 \\
    0 & 1 & 1 & 1 \\
    0 & 0 & 0 & 1 \\
\end{tabular}
\end{center}

\ex{3.16}
As soon as the voltage across $R_5$ gets higher than the $V_\text{EB}$ threshold of Q3, a current starts flowing from its emitter to its collector. As long as Q1 does not saturate, its collector current is fixed (current sink) and Q3 collector current flows into $R_2$. This increases $V_\text{SG}$ of Q2 until it becomes higher than its threshold $V_\text{SG}^\text{th}$
The maximum allowed current $I_\text{S}^\text{max}$ can be computed as it follows:
\[I_\text{C}^\text{Q1}=\frac{\SI{3.3}{\volt}-\SI{0.65}{\volt}}{\SI{15}{\kilo\ohm}}=\SI{0.18}{\milli\ampere}\]
Therefore:
\[V_\text{SG}^\text{th}=(I_\text{C}^\text{Q1}-I_\text{C}^\text{Q3})R_2-R_5I_\text{lim}\]
Since:
\[I_\text{C}^\text{Q3}=I_\text{S}e^\frac{I_\text{lim}R_5}{V_\text{T}}\]
One can obtain, by substituting $I_\text{C}^\text{Q3}$ in the expression for $V_\text{SG}^\text{th}$:
\[V_\text{SG}^\text{th}=(I_\text{C}^\text{Q1}-I_\text{S}e^\frac{I_\text{lim}R_5}{V_\text{T}})R_2-R_5I_\text{lim}\]
This equation can be solved numerically and it gives $I_\text{lim}=\SI{1.25}{\ampere}$ if $V_\text{SG}^\text{th}=\SI{5}{\volt}$ or $I_\text{lim}=\SI{1.29}{\ampere}$ if $V_\text{SG}^\text{th}=\SI{0}{\volt}$.
In both cases, the $V_\text{EB}$ of Q3 is approximately it diode voltage drop \SI{0.65}{\volt}. Therefore,  $I_\text{lim}$ can be approximately obtained is a easire way as:
\[\mans{I_\text{lim}=\frac{\SI{0.65}{\volt}}{R_5}=\SI{1.3}{\volt}}\]

\ex{3.17}
From the exercise data we have the following requirements:
\begin{itemize}
    \item Q2 $V_\text{SD}^\text{max}=\SI{175}{\volt}$
    \item $V_\text{CE}^\text{max}=\SI{175}{\volt}$
    \item $V^\text{LED}=38\,\SI{3.2}{\volt}=\SI{121.6}{\volt}$
    \item Q2 $I_\text{SD}^\text{max}=\SI{0.5}{\ampere}$
\end{itemize}
From Table at page 202 we see that the p-channel MOSFET FQP9P25 is suitable. Looking at the datasheet we see that the $V_\text{GS}^\text{th}=-\SI{5}{\volt}$ and $R_\text{ON}=\SI{0.62}{\ohm}$. Aiming for a $V_\text{GS}$ about \SI{-10}{\volt}, we can compute the ratio of $R_2$ and $R_1$ as:
\[\frac{R_2}{R_1}=\frac{\SI{10}{\volt}}{\SI{3.3}{\volt}-\SI{0.65}{\volt}=3.77}\]
Since the minimum supply voltage is equal to \SI{155}{\volt}, we have to account for a resistor in series with the led equal to:
\[\frac{\SI{155}{\volt}-\SI{121.6}{\volt}}{\SI{0.5}{\ampere}}=\SI{67}{\ohm}\]
From the previous exercise, if we want to limit the drain current through Q2 at \SI{0.5}{\ampere}, we should use a resistor $R_5$ equal to
\[R_5=\frac{\SI{0.65}{\volt}}{\SI{0.5}{\ampere}}=\SI{1.3}{\ohm}\]
For the transistor Q1, from Table 2.1 at page 74 we choose the model MPSA92 whose maximum collector current is equal to \SI{30}{\milli\ampere} and maximum power \SI{625}{\milli\watt}. The maximum power thorugh Q1 can be obtained as:
\[P^{Q1}=V_\text{CE}I_\text{C}=[\SI{175}{\volt}-I_\text{C}(R_1+R_2)]I_\text{C}\leq\SI{625}{\milli\watt}\]
Since:
\[I_\text{C}=\frac{\SI{3.3}{\volt}-\SI{0.65}{\volt}}{R_1}\]
Accounting for a Q1 power of \SI{500}{\milli\watt}:
\[R_1=\SI{860}{\ohm}\]
and
\[R_2=3.77\,R_1=\SI{3.2}{\kilo\ohm}\]
The maximum power dissipated by Q2 can be easily computed accounting for a maximum drain current ($I_\text{D}^\text{Q2}$) equal to \SI{0.5}{\ampere}:
\[P^\text{Q2}={I_\text{D}^\text{Q2}}^2R_\text{ON}=\SI{155}{\milli\watt}\]
Finally, from the datasheet of the FQP9P25 MOSFET, for a single \SI{10}{\milli\second} pulse, the tehermal impedance from junction to case is equal to \SI{0.3}{\celsius\per\watt}. Supposing that the case thermal capacitance is such as the case temperature is not affected by the \SI{10}{\milli\second} pulse, the junction temperature increase will be equal to:
\[\Delta T^\text{Q2}= \SI{0.3}{\celsius\per\watt}\,\SI{155}{\milli\watt}=\SI{0.04}{\celsius}\]
However, if we account for a continous \SI{10}{\milli\second} pulse with \num{0.5} duty cycle, the tehermal impedance from junction to case becomes equal to \SI{0.5}{\celsius\per\watt}. If we neglect the case thermal capacitance, the  junction temperature increase will be equal to:
\[\Delta T^\text{Q2}= (\SI{0.5}{\celsius\per\watt}+\SI{1.04}{\celsius\per\watt})\,\SI{155}{\milli\watt}=\SI{0.24}{\celsius}\]
where \SI{1.04}{\celsius\per\watt} is the thermal resistance from case to ambient as given in the datasheet.

\ex{3.18}
The goal can be achieved by means of an analog switch of the type of Figure 3.106 B at the input of the circuit. With respect to the circuit of Figure 3.106 B, a resistor $R_2$ with a resistance of \SI{55}{\kilo\ohm} is needed because of the lower $V_\text{logic}$ equal to \SI{3}{\volt}.