-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathstm32f4xx_usb_hs.c
1940 lines (1655 loc) · 72.4 KB
/
stm32f4xx_usb_hs.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/** @file stm32f4xx_usb_fs.c
* \brief Driver for STM32F4x5/4x7 device
*
* This driver is written according to STM32F4x5_4x7 reference manual
* (ref. RM0090) Rev 11.
**/
#include "autoconf.h"
#ifdef CONFIG_USR_DRV_USB_HS
#include "stm32f4xx_usb_hs.h"
#include "stm32f4xx_usb_hs_regs.h"
#include "api/usb_control.h"
#include "libc/syscall.h"
#include "libc/stdio.h"
#include "libc/nostd.h"
#include "libc/string.h"
#include "libc/sanhandlers.h"
#define ZERO_LENGTH_PACKET 0
#define OUT_NAK 0x01
#define DataOUT 0x02
#define Data_Done 0x03
#define SETUP_Done 0x04
#define SETUP 0x06
#define USB_REG_CHECK_TIMEOUT 50
#define USB_HS_RX_FIFO_SZ 512
#define USB_HS_TX_FIFO_SZ 512
#define USB_HS_DEBUG 0
#if USB_HS_DEBUG
#define log_printf(...) aprintf(__VA_ARGS__)
#else
#define log_printf(...) {};
#endif
/**
* \struct setup_packet
* \brief Setup packet, used to transfer data on EP0
*/
static struct {
void (*data_sent_callback)(void);
void (*data_received_callback)(uint32_t);
} usb_hs_callbacks;
static uint8_t setup_packet[8];
static volatile uint8_t *buffer_ep0;
static volatile uint32_t buffer_ep0_idx;
static volatile uint32_t buffer_ep0_size;
static volatile uint8_t *buffer_ep1;
static volatile uint32_t buffer_ep1_idx;
static volatile uint32_t buffer_ep1_size;
#define USB_MAX_ISR 32
/******* Helpers to handle delays *****************/
/* [RB] FIXME: these are quick and dirty ways of 'delaying',
* we should migrate to cleaner ways asap ...
*/
/* Get ticks/time in milliseconds */
static uint64_t platform_get_ticks(void){
uint64_t tick = 0;
sys_get_systick(&tick, PREC_MILLI);
return tick;
}
/* Fixed delay of a given number of milliseconds */
static void delay_ms(uint32_t ms_delay){
unsigned long long start_tick, curr_tick;
start_tick = platform_get_ticks();
/* Now wait */
curr_tick = start_tick;
while((curr_tick - start_tick) <= ms_delay){
curr_tick = platform_get_ticks();
}
return;
}
/**************************************************/
static usb_ep_error_t usb_hs_driver_TXFIFO_flush(uint8_t ep){
uint32_t count = 0;
/* Select which ep to flush and do it
* This is the FIFO number that must be flushed using the TxFIFO Flush bit.
* This field must not be changed until the core clears the TxFIFO Flush bit.
*/
count = 0;
while (get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_TXFFLSH)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! Waiting for the core to clear the TxFIFO Flush bit GRSTCTL:TXFFLSH\n");
}
return USB_ERROR_BUSY;
}
/*
* The application must write this bit only after checking that the core is neither writing to the
* TxFIFO nor reading from the TxFIFO. Verify using these registers:
*/
/* FIXME Read: the NAK effective interrupt ensures the core is not reading from the FIFO */
/* Write: the AHBIDL bit in OTG_HS_GRSTCTL ensures that the core is not writing anything to the FIFO */
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, ep, USB_HS_GRSTCTL_TXFNUM);
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, 1, USB_HS_GRSTCTL_TXFFLSH);
count = 0;
while (get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_TXFFLSH)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! Waiting for the core to clear the TxFIFO Flush bit GRSTCTL:TXFFLSH\n");
}
return USB_ERROR_BUSY;
}
return 0;
}
static usb_ep_error_t usb_hs_driver_TXFIFO_flush_all(void){
unsigned int ep;
usb_ep_error_t ret;
/* [RB]: FIXME: put a macro defining the number of endpoints */
for(ep = 0; ep < 4; ep++){
if((ret = usb_hs_driver_TXFIFO_flush(ep)) != USB_OK){
return ret;
}
}
return USB_OK;
}
static usb_ep_error_t usb_hs_driver_RXFIFO_flush(void){
uint32_t count = 0;
/* Select which ep to flush and do it
* This is the FIFO number that must be flushed using the TxFIFO Flush bit.
* This field must not be changed until the core clears the TxFIFO Flush bit.
*/
count = 0;
while (get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_RXFFLSH)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! Waiting for the core to clear the TxFIFO Flush bit GRSTCTL:RXFFLSH\n");
}
return USB_ERROR_BUSY;
}
/*
* The application must write this bit only after checking that the core is neither writing to the
* RxFIFO nor reading from the RxFIFO. Verify using these registers:
*/
/* FIXME Read: the NAK effective interrupt ensures the core is not reading from the FIFO */
/* Write: the AHBIDL bit in OTG_HS_GRSTCTL ensures that the core is not writing anything to the FIFO */
//set_reg(r_CORTEX_M_USB_HS_GRSTCTL, ep, USB_HS_GRSTCTL_RXFNUM);
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, 1, USB_HS_GRSTCTL_RXFFLSH);
count = 0;
while (get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_RXFFLSH)){
if (++count > USB_REG_CHECK_TIMEOUT)
log_printf("HANG! Waiting for the core to clear the RxFIFO Flush bit GRSTCTL:TXFFLSH\n");
return USB_ERROR_BUSY;
}
return 0;
}
void usb_hs_driver_device_connect(void){
set_reg(r_CORTEX_M_USB_HS_DCTL, 0, USB_HS_DCTL_SDIS);
}
/**
*
* The powered state can be exited by software with the soft disconnect feature. The DP pullup
* resistor is removed by setting the soft disconnect bit in the device control register (SDIS
* bit in OTG_HS_DCTL), causing a device disconnect detection interrupt on the host side
* even though the USB cable was not really removed from the host port.
*/
void usb_hs_driver_device_disconnect(void){
set_reg(r_CORTEX_M_USB_HS_DCTL, 1, USB_HS_DCTL_SDIS);
}
static const char *name = "usb-otg-hs";
void OTG_HS_IRQHandler(uint8_t irq __UNUSED, // IRQ number
uint32_t sr, // content of posthook.status,
uint32_t dr); // content of posthook.data)
static int dev_desc = 0;
void usb_hs_driver_map(void)
{
uint8_t ret;
ret = sys_cfg(CFG_DEV_MAP, dev_desc);
if (ret != SYS_E_DONE) {
log_printf("Unable to map USB device !!!\n");
}
}
static uint8_t usb_device_early_init(void) {
e_syscall_ret ret = 0;
device_t dev;
memset((void*)&dev, 0, sizeof(device_t));
memcpy(dev.name, name, strlen(name));
dev.address = USB_OTG_HS_BASE;
dev.size = 0x4000;
dev.irq_num = 1;
/* device is mapped voluntary and will be activated after the full
* authentication sequence
*/
dev.map_mode = DEV_MAP_VOLUNTARY;
/* IRQ configuration */
dev.irqs[0].handler = OTG_HS_IRQHandler;
dev.irqs[0].irq = OTG_HS_IRQ; /* starting with STACK */
dev.irqs[0].mode = IRQ_ISR_FORCE_MAINTHREAD; /* if ISR force MT immediat execution, use FORCE_MAINTHREAD instead of STANDARD, and activate FISR permission */
/*
* IRQ posthook configuration
* The posthook is executed at the end of the IRQ handler mode, *before* the ISR.
* It permit to clean potential status registers (or others) that may generate IRQ loops
* while the ISR has not been executed.
* register read can be saved into 'status' and 'data' and given to the ISR in 'sr' and 'dr' argument
*/
dev.irqs[0].posthook.status = 0x0014; /* SR is first read */
dev.irqs[0].posthook.data = 0x0018; /* Data reg is 2nd read */
dev.irqs[0].posthook.action[0].instr = IRQ_PH_READ;
dev.irqs[0].posthook.action[0].read.offset = 0x0014;
dev.irqs[0].posthook.action[1].instr = IRQ_PH_READ;
dev.irqs[0].posthook.action[1].read.offset = 0x0018;
dev.irqs[0].posthook.action[2].instr = IRQ_PH_MASK;
dev.irqs[0].posthook.action[2].mask.offset_dest = 0x14; /* MASK register offset */
dev.irqs[0].posthook.action[2].mask.offset_src = 0x14; /* MASK register offset */
dev.irqs[0].posthook.action[2].mask.offset_mask = 0x18; /* MASK register offset */
dev.irqs[0].posthook.action[2].mask.mode = 0; /* no binary inversion */
dev.irqs[0].posthook.action[3].instr = IRQ_PH_AND;
dev.irqs[0].posthook.action[3].and.offset_dest = 0x18; /* MASK register offset */
dev.irqs[0].posthook.action[3].and.offset_src = 0x14; /* MASK register offset */
dev.irqs[0].posthook.action[3].and.mask = USB_HS_GINTMSK_RXFLVLM_Msk; /* MASK register offset */
dev.irqs[0].posthook.action[3].and.mode = 1; /* binary inversion */
dev.irqs[0].posthook.action[4].instr = IRQ_PH_AND;
dev.irqs[0].posthook.action[4].and.offset_dest = 0x18; /* MASK register offset */
dev.irqs[0].posthook.action[4].and.offset_src = 0x14; /* MASK register offset */
dev.irqs[0].posthook.action[4].and.mask = USB_HS_GINTMSK_IEPINT_Msk; /* MASK register offset */
dev.irqs[0].posthook.action[4].and.mode = 1; /* binary inversion */
dev.irqs[0].posthook.action[5].instr = IRQ_PH_AND;
dev.irqs[0].posthook.action[5].and.offset_dest = 0x18; /* MASK register offset */
dev.irqs[0].posthook.action[5].and.offset_src = 0x14; /* MASK register offset */
dev.irqs[0].posthook.action[5].and.mask = USB_HS_GINTMSK_OEPINT_Msk; /* MASK register offset */
dev.irqs[0].posthook.action[5].and.mode = 1; /* binary inversion */
/* Now let's configure the GPIOs */
dev.gpio_num = 13;
/* ULPI_D0 */
dev.gpios[0].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[0].kref.port = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_D0].port;
dev.gpios[0].kref.pin = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_D0].pin; /* 3 */
dev.gpios[0].mode = GPIO_PIN_ALTERNATE_MODE;
dev.gpios[0].pupd = GPIO_NOPULL;
dev.gpios[0].type = GPIO_PIN_OTYPER_PP;
dev.gpios[0].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[0].afr = GPIO_AF_OTG_HS;
/* ULPI_CLK */
dev.gpios[1].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[1].kref.port = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_CLK].port;
dev.gpios[1].kref.pin = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_CLK].pin; /* 3 */
dev.gpios[1].mode = GPIO_PIN_ALTERNATE_MODE;
dev.gpios[1].pupd = GPIO_NOPULL;
dev.gpios[1].type = GPIO_PIN_OTYPER_PP;
dev.gpios[1].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[1].afr = GPIO_AF_OTG_HS;
for (uint8_t i = USB_HS_ULPI_D1; i <= USB_HS_ULPI_D7; ++i) {
/* INFO: for this loop to work, USB_HS_ULPI_D1 must start at index 2
* in the JSON file */
/* ULPI_Di */
dev.gpios[i].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[i].kref.port = usb_otg_hs_dev_infos.gpios[i].port;
dev.gpios[i].kref.pin = usb_otg_hs_dev_infos.gpios[i].pin;
dev.gpios[i].mode = GPIO_PIN_ALTERNATE_MODE;
dev.gpios[i].pupd = GPIO_NOPULL;
dev.gpios[i].type = GPIO_PIN_OTYPER_PP;
dev.gpios[i].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[i].afr = GPIO_AF_OTG_HS;
}
/* ULPI_STP */
dev.gpios[9].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[9].kref.port = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_STP].port;
dev.gpios[9].kref.pin = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_STP].pin; /* 3 */
dev.gpios[9].mode = GPIO_PIN_ALTERNATE_MODE;
dev.gpios[9].pupd = GPIO_NOPULL;
dev.gpios[9].type = GPIO_PIN_OTYPER_PP;
dev.gpios[9].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[9].afr = GPIO_AF_OTG_HS;
/* ULPI_DIR */
dev.gpios[10].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[10].kref.port = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_DIR].port;
dev.gpios[10].kref.pin = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_DIR].pin; /* 3 */
dev.gpios[10].mode = GPIO_PIN_ALTERNATE_MODE;
dev.gpios[10].pupd = GPIO_NOPULL;
dev.gpios[10].type = GPIO_PIN_OTYPER_PP;
dev.gpios[10].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[10].afr = GPIO_AF_OTG_HS;
/* ULPI_NXT */
dev.gpios[11].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[11].kref.port = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_NXT].port;
dev.gpios[11].kref.pin = usb_otg_hs_dev_infos.gpios[USB_HS_ULPI_NXT].pin; /* 3 */
dev.gpios[11].mode = GPIO_PIN_ALTERNATE_MODE;
dev.gpios[11].pupd = GPIO_NOPULL;
dev.gpios[11].type = GPIO_PIN_OTYPER_PP;
dev.gpios[11].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[11].afr = GPIO_AF_OTG_HS;
/* Reset */
dev.gpios[12].mask = GPIO_MASK_SET_MODE | GPIO_MASK_SET_PUPD | GPIO_MASK_SET_TYPE | GPIO_MASK_SET_SPEED | GPIO_MASK_SET_AFR;
dev.gpios[12].kref.port = usb_otg_hs_dev_infos.gpios[USB_HS_RESET].port;
dev.gpios[12].kref.pin = usb_otg_hs_dev_infos.gpios[USB_HS_RESET].pin; /* 3 */
dev.gpios[12].mode = GPIO_PIN_OUTPUT_MODE;
dev.gpios[12].pupd = GPIO_PULLUP;//GPIO_PULLDOWN;
dev.gpios[12].type = GPIO_PIN_OTYPER_PP;
dev.gpios[12].speed = GPIO_PIN_VERY_HIGH_SPEED;
dev.gpios[12].afr = GPIO_AF_OTG_HS;
ret = sys_init(INIT_DEVACCESS, &dev, &dev_desc);
return ret;
}
static uint16_t size_from_mpsize(usb_ep_t *ep){
if(ep == NULL){
return 0;
}
if (ep->max_packet_size == USB_HS_D0EPCTL_MPSIZ_64BYTES){
return 64;
}
if (ep->max_packet_size == USB_HS_D0EPCTL_MPSIZ_32BYTES){
return 32;
}
if (ep->max_packet_size == USB_HS_D0EPCTL_MPSIZ_16BYTES){
return 16;
}
if (ep->max_packet_size == USB_HS_D0EPCTL_MPSIZ_8BYTES){
return 8;
}
return ep->max_packet_size;
}
/**********/
/**
* \brief IN Endpoint activation
*
* This section describes the steps required to activate a device endpoint or to configure an
* existing device endpoint to a new type.
* 1. Program the characteristics of the required endpoint into the following fields of the
* OTG_HS_DIEPCTLx register (for IN or bidirectional endpoints)
* – Maximum packet size
* – USB active endpoint = 1
* – Endpoint start data toggle (for interrupt and bulk endpoints)
* – Endpoint type
* – TxFIFO number
*
* 2. Once the endpoint is activated, the core starts decoding the tokens addressed to that
* endpoint and sends out a valid handshake for each valid token received for the
* endpoint.
*
*/
usb_ep_error_t usb_hs_driver_in_endpoint_activate(usb_ep_t *ep)
{
/* Sanitization check */
if (!ep) {
log_printf("EP%d is not initialized \n", ep->num);
return USB_ERROR_BAD_INPUT;
}
/* Checking if enpoint is already active */
if (get_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), USB_HS_DIEPCTL_EPENA)) {
return USB_ERROR_ALREADY_ACTIVE;
}
/* Maximum packet size */
if ((size_from_mpsize(ep) <= 0) || size_from_mpsize(ep) > MAX_DATA_PACKET_SIZE(ep->num)) {
log_printf("EP%d bad maxpacket size: %d\n", ep->num, size_from_mpsize(ep));
return USB_ERROR_RANGE;
}
set_reg_value(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), ep->max_packet_size,
USB_HS_DIEPCTL_MPSIZ_Msk(ep->num),
USB_HS_DIEPCTL_MPSIZ_Pos(ep->num));
/* Define endpoint type */
if (ep->type == USB_HS_DXEPCTL_EPTYP_ISOCHRO) {
log_printf("EP%d Isochronous is not suported yet\n", ep->num);
return USB_ERROR_NOT_SUPORTED;
}
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), ep->type, USB_HS_DIEPCTL_EPTYP);
/* Endpoint start data toggle (for interrupt and bulk endpoints)
* The application uses the SD0PID/SD1PID register fields to program either DATA0 or DATA1 PID.
* 0: DATA0
* 1: DATA1
*/
if ((ep->type == USB_HS_DXEPCTL_EPTYP_INT) || (ep->type == USB_HS_DXEPCTL_EPTYP_BULK)){
if (ep->start_data_toggle == USB_HS_DXEPCTL_SD0PID_SEVNFRM) {
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), 1, USB_HS_DIEPCTL_SD0PID);
}else{
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), 1, USB_HS_DIEPCTL_SD1PID);
}
}
/* USB active endpoint
* Indicates whether this endpoint is active in the current configuration and interface. The core
* clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving
* the SetConfiguration and SetInterface commands, the application must program endpoint registers
* accordingly and set this bit.
*/
set_reg_bits(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), USB_HS_DIEPCTL_USBAEP_Msk);
/* IN endpoint FIFOx transmit RAM start address
* XXX sould be set by user ?
*/
/* FIXME add an allocator allowing to compact memory without holes*/
set_reg(r_CORTEX_M_USB_HS_DIEPTXF(ep->num), (128 * 4)*ep->num + (128 * 4)*2, USB_HS_DIEPTXF_INEPTXSA);
/* IN endpoint TxFIFO depth
* XXX sould be set by user ?
*/
set_reg(r_CORTEX_M_USB_HS_DIEPTXF(ep->num), 128, USB_HS_DIEPTXF_INEPTXFD);
/* Clearing the NAK bit for the endpoint */
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep->num), ep->num, USB_HS_DIEPCTL_CNAK);
/* Unmask IN endpoint global interrupt */
set_reg_bits(r_CORTEX_M_USB_HS_GINTMSK, USB_HS_GINTMSK_IEPINT_Msk);
/* IN EP interrupt mask bits
* The OTG_HS_DAINTMSK register works with the Device endpoint interrupt register to
* interrupt the application when an event occurs on a device endpoint.
* However, the OTG_HS_DAINT register bit corresponding to that interrupt is still set.
*/
write_reg_value(r_CORTEX_M_USB_HS_DAINTMSK, USB_HS_DAINTMSK_IEPM(ep->num));
return USB_OK;
}
/**
* \brief Out Endpoint deactivation
*
* This section describes the steps required to deactivate an existing endpoint.
* 1. In the endpoint to be deactivated, clear the USB active endpoint bit in the
* OTG_HS_DIEPCTLx register (for IN or bidirectional endpoints) or the
* OTG_HS_DOEPCTLx register (for OUT or bidirectional endpoints).
* 2. Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint,
* which results in a timeout on the USB.
*
* Note: The application must meet the following conditions to set up the device core to handle
* traffic: NPTXFEM and RXFLVLM in the OTG_HS_GINTMSK register must be cleared
*/
usb_ep_error_t usb_hs_driver_out_endpoint_deactivate(uint8_t ep){
/* Sanitization check */
if ((ep <= 0) || (ep > 3)) {
return USB_ERROR_BAD_INPUT;
}
/* Checking if enpoint is active */
if (get_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), USB_HS_DOEPCTL_EPENA)) {
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_EPENA);
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_SNAK);
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_EPDIS);
}
return USB_OK;
}
/**
* \brief IN Endpoint deactivation
*
* This section describes the steps required to deactivate an existing endpoint.
* 1. In the endpoint to be deactivated, clear the USB active endpoint bit in the
* OTG_HS_DIEPCTLx register (for IN or bidirectional endpoints) or the
* OTG_HS_DOEPCTLx register (for OUT or bidirectional endpoints).
* 2. Once the endpoint is deactivated, the core ignores tokens addressed to that endpoint,
* which results in a timeout on the USB.
*
* Note: The application must meet the following conditions to set up the device core to handle
* traffic: NPTXFEM and RXFLVLM in the OTG_HS_GINTMSK register must be cleared
*/
usb_ep_error_t usb_hs_driver_in_endpoint_deactivate(uint8_t ep){
/* Sanitization check */
if ((ep <= 0) || (ep > 3)) {
return USB_ERROR_BAD_INPUT;
}
/* Checking if enpoint is active */
if (get_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), USB_HS_DIEPCTL_EPENA)) {
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_EPENA);
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_SNAK);
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_EPDIS);
}
return USB_OK;
}
/**
* \brief Nack OUT endpoint
*
* @param ep Endpoint
*/
void usb_hs_driver_global_nack_out(){
/* Put core in Global OUT NAK mode
* A write to this field sets the Global OUT NAK.
* The application uses this bit to send a NAK handshake on all OUT endpoints.
*
* FIXME The application must set the this bit only after making sure that the Global OUT NAK
* effective bit in the Core interrupt register (GONAKEFF bit in OTG_HS_GINTSTS) is cleared.
*/
set_reg(r_CORTEX_M_USB_HS_DCTL, 1, USB_HS_DCTL_SGONAK);
}
/**
* \brief Nack OUT endpoint
*
* @param ep Endpoint
*/
void usb_hs_driver_clear_global_nack_out(){
/* A write to this field clears the Global OUT NAK. */
set_reg(r_CORTEX_M_USB_HS_DCTL, 1, USB_HS_DCTL_CGONAK);
}
/**
* \brief Nack IN endpoint
*
* @param ep Endpoint
*/
void usb_hs_driver_global_nack_in(){
/* Set global IN NAK
* A write to this field sets the Global non-periodic IN NAK.The application uses this bit to send
* a NAK handshake on all non-periodic IN endpoints.
* The application must set this bit only after making sure that the Global IN NAK effective bit
* in the Core interrupt register (GINAKEFF bit in OTG_HS_GINTSTS) is cleared.
*/
set_reg(r_CORTEX_M_USB_HS_DCTL, 1, USB_HS_DCTL_SGINAK);
}
/**
* \brief Nack IN endpoint
*
* @param ep Endpoint
*/
void usb_hs_driver_clear_global_nack_in(){
/* A write to this field clears the Global IN NAK. */
set_reg(r_CORTEX_M_USB_HS_DCTL, 1, USB_HS_DCTL_CGINAK);
}
/**
* \brief Stall OUT endpoint
*
* @param ep Endpoint
*/
void usb_hs_driver_stall_out(uint8_t ep){
/* Wait for current transmission to END */
while (get_reg_value(r_CORTEX_M_USB_HS_DOEPCTL(ep), USB_HS_DOEPCTL_EPENA_Msk, USB_HS_DOEPCTL_EPENA_Pos)){
continue; //FIXME TIMEOUT
}
/* Disable OUT EP and set STALL bit */
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_EPDIS);
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_STALL);
/* Clear STALL bit when app is ready */
/* On Ctrl 0, this is done when request or data are received */
}
/**
* \brief Stall IN endpoint
*
* @param ep Endpoint
*/
usb_ep_error_t usb_hs_driver_stall_in(uint8_t ep){
/* Wait for current transmission to END */
//while (get_reg_value(r_CORTEX_M_USB_HS_DIEPCTL(ep), USB_HS_DIEPCTL_EPENA_Msk, USB_HS_DIEPCTL_EPENA_Pos)){
// continue; //FIXME TIMEOUT
//}
int count = 0;
while (get_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), USB_HS_DIEPCTL_EPENA)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! DIEPCTL:EPENA\n");
}
return USB_ERROR_BUSY;
}
/* Disable IN EP and set STALL bit */
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_EPDIS);
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_STALL);
/* Assert on Endpoint Disabled interrupt */
//assert(read_reg_value(r_CORTEX_M_USB_HS_DIEPINT(ep)) & USB_HS_DIEPINT_EPDISD_Msk);
/* Flush transmit FIFO
* p1279 Rev14 RM0090
* Read NAK Eff Int and write AHBIL bit
*/
//while (read_reg_value(r_CORTEX_M_USB_HS_GINTSTS) & USB_HS_GINTSTS_GINAKEFF_Msk);
count = 0;
while (get_reg(r_CORTEX_M_USB_HS_GINTSTS, USB_HS_GINTSTS_GINAKEFF)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! GINTSTS:GINAKEFF\n");
}
return USB_ERROR_BUSY;
}
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, 1, USB_HS_GRSTCTL_AHBIDL);
/* Select which ep to flush and do it */
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, ep, USB_HS_GRSTCTL_TXFNUM);
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, 1, USB_HS_GRSTCTL_TXFFLSH);
/* Clear STALL bit */
/* On Ctrl 0, this is done when request is received */
return 0;
}
/**
*
*/
void usb_hs_driver_stall_in_clear(uint8_t ep, uint8_t type, uint8_t start_data_toggle){
/* Clear STALL bit */
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 0, USB_HS_DIEPCTL_STALL);
/* Reset PID */
if ((type == USB_HS_DXEPCTL_EPTYP_INT) || (type == USB_HS_DXEPCTL_EPTYP_BULK)){
if (start_data_toggle == USB_HS_DXEPCTL_SD0PID_SEVNFRM) {
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_SD0PID); /* DATA0 */
}else{
set_reg(r_CORTEX_M_USB_HS_DIEPCTL(ep), 1, USB_HS_DIEPCTL_SD1PID); /* DATA1 */
}
}
}
/**
*
*/
void usb_hs_driver_stall_out_clear(uint8_t ep, uint8_t type, uint8_t start_data_toggle){
/* Clear STALL bit */
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 0, USB_HS_DIEPCTL_STALL);
/* Reset PID */
if ((type == USB_HS_DXEPCTL_EPTYP_INT) || (type == USB_HS_DXEPCTL_EPTYP_BULK)){
if (start_data_toggle == USB_HS_DXEPCTL_SD0PID_SEVNFRM) {
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_SD0PID); /* DATA0 */
}else{
set_reg(r_CORTEX_M_USB_HS_DOEPCTL(ep), 1, USB_HS_DOEPCTL_SD1PID); /* DATA1 */
}
}
}
/**
* \brief USB On-the-Go core RESET
*
*/
static usb_ep_error_t usb_otg_hs_core_reset(void)
{
int count = 0;
/* Wait for AHB master idle */
while (!get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_AHBIDL)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! AHB Idle GRSTCTL:AHBIDL\n");
}
return USB_ERROR_BUSY;
}
/* Core soft reset */
set_reg(r_CORTEX_M_USB_HS_GRSTCTL, 1, USB_HS_GRSTCTL_CSRST);
while (get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_CSRST)){
if (++count > USB_REG_CHECK_TIMEOUT){
log_printf("HANG! Core Soft RESET\n");
}
return USB_ERROR_BUSY;
}
/* Wait for 3 PHY Clocks */
unsigned int i;
for (i = 0; i < 0xff; i++)
continue;
return 0;
}
void usb_otg_hs_core_init(void)
{
uint32_t reg_value;
/**** USB_HS_GCCFG ****/
/* Clear PWDN */
clear_reg_bits(r_CORTEX_M_USB_HS_GCCFG, USB_HS_GCCFG_PWRDWN_Msk);
/*** Initialize the core ULPI interface ****/
reg_value = read_reg_value(r_CORTEX_M_USB_HS_GUSBCFG);
/* Use the internal VBUS */
clear_reg_bits(®_value, USB_HS_GUSBCFG_ULPIEVBUSD_Msk);
/* Data line pulsing using utmi_txvalid */
clear_reg_bits(®_value, USB_HS_GUSBCFG_TSDPS_Msk);
/* ULPI interface selection */
set_reg_bits(®_value, USB_HS_GUSBCFG_UTMISEL_Msk);
/* ULPI Physical interface is 8 bits */
clear_reg_bits(®_value, USB_HS_GUSBCFG_PHYIF_Msk);
/* DDRSEL at single data rate */
clear_reg_bits(®_value, USB_HS_GUSBCFG_DDRSEL_Msk);
clear_reg_bits(®_value, USB_HS_GUSBCFG_ULPIFSLS_Msk);
clear_reg_bits(®_value, USB_HS_GUSBCFG_ULPICSM_Msk);
write_reg_value(r_CORTEX_M_USB_HS_GCCFG, reg_value);
/**** Reset after a PHY select ******/
usb_otg_hs_core_reset();
/**** TODO: DMA enable when necessary ****/
/**** TODO: optional OTG mode needs additional init *****/
}
static void core_soft_reset(void)
{
int16_t timeout;
uint32_t reg_value = 0x00000000;
unsigned short i;
log_printf("[USB HS] %s\n", __FUNCTION__);
set_reg_bits(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_CSRST_Msk);
__asm("DSB");
for (i = 0; i < 0xfff; i++)
continue; /* FIXME: Wait for 3 PHY Clock (3µs) */
/* Wait that reset finish */
timeout = 0xFF;
do {
log_printf("[USB HS] %s: Wait that reset finish: %d\n", __FUNCTION__, timeout);
//if (--timeout < 0)
// printf("Wait that reset finish timeout !");
reg_value = get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_CSRST);
//FIXME: delay(10); feature to add (active (user) & passive (kernel) support needed
delay_ms(10);
} while (reg_value == 1);
/* Wait for AHB master idle */
timeout = 20;
do {
log_printf("[USB HS] %s: Wait for AHB Idle: %d\n", __FUNCTION__, timeout);
//if (--timeout < 0)
// printf("Wait for AHB master idle timeout !");
reg_value = get_reg(r_CORTEX_M_USB_HS_GRSTCTL, USB_HS_GRSTCTL_AHBIDL);
//FIXME:delay(3);
delay_ms(3);
} while (reg_value == 0);
for (i = 0; i < 0xfff; i++)
continue; /* FIXME: Wait for 3 PHY Clock (3µs) */
log_printf("[USB HS] %s: Wait for AHB Idle: DONE\n", __FUNCTION__);
//delay(20); /* FIXME:Wait 20ms */
delay_ms(20);
/* In device mode, just after Power On Reset or a Soft Reset,
* the GINTSTS.Sof bit is set to 1'b1 for debug purposes.
* This status must be cleared and can be ignored.
*/
clear_reg_bits(r_CORTEX_M_USB_HS_GINTSTS, USB_HS_GINTSTS_SOF_Msk);
__asm("DSB");
}
/**
*\brief Device initialization.
*
* See section 34.17.3 of the reference manual
* The application must perform the following steps to initialize the core as a device on powerup
* or after a mode change from host to device.
*
*
* 1. Program the following fields in the OTG_HS_DCFG register:
* – Device speed
* – Non-zero-length status OUT handshake
* - Periodic Frame Interval (If Periodic Endpoints are supported)
* FIXME PERIODIC ENDPPOINTS NOT SUPPORTED YET
* See 7.1 Device Initialization (USB 2.0 Hi-Speed On-The-Go (OTG) Programmer’s Guide)
* 2. Program the Device threshold control register. This is required only if you are using DMA mode and
* you are planning to enable thresholding. /!\ NOT USED HERE
*
* 3. Program the OTG_HS_GINTMSK register to unmask the following interrupts:
* – USB reset
* – Enumeration done
* – Early suspend
* – USB suspend
* – SOF
*
* 4. Clear the DCTL.SftDiscon bit. The core issues a connect after this bit is cleared.
* See 7.1 Device Initialization (USB 2.0 Hi-Speed On-The-Go (OTG) Programmer’s Guide)
*
* 5. Program the VBUSBSEN bit in the OTG_HS_GCCFG register to enable VBUS sensing
* in “B” device mode and supply the 5 volts across the pull-up resistor on the DP line.
*
* 6. Wait for the USBRST interrupt in OTG_HS_GINTSTS. It indicates that a reset has been
* detected on the USB that lasts for about 10 ms on receiving this interrupt.
*
* 7. Wait for the ENUMDNE interrupt in OTG_HS_GINTSTS. This interrupt indicates the end of
* reset on the USB.
*
* At this point, the device is ready to accept SOF packets and perform control transfers on
* control endpoint 0.
*
*/
void usb_otg_hs_device_init(void)
{
/**** Restart the PHY clock *******/
write_reg_value(r_CORTEX_M_USB_HS_PCGCCTL, 0);
/**** Device configuration register ******/
set_reg(r_CORTEX_M_USB_HS_DCFG, USB_HS_DCFG_PFIVL_INTERVAL_80, USB_HS_DCFG_PFIVL);
/**** Flush the FIFOs ****/
usb_hs_driver_TXFIFO_flush_all();
usb_hs_driver_RXFIFO_flush();
/**** Set the speed */
set_reg(r_CORTEX_M_USB_HS_DCFG, USB_HS_DCFG_DSPD_HS, USB_HS_DCFG_DSPD);
usb_hs_driver_device_connect();
/*** Enable the interrupts ****/
/*** [RB]: FIXME: fix interrupts with DMA when needed ***/
set_reg_bits(r_CORTEX_M_USB_HS_GINTMSK,
USB_HS_GINTMSK_USBRST_Msk | /* USB reset: The core sets this bit to indicate that a reset is detected on the USB. */
USB_HS_GINTMSK_ENUMDNEM_Msk | /* Unmask Speed Enumeration done interupt */
USB_HS_GINTMSK_ESUSPM_Msk | /* Unmask Early suspend mask interupt */
USB_HS_GINTMSK_USBSUSPM_Msk | /* Unmask USB suspend mask */
// USB_HS_GINTMSK_SOFM_Msk | /* Unmask Start of frame */
USB_HS_GINTMSK_OEPINT_Msk | /* FIXME Unmask OUT endpoints interrupt */
USB_HS_GINTMSK_IEPINT_Msk |
USB_HS_GINTMSK_RXFLVLM_Msk);
}
static void usb_hs_init_isr_handlers(void);
/* [RB] FIXME: the hard reset of the ULPI does not seem to work with the micro-kernel
* currently. This does not prevent USB HS to work, but this must be fixed ASAP for a
* cleaner way of handling the USB HS state machine ...
*/
static void usb_otg_hs_ulpi_hard_reset(void)
{
/* TODO: macros */
log_printf("[USB HS] %s\n", __FUNCTION__);
log_printf("[USB HS] Resetting ULPI through PE13 pin ...\n");
/* Resetting the ULPI PHY is performed by setting the PE13 pin to 1 during
* some milliseconds.
*/
sys_cfg(CFG_GPIO_SET, (uint8_t)((('E' - 'A') << 4) + 13), 1);
delay_ms(5);
sys_cfg(CFG_GPIO_SET, (uint8_t)((('E' - 'A') << 4) + 13), 0);
}
static void placeholder_data_received(uint32_t dummy __attribute__((unused)))
{
}
/* Register our callback */
ADD_GLOB_HANDLER(placeholder_data_received)
static void placeholder_data_sent(void)
{
}
/* Register our callback */
ADD_GLOB_HANDLER(placeholder_data_sent)
void usb_hs_driver_early_init(void (*data_received)(uint32_t), void (*data_sent)(void))
{
if(data_sent)
usb_hs_callbacks.data_sent_callback = data_sent;
else
usb_hs_callbacks.data_sent_callback = placeholder_data_sent;
if(data_received)
usb_hs_callbacks.data_received_callback = data_received;
else
usb_hs_callbacks.data_received_callback = placeholder_data_received;
usb_device_early_init();
usb_hs_init_isr_handlers();
// NVIC_EnableIRQ(OTG_HS_IRQn);
}
/**
* \brief Inititialize USB driver.
*
* Launch needeed initialization functions.
*/
void usb_hs_driver_init(void)
{
/* First things first: reset the ULPI PHY the hard way */
usb_otg_hs_ulpi_hard_reset();
set_reg(r_CORTEX_M_USB_HS_GAHBCFG, 0, USB_HS_GAHBCFG_GINTMSK);
/* Init ULPI GPIOs */
usb_otg_hs_core_init();
usb_otg_hs_device_init();
set_reg(r_CORTEX_M_USB_HS_GAHBCFG, 1, USB_HS_GAHBCFG_GINTMSK);
}
/**
* \brief Read FIFO.
*
* Read data put in the FIFO.
*
* @param dest Destination address
* @param size Size of the data
* @param ep Endpoint from where data is read
*/
static void _read_fifo(volatile uint8_t *dest, volatile uint32_t size, uint8_t ep)
{
assert(ep <= 1);
assert(size <= USB_HS_RX_FIFO_SZ);
if((size != 0) && (dest == NULL)){
return;
}
uint32_t i = 0;
uint32_t size_4bytes = size / 4;
uint32_t tmp;
uint32_t oldmask = read_reg_value(r_CORTEX_M_USB_HS_GINTMSK);
set_reg_value(r_CORTEX_M_USB_HS_GINTMSK, 0, 0xffffffff, 0);
//disable_irq();