From eda5d3a54c0233243103d69b3ca5b555a2b98ce6 Mon Sep 17 00:00:00 2001 From: tswaehn Date: Wed, 22 Nov 2023 14:28:39 +0100 Subject: [PATCH] copy paste the definition of CMR registers from same70q21 to same70q21b fixes: zephyr #65432 --- asf/sam/include/same70b/component/tc.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/asf/sam/include/same70b/component/tc.h b/asf/sam/include/same70b/component/tc.h index 8f8988a9..b1cc4fb4 100644 --- a/asf/sam/include/same70b/component/tc.h +++ b/asf/sam/include/same70b/component/tc.h @@ -159,6 +159,29 @@ typedef union { #define TC_CMR_BURST_XC0 (TC_CMR_BURST_XC0_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC0 is ANDed with the selected clock. Position */ #define TC_CMR_BURST_XC1 (TC_CMR_BURST_XC1_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC1 is ANDed with the selected clock. Position */ #define TC_CMR_BURST_XC2 (TC_CMR_BURST_XC2_Val << TC_CMR_BURST_Pos) /**< (TC_CMR) XC2 is ANDed with the selected clock. Position */ +#define TC_CMR_LDBSTOP_Pos 6 /**< (TC_CMR) Counter Clock Stopped with RB Loading Position */ +#define TC_CMR_LDBSTOP_Msk (_U_(0x1) << TC_CMR_LDBSTOP_Pos) /**< (TC_CMR) Counter Clock Stopped with RB Loading Mask */ +#define TC_CMR_LDBSTOP TC_CMR_LDBSTOP_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBSTOP_Msk instead */ +#define TC_CMR_LDBDIS_Pos 7 /**< (TC_CMR) Counter Clock Disable with RB Loading Position */ +#define TC_CMR_LDBDIS_Msk (_U_(0x1) << TC_CMR_LDBDIS_Pos) /**< (TC_CMR) Counter Clock Disable with RB Loading Mask */ +#define TC_CMR_LDBDIS TC_CMR_LDBDIS_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_LDBDIS_Msk instead */ +#define TC_CMR_ETRGEDG_Pos 8 /**< (TC_CMR) External Trigger Edge Selection Position */ +#define TC_CMR_ETRGEDG_Msk (_U_(0x3) << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) External Trigger Edge Selection Mask */ +#define TC_CMR_ETRGEDG(value) (TC_CMR_ETRGEDG_Msk & ((value) << TC_CMR_ETRGEDG_Pos)) +#define TC_CMR_ETRGEDG_NONE_Val _U_(0x0) /**< (TC_CMR) The clock is not gated by an external signal. */ +#define TC_CMR_ETRGEDG_RISING_Val _U_(0x1) /**< (TC_CMR) Rising edge */ +#define TC_CMR_ETRGEDG_FALLING_Val _U_(0x2) /**< (TC_CMR) Falling edge */ +#define TC_CMR_ETRGEDG_EDGE_Val _U_(0x3) /**< (TC_CMR) Each edge */ +#define TC_CMR_ETRGEDG_NONE (TC_CMR_ETRGEDG_NONE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) The clock is not gated by an external signal. Position */ +#define TC_CMR_ETRGEDG_RISING (TC_CMR_ETRGEDG_RISING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Rising edge Position */ +#define TC_CMR_ETRGEDG_FALLING (TC_CMR_ETRGEDG_FALLING_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Falling edge Position */ +#define TC_CMR_ETRGEDG_EDGE (TC_CMR_ETRGEDG_EDGE_Val << TC_CMR_ETRGEDG_Pos) /**< (TC_CMR) Each edge Position */ +#define TC_CMR_ABETRG_Pos 10 /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Position */ +#define TC_CMR_ABETRG_Msk (_U_(0x1) << TC_CMR_ABETRG_Pos) /**< (TC_CMR) TIOAx or TIOBx External Trigger Selection Mask */ +#define TC_CMR_ABETRG TC_CMR_ABETRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_ABETRG_Msk instead */ +#define TC_CMR_CPCTRG_Pos 14 /**< (TC_CMR) RC Compare Trigger Enable Position */ +#define TC_CMR_CPCTRG_Msk (_U_(0x1) << TC_CMR_CPCTRG_Pos) /**< (TC_CMR) RC Compare Trigger Enable Mask */ +#define TC_CMR_CPCTRG TC_CMR_CPCTRG_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_CPCTRG_Msk instead */ #define TC_CMR_WAVE_Pos 15 /**< (TC_CMR) Waveform Mode Position */ #define TC_CMR_WAVE_Msk (_U_(0x1) << TC_CMR_WAVE_Pos) /**< (TC_CMR) Waveform Mode Mask */ #define TC_CMR_WAVE TC_CMR_WAVE_Msk /**< \deprecated Old style mask definition for 1 bit bitfield. Use TC_CMR_WAVE_Msk instead */