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I wrote an assertion using auxiliary code that states:
If pdtc_miss_q(internal formal environment signal) rises then pdt_walk_o must go high too.
However, the assertion fails due to the below wrong behavior.
Here is the counter-example of the assertion failure. In the 9th cycle, trans_error goes high but ddtc_cache is updated and in the 12th cycle when flush_ddtc_i == 1, ddtc.lu_hit_o == 1 and again there is trans_error then in the next cycle dev_tr_resp_o.aw_ready must go high, but it stays low which is wrong.
The text was updated successfully, but these errors were encountered:
I wrote an assertion using auxiliary code that states:
However, the assertion fails due to the below wrong behavior.
Here is the counter-example of the assertion failure. In the 9th cycle,
trans_error
goes high but ddtc_cache is updated and in the 12th cycle whenflush_ddtc_i
== 1,ddtc.lu_hit_o
== 1 and again there istrans_error
then in the next cycledev_tr_resp_o.aw_ready
must go high, but it stays low which is wrong.The text was updated successfully, but these errors were encountered: